High-voltage interlocking detection circuit

Abstract

The invention belongs to the technical field of high-voltage interlocking detection, and particularly relates to a high-voltage interlocking detection circuit which comprises an interlocking signal enabling end, an interlocking signal analog quantity detection end, an interlocking signal logic quantity detection end, an interlocking signal analog quantity detection enabling end and an interlocking signal logic quantity detection enabling end. The interlocking signal enabling end is connected with the interlocking signal output control circuit, and the interlocking signal output control circuit is connected with the analog quantity detection control circuit and the logic quantity detection control circuit. And the analog quantity detection control circuit and the logic quantity detection control circuit are respectively connected with an interlocking signal analog quantity detection end and an interlocking signal logic quantity detection end. According to the scheme, a high-voltage interlocking detection mode is added; a high-voltage interlocking detection circuit is simplified; the compatibility of high-voltage interlocking detection is improved; the circuit is simple, reliable in performance, small in number of elements, excellent in cost and not prone to faults.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage interlock detection, and specifically to a high-voltage interlock detection circuit. Background Art

[0002] High-voltage interlock detection in new energy vehicles is a mechanism used to ensure the integrity and safety of electrical connections in the high-voltage system. Through a series of electrical circuits and signal detections, it determines whether the connections between high-voltage components and between high-voltage components and the entire vehicle are reliable, preventing the vehicle from running when there are abnormal connections in the high-voltage system, thereby avoiding the risk of electric shock to personnel and equipment damage.

[0003] The current high-voltage interlock detection circuits in new energy vehicles have the following defects: The current high-voltage interlock detection methods in new energy vehicles are complex, the circuits lack compatibility, and the maintainability of the detection circuits is poor. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-voltage interlock detection circuit to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: A high-voltage interlock detection circuit, comprising:

[0006] An interlock signal enabling terminal, an interlock signal analog quantity detection terminal, an interlock signal logic quantity detection terminal, an interlock signal analog quantity detection enabling terminal, and an interlock signal logic quantity detection enabling terminal;

[0007] Among them, the interlock signal enabling terminal is connected to an interlock signal output control circuit, the interlock signal output control circuit is connected to an analog quantity detection control circuit and a logic quantity detection control circuit, the analog quantity detection control circuit and the logic quantity detection control circuit are respectively connected to the interlock signal analog quantity detection terminal and the interlock signal logic quantity detection terminal, and the analog quantity detection control circuit and the logic quantity detection control circuit are also respectively connected to the interlock signal analog quantity detection enabling terminal and the interlock signal logic quantity detection enabling terminal.

[0008] Preferably, the interlock signal output control circuit includes a resistor R6, a triode Q1, and a resistor R3. One end of the resistor R6 is connected to the interlock signal enabling terminal, the other end of the resistor R6 is connected to the base of the triode Q1, the emitter of the triode Q1 is grounded, the collector of the triode Q1 is connected to one end of the resistor R3, the other end of the resistor R3 is externally connected to a PS12V power supply, and the collector of the triode Q1 is also connected to the analog quantity detection control circuit and the logic quantity detection control circuit.

[0009] Preferably, an R connection is set between the collector of the triode Q1 and the analog quantity detection and control circuit and the logic quantity detection and control circuit. The two ends of the R connection are respectively connected to the interlock signal output port and the interlock signal input port. The collector of the triode Q1 is connected to the interlock signal output port, and the interlock signal input port is respectively connected to the analog quantity detection and control circuit and the logic quantity detection and control circuit.

[0010] Preferably, the analog quantity detection and control circuit includes a resistor R1, a field effect transistor M1, and a resistor R2. One end of the resistor R1 is connected to the interlock signal input port, the other end of the resistor R1 is connected to the gate of the field effect transistor M1, the drain of the field effect transistor M1 is connected to the interlock signal analog quantity detection end and one end of the resistor R2, the other end of the resistor R2 is grounded, and an analog quantity detection conduction control circuit is connected between the source of the field effect transistor M1 and the interlock signal analog quantity detection enable end.

[0011] Preferably, the analog quantity detection conduction control circuit includes resistors R11, R12, R13, R14, triodes Q4, Q5. The interlock signal analog quantity detection enable end is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the base of the triode Q5, the emitter of the triode Q5 is connected to one end of the resistor R14 and grounded, the other end of the resistor R14 is connected to one end of the resistor R12 and the source of the field effect transistor M1, the other end of the resistor R12 is connected to the collector of the triode Q4, the emitter of the triode Q4 is also externally connected to a PS12V power supply, and the base of the triode Q4 is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the collector of the triode Q5.

[0012] Preferably, the logic quantity detection and control circuit includes resistors R4, R5, a field effect transistor M2, and a logic quantity detection conduction control circuit. One end of the resistor R4 is connected to the interlock signal input port, the other end of the resistor R4 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M2 is connected to the interlock signal logic quantity detection end and one end of the resistor R5, the other end of the resistor R5 is grounded, and a logic quantity detection conduction control circuit is connected between the source of the field effect transistor M2 and the interlock signal logic quantity detection enable end.

[0013] Preferably, the logic quantity detection conduction control circuit includes resistors R7, R8, R9, R10, transistors Q2, Q3. The interlock signal logic quantity detection enable terminal is connected to one end of resistor R9. The other end of resistor R9 is connected to the base of transistor Q3. The emitter of transistor Q3 is connected to one end of resistor R10 and grounded. The other end of resistor R10 is connected to one end of resistor R8 and the source of field effect transistor M2. The other end of resistor R8 is connected to the collector of transistor Q2. The emitter of transistor Q2 is also externally connected to a PS12V power supply. The base of transistor Q2 is connected to one end of resistor R7. The other end of resistor R7 is connected to the collector of transistor Q3.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0015] This solution adds a method for high-voltage interlock detection, simplifies the high-voltage interlock detection circuit, increases the compatibility of high-voltage interlock detection, has a simple circuit, reliable performance, fewer components, excellent cost, and is not prone to failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is the circuit schematic diagram of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0018] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0019] Embodiment:

[0020] Please refer to Figure 1 , the present invention provides a technical solution: a high-voltage interlock detection circuit, including:

[0021] An interlock signal enable terminal, an interlock signal analog quantity detection terminal, an interlock signal logic quantity detection terminal, an interlock signal analog quantity detection enable terminal, an interlock signal logic quantity detection enable terminal;

[0022] Among them, the interlock signal enabling terminal is connected to the interlock signal output control circuit, the interlock signal output control circuit is connected to the analog quantity detection control circuit and the logic quantity detection control circuit, the analog quantity detection control circuit and the logic quantity detection control circuit are respectively connected to the interlock signal analog quantity detection terminal and the interlock signal logic quantity detection terminal, and the analog quantity detection control circuit and the logic quantity detection control circuit are also respectively connected to the interlock signal analog quantity detection enabling terminal and the interlock signal logic quantity detection enabling terminal;

[0023] The interlock signal output control circuit includes a resistor R6, a triode Q1 and a resistor R3. One end of the resistor R6 is connected to the interlock signal enabling terminal, the other end of the resistor R6 is connected to the base of the triode Q1, the emitter of the triode Q1 is grounded, the collector of the triode Q1 is connected to one end of the resistor R3, the other end of the resistor R3 is externally connected to the PS12V power supply, and the collector of the triode Q1 is also connected to the analog quantity detection control circuit and the logic quantity detection control circuit. An R connection is set between the collector of the triode Q1 and the analog quantity detection control circuit and the logic quantity detection control circuit. Two ends of the R connection are respectively connected to the interlock signal output port and the interlock signal input port. The collector of the triode Q1 is connected to the interlock signal output port, and the interlock signal input port is respectively connected to the analog quantity detection control circuit and the logic quantity detection control circuit.

[0024] The analog quantity detection control circuit includes a resistor R1, a field effect transistor M1 and a resistor R2. One end of the resistor R1 is connected to the interlock signal input port, the other end of the resistor R1 is connected to the gate of the field effect transistor M1, the drain of the field effect transistor M1 is connected to the interlock signal analog quantity detection terminal and one end of the resistor R2, the other end of the resistor R2 is grounded, and an analog quantity detection conduction control circuit is connected between the source of the field effect transistor M1 and the interlock signal analog quantity detection enabling terminal. The analog quantity detection conduction control circuit includes resistors R11, R12, R13, R114, triodes Q4 and Q5. The interlock signal analog quantity detection enabling terminal is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the base of the triode Q5, the emitter of the triode Q5 is connected to one end of the resistor R14 and grounded, the other end of the resistor R14 is connected to one end of the resistor R12 and the source of the field effect transistor M1, the other end of the resistor R12 is connected to the collector of the triode Q4, the emitter of the triode Q4 is also externally connected to a PS12V power supply, the base of the triode Q4 is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the collector of the triode Q5.

[0025] The logic quantity detection and control circuit includes a resistor R4, a resistor R5, a field effect transistor M2, and a logic quantity detection conduction control circuit. One end of the resistor R4 is connected to the interlock signal input port, the other end of the resistor R4 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M2 is connected to the interlock signal logic quantity detection end and one end of the resistor R5, the other end of the resistor R5 is grounded, and a logic quantity detection conduction control circuit is connected between the source of the field effect transistor M2 and the interlock signal logic quantity detection enable end. The logic quantity detection conduction control circuit includes a resistor R7, a resistor R8, a resistor R9, a resistor R10, a triode Q2, and a triode Q3. The interlock signal logic quantity detection enable end is connected to one end of the resistor R9, the other end of the resistor R9 is connected to the base of the triode Q3, the emitter of the triode Q3 is connected to one end of the resistor R10 and grounded, the other end of the resistor R10 is connected to one end of the resistor R8 and the source of the field effect transistor M2, the other end of the resistor R8 is connected to the collector of the triode Q2, the emitter of the triode Q2 is also externally connected to a PS12V power supply, the base of the triode Q2 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the collector of the triode Q3.

[0026] Analysis of the above circuit content:

[0027] The interlock signal enable end is the enable of the MCU, which has two states: high and low. When it is high, it is 5V, enabling the triode Q1 to conduct; when it is low, it is 0V, enabling the triode Q1 to cut off. When the triode Q1 conducts, the PS12V power supply is pulled to the ground through the resistor R3, and at this time the interlock signal output is 0. When the triode Q1 cuts off, the PS12V power supply reaches the interlock signal output port through the resistor R3.

[0028] R is connected as the contact impedance between the interlock signal output port and the interlock signal input port;

[0029] The interlock signal input port is connected in series with a resistor R1 and a field effect transistor M1 and then voltage-divided by a resistor R2 to the interlock signal analog quantity detection, and the interlock signal analog quantity detection is the AD acquisition port of the MCU;

[0030] The interlock signal input port is also connected in series with a resistor R4 and a field effect transistor M2, and then voltage-divided by a resistor R5 to the interlock signal logic quantity detection end, and the interlock signal logic quantity detection end is the logic quantity acquisition port of the MCU;

[0031] The interlock signal logic quantity detection enable end is the enable of the MCU, which has two states: high and low. When it is high, it is 5V, enabling the triode Q3 to conduct; when it is low, it is 0V, enabling the triode Q3 to cut off. When the triode Q3 conducts, the triode Q2 conducts, and when the triode Q2 conducts, the field effect transistor M2 conducts;

[0032] The enabling terminal for analog detection of the interlock signal is the enabling of the MCU, which has two states, high and low. When it is high, it is 5V, which makes the triode Q5 conduct. When it is low, it is 0V, which makes the triode Q5 cut off. When the triode Q5 conducts, the triode Q4 conducts. When the triode Q4 conducts, the field effect transistor M1 conducts;

[0033] The two enabling ports of the enabling terminal for analog detection of the interlock signal and the enabling terminal for logical detection of the interlock signal are not enabled simultaneously. They can be enabled alternately for detection, or one of them can be enabled alone to complete the detection. The specific enabling method can be flexibly customized according to requirements.

[0034] When the triode Q2 conducts, the voltage at point A (the connection of resistors R8 and R10 in the figure) is 12V. Through voltage division by resistors R8 and R10, the calculated voltage at point A, UA = 12V * 100 / (100 + 10) ≈ 10.9V. When the field effect transistor M2 is not conducting, the voltage at point C (the connection between the drain of the field effect transistor M2 and the interlock signal logical detection terminal) is UC = 0V. At this time, the VGS of the field effect transistor M2 is 10.9V - 0V = 10.9V. Therefore, the field effect transistor M2 conducts. When the field effect transistor M2 conducts, the voltage at point C is 12V, and it is divided by resistors R3, R connection, R4, and R5. When R connection = 0Ω, UC is the largest, and at this time, UC = 12V * 47 / (2 + 100 + 47) ≈ 3.78V. At this time, the VGS of the field effect transistor M2 is 10.9V - 3.78V = 7.12V. Therefore, the field effect transistor M2 will continue to conduct; when the triode Q2 is cut off, the field effect transistor M2 is disconnected;

[0035] When the triode Q4 conducts, the voltage at point B (the connection of resistors R12 and R14) is 12V. Through voltage division by resistors R12 and R14, the calculated UA = 12V * 100 / (100 + 10) ≈ 10.9V. When the field effect transistor M1 is not conducting, the voltage at point E (the connection between the drain of the field effect transistor M1 and the interlock signal analog detection terminal) is UE = 0V. At this time, the VGS of the field effect transistor M1 is 10.9V - 0V = 10.9V. Therefore, the field effect transistor M1 conducts. When the field effect transistor M1 conducts, the voltage at point E is 12V and is divided by resistors R3, R connection, R1, and R2. When R connection = 0Ω, UC is the largest, and at this time, UE = 12V * 47 / (2 + 100 + 47) ≈ 3.78V. At this time, the VGS of the field effect transistor M1 is 10.9V - 3.78V = 7.12V. Therefore, the field effect transistor M1 will continue to conduct; when the triode Q4 is cut off, the field effect transistor M1 is disconnected;

[0036] Interlock detection method 1: Through analog detection

[0037] 1: When the interlock signal is enabled low and the interlock signal analog detection is enabled high, the connection impedance of the interlock connection can be inferred by calculating the voltage UE at point E; R connection = 12V*R2 / UE-R3-R1-R2

[0038] Interlock detection method 2: through logic detection

[0039] 1: When the interlock signal is enabled low and the interlock signal logic detection is enabled, the voltage UC at point C can be calculated to confirm whether the interlock circuit is connected properly. At this time, UC=3.78V, and the interlock signal logic is detected to be high, which means that the interlock circuit is connected intact. When the interlock signal is enabled high and the interlock signal logic detection is enabled, UC=0V, and the lock signal logic is detected to be low. The logic at this time can be identified by the PWM wave.

[0040] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention; therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is limited by the attached claims rather than the above description. Therefore, it is intended to include all changes within the meaning and scope of the equivalent elements of the claims in the present invention, and any figure marks in the claims should not be regarded as limiting the claims involved.

[0041] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high voltage interlock detection circuit, characterized in that: include: Interlock signal enable terminal, interlock signal analog quantity detection terminal, interlock signal logic quantity detection terminal, interlock signal analog quantity detection enable terminal, interlock signal logic quantity detection enable terminal; Among them, the interlock signal enable end is connected to the interlock signal output control circuit, the interlock signal output control circuit is connected to the analog quantity detection control circuit and the logic quantity detection control circuit, the analog quantity detection control circuit and the logic quantity detection control circuit are respectively connected to the interlock signal analog quantity detection end and the interlock signal logic quantity detection end, and the analog quantity detection control circuit and the logic quantity detection control circuit are also respectively connected to the interlock signal analog quantity detection enable end and the interlock signal logic quantity detection enable end.

2. A high voltage interlock detection circuit according to claim 1, characterized in that: The interlock signal output control circuit includes a resistor R6, a transistor Q1 and a resistor R3, one end of the resistor R6 is connected to the interlock signal enable end, the other end of the resistor R6 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to one end of the resistor R3, the other end of the resistor R3 is externally connected to a PS12V power supply, and the collector of the transistor Q1 is also connected to an analog quantity detection control circuit and a logic quantity detection control circuit.

3. A high voltage interlock detection circuit according to claim 2, characterized in that: An R connection is set between the collector of the transistor Q1 and the analog quantity detection control circuit and the logic quantity detection control circuit, and the two ends of the R connection are respectively connected to the interlock signal output port and the interlock signal input port. The collector of the transistor Q1 is connected to the interlock signal output port, and the interlock signal input port is respectively connected to the analog quantity detection control circuit and the logic quantity detection control circuit.

4. A high voltage interlock detection circuit according to claim 1, characterized in that: The analog quantity detection control circuit includes a resistor R1, a field effect transistor M1 and a resistor R2, one end of the resistor R1 is connected to the interlock signal input port, the other end of the resistor R1 is connected to the gate of the field effect transistor M1, the drain of the field effect transistor M1 is connected to the interlock signal analog quantity detection end and one end of the resistor R2, the other end of the resistor R2 is grounded, and the analog quantity detection conduction control circuit is connected between the source of the field effect transistor M1 and the interlock signal analog quantity detection enable end.

5. A high voltage interlock detection circuit according to claim 4, characterized in that: The analog quantity detection conduction control circuit includes resistors R11, R12, R13, R114, transistors Q4 and Q5, the interlock signal analog quantity detection enable end is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the base of the transistor Q5, the emitter of the transistor Q5 is connected to one end of the resistor R14 and grounded, the other end of the resistor R14 is connected to one end of the resistor R12 and the source of the field effect transistor M1, the other end of the resistor R12 is connected to the collector of the transistor Q4, the emitter of the transistor Q4 is also externally connected to a PS12V power supply, the base of the transistor Q4 is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the collector of the transistor Q5.

6. A high voltage interlock detection circuit according to claim 1, characterized in that: The logic quantity detection control circuit includes resistors R4, R5, a field effect transistor M2 and a logic quantity detection conduction control circuit, one end of the resistor R4 is connected to the interlock signal input port, the other end of the resistor R4 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M2 is connected to the interlock signal logic quantity detection end and one end of the resistor R5, the other end of the resistor R5 is grounded, and the logic quantity detection conduction control circuit is connected between the source of the field effect transistor M2 and the interlock signal logic quantity detection enable end.

7. A high voltage interlock detection circuit according to claim 6, characterized in that: The logic quantity detection conduction control circuit includes resistors R7, R8, R9, R10, transistors Q2 and Q3, the interlock signal logic quantity detection enable end is connected to one end of resistor R9, the other end of resistor R9 is connected to the base of transistor Q3, the emitter of transistor Q3 is connected to one end of resistor R10 and grounded, the other end of resistor R10 is connected to one end of resistor R8 and the source of field effect transistor M2, the other end of resistor R8 is connected to the collector of transistor Q2, the emitter of transistor Q2 is also externally connected to a PS12V power supply, the base of transistor Q2 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the collector of transistor Q3.

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