Method and system for optimizing OPC (Optical Proximity Correction) target graph
By performing multiple OPC iterative calculations and logical operations on the initial graphics, optimizing the OPC correction target graphics solves the problem that the existing technology is difficult to correct a large number of corners or continuous corner graphics, and improving the accuracy of OPC correction, the chip performance and yield rate.
Patent Information
- Application Number
- CN202510559669.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-06-13
AI Technical Summary
The existing OPC correction technology is difficult to effectively correct the graphics of a large number of corners or continuous corners, resulting in excessive correction or insufficient correction, which in turn leads to a reduction in chip performance and yield.
By preprocessing the initial graph, the first target graph is obtained and multiple OPC iterations are performed to obtain the first simulated graph. Then, logical operations are performed on the first target graph and the first simulated graph to obtain the second target graph, and then multiple OPC iterations are performed to form the final output second simulated graph.
This method can more accurately correct the graphics with a large number of corners or continuous corners, reduce the deformation and deviation between the mask patterns and silicon wafer patterns, improve the accuracy of OPC correction, and ensure the performance and yield of the chip.
Smart Images
Figure CN120143564A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method and system for optimizing an OPC correction target pattern. Background Art
[0002] Due to the effects of light wave interference and diffraction, the optical proximity effect is inevitable. The currently used optical proximity correction method (OPC) is still based on an edge correction method, which makes the correction result largely limited by the segmentation method and cannot fully perform optical proximity correction. In particular, there are often a large number of corners or continuous corner patterns in the back-end metal layer, and there are obvious deviations between the optical simulation and the actual silicon wafer pattern.
[0003] Currently, the target pattern during OPC correction is obtained through a simple rounding method (curve_target command), which is greatly limited by the segmentation method, the surrounding environment, and simple parameter settings. For patterns with a large number of corners or continuous corners, it is very difficult to achieve the target pattern obtained by rounding during actual OPC correction. On the one hand, it will cause overcorrection during OPC correction and still not reach the target pattern. On the other hand, even if the layout design has been corrected, there is still a possibility of lithography failure.
[0004] The existing OPC correction method uses the rounded pattern as the target pattern, and it is very difficult to achieve the target size for the correction of patterns with a large number of corners or continuous corners, which easily leads to overcorrection or undercorrection of OPC, and further causes deformation and deviation from the mask pattern to the silicon wafer pattern, resulting in a reduction in chip performance and yield.
[0005] Based on this, how to improve the correction effect for patterns with a large number of corners or continuous corners, reduce the deformation and deviation from the mask pattern to the silicon wafer pattern, and ensure the performance and yield of the chip has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention
[0006] The purpose of the present invention is to provide a method and system for optimizing an OPC correction target pattern to solve the problem that the existing OPC correction technology is difficult to achieve the target size for the correction of patterns with a large number of corners or continuous corners, and is prone to overcorrection or undercorrection.
[0007] To achieve the above purpose, the present invention provides a method for optimizing an OPC correction target pattern, including:
[0008] Input an initial pattern, perform preprocessing on the initial pattern to obtain a first target pattern;
[0009] Based on the first target pattern, perform OPC correction in the first preset round to obtain a first simulated pattern;
[0010] Perform a logical operation on the first target pattern and the first simulated pattern to obtain a second target pattern;
[0011] Based on the second target pattern, perform OPC correction in the second preset round to obtain a second simulated pattern, and use the second simulated pattern as the output result.
[0012] Optionally, the preprocessing includes:
[0013] Based on the illumination condition and the pattern feature, process the initial pattern into an OPC correction target pattern;
[0014] Perform a rounding process on the OPC correction target pattern to obtain the first target pattern.
[0015] Optionally, the performing OPC correction in the first preset round based on the first target pattern to obtain a first simulated pattern includes:
[0016] Based on the first target pattern, perform OPC correction in the first preset round to obtain an OPC result;
[0017] Perform fitting on the OPC result to obtain the first simulated pattern.
[0018] Optionally, the first preset round includes 3 to 5 rounds.
[0019] Optionally, the performing a logical operation on the first target pattern and the first simulated pattern to obtain a second target pattern includes:
[0020] Based on the OPC correction target pattern, divide the 1D pattern and the 2D pattern;
[0021] Based on the 1D pattern and the 2D pattern, perform logical operations on the first target pattern and the first simulated pattern respectively to obtain the second target pattern.
[0022] Optionally, the dividing the 1D pattern and the 2D pattern based on the OPC correction target pattern includes:
[0023] Taking the inflection point of the OPC correction target pattern as the center and a preset size as the radius to draw a circle, the area inside the circle is the 2D pattern, and the area outside the circle is the 1D pattern.
[0024] Optionally, the performing logical operations on the first target pattern and the first simulated pattern respectively based on the 1D pattern and the 2D pattern to obtain the second target pattern includes:
[0025] After merging the 2D graphics in the first simulated graphic with the 1D graphics in the first target graphic and removing the sharp corners in the transition region, the second target graphic is obtained.
[0026] Optionally, the preset size is 0.5 times to 1 times the design size.
[0027] Optionally, the second preset round includes 8 rounds to 15 rounds.
[0028] To achieve the above object, the present invention also provides a system for optimizing the OPC-corrected target graphic, applying the method for optimizing the OPC-corrected target graphic as described above, including:
[0029] A preprocessing module for inputting an initial graphic and preprocessing the initial graphic to obtain a first target graphic;
[0030] A first correction module for performing OPC correction in a first preset round based on the first target graphic to obtain a first simulated graphic;
[0031] A logical operation module for performing a logical operation on the first target graphic and the first simulated graphic to obtain a second target graphic;
[0032] A second correction module for performing OPC correction in a second preset round based on the second target graphic to obtain a second simulated graphic.
[0033] Compared with the method for obtaining the OPC-corrected target graphic in the prior art, the method and system for optimizing the OPC-corrected target graphic provided by the present application have the following advantages:
[0034] The method for optimizing the OPC-corrected target graphic provided by the present application performs multiple OPC iterative calculations on the first target graphic obtained by preprocessing the initial graphic to obtain a first simulated graphic, and performs a logical operation on the first target graphic and the first simulated graphic to obtain a second simulated graphic. The second simulated graphic is closer to the actual graphic obtained after silicon wafer exposure than the target graphic directly obtained by rounding processing in the prior art; performing multiple OPC iterative calculations on the basis of the second simulated graphic to obtain the final output graphic can ensure that during the OPC correction process, the correction amount at the entire graphic, especially at positions with a large number of corners or continuous corners, is within a reasonable range, neither under-corrected nor over-corrected, improving the accuracy of OPC correction while reducing the deformation and deviation between the mask graphic and the silicon wafer graphic, thereby ensuring the performance and yield of the chip. Description of the Drawings
[0035] Figure 1 It is a schematic diagram of the OPC-corrected target graphic in the prior art;
[0036] Figure 2 It is a schematic diagram of the difference between the target pattern for OPC correction and the actually corrected pattern in the prior art;
[0037] Figure 3 It is a flowchart of the method for optimizing the OPC correction target pattern provided by an embodiment of the present invention;
[0038] Figure 4 It is a schematic diagram of step S1 provided by an embodiment of the present invention;
[0039] Figure 5 It is a schematic diagram of step S2 provided by an embodiment of the present invention;
[0040] Figure 6 It is a schematic diagram of step S3 provided by an embodiment of the present invention;
[0041] Figure 7 It is a schematic diagram of the system for optimizing the OPC correction target pattern provided by an embodiment of the present invention;
[0042] Among them, the descriptions of the respective reference numerals are as follows:
[0043] 10 - Pretreatment module; 20 - First correction module; 30 - Logic operation module; 40 - Second correction module. Detailed implementation manners
[0044] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and are not drawn to scale, only for facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphases to be shown in the respective drawings are different, and sometimes different scales are used.
[0045] As used in this specification, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. "One end" and "the other end", as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only the endpoints. The terms "mount", "connect", "couple" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be directly connected, or indirectly connected through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements. In addition, as used in this specification, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be construed as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element in any orientation, unless otherwise explicitly specified in the content. The terms "upper", "lower", "top", "bottom" are generally relative position relationships arranged in the direction of gravity; the terms "vertical, vertical direction" generally refer to the direction along the gravity direction, which is generally perpendicular to the ground, and the "horizontal, horizontal plane direction" is generally along the direction parallel to the ground; for those of ordinary skill in the art, the specific meanings of the above terms in this specification can be understood according to specific circumstances.
[0046] The object of the present invention is to provide a method and system for optimizing OPC correction target patterns, so as to solve the problem that the existing OPC correction technology is difficult to achieve the target size for correcting patterns with a large number of corners or continuous corners, and is prone to overcorrection or undercorrection.
[0047] Those skilled in the art can understand, please refer to Figures 1 to 2 , currently the OPC correction method is still based on the edge correction method. When facing patterns with a large number of corners or continuous corners, only relying on simple rounding to form the target pattern (as shown in Figure 1 ), and in the subsequent OPC correction process, the OPC correction result cannot meet the target pattern obtained by rounding (as shown in Figure 2As shown in the figure, there are obvious deviations between the graphics obtained by optical simulation and the actual wafer graphics, which reduces the performance and yield of the chip. Based on this, this embodiment provides a method for optimizing the OPC correction target graphics. Through multiple rounds of correction iterations based on the first target graphics after rounding, a first simulated graphic is obtained, and the first target graphic and the first simulated graphic are logically calculated to form a second target graphic. Finally, multiple rounds of correction iterations are performed based on the second target graphic to form the second simulated graphic for final output, which can ensure that graphics with a large number of corners or continuous corners can be closer to the actual graphics on the wafer, thereby reducing the deformation and deviation from the mask graphics to the wafer graphics to ensure the performance and yield of the chip.
[0048] Please refer to Figures 3 to 6 , the present invention provides a method for optimizing the OPC correction target graphics, including:
[0049] Step S1: Input the initial graphic, preprocess the initial graphic to obtain the first target graphic (as Figure 4 shown);
[0050] Step S2: Based on the first target graphic, perform the first preset round of OPC correction to obtain the first simulated graphic (as Figure 5 shown);
[0051] Step S3: Perform a logical operation on the first target graphic and the first simulated graphic to obtain the second target graphic (as Figure 6 shown);
[0052] Step S4: Based on the second target graphic, perform the second preset round of OPC correction to obtain the second simulated graphic, and use the second simulated graphic as the output result.
[0053] As an optional embodiment, please refer to Figure 4 , in step S1, the preprocessing performed on the initial graphic includes:
[0054] Step S10: Based on the illumination conditions and graphic features, process the initial graphic into an OPC correction target graphic;
[0055] Step S11: Perform a rounding process on the OPC correction target graphic to obtain the first target graphic.
[0056] In step S10, first, the input initial graphic M1 is processed into an OPC correction target graphic A0 according to the illumination conditions and graphic features by using the graphic processing method of DRC (Design Rule Checking) / NM Bias (Negative Mask Bias). In step S11, the OPC correction target graphic A0 is rounded, for example, it can be rounded by parameter control. Among them, parameter control generally refers to the fillet parameter, and the fillet parameter includes convex, concave, and line end, and the characteristic values related to rounding can be set to 0.5 times to 1 times of the design size, and finally the first target graphic A1 is formed (as Figure 4 shown).
[0057] In step S2, please refer to Figure 5 , based on the first target graphic, perform the first preset round of OPC correction to obtain the first simulated graphic, including:
[0058] Step S20: Based on the first target graphic, perform the first preset round of OPC correction to obtain the OPC result;
[0059] Step S21: Fit the OPC result to obtain the first simulated graphic.
[0060] In step S20, taking the first target graphic A1 as the target, first perform 3 to 5 rounds of OPC correction to obtain the OPC result B0. Those skilled in the art can understand that usually one round of OPC correction can include steps such as simulation modeling, error detection, mask correction, and convergence judgment. Multiple rounds of cyclic correction can gradually eliminate the residual error, especially for the cumulative influence of complex 2D graphics with multiple corners or continuous corners. In step S21, perform OPC fitting on the OPC result B0 to form the first simulated graphic C0.
[0061] In step S3, please refer to Figure 6 , perform a logical operation on the first target graphic and the first simulated graphic to obtain the second target graphic, including:
[0062] Step S30: Based on the OPC correction target graphic, divide the 1D graphic and the 2D graphic;
[0063] Step S31: Based on the 1D graphic and the 2D graphic, perform logical operations on the first target graphic and the first simulated graphic respectively to obtain the second target graphic.
[0064] In step S30, based on the OPC-corrected target pattern, the 1D patterns and 2D patterns are divided, including: taking the inflection point of the OPC-corrected target pattern A0 as the center of a circle, and drawing a circle with a preset size as the radius. The area inside the circle is the 2D pattern, and the area outside the circle is the 1D pattern. Among them, the preset size can be 0.5 times to 1 times the design size; in this embodiment, the area inside the circle is defined as the influence area of the 2D pattern, that is, not all the patterns in the area inside the circle are 2D patterns, but because their distance from the 2D pattern (such as a corner) is relatively close and they are easily affected by the correction of the 2D pattern, therefore, this part of the area is also defined in the 2D pattern. In step S31, based on the 1D patterns and 2D patterns, logical operations are respectively performed on the first target pattern and the first simulated pattern to obtain a second target pattern, including: merging the 2D pattern in the first simulated pattern C0 with the 1D pattern in the first target pattern A1, and removing the sharp corners in the transition area to obtain the second target pattern A2. It should be noted that in this embodiment, the first simulated pattern C0 and the first target pattern A1 can be merged by using logical operations, such as Boolean operations; the formula for Boolean operations can be: for 1D patterns: A2 = A1; for 2D patterns: A2 = C0.
[0065] In step S4, taking the second target pattern A2 as the final target pattern, 8 to 15 rounds of OPC corrections are performed to finally obtain a second simulated pattern B2, and the second simulated pattern B2 is output as the result.
[0066] By performing multiple OPC iterative calculations on the first target pattern obtained by preprocessing the initial pattern to obtain a first simulated pattern, and performing logical operations on the first target pattern and the first simulated pattern to obtain a second simulated pattern. The second simulated pattern is closer to the actual pattern obtained after wafer exposure than the target pattern directly obtained by rounding in the prior art; by performing multiple OPC iterative calculations on the basis of the second simulated pattern to obtain the finally output pattern, it can be ensured that during the OPC correction process, the correction amount at the entire pattern, especially at positions with a large number of corners or continuous corners, is within a reasonable range, neither under-corrected nor over-corrected. While improving the accuracy of OPC correction, it can reduce the deformation and deviation between the mask pattern and the wafer pattern, thereby ensuring the performance and yield of the chip.
[0067] Please refer to Figure 7, the present invention also provides a system for optimizing an OPC correction target pattern, applying the method for optimizing an OPC correction target pattern as described above, including: a preprocessing module 10, configured to input an initial pattern and perform preprocessing on the initial pattern to obtain a first target pattern; a first correction module 20, configured to perform a first preset round of OPC correction based on the first target pattern to obtain a first simulated pattern; a logical operation module 30, configured to perform a logical operation on the first target pattern and the first simulated pattern to obtain a second target pattern; and a second correction module 40, configured to perform a second preset round of OPC correction based on the second target pattern to obtain a second simulated pattern.
[0068] It should be noted that the preprocessing module 10, the first correction module 20, the logical operation module 30, and the second correction module 40 can communicate with each other. The preprocessing module 10 can process the input initial pattern M1 based on the illumination condition and pattern feature to form an OPC correction target pattern A0, and perform a rounding process on the OPC correction target pattern to form a first target pattern A1. The first correction module 20 can perform 3 to 5 rounds of OPC correction with the first target pattern A1 as the target to obtain an OPC result B0, and perform OPC fitting on the OPC result B0 to obtain a first simulated pattern C0. The logical operation module 30 can perform a logical operation on the first target pattern A1 and the first simulated pattern C0, merge the 2D pattern region in the first simulated pattern C0 with the 1D pattern region in the first target pattern A1, and remove the sharp corners in the transition region to obtain a second target pattern A2. The second correction module 40 can perform 8 to 15 rounds of OPC correction with the second target pattern A2 as the final target pattern, and finally obtain and output a second simulated pattern B2.
[0069] In summary, in the method and system for optimizing an OPC correction target pattern provided by the embodiments of the present invention, the method for optimizing an OPC correction target pattern includes: inputting an initial pattern, performing preprocessing on the initial pattern to obtain a first target pattern; performing a first preset round of OPC correction based on the first target pattern to obtain a first simulated pattern; performing a logical operation on the first target pattern and the first simulated pattern to obtain a second target pattern; performing a second preset round of OPC correction based on the second target pattern to obtain a second simulated pattern, and using the second simulated pattern as the output result.
[0070] Configured in this way, by performing multiple OPC iterative calculations on the first target pattern obtained through preprocessing of the initial pattern, a first simulated pattern is obtained, and through performing a logical operation on the first target pattern and the first simulated pattern, a second simulated pattern is obtained. The second simulated pattern is closer to the actual pattern obtained after the silicon wafer is exposed than the target pattern directly obtained through rounding processing in the prior art; by performing multiple OPC iterative calculations on the basis of the second simulated pattern, a final output pattern is obtained, which can ensure that during the OPC correction process, the correction amount at the entire pattern, especially at positions with a large number of corners or continuous corners, is within a reasonable range, neither under-corrected nor over-corrected. While improving the accuracy of OPC correction, it can reduce the deformation and deviation between the mask pattern and the silicon wafer pattern, thereby ensuring the performance and yield of the chip.
[0071] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for optimizing an OPC correction target graph, characterized in that: include: Inputting an initial graphic, preprocessing the initial graphic to obtain a first target graphic; Based on the first target pattern, performing a first preset round of OPC correction to obtain a first simulation pattern; Performing a logic operation on the first target pattern and the first simulation pattern to obtain a second target pattern; Based on the second target pattern, a second preset round of OPC correction is performed to obtain a second simulation pattern, and the second simulation pattern is used as an output result.
2. The method for optimizing the OPC correction target graph according to claim 1, characterized in that: The pre-processing comprises: Based on the lighting conditions and the graphic features, the initial graphic is processed into an OPC correction target graphic; The OPC corrected target pattern is circularized to obtain the first target pattern.
3. The method for optimizing the OPC correction target graph according to claim 1, characterized in that: The method of performing a first preset round of OPC correction based on the first target graph to obtain a first simulation graph includes: Based on the first target pattern, performing the first preset round of OPC correction to obtain an OPC result; The OPC result is fitted to obtain the first simulation graph.
4. The method for optimizing the OPC correction target graph as claimed in claim 3, characterized in that: The first preset rounds include 3 to 5 rounds.
5. The method for optimizing the OPC correction target graph as claimed in claim 2, characterized in that: The step of performing a logical operation on the first target pattern and the first simulation pattern to obtain the second target pattern comprises: Based on the OPC correction target graph, a 1D graph and a 2D graph are divided; Based on the 1D graphic and the 2D graphic, logical operations are performed on the first target graphic and the first simulation graphic respectively to obtain the second target graphic.
6. The method for optimizing the OPC correction target graph as claimed in claim 5, characterized in that: The method of correcting the target graphics based on OPC and dividing the 1D graphics and the 2D graphics includes: A circle is drawn with the inflection point of the OPC correction target figure as the center and a preset size as the radius, the area inside the circle is the 2D figure, and the area outside the circle is the 1D figure.
7. The method for optimizing the OPC correction target graph according to claim 6, characterized in that: The method of performing logic operations on the first target graphic and the first simulation graphic based on the 1D graphic and the 2D graphic to obtain the second target graphic comprises: The second target graphic is obtained by merging the 2D graphic in the first simulation graphic and the 1D graphic in the first target graphic and removing the sharp corners in the transition area.
8. The method for optimizing the OPC correction target graph according to claim 6, characterized in that: The preset size is 0.5 to 1 times the design size.
9. The method for optimizing the OPC correction target graph according to claim 1, characterized in that: The second preset rounds include 8 to 15 rounds.
10. A system for optimizing OPC correction target graphics, characterized in that: The method for optimizing the OPC correction target graph according to any one of claims 1 to 9 comprises: A preprocessing module, used for inputting an initial graphic and preprocessing the initial graphic to obtain a first target graphic; A first correction module, configured to perform a first preset round of OPC correction based on the first target pattern to obtain a first simulation pattern; A logic operation module, used for performing a logic operation on the first target pattern and the first simulation pattern to obtain a second target pattern; The second correction module is used to perform a second preset round of OPC correction based on the second target pattern to obtain a second simulation pattern.