Universal automatic test system and method for control module

Abstract

The invention belongs to the technical field of testing, and discloses a general automatic testing system and method for a control module, the testing system is small in equipment quantity and compact in structure, and the comprehensive automation of the testing process is realized through highly integrated hardware design and intelligent upper computer software control. Compared with a traditional test method, the system has the advantages that a tester does not need to manually operate an instrument or test the function of the control module item by item, and does not need to manually record test data, so that errors caused by manual operation are remarkably reduced, and the accuracy and reliability of a test result are improved. Meanwhile, due to the automation characteristic of the system, the test cost is greatly reduced, the test time is saved, and the test efficiency is further improved.

Description

Technical Field

[0001] The present invention mainly relates to the field of testing technologies, and particularly to a general automatic testing system and method for control modules. Background Art

[0002] In the field of radar, as one of the core circuit boards, the control module undertakes key tasks such as signal processing, system scheduling, function control, and collaborative work with other subsystems. Its performance is directly related to the overall operation efficiency and reliability of the radar system. After the control module is produced, it must undergo a strict testing process to verify its functional integrity, whether its performance indicators meet the design requirements, and its stability under different working environments. However, during the use of the control module, faults may occur due to environmental factors, component aging, or design defects. At this time, it is necessary to quickly and accurately locate the fault point in order to quickly complete the repair work, minimize the downtime of the radar system to the greatest extent, and ensure its efficient operation.

[0003] Traditional testing methods mainly rely on various instruments and meters required for a complete set of tests (such as oscilloscopes, signal generators, spectrum analyzers, etc.) and conduct manual tests item by item according to the debugging documents. This method has many drawbacks: First, the testing cost is high, requiring the purchase of a large number of special equipment and the allocation of professional technical personnel; second, the testing efficiency is low, and manual operations take a long time, making it difficult to meet the needs of mass production; third, human judgment is prone to errors, especially when dealing with complex signals or analyzing a large amount of data, and the accuracy of the test results is difficult to guarantee; finally, the test coverage is incomplete. Traditional methods often can only test specific functions or scenarios and are difficult to comprehensively cover all working states and boundary conditions of the module, resulting in potential problems not being discovered in time and the quality of the module being difficult to be effectively guaranteed.

[0004] With the rapid development of science and technology, the complexity and integration of radar systems are continuously increasing, the functions of control modules are becoming more and more powerful, and the types of interfaces are also becoming increasingly rich (such as high-speed digital interfaces, radio frequency interfaces, optical fiber interfaces, etc.). At the same time, the product development cycle has been greatly compressed, and market competition has become increasingly fierce, which puts higher requirements on testing technologies. Traditional manual testing methods can no longer meet the current requirements for testing efficiency, accuracy, coverage, and traceability. Therefore, developing a general automatic testing system for control modules has become an inevitable trend in the industry's development, with important practical significance and broad application prospects. Summary of the Invention

[0005] The object of the present invention is to provide a general automatic test system and method for control modules, aiming to solve the problems of low efficiency, insufficient coverage rate and high cost existing in traditional test methods, so as to meet the test requirements of high-performance and high-reliability control modules in modern radar systems, expand the test coverage range, and effectively reduce the overall cost of the test system.

[0006] To achieve the above object, the present invention provides a general automatic test system for control modules, including a computer processor, a router, a programmable instrument power supply, a signal generator, a main control module and a control module under test; The computer processor is connected to the router through a network cable; The router is connected to the first port of the main control module, the programmable instrument power supply and the signal generator through network cables; The second port of the main control module is connected to the first port of the programmable instrument power supply through a cable; The third port of the main control module is connected to the first port of the signal generator through a radio frequency cable; The fourth port of the main control module is connected to the third port of the control module under test through a single-mode optical fiber; The fifth port of the main control module is connected to the fourth port of the control module under test through a multi-mode optical fiber; The sixth port of the main control module is connected to the fifth port of the control module under test through a multi-mode optical fiber; The seventh port of the main control module is connected to the sixth port of the control module under test through a cable; The eighth port of the main control module is connected to the seventh port of the control module under test through a cable; The ninth port of the main control module is connected to the eighth port of the control module under test through a cable; The tenth port of the main control module is connected to the ninth port of the control module under test through a cable.

[0007] Furthermore, the computer processor runs the upper computer software of the test system, responds to test operations, outputs control instructions, receives and records test data, wherein the control instructions control the main control module, the programmable instrument power supply and the signal generator to execute corresponding working modes, and the test data reflects the electrical performance of the control module under test; The programmable instrument power supply provides working voltages for the main control module and the control module under test, and feeds back the voltage and current test data of the main control module and the control module under test to the upper computer software; When the main control module and the control module under test need a unified clock, the signal generator provides the required clock for the main control module and the control module under test; The main control module receives the control commands from the upper computer, generates test excitations and sends them to the control module under test, receives the signals sent by the control module under test and feeds back the test data to the upper computer software.

[0008] Furthermore, the main control module includes a power conversion circuit, a clock conversion circuit, a single-mode fiber transceiver circuit, a multi-mode fiber transceiver circuit, a TTL transceiver circuit, an RS422 differential transceiver circuit, a CAN interface circuit, a D / A circuit, a matrix switch circuit, an A / D acquisition preprocessing circuit, an Ethernet interface circuit, a light-emitting diode indication circuit, an FPGA, and a FLASH. The FPGA supports a SERDES interface and an A / D acquisition interface.

[0009] Furthermore, the power conversion circuit converts the voltage sent by the programmable instrument power supply into the voltage types required by the components on the main control module. The clock conversion circuit converts the radio frequency clock signal generated by the signal generator into a differential clock signal available for the FPGA, which is used for signal synchronization with the control module under test. The single-mode fiber transceiver circuit receives the single-mode fiber signal, performs optoelectronic conversion, and then sends the SERDES electrical signal to the FPGA for decoding. At the same time, it receives the SERDES electrical signal sent by the FPGA, performs electro-optical conversion, and then sends out the single-mode fiber signal. The single-mode fiber transceiver circuit reports the status of the single-mode fiber transceiver circuit, including the transmitted optical power and the received optical power, to the FPGA through the I2C bus. The multi-mode fiber transceiver circuit is used to receive the multi-mode fiber signal, perform optoelectronic conversion, and then send the SERDES electrical signal to the FPGA for decoding. At the same time, it is used to receive the SERDES electrical signal sent by the FPGA, perform electro-optical conversion, and then send out the multi-mode fiber signal. The multi-mode fiber transceiver circuit reports the status of the multi-mode fiber transceiver circuit, including the transmitted optical power and the received optical power, to the FPGA through the I2C bus. The TTL transceiver circuit uses the bus transceiver HWD16T245 device, which has a signal direction enable control port and can realize two-way control of TTL signals. The RS422 differential transceiver circuit is used for RS422 differential circuit communication. The CAN interface circuit is used for communication testing of the CAN interface of the control module under test. The D / A circuit provides an analog quantity of 0V to 5V for the analog quantity acquisition interface of the control module under test. The matrix switch circuit gates the signals of the TTL transceiver interface, the RS422 differential interface, the CAN interface, and the analog quantity direct input interface and sends them to the A / D acquisition preprocessing circuit. The A / D acquisition preprocessing circuit isolates the signal sent by the matrix switch circuit through a rail-to-rail operational amplifier and then divides the voltage to the working voltage range of the A / D sampling interface of the FPGA for A / D sampling. The Ethernet interface circuit communicates with the FPGA for network electrical signals and also communicates with the computer processor. The light-emitting diode indication circuit will display the status information including the simultaneous clock status, optical fiber reception status, Ethernet communication status, and control module test results of the main control module.

[0010] The present invention also provides a general automatic test method for a control module, comprising the following steps: Step 1: Use a general automatic test system for the control module, the system including a computer processor, a router, a programmable instrument power supply, a signal generator, a main control module, and a control module under test; Step 2: Determine whether the main control module has been powered on. If it has been powered on, configure the working parameters of the main control module; Step 3: Determine whether the control module under test has been powered on. If it has been powered on, read the working voltage and current data of the control module under test; Step 4: Determine whether the working voltage and current of the control module under test are normal. If they are not normal, the control module under test returns to the fault library for repair, and the test ends; If normal, the host computer controls the main control module to send a test timing excitation signal to the control module under test; Step 5: The control module under test feeds back corresponding timing signals to the main control module according to the received timing excitation signal, and the host computer reads the timing signal test data in the main control module; Step 6: The host computer controls the main control module to send a test level excitation signal A to the control module under test, the host computer controls the main control module to send the control module under test into the level A output working mode, the host computer controls the main control module to enter the working mode of collecting interface level data, the host computer reads the timing signal test data of the main control module this time, and stores the test data in the database; Step 7: The host computer controls the main control module to send a test level excitation signal B to the control module under test, the host computer controls the main control module to send the control module under test into the level B output working mode, the host computer controls the main control module to enter the working mode of collecting interface level data, the host computer reads the timing signal test data of the main control module this time, and stores the test data in the database; Step 8: Determine whether the test data is normal. If it is not normal, the host computer sends a test exception command to the main control module; If normal, the host computer sends a test normal command to the main control module.

[0011] Further, it also includes Step 9: Determine whether the control module under test has been powered off. If it has been powered off, determine whether the main control module has been powered off. If the main control module has been powered off, remove the control module under test, and the control module under test flows into the next process, and the test ends.

[0012] Further, in Step 8, if the host computer sends a test exception command to the main control module, the test indicator light flashes; If the host computer sends a normal test command to the main control module, the test indicator light will be on constantly.

[0013] Furthermore, in step 4, the timing excitation signal is generated according to the timing requirements of the installed program of the control module under test, including single-mode optical fiber signal, multi-mode optical fiber signal, TTL signal, RS422 differential signal, CAN bus signal, D / A analog output signal. In step 5, the main control module receives the timing signals fed back by the control module under test, including single-mode optical fiber signal, multi-mode optical fiber signal, TTL signal, RS422 differential signal, CAN bus signal, D / A analog output signal.

[0014] Furthermore, in steps 6 and 7, the host computer controls the main control module to enter the working mode of collecting interface level data. The matrix switch circuit on the main control module sequentially polls and selects a TTL signal, an RS422 differential signal, a CAN bus signal, a D / A analog input signal, a TTL signal, an RS422 differential signal, and a D / A analog output signal. After being isolated and voltage-divided by the A / D sampling and preprocessing circuit, they are sent to the A / D sampling interface of the FPGA to collect level data.

[0015] Furthermore, in steps 6 and 7, the high and low voltage levels of the electrical interface signals can be subjected to coverage testing. The electrical interfaces include RS422 differential interfaces, TTL interfaces, and analog input interfaces.

[0016] Beneficial effects: The present invention provides a general-purpose automatic test system and method for a control module. The test system has few devices and a compact structure. Through a highly integrated hardware design and intelligent host computer software control, the full automation of the test process is realized. Compared with the traditional test method, this system does not require testers to manually operate instruments or test the functions of the control module item by item, nor does it require manual recording of test data, thus significantly reducing the errors introduced by human operations and improving the accuracy and reliability of test results. At the same time, the automation characteristics of the system greatly reduce the test cost, save test time, and further improve the test efficiency. Brief Description of the Drawings

[0018] Figure 1 is a schematic structural diagram of a general-purpose automatic test system for a control module according to an embodiment of the present invention; Figure 2 is a schematic flowchart of a general-purpose automatic test system for a control module according to an embodiment of the present invention Figure 1 ; Figure 3 is a schematic flowchart of a general-purpose automatic test system for a control module according to an embodiment of the present invention Figure 2 ; Figure 4It is a schematic diagram of the function block of the main control module of a general automatic test system for control modules according to an embodiment of the present invention; Figure 5 It is a test flow chart of a general automatic test method for control modules according to an embodiment of the present invention.

[0019] Explanation of reference numerals: 101 is a computer processor; 102 is a router; 103 is a programmable instrument power supply; 104 is a signal generator; 105 is a main control module; 106 is a control module under test; 401 is a single-mode fiber optic transceiver circuit; 402 is a multi-mode fiber optic transceiver circuit; 403 is an Ethernet interface circuit; 404 is a clock conversion circuit; 405 is a differential receiving circuit; 406 is a CAN interface circuit; 407 is a matrix switch circuit; 408 is a TTL transceiver circuit; 409 is a D / A circuit; 410 is an A / D acquisition preprocessing circuit; 411 is a FLASH; 412 is a power conversion circuit; 413 is an FPGA; 414 is a light-emitting diode indication circuit. Specific embodiments

[0020] The preferred mechanisms and implementation methods of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] As Figures 1 to 5 shown, an embodiment of the present invention discloses a general automatic test system and method for control modules. Embodiment 1

[0022] In one example, as Figures 1 to 4 shown, it is a general automatic test system for control modules provided by an embodiment of the present application. The test system may include a computer processor 101, a router 102, a programmable instrument power supply 103, a signal generator 104, a main control module 105, and a control module under test 106, wherein the computer processor is a desktop computer.

[0023] Among them, the desktop computer 101 is connected to the router 102 via a network cable. The router 102 is connected to the first end of the main control module 105, the programmable instrument power supply 103, and the signal generator 104 via network cables. The second end of the main control module 105 is connected to the first end of the programmable instrument power supply 103 via a cable. The third end of the main control module 105 is connected to the first end of the signal generator 104 via a radio frequency cable. The fourth end of the main control module 105 is connected to the third end of the control module 106 via a single-mode optical fiber. The fifth end of the main control module 105 is connected to the fourth end of the control module 106 via a multi-mode optical fiber. The sixth end of the main control module 105 is connected to the fifth end of the control module 106 via a multi-mode optical fiber. The seventh end of the main control module 105 is connected to the sixth end of the control module 106 via a cable. The eighth end of the main control module 105 is connected to the seventh end of the control module 106 via a cable connector. The ninth end of the main control module 105 is connected to the eighth end of the control module 106 via a cable. The tenth end of the main control module 105 is connected to the ninth end of the control module 106 via a cable.

[0024] The desktop computer 101 can be used to run the upper computer software, respond to test operations, and output control instructions. The control instructions can be used to control the voltage and current limiting values output at the first end and the second end of the programmable instrument power supply 103, and read and record the voltage and current test data during its operation. The control instructions can also be used to control the clock frequency and amplitude output at the first end and the second end of the signal generator 104. The control instructions can also be used to control the working mode of the main control module, generate different test excitation signals for testing the control module, and read and record the test data sent by the control module to the main control module. The upper computer software judges the correctness of the test data according to the pre-configured test data comparison file, and sends a test result light-emitting diode display control instruction to the main control module to indicate whether this test is normal.

[0025] The router 102 is used to provide network routing functions. The router 102 connects the desktop computer 101, the programmable instrument power supply 103, the signal generator 104, and the main control module 105 together via network cables.

[0026] The programmable instrument power supply 103 is used to provide a DC voltage source to supply power to the main control module 105 and the control module 106.

[0027] The signal generator 104 is used to provide a clock to the main control module 105 and the control module 106. When the main control module and the control module under test require a unified clock, the signal generator provides the required clock to the main control module and the control module under test.

[0028] The main control module 105 is the core device of the test system. It provides a rich variety of test interfaces. For example, the fourth port can be a single-mode fiber optic transceiver interface, the fifth port can be a multi-mode fiber optic transceiver interface, the sixth port can be a TTL transceiver interface, the seventh port can be an RS422 differential transceiver interface, the eighth port can be a CAN communication interface, the ninth port can be an A / D analog quantity acquisition and preprocessing interface, and the tenth port can be a D / A analog quantity output interface.

[0029] The control module 106 is the device under test in the test system. In a radar system, the number of interface types of the control module is often less than or equal to that of the main control module 105. In this way, the above test system can cover the interface test of the control module and achieve automatic module testing.

[0030] The structural block diagram of the main control module 105 is as Figure 4 shown. The main control module includes a power conversion circuit 412, a clock conversion circuit 404, a single-mode fiber optic transceiver circuit 401, a multi-mode fiber optic transceiver circuit 402, a TTL transceiver circuit 408, an RS422 differential transceiver circuit 405, a CAN interface circuit 406, a D / A circuit 409, a matrix switch circuit 407, an A / D acquisition and preprocessing circuit 410, an Ethernet interface circuit 403, a light-emitting diode indication circuit 414, an FPGA 413, a configuration FLASH 411, etc. The core component of the main control module is the FPGA, and the FPGA needs to support high-speed SERDES interfaces and A / D acquisition interfaces.

[0031] The power conversion circuit 412 is used to convert the voltage supplied by the programmable instrument power supply into the voltage types required by the components on the main control module.

[0032] The clock conversion circuit 404 is used to convert the radio frequency clock signal generated by the signal generator into a differential clock signal available for the FPGA, for signal synchronization with the control module.

[0033] The single-mode fiber optic transceiver circuit 401 is used to receive single-mode fiber optic signals, perform optoelectronic conversion, and send the SERDES electrical signal to the FPGA for decoding processing. At the same time, it is used to receive the SERDES electrical signal sent by the FPGA, perform electro-optical conversion on the electrical signal, and send out single-mode fiber optic signals. The single-mode fiber optic transceiver circuit reports the status of the single-mode fiber optic transceiver circuit, such as the transmitted optical power and the received optical power, to the FPGA through the I2C bus.

[0034] The multimode fiber transceiver circuit 402 is used to receive multimode fiber signals, perform optoelectronic conversion, and then send the SERDES electrical signals to the FPGA for decoding processing. At the same time, it is used to receive the SERDES electrical signals sent by the FPGA, perform electro-optical conversion on the electrical signals, and then send out multimode fiber signals. The multimode fiber transceiver circuit reports the status of the multimode fiber transceiver circuit, such as the transmitted optical power and received optical power, to the FPGA through the I2C bus.

[0035] The TTL transceiver circuit 408 uses the bus transceiver HWD16T245 device, which has a signal direction enable control port and can realize bidirectional control of TTL signals.

[0036] The RS422 differential transceiver circuit 405 is used for RS422 differential circuit communication.

[0037] The CAN interface circuit 406 is used to conduct communication tests with the CAN interface of the measured control module.

[0038] The D / A circuit 409 is used to provide an analog quantity of 0V to 5V for the analog quantity acquisition interface of the measured control module.

[0039] The matrix switch circuit 407 is used to select and gate the signals of the TTL transceiver interface, RS422 differential interface, CAN interface, and analog direct input interface, and send them to the A / D acquisition preprocessing circuit.

[0040] The A / D acquisition preprocessing circuit 410 is used to isolate the signals sent by the matrix switch through a rail-to-rail operational amplifier, then divide the voltage to the working voltage range of the A / D sampling interface of the FPGA for A / D sampling.

[0041] There are significant differences between the rail-to-rail operational amplifier and the ordinary operational amplifier. These differences are mainly reflected in aspects such as input / output range, performance characteristics, application scenarios, and design complexity. The biggest feature of the rail-to-rail operational amplifier is that its input and output ranges can cover from the minimum value of the power supply voltage (usually 0 volts) to the maximum value (i.e., the power supply voltage). This design enables the operational amplifier to make full use of the power supply voltage, thus having higher flexibility and dynamic range when processing signals. For the input voltage, the rail-to-rail operational amplifier can process signals close to the power supply voltage limit without introducing nonlinear distortion. This means that within the power supply voltage range, almost any amplitude of input signal can be effectively amplified. For the output voltage, the rail-to-rail operational amplifier can approach or reach the boundary of the power supply voltage, thus providing a larger output swing. With its characteristics such as wide dynamic range, high gain, low distortion, and low noise, the rail-to-rail operational amplifier shows unique advantages in application scenarios that require high precision, wide dynamic range, and low noise.

[0042] The working range of the A / D sampling interface of the FPGA is generally small. Taking the Xilinx 7-series FPGA as an example, the working voltage range of its A / D interface is 0~1V, while the signal after the operational amplifier may be a signal of 0~5V. Therefore, the signal needs to be divided down to 0~1V after the operational amplifier and then sent to the A / D interface of the FPGA for sampling.

[0043] The Ethernet interface circuit 403 is used for network electrical signal communication with the FPGA 413 and is also used for communication with the desktop computer 101.

[0044] The light-emitting diode indication circuit 414 is used to display the status information such as the simultaneous clock status, optical fiber reception status, Ethernet communication status, and control module test results of the main control module. Embodiment 2

[0045] In one example, as Figure 2 、 Figure 3 and Figure 5 shown, a general automatic test method for a control module provided by an embodiment of the present application.

[0046] In S201, on the computer processor, edit the test items and test sequence, configure the test commands, configure the test data comparison file, input the information of the control module under test, and start the test; After the test starts, the host computer software outputs a program-controlled instrument power control instruction through S202; Set S204 to output a main control module control instruction, including the power supply voltage and current limit value; Set S205 to output a control instruction for the control module under test, including the power supply voltage and current limit value; In S203, output a signal generator control instruction, and set S206 to output the clock required by the main control module, including the clock frequency and amplitude; Set S207 to output the clock required by the control module under test, including the clock frequency and amplitude, and turn on the clock signal output; In S202, the program-controlled instrument power sends a control instruction to turn on the power supply voltage output of the main control module, and reads the voltage and current test data output by the program-controlled instrument power supply to the main control module through S208. If the test data is normal, output a main control module control instruction through S204 to configure the basic control parameters of the main control module; In S202, the program-controlled instrument power sends a control instruction to turn on the power supply voltage output of the control module under test, and reads the voltage and current test data output by the program-controlled instrument power supply to the control module under test through S208; If the test data is normal, proceed to the next test step; If the test data is abnormal, stop the test, and the current control module under test enters the fault library for repair.

[0047] Through S204, control the main control module 105 to send a test timing excitation signal to the control module 106 under test. The timing excitation signal is as Figure 3 shown, and may include S301 single-mode fiber optic signal, S303 multi-mode fiber optic signal, S305 TTL signal, S307 RS422 differential signal, S309 CAN bus signal, S311 D / A analog output signal. These timing signals need to be generated according to the timing requirements of the installation procedure of the control module 106 under test.

[0048] The control module 106 under test feeds back the corresponding timing signal to the main control module 105 according to the received timing excitation signal. The timing signal fed back by the control module 106 can often reflect whether the received timing signal is correct, and can indirectly reflect whether the signal input interface of the control module 106 under test is correct.

[0049] The main control module 105 receives the timing signal fed back by the control module 106 under test, including S302 single-mode fiber optic signal, S304 multi-mode fiber optic signal, S306 TTL signal, S308 RS422 differential signal, S309 CAN bus signal, S310 A / D analog input signal. The upper computer reads the timing signal test data in the main control module 105 and stores the test data in the database.

[0050] Through S204, control the main control module 105 to send the control module 106 into the level output working mode 1. Through S204, control the main control module 105 to send a test level excitation signal 1 to the control module 106. The level excitation signal is as Figure 3 shown, and may include S305 TTL signal, S307 RS422 differential signal, S311 D / A analog output signal. The upper computer controls the main control module 105 to enter the working mode of collecting interface level data. The matrix switch circuit 407 on the main control module 105 sequentially polls and selects one path of S306 TTL signal, S308 RS422 differential signal, S309 CAN bus signal, S310 A / D analog input signal, S305 TTL signal, S307 RS422 differential signal, S311 D / A analog output signal. After being isolated and voltage-divided by the A / D sampling and preprocessing circuit 410, it is sent to the A / D sampling interface of the FPGA 413 to collect level data. The upper computer reads the test data of the main control module 105 this time and stores the test data in the database.

[0051] Through S204, control the main control module 105 to send the control module 106 into the level output working mode 2. Through S204, control the main control module 105 to send a test level excitation signal 2 to the control module 106. The level excitation signal is asFigure 3 As shown, it may include S305 TTL signal, S307 RS422 differential signal, and S311 D / A analog output signal. The host computer controls the main control module 105 to enter the working mode of collecting interface level data. The matrix switch circuit 407 on the main control module 105 sequentially polls and selects a path of S306 TTL signal, S308 RS422 differential signal, S309 CAN bus signal, S310 A / D analog input signal, S305 TTL signal, S307 RS422 differential signal, and S311 D / A analog output signal. After being isolated and voltage-divided by the A / D sampling and preprocessing circuit 410, the signals are sent to the A / D sampling interface of the FPGA 413 to collect level data. The host computer reads the test data of the main control module 105 this time and stores the test data in the database.

[0052] After the above two tests of different level modes, the high-level and low-level voltages of the electrical interface signals can be covered for testing.

[0053] The host computer software makes a final judgment on the test data this time and enters the test results into the database. At the same time, the test results are sent to the main control module 105 through S204. If the test result indicator light of the light-emitting diode on the main control module 105 is always on, it means the test is normal; if the test result indicator light of the light-emitting diode on the main control module 105 flashes, it means the test is abnormal.

[0054] Control the power supply of the programmable instrument 103 through S202 to turn off the power of the DUT control module 106 and the main control module 105 in sequence.

[0055] Remove the DUT control module 106. Those with normal tests flow into the next process, and those with abnormal tests are returned to the fault library for repair.

[0056] The present invention provides a general automatic test system and method for a control module. The test system has few equipment and a compact structure. Through a highly integrated hardware design and intelligent host computer software control, it realizes the full automation of the test process. Compared with the traditional test method, this system does not require testers to manually operate instruments or test the functions of the control module item by item, nor does it require manual recording of test data, thus significantly reducing the errors introduced by human operations and improving the accuracy and reliability of test results. At the same time, the automated characteristics of the system greatly reduce the test cost, save the test time, and further improve the test efficiency.

[0057] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A universal automatic test system for control modules, characterized in that: It includes a computer processor, a router, a programmable instrument power supply, a signal generator, a main control module and a control module under test; The computer processor is connected to the router via an Ethernet cable; The router is connected to the first port of the main control module, the power supply of the program-controlled instrument, and the signal generator through a network cable; The second port of the main control module is connected to the first port of the program-controlled instrument power supply through a cable; The third port of the main control module is connected to the first port of the signal generator via a radio frequency cable; The fourth port of the main control module is connected to the third port of the control module under test through a single-mode optical fiber; The fifth port of the main control module is connected to the fourth port of the control module under test via a multimode optical fiber; The sixth port of the main control module is connected to the fifth port of the control module under test via a multimode optical fiber; The seventh port of the main control module is connected to the sixth port of the control module under test through a cable; The eighth port of the main control module is connected to the seventh port of the control module under test through a cable; The ninth port of the main control module is connected to the eighth port of the control module under test through a cable; The tenth port of the main control module is connected to the ninth port of the tested control module through a cable.

2. The universal automatic test system for control modules according to claim 1, characterized in that: The computer processor runs the host computer software of the test system, responds to the test operation, outputs the control instruction, receives and records the test data, wherein the control instruction controls the main control module, the programmable instrument power supply, and the signal generator to execute the corresponding working mode, and the test data reflects the electrical performance of the control module under test; The program-controlled instrument power supply provides working voltage to the main control module and the control module under test, and feeds back the voltage and current test data of the main control module and the control module under test to the host computer software; The signal generator provides the required clock to the main control module and the control module under test; The main control module receives control commands from the host computer, generates test stimuli and sends them to the control module under test, receives signals from the control module under test and feeds back test data to the host computer software.

3. The universal automatic test system for control modules according to claim 1, characterized in that: The main control module includes power conversion circuit, clock conversion circuit, single-mode optical fiber transceiver circuit, multi-mode optical fiber transceiver circuit, TTL transceiver circuit, RS422 differential transceiver circuit, CAN interface circuit, D / A circuit, matrix switch circuit, A / D acquisition preprocessing circuit, Ethernet interface circuit, light-emitting diode indication circuit, FPGA, FLASH, among which FPGA can support SERDES interface and A / D acquisition interface.

4. The universal automatic test system for control modules according to claim 3, characterized in that: The power conversion circuit converts the voltage sent by the program-controlled instrument power supply into the voltage type required by the components on the main control module; The clock conversion circuit converts the RF clock signal generated by the signal generator into a differential clock signal that can be used by the FPGA, which is used for signal synchronization with the control module under test; The single-mode fiber transceiver circuit receives the single-mode fiber signal and sends the SERDES electrical signal to the FPGA for decoding after performing photoelectric conversion. At the same time, it receives the SERDES electrical signal sent by the FPGA and sends the single-mode fiber signal after performing electro-optical conversion. The single-mode fiber transceiver circuit and the FPGA report the status of the single-mode fiber transceiver circuit through the I2C bus, including the sending optical power and the receiving optical power. The multi-mode optical fiber transceiver circuit is used to receive the multi-mode optical fiber signal and send the SERDES electrical signal to the FPGA for decoding after performing the photoelectric conversion. It is also used to receive the SERDES electrical signal sent by the FPGA and send the multi-mode optical fiber signal after performing the electro-optical conversion. The multi-mode optical fiber transceiver circuit and the FPGA report the status of the multi-mode optical fiber transceiver circuit through the I2C bus, including the sending optical power and the receiving optical power. The TTL transceiver circuit uses a bus transceiver HWD16T245 device, which has a signal direction enable control port to achieve bidirectional control of TTL signals; RS422 differential transceiver circuit is used for RS422 differential circuit communication; The CAN interface circuit is used for communication testing of the CAN interface of the control module under test; The D / A circuit provides 0V~5V analog quantity for the analog quantity acquisition interface of the control module under test; The matrix switch circuit selects the signals of the TTL transceiver interface, the RS422 differential interface, the CAN interface, and the analog direct input interface and sends them to the A / D acquisition preprocessing circuit; The A / D acquisition preprocessing circuit divides the signal sent after the matrix switch circuit is selected and isolates it through a rail-to-rail operational amplifier to the working voltage range of the A / D sampling interface of the FPGA for A / D sampling; The Ethernet interface circuit communicates with the FPGA through network electrical signals and also communicates with the computer processor; The light emitting diode indication circuit displays information including the simultaneous clock status of the main control module, the optical fiber receiving status, the Ethernet communication status, and the control module test result.

5. A universal automatic testing method for a control module, characterized in that: The following steps are involved: Step 1: using a universal automatic test system for a control module, the system comprising a computer processor, a router, a programmable instrument power supply, a signal generator, a main control module and a control module under test; Step 2: Determine whether the main control module is powered on. If it is powered on, configure the working parameters of the main control module; Step 3: Determine whether the control module under test has been powered on. If it has been powered on, read the operating voltage and current data of the control module under test; Step 4: Determine whether the working voltage and current of the tested control module are normal. If not, the tested control module is returned to the fault library for repair, and the test ends. If it is normal, the host computer controls the main control module to send a test timing excitation signal to the control module under test; Step 5: The control module under test feeds back the corresponding timing signal to the main control module according to the received timing excitation signal, and the host computer reads the timing signal test data in the main control module; Step 6: The host computer controls the main control module to send the test level excitation signal A to the control module under test, the host computer controls the main control module to send the control module under test to enter the level A output working mode, the host computer controls the main control module to enter the acquisition interface level data working mode, the host computer reads the timing signal test data of the main control module this time, and stores the test data in the database; Step 7: The host computer controls the main control module to send the test level excitation signal B to the control module under test, the host computer controls the main control module to send the control module under test to enter the level B output working mode, the host computer controls the main control module to enter the acquisition interface level data working mode, the host computer reads the timing signal test data of the main control module this time, and stores the test data in the database; Step 8: Determine whether the test data is normal. If not, the host computer sends a test abnormality command to the main control module; If normal, the host computer sends a normal test command to the main control module.

6. The universal automatic test method for control modules according to claim 5, characterized in that: The process also includes step 9: determining whether the tested control module has been powered off; if so, determining whether the main control module has been powered off; if the main control module has been powered off, removing the tested control module, and the tested control module flows into the next process, and the test ends.

7. The universal automatic test method for control modules according to claim 5, characterized in that: In step 8, if the host computer sends a test abnormality command to the main control module, the test indicator light flashes; If the host computer sends a normal test command to the main control module, the test indicator light will be on.

8. The universal automatic testing method for control modules according to claim 5, characterized in that: In step 4, the timing excitation signal is generated according to the timing requirements of the installation program of the control module under test, including single-mode fiber signal, multi-mode fiber signal, TTL signal, RS422 differential signal, CAN bus signal, D / A analog output signal; In step 5, the timing signals fed back by the control module under test and received by the main control module include single-mode optical fiber signals, multi-mode optical fiber signals, TTL signals, RS422 differential signals, CAN bus signals, and D / A analog output signals.

9. The universal automatic test method for control modules according to claim 8, characterized in that: In step 6 and step 7, the host computer controls the main control module to enter the interface level data acquisition working mode. The matrix switch circuit on the main control module polls and selects one TTL signal, RS422 differential signal, CAN bus signal, D / A analog input signal, TTL signal, RS422 differential signal, and D / A analog output signal in turn, and then sends them to the A / D sampling interface of the FPGA to collect level data after isolation and voltage division by the A / D sampling preprocessing circuit.

10. The universal automatic test method for control modules according to claim 5, characterized in that: In step 6 and step 7, the high level and low level voltages of the electrical interface signal may be subjected to coverage testing, and the electrical interface includes an RS422 differential interface, a TTL interface, and an analog input interface.

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