Low dropout regulator with off-chip capacitor and power supply

Abstract

The invention provides a low dropout regulator with an off-chip capacitor and a power supply, the low dropout regulator comprises a bias module, a control voltage generation module and a voltage stabilization module, the input end of the control voltage generation module is connected with a reference voltage, and a stable control voltage is generated through dynamic adjustment of a negative feedback structure; the voltage stabilizing module provides voltage for the output end of the low-dropout voltage stabilizer based on the control voltage, a plurality of voltage followers and a plurality of power transistors are arranged in the voltage stabilizing module, and the output voltage of the low-dropout voltage stabilizer is fed back to the voltage followers. And the plurality of voltage followers control the parasitic capacitors in the corresponding power transistors to charge or discharge based on the output voltage, so that the output voltage is stabilized. According to the voltage stabilizer, the power transistor is divided into multiple parts, the voltage follower arranged in the voltage stabilizing module has push-pull capacity, the transient response speed of the voltage stabilizer is increased, the power supply rejection ratio is improved, the reaction efficiency of the voltage stabilizer is improved, and the performance of the voltage stabilizer is also improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic component design, and particularly to a low dropout regulator with an external capacitor and a power supply. Background Art

[0002] In modern electronic devices, the power supply is the foundation of the entire circuit. However, the operating state of the circuit changes with the load, causing the current in the circuit to fluctuate, which raises the requirements for the power supply. To meet the needs of low power consumption and high efficiency and provide a stable power supply rail for analog and digital signal circuits, a low dropout regulator (LDO) has become one of the means to improve the power supply performance.

[0003] In the prior art, a low dropout regulator with an external level is generally adopted. The additional capacitor increases the space requirement of the printed circuit board and the cost of the bill of materials (BOM), and also increases the assembly complexity and potential failure points. A larger value capacitor will result in a longer start-up time and, in some cases, increase the static power consumption because the LDO needs to charge the additional capacitor.

[0004] Therefore, how to provide a low dropout regulator with an external capacitor that has less dependence on the external capacitor and responds quickly is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the present invention provides a low dropout regulator with an external capacitor to solve at least one of the above-mentioned technical problems.

[0006] To achieve the above object and other related objects, the technical solutions provided in the present application are as follows.

[0007] In a first aspect, according to the embodiments provided in the present application, there is provided a low dropout regulator with an external capacitor, including:

[0008] A control voltage generation module, which receives a reference voltage, performs negative feedback on the reference voltage, and obtains a control voltage;

[0009] A voltage regulation module, which is connected to the control voltage generation module. It includes N voltage followers and N power transistors, provides a voltage for the output end of the low dropout regulator based on the control voltage, and feeds back the output voltage of the low dropout regulator to the N voltage followers, so as to use the voltage followers to control the charging or discharging of the parasitic capacitance in the corresponding power transistors based on the output voltage, thereby stabilizing the output voltage;

[0010] A bias module for providing a bias voltage for the current sources in the control voltage generation module and the voltage regulation module;

[0011] Where N≥2 and N is a positive integer.

[0012] In an embodiment of the present application, the bias module includes a current source, a first NMOS transistor, a second NMOS transistor, and a first PMOS transistor. The input terminal of the current source is connected to the power supply voltage, the output terminal of the current source is connected to the drain of the first NMOS transistor, the drain of the first NMOS transistor is also connected to the gate of the first NMOS transistor, the gate of the first NMOS transistor is also connected to the gate of the second NMOS transistor, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, the source of the first NMOS transistor is grounded, the source of the first PMOS transistor is connected to the power supply voltage, the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the first PMOS transistor is also connected to the drain of the second NMOS transistor. Wherein, the gates of the first PMOS transistor and the first NMOS transistor output the bias voltage.

[0013] In an embodiment of the present application, the control voltage generation module includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage, the source of the second PMOS transistor is also connected to the source of the third PMOS transistor, the gate of the second PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the third PMOS transistor is also connected to the drain of the third PMOS transistor, the drain of the second PMOS transistor is also connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is grounded, the source of the third NMOS transistor is also connected to the source of the fourth NMOS transistor, the drain of the second PMOS transistor is also connected to the gate of the fourth PMOS transistor, the drain of the third PMOS transistor is also connected to the drain of the fourth NMOS transistor, the source of the fourth PMOS transistor is connected to the source of the second PMOS transistor, the drain of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fourth PMOS transistor is also connected to the source of the fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is grounded. Wherein, the gate of the third NMOS transistor is connected to the reference voltage, the gates of the fifth NMOS transistor and the sixth NMOS transistor are connected to the bias voltage, and the gate of the fifth PMOS transistor outputs the control voltage.

[0014] In an embodiment of the present application, the voltage regulation module includes a voltage inverter, N voltage followers, and N power transistors. The voltage inverter is connected to the output voltage and the bias voltage, provides a voltage equal to the reference voltage for the output terminal of the low-dropout regulator based on the control voltage, and generates a first driving voltage according to the output voltage and the bias voltage. The first voltage follower is connected to the first driving voltage, the non-inverting input terminal of the next voltage follower is connected to the output terminal of the previous voltage follower, the output terminals of the N voltage followers are respectively connected to the gates of the N power transistors. The first driving voltage is followed and output through the N voltage followers to obtain N second driving voltages, so as to control N corresponding parasitic capacitors to charge or discharge through the N second driving voltages, and regulate the output voltage commonly output by the drains of the N power transistors.

[0015] In an embodiment of the present application, the voltage inverter includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a seventh NMOS transistor. The source of the sixth PMOS transistor is connected to the drain of the Nth power transistor, the drain of the sixth PMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is grounded, the drain of the sixth PMOS transistor is also connected to the gate of the seventh PMOS transistor, the source of the eighth PMOS transistor is connected to the power supply voltage, the drain of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor, and the drain of the seventh PMOS transistor is grounded. Wherein, the gate of the sixth PMOS transistor is connected to the control voltage, the gate of the seventh NMOS transistor is connected to the bias voltage, the gate of the eighth PMOS transistor is connected to the bias voltage, and the drain of the eighth PMOS transistor outputs the first driving voltage.

[0016] In an embodiment of the present application, the voltage follower includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. The source of the eighth NMOS transistor is connected to the source of the ninth NMOS transistor, and the source of the eighth NMOS transistor is also connected to the drain of the twelfth NMOS transistor. The source of the twelfth NMOS transistor is grounded. The drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the drain of the ninth PMOS transistor is also connected to the gate of the ninth PMOS transistor. The gate of the ninth PMOS transistor is connected to the gate of the eleventh PMOS transistor. The source of the ninth PMOS transistor is connected to the power supply voltage, and the source of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor. The drain of the eleventh PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the eleventh PMOS transistor is also connected to the gate of the ninth NMOS transistor. The source of the eleventh NMOS transistor is grounded. The gate of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor. The source of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor. The drain of the tenth PMOS transistor is connected to the drain of the ninth NMOS transistor. The gate of the tenth PMOS transistor is connected to the gate of the twelfth PMOS transistor, and the gate of the tenth PMOS transistor is also connected to the drain of the tenth PMOS transistor. The source of the tenth PMOS transistor is connected to the source of the twelfth PMOS transistor. The drain of the twelfth PMOS transistor is connected to the drain of the tenth NMOS transistor. The drain of the tenth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the gate of the tenth NMOS transistor is grounded. Wherein, the gate of the twelfth PMOS transistor is connected to the bias voltage. The gate of the eighth NMOS transistor is the positive-phase input terminal of the voltage follower, the gate of the ninth NMOS transistor is the negative-phase input terminal of the voltage follower, and the drain of the eleventh PMOS transistor is the output terminal of the voltage follower.

[0017] In an embodiment of the present application, the sources of the N power transistors are connected to the power supply voltage, the drains of the N power transistors are connected to each other, the drain of the first power transistor is also grounded, and the drain of the Nth power transistor outputs the output voltage.

[0018] In an embodiment of the present application, the low-dropout regulator further includes a low-pass filter module. The low-pass filter module includes a first capacitor and a first resistor. One end of the first resistor is connected to the bias module, the second end of the first resistor is connected to the voltage regulation module, and the second end of the first resistor is grounded after being connected in series with the first capacitor.

[0019] In a second aspect, the present application also provides a power supply, which includes the low-dropout regulator with an off-chip capacitor as described above to stabilize the voltage provided by the power supply.

[0020] The present application provides a low-dropout regulator with an off-chip capacitor and a power supply. The low-dropout regulator includes a bias module, a control voltage generation module, and a voltage regulation module. The input end of the control voltage generation module is connected to a reference voltage, and a stable control voltage is generated by using a negative feedback structure for dynamic adjustment. The voltage regulation module provides a voltage for the output end of the low-dropout regulator based on the control voltage. A plurality of voltage followers and a plurality of power transistors are arranged in the voltage regulation module. The output voltage of the low-dropout regulator is fed back to the voltage followers, so that the plurality of voltage followers control the charging or discharging of the parasitic capacitance in the corresponding power transistors based on the output voltage, making the output voltage of the regulator always in a stable state. The regulator provided by the present application divides the output voltage into multiple parts through the power transistors. The plurality of voltage followers arranged in the voltage regulation module have push-pull capabilities, improving the transient response speed of the regulator and the power supply rejection ratio. It not only improves the reaction efficiency of the regulator but also improves the performance of the regulator, thus providing a more efficient, compact, and responsive regulator for the power management of modern electronic devices.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0023] Figure 1 is a block diagram of a low-dropout regulator with an off-chip capacitor shown in an exemplary embodiment of the present invention;

[0024] Figure 2 is a specific structural diagram of a low-dropout regulator with an off-chip capacitor shown in an exemplary embodiment of the present invention;

[0025] Figure 3 is a specific structural diagram of a voltage follower shown in an exemplary embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of the transient response process of a low-dropout regulator with an off-chip capacitor shown in an exemplary embodiment of the present invention;

[0027] Figure 5It is the power supply rejection ratio curve of a low dropout regulator with off-chip capacitors shown in an exemplary embodiment of the present invention. Detailed implementation manners

[0028] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for explaining the present invention, rather than for limiting the protection scope of the present invention.

[0029] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0030] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0031] A system-on-chip, usually referred to as a system on chip (SoC), is a highly integrated microelectronic device.

[0032] The power supply rejection ratio (PSRR) is a key parameter for measuring the ability of a linear regulator (such as an LDO) to suppress input power supply noise. It represents the ability of the regulator to keep the output voltage stable when there is noise or fluctuation in the input voltage.

[0033] In modern electronic devices, especially for system-on-chip (SoC), power management is the key to ensuring the stable operation of each sub-module. A large number of digital circuits and analog circuits are integrated inside the SoC. The working states of these circuits change continuously with the load demand, resulting in frequent fluctuations in the current demand in the circuit, which raises the requirements for the power management system. In order to meet the requirements of low power consumption and high efficiency, and at the same time provide a stable power supply rail for sensitive analog and mixed-signal circuits, a low dropout linear regulator (LDO) has become a key device for stabilizing the voltage in the circuit.

[0034] As a linear voltage regulator, an LDO can operate with a very small difference between the input voltage and the output voltage. By adjusting the conduction degree of the internal power transistor, it maintains the output voltage at a constant level. However, when faced with rapidly changing load conditions, the small internal capacitors of the LDO alone may not be able to provide sufficient transient response speed and filtering effect. In related technologies, large off-chip capacitors are introduced in many LDO designs. Such capacitors are usually located at the output of the LDO, which can quickly release the stored energy to supplement the load, prevent the output voltage from dropping, and effectively filter out high-frequency noise on the power line, reduce ripple, and ensure the purity of the output voltage. In addition, the external capacitor can relieve the pressure inside the LDO chip to a certain extent, help dissipate heat, and improve the reliability of long-term operation.

[0035] Although the large off-chip capacitor brings significant advantages, the additional capacitor increases the space requirement of the printed circuit board and the cost of the bill of materials (BOM). At the same time, it also increases the assembly complexity and potential failure points; the larger off-chip capacitor will result in a longer start-up time and, in some cases, increase the static power consumption because the LDO needs to charge the off-chip capacitor.

[0036] To solve the above problems, as Figure 1 shown, the present application provides a low-dropout regulator with an off-chip capacitor, including:

[0037] A control voltage generation module, connected to the reference voltage V REF , performs negative feedback on the reference voltage V REF to obtain the control voltage V set ;

[0038] A voltage regulation module, connected to the control voltage generation module, which includes N voltage followers and N power transistors. The control voltage provides voltage for the output end of the low-dropout regulator, and feeds back the output voltage V OUT of the low-dropout regulator to the N voltage followers, so as to use the voltage followers to charge or discharge the parasitic capacitance in the corresponding power transistors based on the output voltage V OUT to stabilize the output voltage V OUT ;

[0039] A bias module, used to provide a bias voltage V bias for the current sources in the control voltage generation module and the voltage regulation module;

[0040] wherein, N≥2, and N is a positive integer.

[0041] Specifically, as Figure 2As shown, the bias module includes a current source, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first PMOS transistor MP1. The input terminal of the current source is connected to the power supply voltage V IN , the output terminal of the current source is connected to the drain of the first NMOS transistor MN1. The drain of the first NMOS transistor MN1 is also connected to the gate of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is also connected to the gate of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is grounded. The source of the first PMOS transistor MP1 is connected to the power supply voltage V IN , the gate of the first PMOS transistor MP1 is connected to the drain of the first PMOS transistor MP1. The drain of the first PMOS transistor MP1 is also connected to the drain of the second NMOS transistor MN2. Among them, the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 output the bias voltage V bias .

[0042] Specifically, as Figure 2 shown, the control voltage generation module includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. The source of the second PMOS transistor MP2 is connected to the power supply voltage V IN , the source of the second PMOS transistor MP2 is also connected to the source of the third PMOS transistor MP3. The gate of the second PMOS transistor MP2 is connected to the gate of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is also connected to the drain of the third PMOS transistor MP3. The drain of the second PMOS transistor MP2 is also connected to the drain of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5. The source of the fifth NMOS transistor MN5 is grounded. The source of the third NMOS transistor MN3 is also connected to the source of the fourth NMOS transistor MN4. The drain of the second PMOS transistor MP2 is also connected to the gate of the fourth PMOS transistor MP4. The drain of the third PMOS transistor MP3 is also connected to the drain of the fourth NMOS transistor MN4. The source of the fourth PMOS transistor MP4 is connected to the source of the second PMOS transistor MP2. The drain of the fourth PMOS transistor MP4 is connected to the gate of the fourth NMOS transistor MN4. The drain of the fourth PMOS transistor MP4 is also connected to the source of the fifth PMOS transistor MP5. The gate of the fifth PMOS transistor MP5 is connected to the drain of the fifth PMOS transistor MP5. The drain of the fifth PMOS transistor MP5 is connected to the drain of the sixth NMOS transistor MN6. The source of the sixth NMOS transistor MN6 is grounded. Among them, the gate of the third NMOS transistor MN3 is connected to the reference voltage V REF , the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to the bias voltage V bias, the gate of the fifth NMOS transistor MN5 is connected to the gate of the first NMOS transistor MN1, the gate of the sixth NMOS transistor MN6 is connected to the gate of the first NMOS transistor MN1, and the gate of the fifth PMOS transistor MP5 outputs the control voltage Vset.

[0043] Specifically, the voltage regulation module includes a voltage inverter, N voltage followers (VF1 to VFN), and N power transistors (MJ1 to MJN). The voltage inverter is connected to the output voltage V OUT and the bias voltage V bias , based on the control voltage V set to provide a voltage equal to the reference voltage V REF for the output terminal of the low-dropout regulator, and to generate the first driving voltage according to the output voltage V OUT and the bias voltage V bias ; the first voltage follower VF1 is connected to the first driving voltage, the non-inverting input terminal of the next voltage follower is connected to the output terminal of the previous voltage follower, and the output terminals of the N voltage followers (VF1 to VFN) are respectively connected to the gates of the N power transistors (MJ1 to MJN). The first driving voltage is followed and output through the N voltage followers (VF1 to VFN) to obtain N second driving voltages, so as to control N corresponding parasitic capacitors to charge or discharge through the N second driving voltages, and to adjust the output voltage V OUT cooperatively output by the drains of the N power transistors (MJ1 to MJN).

[0044] More specifically, as Figure 2 shown, the voltage inverter includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a seventh NMOS transistor MN7. The source of the sixth PMOS transistor MP6 is connected to the drain of the Nth power transistor MJN, the drain of the sixth PMOS transistor MP6 is connected to the drain of the seventh NMOS transistor MN7, the source of the seventh NMOS transistor MN7 is grounded, the drain of the sixth PMOS transistor MP6 is also connected to the gate of the seventh PMOS transistor MP7, the source of the eighth PMOS transistor MP8 is connected to the power supply voltage V IN , the drain of the eighth PMOS transistor MP8 is connected to the source of the seventh PMOS transistor MP7, and the drain of the seventh PMOS transistor MP7 is grounded. Among them, the gate of the sixth PMOS transistor MP6 is connected to the control voltage Vset, the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7 is connected to the bias voltage V bias , the gate of the seventh NMOS transistor MN7 is connected to the gate of the first NMOS transistor MN1, the gate of the eighth PMOS transistor MP8 is connected to the bias voltage V bias , the gate of the eighth PMOS transistor MP8 is connected to the gate of the first PMOS transistor MP1 ( Figure 2(not directly marked in the figure), the drain of the eighth PMOS transistor MP8 outputs the first driving voltage.

[0045] More specifically, as Figure 3 shown, the voltage follower includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. The source of the eighth NMOS transistor MN8 is connected to the source of the ninth NMOS transistor MN9, and the source of the eighth NMOS transistor MN8 is also connected to the drain of the twelfth NMOS transistor MN12. The source of the twelfth NMOS transistor MN12 is grounded. The drain of the eighth NMOS transistor MN8 is connected to the drain of the ninth PMOS transistor MP9. The drain of the ninth PMOS transistor MP9 is also connected to the gate of the ninth PMOS transistor MP9. The gate of the ninth PMOS transistor MP9 is connected to the gate of the eleventh PMOS transistor MP11. The source of the ninth PMOS transistor MP9 is connected to the power supply voltage V IN , the source of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11. The drain of the eleventh PMOS transistor MP11 is connected to the drain of the eleventh NMOS transistor MN11. The drain of the eleventh PMOS transistor MP11 is also connected to the gate of the ninth NMOS transistor MN9. The source of the eleventh NMOS transistor MN11 is grounded. The gate of the eleventh NMOS transistor MN11 is connected to the gate of the tenth NMOS transistor MN10. The source of the tenth PMOS transistor MP10 is connected to the source of the ninth PMOS transistor MP9. The drain of the tenth PMOS transistor MP10 is connected to the drain of the ninth NMOS transistor MN9. The gate of the tenth PMOS transistor MP10 is connected to the gate of the twelfth PMOS transistor MP12. The gate of the tenth PMOS transistor MP10 is also connected to the drain of the tenth PMOS transistor MP10. The source of the tenth PMOS transistor MP10 is connected to the source of the twelfth PMOS transistor MP12. The drain of the twelfth PMOS transistor MP12 is connected to the drain of the tenth NMOS transistor MN10. The drain of the tenth NMOS transistor MN10 is connected to the gate of the tenth NMOS transistor MN10. The gate of the tenth NMOS transistor MN10 is grounded. Among them, the gate of the twelfth PMOS transistor MP12 is connected to the bias voltage V bias , the gate of the twelfth PMOS transistor MP12 is connected to the gate of the first NMOS transistor MN1. The gate of the eighth NMOS transistor MN8 is the positive-phase input terminal of the voltage follower. The gate of the ninth NMOS transistor MN9 is the negative-phase input terminal of the voltage follower. The drain of the eleventh PMOS transistor MP11 is the output terminal of the voltage follower.

[0046] Specifically, as Figure 2 shown, the sources of the N power transistors MJ1 to MJN are connected to the power supply voltage V IN, the drains of N power transistors MJ1 to MJN are interconnected. The drain of the first power transistor MJ1 is also grounded, and the drain of the Nth power transistor MJN outputs the output voltage V OUT .

[0047] Specifically, as Figure 2 shown, the low dropout regulator further includes a low-pass filter module. The low-pass filter module includes a first capacitor C1 and a first resistor R1. The first end of the first resistor R1 is connected to the bias module, the first end of the first resistor R1 is connected to the gate of the first PMOS transistor MP1, the second end of the first resistor R1 is connected to the voltage regulation module, the second end of the first resistor R1 is connected to the gate of the eighth PMOS transistor, and the second end of the first resistor R1 is grounded after being connected in series with the first capacitor C1.

[0048] As Figures 1 - 5 shown, the working principle of the low dropout regulator with an external capacitor provided by this application is as follows:

[0049] As Figure 1 shown, the power supply voltage V IN is generally 1.5V to 1.8V. Usually, 1.5V is used as the power supply voltage of the low dropout regulator. If the load capacitor C L is set to 1 μF, the corresponding load driving current can be 0.1 to 50 mA, so that the output voltage V OUT of the low dropout regulator is stabilized at 1.2V.

[0050] As Figures 1 - 2 shown, the input end of the control voltage generation module is connected to the reference voltage V REF , and the second PMOS transistor MP2, the third PMOS transistor MP3, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the control voltage generation module form an error amplifier. The error amplifier feeds back the drain of the second PMOS transistor (the output end of the error amplifier) and the reference voltage V REF to the non-inverting input end (the gate of the fourth NMOS transistor MN4) of the error amplifier through the fourth PMOS transistor MP4. Through this negative feedback loop, the gate voltage of the fourth NMOS transistor MN4 is equal to the reference voltage V REF . Then, through the current mirror with a ratio of 1:1 formed by the sixth PMOS transistor MP6 in the voltage regulation module and the fifth PMOS transistor MP5 in the control voltage module, the control voltage Vset at the source of the fifth PMOS transistor MP5 is copied to the source of the sixth PMOS transistor MP6 to provide a voltage for the output end of the low dropout regulator under DC conditions, that is, V OUT = V REF .

[0051] As Figure 2As shown, the current source in the bias module provides a reference current I 0 , generating a bias voltage V bais at the gate of the first NMOS transistor MN1. Through the mirror structure of the first NMOS transistor MN1 and the second NMOS transistor MN2, the bias voltage V bais is copied, generating a bias voltage V bais at the gate of the first PMOS transistor MP1, and providing the bias voltage V bais to the gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6 in the control voltage generation module, the gate of the seventh NMOS transistor MN7, and the eighth PMOS transistor MP8 in the voltage regulator module.

[0052] The output voltage V OUT of the low-dropout regulator is monitored in real time through the sixth PMOS transistor MP6 in the voltage inverter, and the monitoring situation is fed back to the non-inverting input terminal of the first voltage follower VF1. The non-inverting input terminal of the first voltage follower VF1 is connected to the input bias voltage V bias . Thus, according to the output voltage V OUT of the low-dropout regulator and the bias voltage V bias , a first driving voltage is generated. The first driving voltage adjusts the second driving voltages output by N voltage followers, and controls the parasitic capacitances of the gates of the corresponding power transistors to charge or discharge through the N second driving voltages, so that the output voltage of the low-dropout regulator is in a stable state.

[0053] Four MOS transistors in the voltage inverter form a local loop. When the output voltage V OUT fluctuates, it can quickly detect the change in the output terminal voltage V OUT , and quickly suppress the undershoot and overshoot phenomena at the output terminal of the low-dropout regulator. If there are 4 voltage followers and 4 power transistors, when the output voltage V OUT drops, the voltage of the sixth PMOS transistor MP6 drops, the voltage of the seventh PMOS transistor MP7 drops, the first driving voltage drops, that is, the voltage at the non-inverting input terminal of the first voltage follower VF1 drops, the output terminal voltages of the 4 voltage followers (VF1~VF4) drop, the 4 second driving voltages drop, controlling the parasitic capacitances of the gates of the 4 power transistors (MJ1~MJ4) to discharge simultaneously, increasing the drain voltages of the 4 power transistors (MJ1~MJ4), so that the output voltage V OUT rises, thus stabilizing the output voltage V OUT .

[0054] When the output voltage V OUTWhen rising, the voltage of the sixth PMOS transistor MP6 rises, the voltage of the seventh PMOS transistor MP7 rises, the first driving voltage rises, that is, the voltage at the non-inverting input terminal of the first voltage follower VF1 rises, the output voltages of the 4 voltage followers (VF1 to VF4) rise, the 4 second driving voltages rise, controlling the gate parasitic capacitances of the 4 power transistors (MJ1 to MJ4) to be charged simultaneously, reducing the drain voltages of the 4 power transistors (MJ1 to MJ4), and the output voltage V OUT drops, thereby stabilizing the output voltage V OUT .

[0055] The power supply ripple in the high-frequency band is filtered out by the low-pass filter module, improving the power supply rejection ratio (PSRR, Power Supply Rejection Ratio) in the high-frequency band.

[0056] As Figure 4 shown,[[]]END]] Figure 4 shows the transient response process of the provided low-dropout regulator with an external capacitor. Dividing the power transistor into four small-sized power transistors MJ1 to MJ4 can effectively reduce the gate parasitic capacitance, and the introduced voltage follower has push-pull ability. The two can improve the transient response speed. Under the conditions of an edge time of 100 ps and a load capacitance of 1 μF, when the load current jumps from 100 μA to 50 mA, the undershoot voltage is 10.1 mV, and the recovery time is only about 1 μs. When the load current jumps from 50 mA to 100 μA, the overshoot voltage is about 8.9 mV, and the recovery time is also less than 10 μs, effectively improving the transient response speed.

[0057] As Figure 5 shown, the power supply rejection ratio (PSRR) of the low-dropout regulator with an external capacitor is better than 30 dB within the full passband, and under the load conditions of 0.1 mA and 50 mA, the power supply rejection ratios (PSRR) at 1 GHz are as high as -105 dB and -93 dB respectively, having good power supply ripple rejection ability.

[0058] This application also provides a power supply, which includes the low-dropout regulator with an external capacitor described above to stabilize the voltage provided by the power supply.

[0059] The present application provides a low-dropout regulator and a power supply with an off-chip capacitor. The low-dropout regulator includes a bias module, a control voltage generation module, a voltage regulation module, and a low-pass filter module. The input end of the control voltage generation module is connected to a reference voltage, and a stable control voltage is generated by dynamically adjusting using a negative feedback structure. A voltage equal to the reference voltage is provided for the output end of the low-dropout regulator through a current mirror structure. Multiple voltage followers and multiple power transistors are arranged in the voltage regulation module. The output voltage of the low-dropout regulator is fed back to the voltage followers, so that the multiple voltage followers control the charging or discharging of the parasitic capacitance in the corresponding power transistors based on the output voltage, making the output voltage of the regulator always in a stable state. The high-frequency power supply ripple of the power supply voltage is also filtered through the low-pass filter module. The regulator provided by the present application divides the power transistors into multiple parts. The voltage followers arranged in the voltage regulation module have push-pull capabilities. The voltage followers output multiple second drive voltages according to the fed-back output voltage, thereby controlling the gates of the power transistors to intelligently perform charging or discharging operations. This not only improves the response speed of the stable output voltage, but also enables on-chip integration, supports a wide load current range, provides a high-precision output voltage, efficiently utilizes the area of the power transistors, achieves a high power supply rejection ratio (PSRR) through the low-pass filter module, maintains high stability and low output ripple, and particularly optimizes thermal management and space utilization.

[0060] The above embodiments merely illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A low voltage dropout regulator with an off-chip capacitor, characterized in that: include: A control voltage generating module is connected to a reference voltage and performs negative feedback on the reference voltage to obtain a control voltage; A voltage stabilizing module, connected to the control voltage generating module, comprising N voltage followers and N power transistors, providing a voltage to an output terminal of a low voltage dropout regulator based on the control voltage, and feeding back the output voltage of the low voltage dropout regulator to the N voltage followers, so as to utilize the voltage followers to control the corresponding parasitic capacitance in the power transistor to charge or discharge based on the output voltage, thereby stabilizing the output voltage; A bias module, used for providing a bias voltage for the control voltage generating module and the current source in the voltage stabilizing module; Wherein, N≥2, and N is a positive integer.

2. The low voltage dropout regulator with off-chip capacitor according to claim 1, characterized in that: The bias module includes a current source, a first NMOS tube, a second NMOS tube and a first PMOS tube, an input end of the current source is connected to a power supply voltage, an output end of the current source is connected to a drain of the first NMOS tube, the drain of the first NMOS tube is also connected to a gate of the first NMOS tube, the gate of the first NMOS tube is also connected to a gate of the second NMOS tube, a source of the first NMOS tube is connected to a source of the second NMOS tube, the source of the first NMOS tube is grounded, a source of the first PMOS tube is connected to the power supply voltage, the gate of the first PMOS tube is connected to a drain of the first PMOS tube, the drain of the first PMOS tube is also connected to a drain of the second NMOS tube, wherein the gate of the first NMOS tube and the gate of the first PMOS tube output the bias voltage.

3. The low voltage dropout regulator with off-chip capacitor according to claim 2, characterized in that: The control voltage generation module includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the source of the second PMOS tube is also connected to the source of the third PMOS tube, the gate of the second PMOS tube is connected to the gate of the third PMOS tube, the gate of the third PMOS tube is also connected to the drain of the third PMOS tube, the drain of the second PMOS tube is also connected to the drain of the third NMOS tube, the source of the third NMOS tube is connected to the drain of the fifth NMOS tube, the source of the fifth NMOS tube is grounded, the source of the third NMOS tube is also connected to the source of the fourth NMOS tube, The drain of the second PMOS tube is also connected to the gate of the fourth PMOS tube, the drain of the third PMOS tube is also connected to the drain of the fourth NMOS tube, the source of the fourth PMOS tube is connected to the source of the second PMOS tube, the drain of the fourth PMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth PMOS tube is also connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the fifth PMOS tube is connected to the drain of the sixth NMOS tube, and the source of the sixth NMOS tube is grounded, wherein the gate of the third NMOS tube is connected to the reference voltage, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are connected to the bias voltage, and the gate of the fifth PMOS tube outputs the control voltage.

4. The low voltage dropout regulator with off-chip capacitor according to claim 2, characterized in that: The voltage stabilizing module comprises a voltage flipper, N voltage followers and N power transistors, wherein the voltage flipper is connected to the output voltage and the bias voltage, provides a voltage equal to the reference voltage to the output end of the low voltage difference regulator based on the control voltage, and generates a first driving voltage according to the output voltage and the bias voltage; The first voltage follower is connected to the first driving voltage, the non-phase input terminal of the next voltage follower is connected to the output terminal of the previous voltage follower, the output terminals of the N voltage followers are connected to the gates of the N power transistors in a one-to-one correspondence, and the first driving voltage is followed and output by the N voltage followers to obtain N second driving voltages, so as to control the charging or discharging of the N corresponding parasitic capacitors through the N second driving voltages, and adjust the output voltage outputted jointly by the drains of the N power transistors.

5. The low voltage dropout regulator with off-chip capacitor according to claim 4, characterized in that: The voltage flipper includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and a seventh NMOS tube, the source of the sixth PMOS tube is connected to the drain of the Nth power transistor, the drain of the sixth PMOS tube is connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is grounded, the drain of the sixth PMOS tube is also connected to the gate of the seventh PMOS tube, the source of the eighth PMOS tube is connected to the power supply voltage, the drain of the eighth PMOS tube is connected to the source of the seventh PMOS tube, and the drain of the seventh PMOS tube is grounded, wherein the gate of the sixth PMOS tube is connected to the control voltage, the gate of the seventh NMOS tube is connected to the bias voltage, the gate of the eighth PMOS tube is connected to the bias voltage, and the drain of the eighth PMOS tube outputs the first driving voltage.

6. The low voltage dropout regulator with off-chip capacitor according to claim 4, characterized in that: The voltage follower includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube, the source of the eighth NMOS tube is connected to the source of the ninth NMOS tube, the source of the eighth NMOS tube is also connected to the drain of the twelfth NMOS tube, the source of the twelfth NMOS tube is grounded, the drain of the eighth NMOS tube is connected to the drain of the ninth PMOS tube, the drain of the ninth PMOS tube is also connected to the gate of the ninth PMOS tube, the gate of the ninth PMOS tube is connected to the gate of the eleventh PMOS tube, the source of the ninth PMOS tube is connected to the power supply voltage, the source of the ninth PMOS tube is connected to the source of the eleventh PMOS tube, the drain of the eleventh PMOS tube is connected to the drain of the eleventh NMOS tube, the drain of the eleventh PMOS tube is also connected to the gate of the ninth NMOS tube, and the gate of the eleventh PMOS tube is connected to the gate of the eleventh PMOS tube. The source of the NMOS tube is grounded, the gate of the eleventh NMOS tube is connected to the gate of the tenth NMOS tube, the source of the tenth PMOS tube is connected to the source of the ninth PMOS tube, the drain of the tenth PMOS tube is connected to the drain of the ninth NMOS tube, the gate of the tenth PMOS tube is connected to the gate of the twelfth PMOS tube, the gate of the tenth PMOS tube is also connected to the drain of the tenth PMOS tube, the source of the tenth PMOS tube is connected to the source of the twelfth PMOS tube, the drain of the twelfth PMOS tube is connected to the drain of the tenth NMOS tube, the drain of the tenth NMOS tube is connected to the gate of the tenth NMOS tube, and the gate of the tenth NMOS tube is grounded, wherein the gate of the twelfth PMOS tube is connected to the bias voltage, the gate of the eighth NMOS tube is the positive phase input terminal of the voltage follower, the gate of the ninth NMOS tube is the negative phase input terminal of the voltage follower, and the drain of the eleventh PMOS tube is the output terminal of the voltage follower.

7. The low voltage dropout regulator with off-chip capacitor according to claim 4, characterized in that: The sources of the N power transistors are connected to the power supply voltage, the drains of the N power transistors are connected to each other, the drain of the first power transistor is also grounded, and the drain of the Nth power transistor outputs the output voltage.

8. The low voltage dropout regulator with off-chip capacitor according to claim 1, characterized in that: The low voltage difference regulator also includes a low-pass filter module, which includes a first capacitor and a first resistor, one end of the first resistor is connected to the bias module, the second end of the first resistor is connected to the voltage stabilization module, and the second end of the first resistor is connected to the ground via the first capacitor in series.

9. A power supply, characterized in that: The power supply comprises a low voltage dropout regulator with an off-chip capacitor as claimed in any one of claims 1 to 8, so as to stabilize the voltage provided by the power supply.

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