Electronic device

Abstract

An electronic device includes a display layer and an anti-reflection layer disposed on the display layer. The display layer includes a first light emitting element having a first light emitting region, a first sensing element adjacent to the first light emitting element and having a first sensing region, a second light emitting element having a second light emitting region, and a second sensing element adjacent to the second light emitting element and having a second sensing region. The area of the first sensing region is larger than that of the second sensing region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0178308, filed with the Korean Intellectual Property Office on December 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to an electronic device, and more particularly, to an electronic device including a light - emitting element and a light - sensing element. Background art

[0004] An electronic device can combine a display panel for showing data to a user and a touch sensor for recording the user's touch, thereby providing an efficient and intuitive input and output method. Recent electronic devices can additionally be capable of sensing biometric information provided by the user, etc. Examples of methods for identifying user information include a capacitive method of sensing a change in capacitance formed between electrodes, an optical method of sensing input light using an optical sensor, or an ultrasonic method, etc. Summary of the invention

[0005] An electronic device includes a display layer and an anti - reflection layer disposed on the display layer. The display layer includes: a first light - emitting element having a first light - emitting region, a first sensing element adjacent to the first light - emitting element in a first direction and having a first sensing region, a second light - emitting element having a second light - emitting region, and a second sensing element adjacent to the second light - emitting element in the first direction and having a second sensing region. In a plane defined by the first direction and a second direction intersecting the first direction, the area of the first sensing region is larger than the area of the second sensing region.

[0006] The area of the first light - emitting region may be smaller than the area of the second light - emitting region.

[0007] The first light - emitting element may include a first pixel electrode, the second light - emitting element may include a second pixel electrode, the first sensing element may include a first sensor electrode, and the second sensing element may include a second sensor electrode. The display layer may further include a pixel defining film that partially covers the first pixel electrode, the second pixel electrode, the first sensor electrode, and the second sensor electrode, and may include a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, a third opening overlapping the first sensor electrode, and a fourth opening overlapping the second sensor electrode.

[0008] In a plan view, the size of the first opening may be smaller than the size of the second opening.

[0009] In a plan view, the size of the third opening may be larger than the size of the fourth opening.

[0010] The gap between the first opening and the third opening can be substantially the same as the gap between the second opening and the fourth opening.

[0011] The first light-emitting region can be defined by the first opening, the second light-emitting region can be defined by the second opening, the first sensing region can be defined by the third opening, and the second sensing region can be defined by the fourth opening.

[0012] The antireflection layer can include a separation layer that includes a first separation opening, a second separation opening, a third separation opening, and a fourth separation opening that overlap the first opening, the second opening, the third opening, and the fourth opening in a one-to-one correspondence.

[0013] The difference between the maximum width of the first separation opening and the maximum width of the first opening can be greater than the difference between the maximum width of the second separation opening and the maximum width of the second opening.

[0014] The distance between the first separation opening and the third separation opening can be less than the distance between the second separation opening and the fourth separation opening.

[0015] The antireflection layer can further include: a first color filter covering the first separation opening; and a second color filter covering the second separation opening, and the thickness of the first color filter can be less than the thickness of the second color filter.

[0016] The first light-emitting element and the second light-emitting element can output light of the same color.

[0017] The distance between the center of the first light-emitting region and the center of the first sensing region can be substantially the same as the distance between the center of the second light-emitting region and the center of the second sensing region.

[0018] The display layer can further include: a sensor driving circuit electrically connected to the first sensing element, and the second sensing element can be a dummy element.

[0019] An electronic device includes a display layer and an antireflection layer disposed on the display layer. The display layer includes: a first pixel electrode; a second pixel electrode; a first sensor electrode adjacent to the first pixel electrode in a first direction; a second sensor electrode adjacent to the second pixel electrode in the first direction; and a pixel defining film that partially covers the first pixel electrode, the second pixel electrode, the first sensor electrode, and the second sensor electrode, and includes a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, a third opening overlapping the first sensor electrode, and a fourth opening overlapping the second sensor electrode. In a plane defined by the first direction and a second direction intersecting the first direction, the size of the third opening is larger than the size of the fourth opening.

[0020] In a plan view, the size of the first opening may be smaller than the size of the second opening.

[0021] The gap between the first opening and the third opening may be substantially the same as the gap between the second opening and the fourth opening.

[0022] The antireflection layer may include a separation layer including first, second, third, and fourth separation openings that overlap the first, second, third, and fourth openings in a one-to-one correspondence.

[0023] The difference between the maximum width of the first separation opening and the maximum width of the first opening may be greater than the difference between the maximum width of the second separation opening and the maximum width of the second opening, and the distance between the first separation opening and the third separation opening may be less than the distance between the second separation opening and the fourth separation opening.

[0024] The antireflection layer may further include: a first color filter covering the first separation opening; and a second color filter covering the second separation opening, and the thickness of the first color filter may be less than the thickness of the second color filter.

[0025] An electronic device includes: a display panel including a first light-emitting element having a first light-emitting region, a first sensing element adjacent to the first light-emitting element in a first direction and having a first sensing region, a second light-emitting element having a second light-emitting region, and a second sensing element adjacent to the second light-emitting element in the first direction and having a second sensing region. In a plane defined by the first direction and a second direction intersecting the first direction, the area of the first sensing region may be greater than the area of the second sensing region, and a fingerprint or external illumination is sensed using the first sensing element.

[0026] The brightness of an image displayed on the display panel may be adjusted according to external illumination. Description of the Drawings

[0027] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0028] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0029] Figure 2 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 3 is a block diagram illustrating a display layer and a display driver according to an embodiment of the present disclosure.

[0031] Figure 4 is an equivalent circuit diagram of a pixel and a sensor according to an embodiment of the present disclosure.

[0032] Figure 5A It is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0033] Figure 5B It is a schematic cross-sectional view of a part of a display layer according to an embodiment of the present disclosure.

[0034] Figure 6A It is a plan view illustrating components of an electronic device according to an embodiment of the present disclosure.

[0035] Figure 6B It is a plan view illustrating components of an electronic device according to an embodiment of the present disclosure.

[0036] Figure 7A It is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0037] Figure 7B It is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0038] Figure 8 It is a plan view of components of an electronic device according to an embodiment of the present disclosure.

[0039] Figure 9 It is a plan view illustrating components of an electronic device according to an embodiment of the present disclosure.

[0040] Figure 10 It is a block diagram illustrating a display layer and a display driver according to an embodiment of the present disclosure.

[0041] Figure 11 It is a plan view of components of an electronic device according to an embodiment of the present disclosure. Detailed Description

[0042] In this specification, the expression that a first component (or region, layer, part, portion, etc.) is "on" a second component, "connected" or "coupled to" the second component means that the first component is directly on the second component, directly connected to or directly coupled to the second component, or means that a third component is disposed between the first component and the second component.

[0043] Throughout the specification and the drawings, the same reference numerals may refer to the same components. The expression "and / or" includes one or more combinations that the associated components can define.

[0044] Although terms such as "first", "second", etc. may be used to describe various components, the components do not have to be limited by the terms. The terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component, without departing from the scope of the rights of the present disclosure. Singular expressions include plural expressions unless clearly indicated otherwise in the context.

[0045] In addition, terms such as "beneath", "below", "above", "over", etc. may be used to describe the relevance of components illustrated in the drawings. Conceptually opposite terms are described based on the directions illustrated in the drawings.

[0046] It will be understood that terms such as "comprising", "including", "having", etc. specify the presence of the features, quantities, steps, operations, elements or components described in this specification, or combinations thereof, and do not preclude the presence or addition of one or more other features, quantities, steps, operations, elements or components, or combinations thereof.

[0047] The terms "part" and "unit" mean software components or hardware components that perform specific functions. Hardware components may include, for example, field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Software components may refer to executable code and / or data used by the executable code in an addressable storage medium. Thus, software components may be, for example, object-oriented software components, class components, and task components, and may include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0048] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0049] Figure 1 is a perspective view of an electronic device 1000 according to an embodiment of the present disclosure.

[0050] Referring to Figure 1 , the electronic device 1000 may be a device activated according to an electrical signal. For example, the electronic device 1000 may include a mobile phone (such as a foldable mobile phone), a laptop computer, a television, a tablet computer, a car navigation system, a portable game console, or a wearable device, but the present disclosure is not necessarily limited thereto. In Figure 1 an example in which the electronic device 1000 is a mobile phone is illustrated.

[0051] An active area 1000A and a peripheral area 1000NA may be defined in an electronic device 1000. The electronic device 1000 may display an image through the active area 1000A. The active area 1000A may include a surface defined by a first direction DR1 and a second direction DR2. The peripheral area 1000NA may surround the active area 1000A on two or more sides of the active area 1000A. In an embodiment of the present disclosure, the peripheral area 1000NA may be omitted.

[0052] A thickness direction of the electronic device 1000 may be a third direction DR3 that intersects the first direction DR1 and the second direction DR2. Accordingly, a front surface (or an upper surface) and a rear surface (or a lower surface) of components constituting the electronic device 1000 may be defined based on the third direction DR3.

[0053] Figure 2 is a block diagram of an electronic device 1000 according to an embodiment of the present disclosure.

[0054] Reference Figure 2 , the electronic device 1000 may include a display panel DP, a display driver 100C, a sensor driver 200C, and a main driver 1000C. The display panel DP may include a display layer 100 and a sensor layer 200.

[0055] The display layer 100 may be a component that substantially generates an image. The display layer 100 may be a light-emitting display layer. For example, the display layer 100 may be an organic light-emitting diode (OLED) display layer, an inorganic light-emitting display layer, an organic-inorganic light-emitting display layer, a quantum dot display layer, a micro light-emitting diode (LED) display layer, or a nano LED display layer. In addition, the display layer 100 may include a sensor that senses or responds to light reflected by a user fingerprint 2000fp.

[0056] The sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may sense an external input 2000 applied from the outside (e.g., from a surface 1000SF of the electronic device 1000). The external input 2000 may include all input means capable of providing a change in capacitance. For example, in addition to a passive type input unit such as a user's body, the sensor layer 200 may even sense an input applied through an active type input unit that provides a driving signal.

[0057] The main driver 1000C may control an overall operation of the electronic device 1000. For example, the main driver 1000C may control operations of the display driver 100C and the sensor driver 200C. The main driver 1000C may include at least one microprocessor and may further include a graphics processor. The main driver 1000C may be referred to as an application processor, a central processing unit, or a main processor.

[0058] The display driver 100C can drive the display layer 100. The display driver 100C can receive image data RGB and a control signal D-CS from the main driver 1000C. The control signal D-CS can include various signals. For example, the control signal D-CS can include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal, etc. The display driver 100C can generate a vertical synchronization signal and a horizontal synchronization signal for controlling the timing of supplying signals to the display layer 100 based on the control signal D-CS.

[0059] The sensor driver 200C can drive the sensor layer 200. The sensor driver 200C can receive a control signal I-CS from the main driver 1000C. The control signal I-CS can include a mode determination signal for determining the driving mode of the sensor driver 200C and a clock signal.

[0060] The sensor driver 200C can calculate information about the input coordinates based on the signals received from the sensor layer 200, and can provide a coordinate signal I-SS having information about the coordinates to the main driver 1000C. The main driver 1000C performs an operation corresponding to the user's input based on the coordinate signal I-SS. For example, the main driver 1000C can drive the display driver 100C such that a new application image is displayed on the display layer 100.

[0061] Figure 3 is a block diagram illustrating the display layer 100 and the display driver 100C according to an embodiment of the present disclosure.

[0062] Reference Figure 2 and Figure 3 and, the display driver 100C can include a driving controller 100C1, a data driver 100C2, a scan driver 100C3, a light-emitting driver 100C4, a voltage generator 100C5, and a sensor controller 100C6.

[0063] The display layer 100 can include a display area DA corresponding to the active area 1000A (see Figure 1 ) and a non-display area NDA corresponding to the peripheral area 1000NA (see Figure 1 ). The display area DA can include a fingerprint sensing area FSA and a fingerprint non-sensing area NFSA.

[0064] The display layer 100 may include a plurality of pixels PX disposed in the display area DA, a plurality of sensors FX disposed in the fingerprint sensing area FSA, and a plurality of dummy sensors FX-d disposed in the fingerprint non-sensing area NFSA. The display layer 100 may further include initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. Herein, m, n, and h are integers greater than zero.

[0065] The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn extend in the second direction DR2. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn are spaced apart from each other in the first direction DR1. The data lines DL1 to DLm and the readout lines RL1 to RLh extend in the first direction DR1 and are spaced apart from each other in the second direction DR2.

[0066] The plurality of pixels PX are electrically connected to the initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, the emission control lines EML1 to EMLn, and the data lines DL1 to DLm. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX does not have to be limited thereto and may be changed.

[0067] The plurality of sensors FX are respectively electrically connected to the readout lines RL1 to RLh. One sensor FX may be electrically connected to one scan line, for example, one of the write scan lines SWL1 to SWLn. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may be changed. As an example of the present disclosure, the number of the readout lines RL1 to RLh may correspond to half of the number of the data lines DL1 to DLm. However, the present disclosure is not limited thereto. Alternatively, the number of the readout lines RL1 to RLh may correspond to one-fourth or one-eighth of the number of the data lines DL1 to DLm.

[0068] In an embodiment of the present disclosure, dummy sensors FX-d may be provided in a fingerprint non-sensing area NFSA to reduce a difference between an amount of external light reflected in a fingerprint sensing area FSA and an amount of external light reflected in the fingerprint non-sensing area NFSA. The dummy sensors FX-d may be sensors that are not actually operated to obtain fingerprint information of a user. For example, each of the dummy sensors FX-d may include dummy elements and may not include a dummy circuit for driving the dummy elements. However, this is an example, and the present disclosure is not necessarily specifically limited thereto. For example, each of the dummy sensors FX-d includes dummy elements and a dummy circuit, and the dummy circuit may not be actually operated.

[0069] The driving controller 100C1 receives image data RGB and a control signal D-CS. The driving controller 100C1 generates an image data signal DATA by converting a data format of the image data RGB in accordance with a specification of an interface with the data driver 100C2. The driving controller 100C1 outputs a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal RCS.

[0070] The data driver 100C2 receives the third control signal DCS and the image data signal DATA from the driving controller 100C1. The data driver 100C2 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, which will be described below. The data signal refers to an analog voltage corresponding to a gray value of the image data signal DATA.

[0071] The scan driver 100C3 receives the first control signal SCS from the driving controller 100C1. The scan driver 100C3 may output scan signals to scan lines in response to the first control signal SCS. For example, in response to the first control signal SCS, the scan driver 100C3 outputs initialization scan signals to initialization scan lines SIL1 to SILn and may output compensation scan signals to compensation scan lines SCL1 to SCLn. In addition, in response to the first control signal SCS, the scan driver 100C3 may output write scan signals to write scan lines SWL1 to SWLn and may output black scan signals to black scan lines SBL1 to SBLn.

[0072] The scan driver 100C3 may be disposed in a non-display area NDA of the display layer 100. However, the present disclosure is not necessarily specifically limited thereto. For example, at least a part of the scan driver 100C3 may be disposed in the display area DA.

[0073] The light-emitting driver 100C4 may be disposed in the non-display area NDA of the display layer 100. The light-emitting driver 100C4 receives a second control signal ECS from the driving controller 100C1. The light-emitting driver 100C4 may output a light-emitting control signal to the light-emitting control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, the scan driver 100C3 may be connected to the light-emitting control lines EML1 to EMLn. In this case, the light-emitting driver 100C4 may be omitted, and the scan driver 100C3 may output a light-emitting control signal to the light-emitting control lines EML1 to EMLn.

[0074] The voltage generator 100C5 generates voltages required for the operation of the display layer 100. In an embodiment, the voltage generator 100C5 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a reset voltage Vrst.

[0075] The sensor controller 100C6 receives a fourth control signal RCS from the driving controller 100C1.

[0076] The sensor controller 100C6 may receive sensor signals from the readout lines RL1 to RLh in response to the fourth control signal RCS. The sensor controller 100C6 may process the sensor signals received from the readout lines RL1 to RLh, and provide the processed sensor signal S_FS to the driving controller 100C1.

[0077] Each of the sensors FX may receive light during a predetermined light reception period. In an embodiment of the present disclosure, the sensor FX may sense a fingerprint. In an embodiment of the present disclosure, the sensor FX may be used to sense external illumination as well as a fingerprint. For example, when using the sensor FX to sense illumination, a wider range of illumination can be sensed compared to a case where an illumination sensor is disposed in a specific area. In addition, by adjusting the brightness of an image displayed on the display panel DP (see Figure 2 )(e.g., the display layer 100) according to the sensed illumination, the usability and power consumption efficiency of the electronic device 1000 can be improved.

[0078] Figure 4 is an equivalent circuit diagram of the pixel PXij and the sensor FXdj according to an embodiment of the present disclosure.

[0079] Figure 4 illustrates a plurality of pixels PX (see Figure 3)The equivalent circuit diagram of one pixel PXij among them. In this article, i is an integer greater than zero and less than m or equal to m, and j is an integer greater than zero and less than n or equal to n. Without describing the components in detail with reference to this drawing, it can be understood that the component is at least similar to the corresponding component described elsewhere within the present disclosure. For example, multiple pixels PX may have the same circuit structure as pixel PXij. Additionally, Figure 4 is Figure 3 the equivalent circuit diagram of one sensor FXdj among the multiple sensors FX illustrated in

[0080] Referring to Figure 3 and Figure 4 , pixel PXij is connected to the i-th data line DLi among data lines DL1 to DLm, the j-th initialization scan line SILj among initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among write scan lines SWL1 to SWLn, the j-th black scan line SBLj among black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among emission control lines EML1 to EMLn.

[0081] Pixel PXij includes a light-emitting element ED and a pixel driving circuit PDC. The light-emitting element ED may be a light-emitting diode (LED). As an example of the present disclosure, the light-emitting element ED may be an organic light-emitting diode including an organic light-emitting layer, but the present disclosure is not necessarily specifically limited thereto.

[0082] The pixel driving circuit PDC includes first to fifth transistors T1, T2, T3, T4, and T5, a first emission control transistor ET1 and a second emission control transistor ET2, and a capacitor Cst.

[0083] At least one of the first to fifth transistors T1, T2, T3, T4, and T5 and the first emission control transistor ET1 and the second emission control transistor ET2 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to fifth transistors T1, T2, T3, T4, and T5 and the first emission control transistor ET1 and the second emission control transistor ET2 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, and the fifth transistor T5 and the first emission control transistor ET1 and the second emission control transistor ET2 may be LTPS transistors.

[0084] For example, directly affecting the electronic device 1000 (seeFigure 1 ) The first transistor T1 for the brightness includes a highly reliable polysilicon semiconductor layer, and thus, a high-resolution display device can be achieved. Since the oxide semiconductor has a high carrier mobility and a low leakage current, even when the driving time is long, the voltage drop is not large. For example, since even during low-frequency driving, the color change of the image due to the voltage drop is not large, low-frequency driving can be performed. In this way, since the oxide semiconductor has a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the third electrode (or gate electrode) of the first transistor T1 can be an oxide semiconductor transistor, and thus, the leakage current that may flow to the gate electrode can be prevented, and at the same time, the power consumption can be reduced.

[0085] Some of the first to fifth transistors T1, T2, T3, T4, and T5 and the first light-emitting control transistor ET1 and the second light-emitting control transistor ET2 can be P-type transistors, and the other transistors among them can be N-type transistors. For example, the first transistor T1, the second transistor T2, and the fifth transistor T5 and the first light-emitting control transistor ET1 and the second light-emitting control transistor ET2 can be P-type transistors, and the third transistor T3 and the fourth transistor T4 can be N-type transistors.

[0086] The configuration of the pixel driving circuit PDC according to the present disclosure does not have to be limited to Figure 4 the embodiment illustrated therein. Figure 4 The pixel driving circuit PDC illustrated therein is only an example, and the configuration of the pixel driving circuit PDC can be modified and implemented. For example, each of the first to fifth transistors T1, T2, T3, T4, and T5 and the first light-emitting control transistor ET1 and the second light-emitting control transistor ET2 can be a P-type transistor or an N-type transistor.

[0087] The j-th initialization scan line SILj, the j-th compensation scan line SCLj, the j-th write scan line SWLj, the j-th black scan line SBLj, and the j-th light-emitting control line EMLj can respectively transmit the j-th initialization scan signal SIj, the j-th compensation scan signal SCj, the j-th write scan signal SWj, the j-th black scan signal SBj, and the j-th light-emitting control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have a voltage level corresponding to the image data RGB (see Figure 2 ) input to the electronic device 1000 (see Figure 2 ).

[0088] The first driving voltage line VL1 and the second driving voltage line VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first initialization voltage line VL3 and the second initialization voltage line VL4 can transmit the first initialization voltage VINT1 and the second initialization voltage VINT2 to the pixel PXij, respectively.

[0089] The first transistor T1 is connected between the first driving voltage line VL1 that receives the first driving voltage ELVDD and the light-emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the first light-emitting control transistor ET1, a second electrode connected to the light-emitting element ED via the second light-emitting control transistor ET2, and a third electrode (e.g., gate electrode) connected to one end (e.g., the first node N1) of the capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and supply the driving current Id to the light-emitting element ED.

[0090] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 can be turned on according to the write scan signal SWj transmitted through the j-th write scan line SWLj, and can transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0091] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 can be turned on according to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, can connect the third electrode and the second electrode of the first transistor T1 to each other, and thus, can diode-connect the first transistor T1.

[0092] The fourth transistor T4 is connected between a first initialization voltage line VL3 to which a first initialization voltage VINT1 is applied and a first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT1 is transmitted thereto, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line SILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal SIj transmitted through the j-th initialization scan line SILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT1 to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0093] The first light emission control transistor ET1 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line EMLj.

[0094] The second light emission control transistor ET2 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second electrode of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line EMLj.

[0095] The first light emission control transistor ET1 and the second light emission control transistor ET2 are simultaneously turned on depending on the j-th light emission control signal EMj transmitted through the j-th light emission control line EMLj. The first driving voltage ELVDD applied through the turned-on first light emission control transistor ET1 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED.

[0096] The fifth transistor T5 includes a first electrode connected to a second initialization voltage line VL4 to which a second initialization voltage VINT2 is transmitted thereto, a second electrode connected to the second electrode of the second light emission control transistor ET2, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The voltage level of the second initialization voltage VINT2 can be less than or equal to the voltage level of the first initialization voltage VINT1. The second electrode of the second light emission control transistor ET2, the second electrode of the fifth transistor T5, and the light emitting element ED can be electrically connected to a second node N2.

[0097] As described above, one end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting element ED may be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the voltage level of the first driving voltage ELVDD.

[0098] The sensor FXdj is connected to the d-th readout line RLd among the readout lines RL1 to RLh, the j-th write scan line SWLj (or referred to as an output control line), and the reset control line RCL.

[0099] The sensor FXdj includes a sensing element OPD (or referred to as an optical sensing element) and a sensor driving circuit O_SD.

[0100] The sensing element OPD may be a photodiode. As an example of the present disclosure, the sensing element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. The first electrode AE-S of the sensing element OPD (see Figure 5A ) may be connected to the first sensing node SN1, and the second electrode CE of the sensing element OPD (see Figure 5A ) may be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. Figure 4 The figure shows that the sensor FXdj includes one sensing element OPD, but the present disclosure is not necessarily limited thereto. For example, the sensor FXdj may include z sensing elements connected in parallel with each other. Here, z may be an integer of 2 or more. The first electrode AE-S may be referred to as the sensor electrode AE-S.

[0101] The sensor driving circuit O_SD includes three transistors ST1, ST2, and ST3. The three transistors ST1, ST2, and ST3 may include a reset transistor ST1, an amplifying transistor ST2, and an output transistor ST3. At least one of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. As an example of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, the present disclosure is not necessarily limited thereto. For example, at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS transistor.

[0102] In addition, some of the reset transistor ST1, the amplification transistor ST2, and the output transistor ST3 may be P-type transistors, and the other transistors among them may be N-type transistors. As an example of the present disclosure, the amplification transistor ST2 and the output transistor ST3 may be P-type transistors, and the reset transistor ST1 may be an N-type transistor. However, the present disclosure is not necessarily limited thereto. For example, all of the transistors ST1, ST2, and ST3 may be N-type transistors or P-type transistors.

[0103] The circuit configuration of the sensor driving circuit O_SD according to the present disclosure is not necessarily limited to Figure 4 . Figure 4 The sensor driving circuit O_SD illustrated in is an example, and the configuration of the sensor driving circuit O_SD may be modified and implemented.

[0104] The reset transistor ST1 includes a first electrode connected to the third initialization voltage line VL5 and receiving the reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving the reset control signal RST. The reset transistor ST1 can reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal RST. The reset control signal RST may be a signal provided through the reset control line RCL.

[0105] The amplification transistor ST2 includes a first electrode receiving the sense driving voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplification transistor ST2 can be turned on according to the potential of the first sensing node SN1 to apply the sense driving voltage SLVD to the second sensing node SN2. As an example of the present disclosure, the sense driving voltage SLVD may correspond to one of the first driving voltage ELVDD and the first initialization voltage VINT1 and the second initialization voltage VINT2.

[0106] When the sense driving voltage SLVD corresponds to the first driving voltage ELVDD, the first electrode of the amplification transistor ST2 may be electrically connected to the first driving voltage line VL1. When the sense driving voltage SLVD corresponds to the first initialization voltage VINT1, the first electrode of the amplification transistor ST2 may be electrically connected to the first initialization voltage line VL3. When the sense driving voltage SLVD corresponds to the second initialization voltage VINT2, the first electrode of the amplification transistor ST2 may be electrically connected to the second initialization voltage line VL4.

[0107] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the d-th readout line RLd, and a third electrode receiving an output control signal. The output transistor ST3 can transmit the sensing signal FSd to the d-th readout line RLd in response to the output control signal. The output control signal can be the j-th write scan signal SWj (or referred to as the j-th output control signal) supplied through the j-th write scan line SWLj. For example, the output transistor ST3 can receive the j-th write scan signal SWj supplied from the j-th write scan line SWLj as the output control signal.

[0108] The reset period can be defined as the activation period (e.g., high-level period) of the reset control line RCL. When the reset control signal RST with a high level is supplied through the reset control line RCL, the reset transistor ST1 is turned on. Alternatively, when the reset transistor ST1 is a P-channel metal oxide semiconductor (PMOS) transistor, during the reset period, the reset control signal RST with a low level can be supplied to the reset control line RCL. During the reset period, the first sensing node SN1 can be reset to a potential corresponding to the reset voltage Vrst. As an example of the present disclosure, the reset voltage Vrst can have a voltage level lower than the voltage level of the second driving voltage ELVSS.

[0109] The sensing element OPD of the sensor FXdj can be exposed to light during the light emission period of the light emitting element ED. During the reset period, the voltage of the first sensing node SN1 is maintained at the reset voltage Vrst, and as the sensing element OPD is exposed to light, the voltage of the first sensing node SN1 can gradually shift to the second driving voltage ELVSS. The amplifying transistor ST2 can be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the first sensing node SN1 input to the third electrode of the amplifying transistor ST2.

[0110] In the readout period, the j-th write scan signal SWj with a low level is supplied to the output transistor ST3 through the j-th write scan line SWLj. When the output transistor ST3 is turned on in response to the j-th write scan signal SWj with a low level, the sensing signal FSd corresponding to the current flowing through the amplifying transistor ST2 can be output to the d-th readout line RLd.

[0111] Figure 5A is a cross-sectional view of the electronic device 1000 according to an embodiment of the present disclosure. Figure 5B is a schematic cross-sectional view of a part of the display layer 100 according to an embodiment of the present disclosure.

[0112] Reference Figure 5A, the display layer 100 may include a base layer BL, a circuit layer DP_CL disposed on the base layer BL, an element layer DP_ED, and a packaging layer TFE.

[0113] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and / or hafnium oxide. The inorganic layer may be formed as a multi-layer. The multi-layer inorganic layer may constitute the barrier layers BR1 and BR2 and / or the buffer layer BFL described below. The barrier layers BR1 and BR2 and the buffer layer BFL may be selectively arranged.

[0114] The barrier layers BR1 and BR2 prevent foreign substances from being introduced from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0115] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. A first post-metal layer BMC1 may be disposed between the first barrier layer BR1 and the second barrier layer BR2. In an embodiment of the present disclosure, the first post-metal layer BMC1 may be omitted. The first post-metal layer BMC1 may be referred to as a first back metal layer or a first lower metal layer.

[0116] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL increases the coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0117] A first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and polycrystalline silicon, etc. For example, the first semiconductor pattern may include low-temperature polycrystalline silicon.

[0118] Figure 5A The portion of the first semiconductor pattern disposed on the buffer layer BFL is illustrated, and another portion of the first semiconductor pattern may be disposed in another region. The first semiconductor pattern may be provided throughout the pixels according to a specific rule. Depending on whether the first semiconductor pattern is doped, the first semiconductor pattern may have different electrical characteristics. The first semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or may be a region doped with a lower concentration than that of the first region.

[0119] The conductivity of the first region can be greater than that of the second region, and the first region can substantially serve as an electrode or a signal line. The second region can substantially correspond to the active region (or channel) of the transistor. For example, a part of the semiconductor pattern can be the active region of the transistor, another part of the semiconductor pattern can be the source region or the drain region of the transistor, and still another part of the semiconductor pattern can be a connecting electrode or a connecting signal line.

[0120] The first electrode S1, the active region A1, and the second electrode D1 of the first transistor T1 are formed from the first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the active region A1 in opposite directions in a cross-section.

[0121] Figure 5A A part of the connecting signal line CSL formed from the first semiconductor pattern is illustrated. In a plan view, the connecting signal line CSL can be connected to the second electrode of the fifth transistor T5 (see Figure 4 ).

[0122] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can overlap with a plurality of pixels in common and can cover the first semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer and can have a single-layer structure or a multi-layer structure. The first insulating layer 10 can include alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and / or hafnium oxide. In an embodiment, the first insulating layer 10 can be a single-layer silicon oxide layer. The insulating layers of the circuit layer DP_CL described below and the first insulating layer 10 can be an inorganic layer and / or an organic layer and can have a single-layer structure or a multi-layer structure. The inorganic layer can include at least one of the materials described above, but the present disclosure is not necessarily limited thereto.

[0123] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 of the first transistor T1 can be a part of a metal pattern. The third electrode G1 of the first transistor T1 overlaps with the active region A1 of the first transistor T1. The third electrode G1 of the first transistor T1 can be used as a mask in the process of doping the first semiconductor pattern. The third electrode G1 can include titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), etc., but the present disclosure is not necessarily specifically limited thereto.

[0124] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include silicon oxide, silicon nitride, and / or silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0125] The upper electrode UE and the second post-metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the third electrode G1. The upper electrode UE may be part of a metal pattern. A part of the third electrode G1 and the upper electrode UE overlapping with this part of the third electrode G1 may define a capacitor Cst (see Figure 4 ). In an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and the upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0126] The second post-metal layer BMC2 may correspond to the lower part of, for example, the third transistor T3 of an oxide thin film transistor. The second post-metal layer BMC2 may receive a constant voltage or signal.

[0127] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second post-metal layer BMC2. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0128] A second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguishable depending on whether the metal oxide is reduced. A region where the metal oxide is reduced (hereinafter referred to as a reduced region) has a higher conductivity than a region where the metal oxide is not reduced (hereinafter referred to as a non-reduced region). The reduced region is substantially used as a source region / drain region of a transistor or as a signal line. The non-reduced region substantially corresponds to the active region (or semiconductor region or channel) of the transistor. For example, a part of the semiconductor pattern may be the active region of a transistor, another part of the semiconductor pattern may be the source region or drain region of the transistor, and still another part of the semiconductor pattern may be a connection electrode or a connection signal line.

[0129] The first electrode S3, the active region A3, and the second electrode D3 of the third transistor T3 are formed from the second semiconductor pattern. The first electrode S3 and the second electrode D3 include a metal reduced from a metal oxide semiconductor. The first electrode S3 and the second electrode D3 may extend from the active region A3 in opposite directions in a cross-section.

[0130] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap with a plurality of pixels in common and may cover the second semiconductor pattern. The fourth insulating layer 40 may include alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and / or hafnium oxide.

[0131] The third electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The third electrode G3 may be part of a metal pattern. The third electrode G3 of the third transistor T3 overlaps with the active region A3 of the third transistor T3. In the process of reducing the second semiconductor pattern, the third electrode G3 may be used as a mask. In an embodiment of the present disclosure, the fourth insulating layer 40 may be replaced with an insulating pattern.

[0132] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the third electrode G3. The fifth insulating layer 50 may be an organic layer.

[0133] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating through the first to fifth insulating layers 10, 20, 30, 40, and 50.

[0134] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include common polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), and polystyrene (PS), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and blends thereof, but the present disclosure is not necessarily specifically limited thereto.

[0135] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating through the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 to cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0136] The circuit layer DP_CL may further include a sensor driving circuit O_SD (see Figure 4) For ease of description, the reset transistor ST1 in the sensor driving circuit O_SD is illustrated. The first electrode STS1, the active region STA1, and the second electrode STD1 of the reset transistor ST1 are formed from the second semiconductor pattern. The first electrode STS1 and the second electrode STD1 include metals reduced from metal oxides. The fourth insulating layer 40 is provided to cover the first electrode STS1, the active region STA1, and the second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 is disposed on the fourth insulating layer 40. In an embodiment, the third electrode STG1 may be a part of a metal pattern. The third electrode STG1 of the reset transistor ST1 overlaps with the active region STA1 of the reset transistor ST1.

[0137] As an example of the present disclosure, the reset transistor ST1 may be disposed on the same layer as the third transistor T3. For example, the first electrode STS1, the active region STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by the same process as the first electrode S3, the active region A3, and the second electrode D3 of the third transistor T3, respectively. The third electrode STG1 of the reset transistor ST1 may be formed simultaneously with the third electrode G3 of the third transistor T3 by the same process. Although not separately illustrated, the first and second electrodes of the amplification transistor ST2 and the output transistor ST3 in the sensor driving circuit O_SD may be formed by the same process as the first electrode S1 and the second electrode D1 of the first transistor T1, respectively. Since the reset transistor ST1 and the third transistor T3 can be formed on the same layer by the same process, no additional process for forming the reset transistor ST1 is required, thereby improving the process efficiency and reducing the cost.

[0138] Refer together to Figure 5A and Figure 5B , the element layer DP_ED may be disposed on the circuit layer DP_CL. The element layer DP_ED may include light-emitting elements ED-R, ED-G, and ED-B and a sensing element OPD. The light-emitting elements ED-R, ED-G, and ED-B may include a red light-emitting element ED-R, a green light-emitting element ED-G, and a blue light-emitting element ED-B. Figure 5A Representatively, one green light-emitting element ED-G and one sensing element OPD are illustrated.

[0139] The red light-emitting region PXA-R may be defined to correspond to the red light-emitting element ED-R, the green light-emitting region PXA-G may be defined to correspond to the green light-emitting element ED-G, the blue light-emitting region PXA-B may be defined to correspond to the blue light-emitting element ED-B, and the sensing region SA may be defined to correspond to the sensing element OPD. Each of the red light-emitting region PXA-R, the green light-emitting region PXA-G, the blue light-emitting region PXA-B, and the sensing region SA may be defined by a pixel defining film PDL to be described below.

[0140] The red light-emitting element ED-R, the green light-emitting element ED-G, and the blue light-emitting element ED-B may include first electrodes AE-R, AE-G, and AE-B, a first functional layer HFL, light-emitting layers EL-R, EL-G, and EL-B, a second functional layer EFL, and a second electrode CE. The first electrodes AE-R, AE-G, and AE-B may be referred to as pixel electrodes. The sensing element OPD may include a first electrode AE-S, a first functional layer HFL, a photoelectric conversion layer RL, a second functional layer EFL, and a second electrode CE. The first electrode AE-S may be referred to as a sensor electrode. The first functional layer HFL, the second functional layer EFL, and the second electrode CE may be provided in common in the pixel PX (see Figure 3 ), the sensor FX (see Figure 3 ), and the dummy sensor FX-d (see Figure 3 ).

[0141] Reference Figure 5A , the first electrode AE-G of the light-emitting element ED-G and the first electrode AE-S of the sensing element OPD are disposed on the seventh insulating layer 70. The first electrode AE-G of the light-emitting element ED-G may be connected to the second connection electrode CNE20 through a third contact hole CH3 passing through the seventh insulating layer 70.

[0142] The light-emitting elements ED-R, ED-G, and ED-B may further include a first auxiliary layer SL1, a second auxiliary layer SL2, and a third auxiliary layer SL3. In an embodiment of the present disclosure, at least some of the first auxiliary layer SL1, the second auxiliary layer SL2, and the third auxiliary layer SL3 may be omitted.

[0143] The auxiliary layers SL1, SL2, and SL3 include a first auxiliary layer SL1 disposed in the red light-emitting region PXA-R, a second auxiliary layer SL2 commonly disposed in the green light-emitting region PXA-G and the sensing region SA, and a third auxiliary layer SL3 disposed in the blue light-emitting region PXA-B. The first auxiliary layer SL1 may be disposed between the first functional layer HFL and the red light-emitting layer EL-R, and the second auxiliary layer SL2 may be disposed between the first functional layer HFL and the green light-emitting layer EL-G and between the first functional layer HFL and the photoelectric conversion layer RL. The third auxiliary layer SL3 may be disposed between the first functional layer HFL and the blue light-emitting layer EL-B.

[0144] The first auxiliary layer SL1, the second auxiliary layer SL2, and the third auxiliary layer SL3 may be provided to control the resonance distance. Accordingly, the thicknesses of the first auxiliary layer SL1, the second auxiliary layer SL2, and the third auxiliary layer SL3 may be different from each other. Figure 5B It is illustrated that the thickness of the first auxiliary layer SL1 is the largest and the thickness of the third auxiliary layer SL3 is the smallest, but the present disclosure is not necessarily specifically limited thereto.

[0145] According to an embodiment of the present disclosure, the second auxiliary layer SL2 of the sensing element OPD and the second auxiliary layer SL2 disposed in the green light-emitting region PXA-G may be formed simultaneously through the same process. For example, the second auxiliary layer SL2 may be formed using a single fine metal mask. Accordingly, the process time required for manufacturing the electronic device 1000 (see Figure 1 ) may be reduced.

[0146] The pixel defining film PDL may be disposed on the seventh insulating layer 70 and may cover a part of the first electrodes AE-R, AE-G, AE-B, and AE-S. Accordingly, the pixel defining film PDL may partially cover the first electrodes AE-R, AE-G, AE-B, and AE-S. The openings PDLop1 and PDLop2 are provided in the pixel defining film PDL. The plurality of light-emitting regions PXA-R, PXA-G, and PXA-B and the plurality of sensing regions SA may be defined by the openings PDLop1 and PDLop2.

[0147] Figure 5A It is illustrated the green light-emitting region PXA-G among the plurality of light-emitting regions PXA-R, PXA-G, and PXA-B and one of the plurality of sensing regions SA. For example, the green light-emitting region PXA-G may be defined by the first region defining opening PDLop1, and the sensing region SA may be defined by the second region defining opening PDLop2. The first region defining opening PDLop1 may expose at least a part of the first electrode AE-G of the light-emitting element ED-G, and the second region defining opening PDLop2 may expose at least a part of the first electrode AE-S of the sensing element OPD.

[0148] In an embodiment of the present disclosure, the pixel defining layer PDL may include a black material. The pixel defining layer PDL may include a black organic dye / pigment such as carbon black or aniline black. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a hydrophobic organic substance.

[0149] The light emitting layer EL-G of the light emitting element ED-G may be disposed in a region corresponding to the first region defining opening PDLop1. The light emitting layer EL-G may generate light of a predetermined color. In an embodiment, the patterned light emitting layers EL-R, EL-G, and EL-B are illustrated, but one light emitting layer may be commonly disposed in a plurality of light emitting regions. In this case, the light emitting layer may generate white light or blue light. Further, the light emitting layer may have a multi-layer structure called a tandem.

[0150] The light emitting layers EL-R, EL-G, and EL-B may include a low molecular organic material or a high molecular organic material as a light emitting material. Alternatively, the light emitting layers EL-R, EL-G, and EL-B may include a quantum dot material as a light emitting material. The core of the quantum dot may be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0151] The photoelectric conversion layer RL may be disposed in a region corresponding to the second region defining opening PDLop2. The photoelectric conversion layer RL may include an organic photosensitive material. The second electrode CE may be disposed on the photoelectric conversion layer RL. The first electrode AE-S and the second electrode CE may receive an electrical signal. The first electrode AE-S and the second electrode CE may receive different signals. Thus, a predetermined electric field may be formed between the first electrode AE-S and the second electrode CE. The photoelectric conversion layer RL generates an electrical signal corresponding to the light input to the sensor FX.

[0152] The charges generated in the photoelectric conversion layer RL change the electric field between the first electrode AE-S and the second electrode CE. The amount of charges generated in the photoelectric conversion layer RL may change according to whether light is input to the sensing element OPD and the amount and intensity of the light input to the sensing element OPD. Accordingly, the electric field formed between the first electrode AE-S and the second electrode CE may change. The sensing element OPD according to the present disclosure may obtain information about the user's fingerprint through the change in the electric field between the first electrode AE-S and the second electrode CE.

[0153] The element layer DP_ED may further include a capping layer disposed on the second electrode CE. The capping layer may be used to improve the light emission efficiency by the principle of constructive interference. The capping layer may include a material having a refractive index of 1.6 or higher for light having a wavelength of 589 nm. The capping layer may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. For example, the capping layer CPL may include a carbocyclic compound, a heterocyclic compound, an amino group-containing compound, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or any combination thereof. The carbocyclic compound, the heterocyclic compound, and the amino group-containing compound may optionally be substituted with substituents including O, N, S, Se, Si, F, Cl, Br, I, or any combination thereof.

[0154] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE includes at least an inorganic layer (or an encapsulating inorganic layer) or an organic layer (or an encapsulating organic layer). In an embodiment of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. According to an embodiment of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0155] The encapsulating inorganic layer protects the light-emitting element ED and the sensing element OPD from the influence of moisture / oxygen, and the encapsulating organic layer protects the light-emitting element ED and the sensing element OPD from foreign substances such as dust particles. The encapsulating inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but the present disclosure is not specifically limited thereto. The encapsulating organic layer may include an acrylic organic layer, and the present disclosure is not specifically limited thereto.

[0156] The electronic device 1000 (see Figure 1 ) may further include a sensor layer 200 and an antireflection layer 300.

[0157] The sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may sense an external input applied from an external unit. The external input may be an input of a user. The input of the user may include various types of external inputs, such as a part of the user's body, light, heat, a pen, and pressure. The sensor layer 200 may be referred to as a sensor, an input sensing layer, or an input sensing panel. The sensor layer 200 may include a sensor base layer 201, a first sensor conductive layer 202, an intermediate insulating layer 203, a second sensor conductive layer 204, and a covering insulating layer 205.

[0158] The sensor base layer 201 may be directly disposed on the display layer 100. The sensor base layer 201 may be an inorganic layer including silicon nitride, silicon oxynitride, and / or silicon oxide. Alternatively, the sensor base layer 201 may be an organic layer including epoxy resin, acrylic resin, or imide resin. The sensor base layer 201 may have a single-layer structure, or may have a multi-layer structure in which multiple layers are stacked in the third direction DR3.

[0159] Each of the first sensor conductive layer 202 and the second sensor conductive layer 204 may have a single-layer structure, or may have a multi-layer structure in which multiple layers are stacked in the third direction DR3.

[0160] The sensor conductive layers 202 and 204 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide, or indium zinc tin oxide. In addition, the transparent conductive layer may include a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, or graphene.

[0161] The sensor conductive layers 202 and 204 having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure such as titanium / aluminum / titanium, for example. The sensor conductive layers 202 and 204 having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0162] The intermediate insulating layer 203 may be disposed between the first sensor conductive layer 202 and the second sensor conductive layer 204. The intermediate insulating layer 203 may include an inorganic film. The inorganic film may include aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and / or hafnium oxide.

[0163] Alternatively, the intermediate insulating layer 203 may include an organic film. The organic film may include acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and / or perylene resin.

[0164] The cover insulating layer 205 may be disposed on the intermediate insulating layer 203 and cover the second sensor conductive layer 204. The second sensor conductive layer 204 may include a conductive pattern. The cover insulating layer 205 may cover the conductive pattern to reduce or eliminate the possibility of damaging the conductive pattern in subsequent processes. The cover insulating layer 205 may include an inorganic material. For example, the cover insulating layer 205 may include silicon nitride, but the present disclosure is not necessarily limited thereto specifically. In an embodiment of the present disclosure, the cover insulating layer 205 may be omitted.

[0165] The anti-reflection layer 300 may be disposed on the sensor layer 200. The anti-reflection layer 300 may include a separation layer 310, a plurality of color filters 320, and a planarization layer 330.

[0166] The separation layer 310 may overlap with the conductive pattern of the second sensor conductive layer 204. A covering insulating layer 205 may be disposed between the separation layer 310 and the second sensor conductive layer 204. The separation layer 310 may prevent external light from being reflected by the second sensor conductive layer 204. The material for forming the separation layer 310 is not particularly limited as long as the material absorbs light. The separation layer 310 is a layer having a black color, and in an embodiment, the separation layer 310 may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The separation layer 310 may be referred to as a light-shielding layer or a black matrix.

[0167] A plurality of separation openings may be defined in the separation layer 310. The plurality of separation openings may overlap with the light-emitting layers EL-R, EL-G, and EL-B and the photoelectric conversion layer RL. The color filters 320 may be arranged to correspond to the plurality of separation openings. The color filters 320 may transmit the light provided from the light-emitting layers EL-R, EL-G, and EL-B that overlap with the color filters 320. Alternatively, the light may pass through the color filters 320 and may be provided to the photoelectric conversion layer RL.

[0168] Figure 5A It is illustrated that one color filter 320 is commonly provided in the light-emitting layer EL-G and the photoelectric conversion layer RL. However, the present disclosure is not particularly limited thereto. For example, color filters for other colors except the green color filter may be disposed on the photoelectric conversion layer RL. Alternatively, the color filters 320 may not be disposed on the photoelectric conversion layer RL.

[0169] The planarization layer 330 may cover the separation layer 310 and the color filters 320. The planarization layer 330 may include an organic material, and a flat surface may be provided to the upper surface of the planarization layer 330. In an embodiment, the planarization layer 330 may be omitted.

[0170] In an embodiment of the present disclosure, the anti-reflection layer 300 may include a reflection adjustment layer instead of the color filters 320. For example, in Figure 5A the illustration, the color filters 320 may be omitted, and a reflection adjustment layer may be added at the place where the color filters 320 are omitted. The reflection adjustment layer may selectively absorb the light having a partial frequency band among the light reflected from the display layer 100 and / or the inside of the electronic device 1000 and the light input from the outside of the display layer 100 and / or the electronic device 1000.

[0171] As an example, the reflection adjustment layer absorbs light in a first wavelength region in the range of 490 nm to 505 nm and light in a second wavelength region in the range of 585 nm to 600 nm, such that the light transmittance in the first wavelength region and the second wavelength region is 40% or less. The reflection adjustment layer can absorb light having a wavelength deviated from the wavelength ranges of red light, green light, and blue light emitted from the light-emitting layers EL-R, EL-G, and EL-B. In this way, the reflection adjustment layer can absorb light having a wavelength that does not belong to the wavelength ranges of red light, green light, or blue light emitted from the light-emitting layers EL-R, EL-G, and EL-B, thereby preventing or minimizing a decrease in the brightness of the display layer 100 and / or the electronic device 1000. Further, simultaneously, deterioration of the luminous efficiency of the display layer 100 and / or the electronic device 1000 can be prevented or minimized, and visibility can be improved.

[0172] The reflection adjustment layer can be provided as an organic material layer including a dye, a pigment, or a combination thereof. The reflection adjustment layer can include a tetraazaporphyrin (TAP) compound, a porphyrin compound, a metal porphyrin compound, an oxazine compound, a squarylium compound, a triarylmethane compound, a polymethine compound, an anthraquinone compound, a phthalocyanine compound, a perylene compound, a xanthene compound, a diiminium compound, a pyrromethane compound, a cyanine compound, and combinations thereof.

[0173] In an embodiment, the reflection adjustment layer can have a light transmittance of about 64% to 72%. The light transmittance of the reflection adjustment layer can be adjusted according to the content of the pigment and / or dye included in the reflection adjustment layer.

[0174] Figure 6A is a plan view illustrating components of an electronic device 1000 according to an embodiment of the present disclosure. Figure 6B is a plan view illustrating components of an electronic device 1000 according to an embodiment of the present disclosure. Figure 6A illustrates the fingerprint sensing area FSA in an enlarged manner, and Figure 6B illustrates the fingerprint non-sensing area NFSA in an enlarged manner.

[0175] Reference Figure 5A 、 Figure 6A and Figure 6B , a plurality of first region-defining openings PDLop1 can be defined in the pixel-defining layer PDL. A plurality of light-emitting regions PXA-R, PXA-G, PXA-B, and PXA-Ba can be defined by the first region-defining openings PDLop1. A plurality of second region-defining openings PDLop2 can be defined in the pixel-defining layer PDL. A plurality of sensing regions SA and SA-dm can be defined by the second region-defining openings PDLop2.

[0176] The light-emitting regions PXA-R, PXA-G, PXA-B, and PXA-Ba may include a first light-emitting region PXA-B defined (provided or formed) in the fingerprint sensing region FSA and a second light-emitting region PXA-Ba defined in the fingerprint non-sensing region NFSA. The first light-emitting region PXA-B and the second light-emitting region PXA-Ba may output light of the same color. For example, the light may be blue light. Accordingly, a first pixel including the first light-emitting region PXA-B and a second pixel including the second light-emitting region PXA-Ba may output light of the same color.

[0177] The first light-emitting element ED1 may have the first light-emitting region PXA-B, and the second light-emitting element ED2 may have the second light-emitting region PXA-Ba. For example, the first light-emitting element ED1 may include a first pixel electrode AE-B, and the second light-emitting element ED2 may include a second pixel electrode AE-Ba. Among the openings PDLop1 defined in the first region, an opening that overlaps with the first pixel electrode AE-B and through which at least a part of the first pixel electrode AE-B is exposed is referred to as a first opening PDLop1b. Among the openings PDLop1 defined in the first region, an opening that overlaps with the second pixel electrode AE-Ba and through which at least a part of the second pixel electrode AE-Ba is exposed is referred to as a second opening PDLop1ba.

[0178] The sensing regions SA and SA-dm may include a first sensing region SA defined in the fingerprint sensing region FSA and a second sensing region SA-dm defined in the fingerprint non-sensing region NFSA. The second sensing region SA-dm may be a region that substantially does not sense fingerprints and may be referred to as a dummy region.

[0179] The first sensing element SD may have the first sensing region SA, and the second sensing element SD-dm may have the second sensing region SA-dm. For example, the first sensing element SD may include a first sensor electrode AE-S, and the second sensing element SD-dm may include a second sensor electrode AE-Sdm. Among the openings PDLop2 defined in the second region, an opening that overlaps with the first sensor electrode AE-S and through which at least a part of the first sensor electrode AE-S is exposed is referred to as a third opening PDLop2. Among the openings PDLop2 defined in the second region, an opening that overlaps with the second sensor electrode AE-Sdm and through which at least a part of the second sensor electrode AE-Sdm is exposed is referred to as a fourth opening PDLop2a. The first sensing element SD may correspond to Figure 4 the sensing element OPD described in

[0180] In the fingerprint sensing area FSA, the first light-emitting element ED1 and the first sensing element SD can be adjacent to each other in the first direction DR1. In the non-fingerprint sensing area NFSA, the second light-emitting element ED2 and the second sensing element SD-dm can be adjacent to each other in the first direction DR1.

[0181] In an embodiment of the present disclosure, the first sensing element SD defining the first sensing area SA can be an element electrically connected to the sensor driving circuit O_SD (see Figure 4 ) and sensing fingerprints. The second sensing element SD-dm defining the second sensing area SA-dm may not be an element for substantially sensing fingerprints. For example, the second sensing element SD-dm can be a dummy element.

[0182] In an embodiment of the present disclosure, the area of the first sensing area SA and the area of the second sensing area SA-dm can be different from each other in a plane defined by the first direction DR1 and the second direction DR2 intersecting the first direction DR1. For example, the area of the first sensing area SA can be larger than the area of the second sensing area SA-dm. Therefore, in a plan view, for example, when viewed in the third direction DR3, the size of the third opening PDLop2 defining the first sensing area SA can be larger than the size of the fourth opening PDLop2a defining the second sensing area SA-dm. In this case, the aperture ratio of the first sensing area SA relatively increases, and thus, the fingerprint sensing sensitivity can be improved.

[0183] In an embodiment of the present disclosure, the area of the first light-emitting area PXA-B and the area of the second light-emitting area PXA-Ba can be different from each other. For example, the area of the first light-emitting area PXA-B can be smaller than the area of the second light-emitting area PXA-Ba. Therefore, the size of the first opening PDLop1b defining the first light-emitting area PXA-B can be smaller than the size of the second opening PDLop1ba defining the second light-emitting area PXA-Ba.

[0184] In an embodiment of the present disclosure, the gap GD1 between the first opening PDLop1b and the third opening PDLop2 can be substantially the same as the gap GD2 between the second opening PDLop1ba and the fourth opening PDLop2a. In addition, the distance DT1 between the center of the first light-emitting area PXA-B and the center of the first sensing area SA can be substantially the same as the distance DT2 between the center of the second light-emitting area PXA-Ba and the center of the second sensing area SA-dm.

[0185] Figure 7A is a schematic cross-sectional view of the electronic device 1000 according to an embodiment of the present disclosure. Figure 7B is a schematic cross-sectional view of the electronic device 1000 according to an embodiment of the present disclosure. Figure 8is a plan view of components of an electronic device 1000 according to an embodiment of the present disclosure. For example, Figure 7A is a cross-sectional view taken along line I-I’ illustrated in Figure 6A and Figure 7B is a cross-sectional view taken along line II-II’ illustrated in Figure 6B Reference

[0186] Referring to Figure 7A and Figure 7B and Figure 8 , the anti-reflection layer 300 may include a partition layer 310. A first partition opening 310op1, a second partition opening 310op2, a third partition opening 310ops1, and a fourth partition opening 310ops2 may be defined (provided or formed) in the partition layer 310. The first partition opening 310op1, the second partition opening 310op2, the third partition opening 310ops1, and the fourth partition opening 310ops2 may overlap the first opening PDLop1b, the second opening PDLop1ba, the third opening PDLop2, and the fourth opening PDLop2a in a one-to-one correspondence.

[0187] The anti-reflection layer 300 may include a first color filter 320-1, a second color filter 320-2, a third color filter 320-S1, and a fourth color filter 320-S2 that cover the first partition opening 310op1, the second partition opening 310op2, the third partition opening 310ops1, and the fourth partition opening 310ops2 in a one-to-one correspondence.

[0188] In an embodiment of the present disclosure, the first difference DFD1 may be half of the difference between the maximum width MX1 of the first partition opening 310op1 and the maximum width MX1-A of the first opening PDLop1b. The second difference DFD2 may be half of the difference between the maximum width MX2 of the second partition opening 310op2 and the maximum width MX2-A of the second opening PDLop1ba. The first difference DFD1 may be greater than the second difference DFD2. In this case, a first width WT1 of the partition layer 310 between the first partition opening 310op1 and the third partition opening 310ops1 may be less than a second width WT2 of the partition layer 310 between the second partition opening 310op2 and the fourth partition opening 310ops2.

[0189] In an embodiment of the present disclosure, since the size of the first separation opening 310op1 is adjusted, the thickness TK1 of the first color filter 320-1 can be smaller than the second thickness TK2 of the second color filter 320-2. Accordingly, the light transmittance of the first color filter 320-1 can be higher than that of the second color filter 320-2. In this case, assuming that light of the same intensity is output, the brightness of the light output from the first light-emitting layer EL-B can be higher than the brightness of the light output from the second light-emitting layer EL-Ba. In this case, when displaying an image of the same brightness, the current supplied to the first light-emitting element ED1 including the first light-emitting layer EL-B can be smaller than the current supplied to the second light-emitting element ED2 including the second light-emitting layer EL-Ba.

[0190] According to an embodiment of the present disclosure, even when the first light-emitting layer EL-B has an area smaller than that of the second light-emitting layer EL-Ba, the first thickness TK1 of the first color filter 320-1 is smaller than the second thickness TK2 of the second color filter 320-2, and thus, the light-emitting efficiency of the first light-emitting region PXA-B (see Figure 6A ) can be greater than the light-emitting efficiency of the second light-emitting region PXA-Ba (see Figure 6B ). Accordingly, the difference in their lifetimes due to the difference in their areas can be reduced by the difference in the light-emitting efficiencies between the first light-emitting layer EL-B and the second light-emitting layer EL-Ba.

[0191] Accordingly, according to an embodiment of the present disclosure, the size of the third opening PDLop2 is larger than the size of the fourth opening PDLop2a that defines the second sensing region SA-dm (see Figure 6B ), so that fingerprint sensing sensitivity can be improved. Further, as the first thickness TK1 of the first color filter 320-1 becomes smaller than the second thickness TK2 of the second color filter 320-2, the difference in their lifetimes due to the difference in the areas between the first light-emitting layer EL-B and the second light-emitting layer EL-Ba can be reduced. Accordingly, the fingerprint sensing sensitivity of the electronic device 1000 (see Figure 1 ) can be improved, and the difference in the lifetimes of the pixels PX (see Figure 3 ) in the fingerprint sensing region FSA (see Figure 3 ) and the fingerprint non-sensing region NFSA (see Figure 3 ) can be reduced.

[0192] According to an embodiment of the present disclosure, the first difference DFD1s may be half of the difference between the width of the third partition opening 310ops1 and the width of the third opening PDLop2. The second difference DFD2s may be half of the difference between the width of the fourth partition opening 310ops2 and the width of the fourth opening PDLop2a. The first difference DFD1s may be substantially the same as the second difference DFD2s. Accordingly, the third opening PDLop2 may be greater than the fourth opening PDLop2a, and the third partition opening 310ops1 may be greater than the fourth partition opening 310ops2.

[0193] Figure 9 is a plan view showing components of an electronic device 1000 according to an embodiment of the present disclosure.

[0194] Reference Figure 9 , the first difference DFD1sa may be half of the difference between the width of the third partition opening 310ops1a and the width of the third opening PDLop2. The second difference DFD2s may be half of the difference between the width of the fourth partition opening 310ops2a and the width of the fourth opening PDLop2a. The first difference DFD1sa may be greater than the second difference DFD2s. The third opening PDLop2 may be greater than the fourth opening PDLop2a, and the third partition opening 310ops1a may be greater than the fourth partition opening 310ops2a.

[0195] A first width WT1a of the partition layer 310 between the first partition opening 310op1 and the third partition opening 310ops1a may be less than a second width WT2 of the partition layer 310 between the second partition opening 310op2 and the fourth partition opening 310ops2a.

[0196] Figure 10 is a block diagram showing a display layer 100 and a display driver 100C according to an embodiment of the present disclosure. Figure 11 is a plan view of components of an electronic device 1000 according to an embodiment of the present disclosure.

[0197] Reference Figure 10 and Figure 11 , the display area DA may include a fingerprint sensing area FSA, an auxiliary fingerprint sensing area FSA-ad, and a fingerprint non-sensing area NFSA.

[0198] The display layer 100 may include a plurality of pixels PX arranged in the display area DA, a plurality of sensors FX arranged in the fingerprint sensing area FSA, a plurality of auxiliary sensors FX-m arranged in the auxiliary fingerprint sensing area FSA-ad, and a plurality of dummy sensors FX-d arranged in the fingerprint non-sensing area NFSA.

[0199] Reference Figure 5A ,Figure 10 and Figure 11 and the third light-emitting element ED2m and the third sensing element SDm may be disposed in the auxiliary fingerprint sensing area FSA-ad. The third light-emitting element ED2m and the third sensing element SDm may have a cross-sectional structure similar to the cross-sectional structure described in Figure 5A . A fifth opening PDLop1bm overlapping the third light-emitting element ED2m and a sixth opening PDLop2m overlapping the third sensing element SDm may be defined in the pixel defining layer PDL. A fifth partition opening 310opm overlapping the fifth opening PDLop1bm and a sixth partition opening 310opsm overlapping the sixth opening PDLop2m may be defined in the partition layer 310.

[0200] According to an embodiment of the present disclosure, the difference DFDm may be half of the difference between the width of the fifth partition opening 310opm and the width of the fifth opening PDLop1bm. Half of the difference between the width of the sixth partition opening 310opsm and the width of the sixth opening PDLop2m may be substantially the same as the difference DFDm.

[0201] According to an embodiment of the present disclosure, the sensitivity of the sensor FX required in the fingerprint sensing area FSA may be greater than the sensitivity of the auxiliary sensor FX-m required in the auxiliary fingerprint sensing area FSA-ad. For example, the sixth opening PDLop2m may be smaller than the third opening PDLop2 (see Figure 8 ) and greater than the fourth opening PDLop2a (see Figure 8 ). In addition, the sixth partition opening 310opsm may be smaller than the third partition opening 310ops1 (see Figure 8 ) and greater than the fourth partition opening 310ops2 (see Figure 8 ).

[0202] In an embodiment of the present disclosure, the size of the fifth opening PDLop1bm defining the area of the light-emitting region of the third light-emitting element ED2m may be greater than the size of the first opening PDLop1b (see Figure 6A ) defining the first light-emitting region PXA-B (see Figure 6A ), and smaller than the size of the second opening PDLop1ba (see Figure 6B ) defining the second light-emitting region PXA-Ba (see Figure 6B ). Further, the gap GDm between the fifth opening PDLop1bm and the sixth opening PDLop2m may be substantially the same as the gap GD1 (see Figure 8 ) between the first opening PDLop1b (see Figure 8 ) and the third opening PDLop2 (see Figure 8 ).

[0203] According to the above description, the area of the first sensing area of the fingerprint sensing area and the area of the second sensing area of the fingerprint non-sensing area can be different from each other. For example, the area of the first sensing area can be larger than the area of the second sensing area. Therefore, the aperture ratio of the first sensing area is relatively increased, and thus, the fingerprint sensing sensitivity can be improved.

[0204] Furthermore, since the area of the first sensing area is increased, the area of the first light-emitting layer provided in the fingerprint sensing area and the area of the second light-emitting layer provided in the fingerprint non-sensing area can be different from each other. Since the first thickness of the first color filter provided on the first light-emitting layer becomes smaller than the second thickness of the second color filter provided on the second light-emitting layer, the difference in their lifetimes caused by the difference in the areas between the first light-emitting layer and the second light-emitting layer can be reduced. When displaying an image with the same brightness, the current supplied to the first light-emitting element including the first light-emitting layer can be smaller than the current supplied to the second light-emitting element including the second light-emitting layer. Therefore, the difference in lifetimes between the pixels in the fingerprint sensing area and the pixels in the fingerprint non-sensing area can be reduced.

[0205] Although the above has been described with reference to embodiments of the present disclosure, it can be understood that those skilled in the art or those with ordinary knowledge in the art can modify and change the present disclosure differently without departing from the spirit and technical scope of the present disclosure.

Claims

1. An electronic device, comprising: Display layer; as well as an anti-reflection layer, disposed on the display layer, The display layer includes: a first light-emitting element having a first light-emitting area, a first sensing element adjacent to the first light-emitting element in a first direction and having a first sensing area, a second light-emitting element having a second light-emitting area, and a second sensing element adjacent to the second light-emitting element in the first direction and having a second sensing area, and In a plane defined by the first direction and a second direction intersecting the first direction, an area of ​​the first sensing region is greater than an area of ​​the second sensing region.

2. The electronic device according to claim 1, wherein: The area of ​​the first light emitting area is smaller than that of the second light emitting area.

3. The electronic device according to claim 1, wherein: The first light emitting element includes a first pixel electrode, the second light emitting element includes a second pixel electrode, the first sensing element includes a first sensor electrode, and the second sensing element includes a second sensor electrode, and The display layer further includes a pixel defining film, which partially covers the first pixel electrode, the second pixel electrode, the first sensor electrode and the second sensor electrode, and includes a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, a third opening overlapping the first sensor electrode, and a fourth opening overlapping the second sensor electrode.

4. The electronic device according to claim 3, wherein: On the plane, a size of the first opening is smaller than a size of the second opening.

5. The electronic device according to claim 3, wherein: On the plane, a size of the third opening is larger than a size of the fourth opening.

6. The electronic device according to claim 3, wherein: A gap between the first opening and the third opening is the same as a gap between the second opening and the fourth opening.

7. The electronic device according to claim 3, wherein: The first light emitting area is defined by the first opening, the second light emitting area is defined by the second opening, the first sensing area is defined by the third opening, and the second sensing area is defined by the fourth opening.

8. The electronic device according to claim 3, wherein: The anti-reflection layer includes a separation layer including a first separation opening, a second separation opening, a third separation opening, and a fourth separation opening overlapping with the first opening, the second opening, the third opening, and the fourth opening in a one-to-one correspondence.

9. The electronic device according to claim 8, wherein: A difference between a maximum width of the first partition opening and a maximum width of the first opening is greater than a difference between a maximum width of the second partition opening and a maximum width of the second opening.

10. The electronic device according to claim 8, wherein: A distance between the first partition opening and the third partition opening is smaller than a distance between the second partition opening and the fourth partition opening.

11. The electronic device according to claim 8, wherein: The anti-reflection layer further comprises: a first color filter configured to cover the first separation opening; and a second color filter configured to cover the second separation opening, and The thickness of the first color filter is smaller than the thickness of the second color filter.

12. The electronic device according to claim 1, wherein: The first light emitting element and the second light emitting element output light having the same color.

13. The electronic device according to claim 1, wherein: A distance between a center of the first light emitting area and a center of the first sensing area is the same as a distance between a center of the second light emitting area and a center of the second sensing area.

14. The electronic device according to any one of claims 1 to 13, wherein: The display layer further comprises: a sensor driving circuit electrically connected to the first sensing element, and The second sensing element is a dummy element.

15. An electronic device comprising: Display layer; as well as an anti-reflection layer, disposed on the display layer, The display layer includes: a first pixel electrode; a second pixel electrode; a first sensor electrode, adjacent to the first pixel electrode in a first direction; a second sensor electrode adjacent to the second pixel electrode in the first direction; and a pixel defining film configured to partially cover the first pixel electrode, the second pixel electrode, the first sensor electrode, and the second sensor electrode, and including a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, a third opening overlapping the first sensor electrode, and a fourth opening overlapping the second sensor electrode, and On a plane defined by the first direction and a second direction intersecting the first direction, a size of the third opening is larger than a size of the fourth opening.

16. The electronic device according to claim 15, wherein: On the plane, a size of the first opening is smaller than a size of the second opening.

17. The electronic device according to claim 15, wherein: A gap between the first opening and the third opening is the same as a gap between the second opening and the fourth opening.

18. The electronic device according to claim 15, wherein: The anti-reflection layer includes a separation layer including a first separation opening, a second separation opening, a third separation opening, and a fourth separation opening overlapping with the first opening, the second opening, the third opening, and the fourth opening in a one-to-one correspondence.

19. The electronic device according to claim 18, wherein: A difference between a maximum width of the first partition opening and a maximum width of the first opening is greater than a difference between a maximum width of the second partition opening and a maximum width of the second opening, and A distance between the first partition opening and the third partition opening is smaller than a distance between the second partition opening and the fourth partition opening.

20. The electronic device according to claim 18, wherein: The anti-reflection layer further comprises: a first color filter configured to cover the first separation opening; and a second color filter configured to cover the second separation opening, and The thickness of the first color filter is smaller than the thickness of the second color filter.

21. An electronic device comprising: The display panel includes a first light-emitting element having a first light-emitting area, a first sensing element adjacent to the first light-emitting element in a first direction and having a first sensing area, a second light-emitting element having a second light-emitting area, and a second sensing element adjacent to the second light-emitting element in the first direction and having a second sensing area. wherein on a plane defined by the first direction and a second direction intersecting the first direction, an area of ​​the first sensing region is larger than an area of ​​the second sensing region, and A fingerprint or external illumination is sensed using the first sensing element.

22. The electronic device according to claim 21, wherein: The brightness of an image displayed on the display panel is adjusted according to the external lighting.

Images