Ultrahigh-voltage silicon carbide starting control chip protection method and system

Abstract

The invention relates to an ultrahigh-voltage silicon carbide start control chip protection method and system, and the method comprises the steps: obtaining the operation parameters and composite structure characteristic data of an ultrahigh-voltage silicon carbide start control chip, and carrying out the TVS-MOSFET hierarchical characteristic analysis, and obtaining the real-time state information of the chip; acquiring a grid charging curve of the ultrahigh-voltage silicon carbide starting control chip, and performing correlation analysis on the grid charging curve and the real-time state information of the chip to obtain a multi-threshold protection parameter; acquiring current change data of the ultrahigh-voltage silicon carbide starting control chip, and performing Miller platform feature analysis on the real-time state information of the chip to obtain a current abnormal trend; performing temperature control construction on a multi-threshold protection parameter and the current abnormal trend to obtain an initial control scheme; and carrying out clamping turn-off strategy construction on the initial control scheme and the potential fault area to obtain a chip start protection strategy. Optimized starting protection of the chip can be achieved through the comprehensive adjustment strategy, and therefore the service life of the chip is effectively prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of control chips, and particularly relates to a protection method and system for an ultra-high voltage silicon carbide startup control chip. Background Art

[0002] Ultra-high voltage silicon carbide startup control chips have important application values in modern electronic devices. Their high performance and high reliability make them the core components of various high-performance power electronic systems. With the continuous improvement of the performance requirements of electronic devices, how to ensure the stable operation of ultra-high voltage silicon carbide startup control chips under various complex working conditions has become one of the research focuses. Existing protection methods usually only focus on single working parameters or simple protection mechanisms, ignoring the comprehensive characteristic analysis of the chip under different working states and the multi-level protection requirements. Such a simplified protection method may cause the chip to be easily affected by abnormal currents or temperature fluctuations during operation, thereby reducing its overall performance and lifespan. Summary of the Invention

[0003] The main object of the present invention is to provide a protection method and system for an ultra-high voltage silicon carbide startup control chip, which can achieve optimized startup protection of the chip through a comprehensive adjustment strategy, thereby effectively extending the lifespan of the chip.

[0004] To achieve the above object, the present invention provides a protection method for an ultra-high voltage silicon carbide startup control chip, including: Obtaining the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide startup control chip, and performing a step-by-step characteristic analysis of TVS-MOSFET to obtain the real-time state information of the chip; Obtaining the gate charging curve of the ultra-high voltage silicon carbide startup control chip, and performing a correlation analysis with the real-time state information of the chip to obtain multi-threshold protection parameters; Obtaining the current change data of the ultra-high voltage silicon carbide startup control chip, and performing a Miller plateau characteristic analysis on the real-time state information of the chip to obtain an abnormal current trend; Constructing a temperature control based on the multi-threshold protection parameters and the abnormal current trend to obtain an initial control scheme; Performing a fault self-diagnosis on the real-time state information of the chip to obtain a fault warning message, and performing a fault prediction with the gate charging curve to obtain a potential fault area; Constructing a clamping-off strategy based on the initial control scheme and the potential fault area to obtain a chip startup protection strategy.

[0005] Further, the obtaining the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide startup control chip, and performing a step-by-step characteristic analysis of TVS-MOSFET to obtain the real-time state information of the chip includes: Perform power calculation based on the operating parameters and conduct switching frequency analysis to obtain effective frequency data; Extract basic parameters from the operating parameters to obtain chip basic parameters; Associate the effective frequency data with the chip basic parameters to obtain an effective operating parameter set; Perform coupled calculations of material dielectric constant, interlayer thermal conductivity, and interfacial stress distribution on the composite structure characteristic data to obtain a structure coupling coefficient; Modify the data of the effective operating parameter set based on the structure coupling coefficient to obtain modified operating parameters; Conduct TVS-MOSFET hierarchical characteristic analysis on the modified operating parameters to obtain the real-time status information of the chip.

[0006] Further, the conducting TVS-MOSFET hierarchical characteristic analysis on the modified operating parameters to obtain the real-time status information of the chip includes: Perform thermoelectric field coupling calculation on the modified operating parameters to obtain a nanoscale heat flux distribution map; Conduct TVS structure tunneling current density analysis based on the heat flux distribution map to obtain a leakage characteristic curve in the subthreshold region; Perform Gaussian orthogonal polynomial fitting on the leakage characteristic curve in the subthreshold region to obtain a target inflection point parameter set; Calculate the degradation of MOSFET channel carrier mobility based on the target inflection point parameter set to obtain an interface trap distribution function; Perform adaptive grid fusion on the interface trap distribution function and the heat flux distribution map to obtain the real-time status information of the chip.

[0007] Further, the obtaining the gate charging curve of the ultra-high voltage silicon carbide startup control chip and conducting correlation analysis with the real-time status information of the chip to obtain multi-threshold protection parameters includes: Sample the gate voltage of the ultra-high voltage silicon carbide startup control chip to obtain original gate voltage data; Eliminate interference noise from the original gate voltage data and conduct curve mapping to obtain the gate charging curve; Calculate the stage critical time points of the gate charging curve to obtain segmented charging characteristic parameters; Perform temperature compensation calculation on the segmented charging characteristic parameters according to the real-time status information of the chip to obtain a normalized charging characteristic curve; Obtain the historical safe operation data of the ultra-high voltage silicon carbide startup control chip and conduct deviation analysis on the normalized charging characteristic curve to obtain a critical safety boundary value; Calculate the threshold value based on the critical safety boundary value and the real-time status information of the chip to obtain the multi-threshold protection parameters, where the multi-threshold protection parameters include a lower voltage threshold, an overcurrent protection threshold, and a time-delay protection threshold.

[0008] Further, obtain the current change data of the ultra-high voltage silicon carbide startup control chip, and perform a Miller plateau characteristic analysis on the real-time status information of the chip to obtain an abnormal current trend, including: Extract the Miller plateau fluctuation coefficient from the current change data to obtain the Miller plateau current characteristic function; Calculate the current harmonic components based on the Miller plateau current characteristic function and the real-time status information of the chip to obtain a harmonic distribution map; Identify the non-linear current components and abnormal current waveforms in the harmonic distribution map to obtain an abnormal current feature vector; Predict the current change trend based on the abnormal current feature vector to obtain a predicted current curve; Calculate the deviation coefficient and abnormal probability of the predicted current curve to obtain abnormal trend data; Perform a fine-grained analysis of the Miller plateau region on the real-time status information of the chip according to the abnormal trend data to obtain the abnormal current trend.

[0009] Further, perform temperature control construction on the multi-threshold protection parameters and the abnormal current trend to obtain an initial control scheme, including: Perform an analysis of the current change gradient on the abnormal current trend to obtain a temperature compensation coefficient; Adaptive adjustment of the multi-threshold protection parameters according to the temperature compensation coefficient to obtain a temperature correction threshold; Construct a multi-dimensional protection space by combining the temperature correction threshold and the abnormal current trend; Optimize the temperature partition of the multi-dimensional protection space to obtain a temperature-graded protection area; Plan the control timing of the temperature-graded protection area to obtain a dynamic protection strategy; Predict the loss of the abnormal current trend to obtain power loss prediction data; Optimize the temperature control of the dynamic protection strategy based on the power loss prediction data to obtain an initial control scheme.

[0010] Further, perform a fault self-diagnosis on the real-time status information of the chip to obtain a fault warning message, and perform a fault prediction with the gate charging curve to obtain a potential fault area, including: Calculate the chip node voltage for the real-time status information of the chip, and perform threshold offset analysis to obtain the node anomaly metric value; Perform cumulative probability distribution calculation on the node anomaly metric value to obtain a fault probability distribution diagram; Extract the temperature-voltage correlation characteristics based on the real-time status information of the chip, and perform early warning correlation with the fault probability distribution diagram to obtain a fault early warning parameter set; Match according to a preset fault type table and the fault early warning parameter set to obtain fault type early warning identification information; Perform voltage stress distribution calculation on the fault type early warning identification information and the gate charging curve to obtain a pressure operating range; Predict the critical value of the chip parasitic parameters according to the pressure operating range to obtain avalanche breakdown prediction region data; Perform cross-validation on the avalanche breakdown prediction region data and the gate charging curve to obtain a potential fault region.

[0011] Further, construct a clamping-off strategy for the initial control scheme and the potential fault region to obtain a chip startup protection strategy, including: Perform non-linear threshold grading on the initial control scheme based on preset silicon carbide material characteristic data to obtain adaptive voltage protection threshold data; Extract differential features of the potential fault region and analyze the fluctuation characteristics of fault precursor signals to obtain a fault precursor feature vector; Perform multi-phase response time curve analysis according to the adaptive voltage protection threshold data and the fault precursor feature vector, and construct a strategy to obtain a dynamic protection response strategy; Perform fast and slow dual clamping voltage analysis on the dynamic protection response strategy based on a preset second-order damping coefficient regulation algorithm to obtain a dual-channel clamping control instruction; Perform drive circuit variable slope control analysis according to the dual-channel clamping control instruction to obtain an intelligent turn-off control signal; Optimize the startup protection of the initial control scheme according to the intelligent turn-off control signal and the dual-channel clamping control instruction to obtain the chip startup protection strategy.

[0012] The present invention also provides a super-high voltage silicon carbide startup control chip protection system, which is applied to the super-high voltage silicon carbide startup control chip protection method described in any one of the above, including: An acquisition module, which is used to obtain the operating parameters and composite structure characteristic data of the super-high voltage silicon carbide startup control chip, and perform TVS-MOSFET step characteristic analysis to obtain the real-time status information of the chip; An analysis module, which is used to obtain the gate charging curve of the ultra-high voltage silicon carbide startup control chip, perform correlation analysis with the real-time status information of the chip, and obtain multi-threshold protection parameters; A correlation module, which is used to obtain the current change data of the ultra-high voltage silicon carbide startup control chip, perform Miller platform characteristic analysis on the real-time status information of the chip, and obtain the current anomaly trend; A processing module, which is used to construct temperature control for the multi-threshold protection parameters and the current anomaly trend to obtain an initial control scheme; A control module, which is used to perform fault self-diagnosis on the real-time status information of the chip to obtain fault warning information, and perform fault prediction with the gate charging curve to obtain potential fault areas; An execution module, which is used to construct a clamping-off strategy for the initial control scheme and the potential fault areas to obtain a chip startup protection strategy.

[0013] A method and system for protecting an ultra-high voltage silicon carbide startup control chip provided by the present invention have the following beneficial effects: By comprehensively analyzing the operating parameters and composite structure characteristic data of the startup control chip, and combining with the step-by-step characteristics analysis of TVS-MOSFET, the real-time status information of the chip can be evaluated more accurately, thereby improving the accuracy of the chip protection mechanism and providing a more reliable basis for the design and operation of the chip. By performing correlation analysis on the gate charging curve and the real-time status information of the chip to obtain multi-threshold protection parameters, refined management of the chip in different working states is realized, which helps to identify the current anomaly trend in advance and avoid damage to the chip caused by sudden abnormal current during operation. Based on temperature control, an initial control scheme is constructed to ensure that the chip can operate efficiently at different working temperatures, reduce unnecessary energy consumption, and improve the overall operating efficiency of the chip. By performing fault self-diagnosis on the real-time status information of the chip and combining with the gate charging curve for fault prediction, a more reasonable clamping-off strategy can be formulated, and the optimized startup protection of the chip can be achieved through comprehensive adjustment of the strategy, thereby effectively extending the chip life, reducing faults, and improving the stability and reliability of the system. And by considering the influence of potential fault areas, the protection strategy can be flexibly adjusted according to different working scenarios, making the chip more adaptable to diverse application requirements. Brief Description of the Drawings

[0014] Figure 1 is a flowchart of a method for protecting an ultra-high voltage silicon carbide startup control chip provided by the present invention; Figure 2 is a structural diagram of a system for protecting an ultra-high voltage silicon carbide startup control chip provided by the present invention.

[0015] The realization, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed Embodiments

[0016] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] Next, with reference to the accompanying drawings and specific embodiments, the present invention will be further described.

[0018] Referring to Figure 1 as shown, the present invention provides a method for protecting an ultra-high voltage silicon carbide startup control chip, including: Step S1: Obtain the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide startup control chip, and perform TVS-MOSFET step characteristic analysis to obtain the real-time state information of the chip; Step S2: Obtain the gate charging curve of the ultra-high voltage silicon carbide startup control chip, and perform correlation analysis with the real-time state information of the chip to obtain multi-threshold protection parameters; Step S3: Obtain the current change data of the ultra-high voltage silicon carbide startup control chip, and perform Miller plateau characteristic analysis on the real-time state information of the chip to obtain the abnormal current trend; Step S4: Construct temperature control for the multi-threshold protection parameters and the abnormal current trend to obtain an initial control scheme; Step S5: Perform fault self-diagnosis on the real-time state information of the chip to obtain fault warning information, and perform fault prediction with the gate charging curve to obtain potential fault areas; Step S6: Construct a clamping-off strategy for the initial control scheme and the potential fault areas to obtain a chip startup protection strategy.

[0019] Based on the above steps, the detailed step process is as follows: Step S1: Establish a real-time chip status monitoring system by collecting chip operating parameters and composite structure characteristic data. The operating parameters include core indicators such as the chip operating voltage range, maximum allowable current, temperature coefficient, switching frequency, driving ability, and parasitic parameters. Among them, the chip operating voltage range includes voltage levels between 650V and 3.3kV, covering voltage levels of 1200V, 1700V, and 3300V. The composite structure characteristic data covers the structural parameters, material characteristics, and coupling effect data of the internal TVS protection structure and MOSFET power device of the chip. The TVS-MOSFET step-by-step characteristic analysis divides the chip operating state into three stages: normal conduction, critical state, and abnormal operation, and each stage has different voltage-current characteristic curves. By establishing a mathematical model, multiple characteristic points are set on the voltage axis and current axis, and parameters such as the on-resistance, drain-source breakdown voltage, and gate threshold voltage in each stage are calculated to form a panoramic map of chip performance. This analysis also considers the characteristic changes of silicon carbide materials in high-temperature environments, and corrects the offset of each parameter with temperature change through a temperature compensation algorithm. Combining time-domain waveform analysis and frequency-domain characteristic analysis, a chip status evaluation matrix is constructed to realize the quantitative characterization of the chip's transient response. The analysis results are directly converted into real-time chip status information, including three core indicators: the current operating point position, safety margin evaluation, and potential risk warning, providing basic data support for the formulation of subsequent protection strategies.

[0020] Step S2: Generate a multi-level protection parameter system through correlation analysis with the real-time chip status information. The gate charging curve reflects the entire process of the MOSFET from off to fully on, recording the complete trajectory of the gate voltage changing with time. The acquisition process uses a high-precision oscilloscope with a sampling rate of not less than 1GS / s to ensure capturing nanosecond-level transient changes. The obtained charging curve is decomposed into four typical regions: pre-charge section, fast-rising section, Miller plateau section, and saturation section. Key parameters such as time constant, slope change rate, and voltage increment are calculated for each region. Cross-analysis is carried out with the real-time chip status information obtained in Step S1 to establish the mapping relationship between the gate charging characteristics and the internal state of the chip. Through mathematical fitting and statistical analysis, the fluctuation range of the gate charging curve under normal operating conditions is identified, and the curve distortion characteristics in abnormal situations are calibrated. The correlation analysis process applies a pattern recognition algorithm to extract the feature vectors of the charging curve, calculate the correlation with the chip state vector, and construct a non-linear mapping model between the two. Based on this model, a multi-dimensional protection parameter set including voltage threshold, time threshold, and slope threshold is generated. These parameters set over-voltage protection points, under-voltage protection points, and optimal operating intervals in the voltage dimension; determine the shortest safe charging time and the longest allowable charging time in the time dimension; and limit the safe boundary of the gate voltage change rate in the slope dimension. The multi-threshold protection parameters become the direct basis for the implementation of subsequent protection strategies.

[0021] Step S3: Focus on in-depth analysis of the current change data of the ultra-high voltage silicon carbide startup control chip, especially the analysis of the Miller plateau characteristics, to identify potential current anomaly trends. The current change data acquisition uses non-destructive measurement techniques. High-precision current probes are arranged on the chip pins and key paths to collect the current waveforms during the entire startup process. The data acquisition covers three key parts: gate drive current, drain-source main current, and protection circuit current, forming a complete current distribution map. After the collected data is filtered for noise and baseline corrected, it enters the Miller plateau characteristic analysis stage. The Miller plateau is a key stage in the MOSFET switching process, during which the gate voltage remains relatively stable while the drain-source voltage changes rapidly. This characteristic is particularly obvious in silicon carbide devices. In the analysis process, a mathematical model of the Miller plateau is established to calculate three core parameters: plateau duration, plateau voltage stability, and current rise rate. Combining with the real-time status information of the chip obtained in Step S1, an association model between the Miller plateau parameters and the internal state of the chip is constructed. Through statistical analysis of historical data, a reference mode of current change is established, and any change deviating from this mode is identified as a potential anomaly. The anomaly determination uses a multi-dimensional threshold method, comprehensively considering current amplitude deviation, rise time change, and waveform distortion degree. The current anomaly trend is quantified through a trend prediction algorithm to generate an anomaly feature vector containing anomaly type, severity, and development trend, providing key inputs for subsequent temperature control and fault warning.

[0022] Step S4: Temperature, as a key influencing factor for the performance of silicon carbide devices, plays a decisive role in formulating protection strategies. For temperature control, first, a mapping relationship between temperature and protection parameters is established. The temperature distribution map of the chip and its surrounding environment is obtained through thermocouple or infrared temperature measurement technology, with the accuracy controlled within ±1°C. A temperature-protection parameter matrix is established to dynamically adjust each threshold parameter according to temperature changes. For the gate voltage threshold, when the temperature rises, the overvoltage protection point is appropriately reduced, the undervoltage protection point is increased, and the safe operating window is narrowed; for the time threshold, when the temperature rises, the longest allowable charging time is shortened, and the shortest safe charging time is extended; for the slope threshold, when the temperature rises, the maximum allowable change rate is reduced. The temperature compensation of the current anomaly trend is achieved by establishing a current-temperature characteristic model to correct the current anomaly determination criteria. At high temperatures, the current threshold is relatively reduced, and the anomaly determination is more sensitive; at low temperatures, the current threshold is relatively increased, allowing a larger fluctuation range. Based on the temperature correlation analysis of the two sets of data, a three-dimensional control model is constructed, with the X-axis being temperature, the Y-axis being protection parameters, and the Z-axis being the anomaly trend index. Through this model, a control strategy library for different temperature ranges is generated to form an initial control scheme. This scheme has temperature self-adaptive characteristics and can automatically adjust the protection strategy parameters according to real-time temperature changes to ensure the safe and reliable operation of the ultra-high voltage silicon carbide startup control chip within the full temperature range.

[0023] Step S5: Fault self-diagnosis establishes a state anomaly detection model based on the obtained real-time chip status information. This model uses the self-organizing mapping algorithm to map the chip status data into a two-dimensional feature space, and identifies the normal state cluster and the abnormal state cluster through cluster analysis. The abnormal state is further divided into four basic fault modes: overvoltage state, overcurrent state, temperature anomaly state, and parasitic oscillation state. Calculate the confidence index for each fault mode, and generate fault warning information, which includes three dimensions: fault type, severity, and occurrence probability. Conduct a correlation analysis on the fault warning information and the obtained gate charging curve to establish the mapping relationship between the fault mode and the distortion characteristics of the charging curve. Train a fault prediction model based on historical data. This model can predict the occurrence trend of potential faults from the minute changes in the current charging curve. The prediction process uses the dynamic time warping algorithm to compare the deviation between the current charging curve and the standard curve, and combines trend extrapolation technology to calculate the fault development trajectory. Through the Monte Carlo simulation method, generate multiple possible fault evolution scenarios, calculate the probability distribution of each scenario, and determine the high-risk fault area. The potential fault area is represented in the three-dimensional voltage-current-time space to form a fault risk heat map, which intuitively shows the high-risk operation points and dangerous working intervals. This heat map identifies the time period and the corresponding voltage and current parameter ranges that are most likely to trigger faults during the gate charging process, providing an accurate intervention timing and parameter basis for the next clamping-off strategy.

[0024] Step S6: Integrate the initial control scheme with the identified potential fault regions to construct an accurate clamping-off strategy, forming a complete chip startup protection strategy. When constructing the clamping-off strategy, first divide the potential fault regions into different risk levels, and assign different processing priorities to the high-risk regions, medium-risk regions, and low-risk regions respectively. For high-risk regions, adopt a hard clamping strategy. Once it is detected that the operating parameters enter this region, immediately trigger the hard-off protection. For medium-risk regions, adopt a soft clamping strategy, and guide the chip operating parameters away from the dangerous region by controlling the gate charging current or adjusting the gate voltage slope. For low-risk regions, adopt a monitoring strategy to continuously track the parameter changes without active intervention. The clamping threshold is set based on the multi-threshold protection parameters in the initial control scheme and fine-tuned according to the boundary characteristics of the potential fault regions to ensure that the clamping point is at a safe position before the fault occurs. The turn-off timing design takes into account the fast switching characteristics of silicon carbide devices. The hard turn-off adopts a stepped turn-off mode, first quickly reducing the gate voltage below the threshold, and then slowly releasing the gate charge to avoid voltage spikes and oscillations caused by too fast turn-off. A negative feedback control loop is introduced during the soft clamping process to continuously monitor the parameter changes and dynamically adjust the clamping intensity. The entire strategy is implemented through a decision tree structure, establishing a clear mapping between various possible operating states and corresponding processing measures. The finally formed chip startup protection strategy includes four functional modules: status monitoring, anomaly recognition, risk assessment, and protection execution, as well as state transition logic and recovery mechanisms. This strategy can achieve full-process and multi-dimensional precise protection for the ultra-high voltage silicon carbide startup control chip, effectively improving the reliability and stability of the chip under complex working conditions.

[0025] A method for protecting an ultra-high voltage silicon carbide start control chip provided by the present invention can more accurately evaluate the real-time state information of the chip by comprehensively analyzing the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide start control chip and combining the step-by-step characteristics analysis of TVS-MOSFET, thereby improving the accuracy of the chip protection mechanism and providing a more reliable basis for the design and operation of the chip. By correlating the gate charging curve with the real-time state information of the chip, multi-threshold protection parameters are obtained to achieve refined management of the chip in different operating states, which helps to identify abnormal current trends in advance and avoid damage to the chip caused by sudden abnormal currents during operation. An initial control scheme is constructed based on temperature control to ensure that the chip can operate efficiently at different operating temperatures, reduce unnecessary energy consumption, and improve the overall operating efficiency of the chip. By performing fault self-diagnosis on the real-time state information of the chip and combining the gate charging curve for fault prediction, a more reasonable clamping-off strategy can be formulated, and the optimized start protection of the chip can be achieved through comprehensive adjustment strategies, thereby effectively extending the chip life, reducing faults, and improving the stability and reliability of the system. By considering the influence of potential fault areas, the protection strategy can be flexibly adjusted according to different operating scenarios, making the chip more adaptable to diverse application requirements.

[0026] In one embodiment, the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide start control chip are obtained, and the step-by-step characteristics analysis of TVS-MOSFET is performed to obtain the real-time state information of the chip, including: In the stage of obtaining the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide start control chip, the system collects the operating parameters such as the working voltage, working current, switching timing, and temperature distribution of the chip. At the same time, the structure characteristic data such as the material composition, layer thickness distribution, and interface characteristics of the TVS-MOSFET composite structure inside the chip are collected. The operating parameters are collected in real time through an integrated sensor network, and the composite structure characteristic data are obtained through material characterization and structure analysis during the chip design stage and stored in the internal parameter library of the chip.

[0027] In the stage of calculating the power according to the operating parameters and performing the switching frequency analysis to obtain the effective frequency data, the system calculates the instantaneous power of the chip according to the collected working voltage V and working current I. The switching frequency analysis uses the fast Fourier transform (FFT) to process the voltage and current waveforms and extract the fundamental and harmonic frequency components. The system compares the extracted frequency components with the preset frequency range and screens out the effective frequency data that meet the chip design specifications. The calculation period of this process is 10 μs to ensure that the system can quickly respond to the chip state changes. The processing result is a set of effective frequency data, including the frequency values and their corresponding power distributions.

[0028] In the stage of extracting basic chip parameters from the operating parameters, the system extracts basic chip parameters such as switching time, channel resistance, breakdown voltage, gate threshold voltage, and thermal resistance from the collected operating parameters. The extraction process uses a parameter identification algorithm, which is based on a pre-established parameter model and extracts each parameter value by fitting the measured data curve using the least squares method. The system validates the effectiveness of the extracted parameters, eliminates outliers, and ensures the accuracy of the parameters. The processing result is a set of basic chip parameters, which are stored in the form of structured data.

[0029] In the stage of associating the effective frequency data with the basic chip parameters to obtain the set of effective operating parameters, the system establishes a frequency-parameter mapping matrix, and the matrix elements represent the association strength between the frequency and the parameters. The association strength is determined based on sensitivity analysis and characterizes the sensitivity of the parameters to changes in frequency. The system calculates the effective values of each parameter under the current frequency condition through a weighted summation method. The association process follows the principle of physical consistency to ensure that the association result conforms to the physical characteristics of the device. The processing result is a set of effective operating parameters, which includes the effective values of each parameter under the current frequency condition.

[0030] In the stage of coupling the material dielectric constant, interlayer thermal conductivity, and interface stress distribution of the composite structure characteristic data to obtain the structure coupling coefficient, the system establishes a multi-physics field coupling model, including the electric field, thermal field, and stress field. The material dielectric constant affects the electric field distribution, the interlayer thermal conductivity determines the heat conduction characteristics, and the interface stress affects the material interface characteristics. The system uses the finite element method to solve the three-field coupling equations and calculates the distribution of each physical quantity in the structure. The coupling calculation considers the influence coefficient of temperature on the dielectric constant, the influence coefficient of stress on the thermal conductivity, and the influence coefficient of the electric field on the interface stress. The processing result is the structure coupling coefficient, which represents the coupling strength between different physical quantities.

[0031] In the stage of correcting the set of effective operating parameters based on the structure coupling coefficient to obtain the corrected operating parameters, the system applies the structure coupling coefficient to the set of effective operating parameters and calculates the corrected parameters. The correction process considers the mutual influence between parameters to avoid errors caused by simple linear superposition. For key parameters such as breakdown voltage and thermal resistance, the system uses a more detailed correction model to ensure the correction accuracy. The correction process follows the conservative principle and tends to select safer parameter values in case of data uncertainty. The processing result is a set of corrected operating parameters, which reflects the actual device characteristics considering the structure coupling effect.

[0032] In the stage of analyzing the staged characteristics of TVS-MOSFET with the corrected operating parameters to obtain the real-time status information of the chip, the system substitutes the corrected operating parameters into the TVS-MOSFET device model to analyze the characteristics of the device in different operating stages. The staged characteristic analysis includes four stages: normal conduction state, blocking state, avalanche breakdown state, and thermal stability analysis. The system calculates the key indicators in each state, such as conduction loss, blocking leakage current, avalanche energy, junction temperature, etc. The system compares the calculation results with the preset safety threshold to determine whether the current state of the chip is safe. If a certain indicator exceeds the safe range, the system generates a corresponding warning signal. The processing result is the real-time status information of the chip, including the current values of each indicator and the safety status flag.

[0033] In this embodiment, by obtaining the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide startup control chip, the working state of the chip can be monitored in real time, improving the accuracy and response speed of chip protection. By processing the voltage and current waveforms through fast Fourier transform (FFT) to extract effective frequency data, the accuracy of frequency analysis is ensured, avoiding the influence of frequency distortion on chip operation. By using the parameter identification algorithm to extract the basic parameters of the chip and conducting validity verification, the accuracy and reliability of the parameters are guaranteed. By establishing a frequency-parameter mapping matrix and a multi-physical field coupling model, the mutual influence between parameters can be comprehensively considered, ensuring the scientificity and practicality of the corrected operating parameters. By analyzing the staged characteristics of TVS-MOSFET, the key indicators of the chip in different operating states can be comprehensively evaluated, providing comprehensive real-time status information of the chip. This protection method can quickly respond to abnormal states such as overvoltage, overcurrent, and overheating in practical applications, effectively extending the service life of the chip and improving the reliability and stability of the system.

[0034] In one embodiment, analyzing the staged characteristics of TVS-MOSFET with the corrected operating parameters to obtain the real-time status information of the chip includes: In the process of analyzing the staged characteristics of TVS-MOSFET with the corrected operating parameters, it is first necessary to obtain the operating parameters of the chip. These operating parameters need to be corrected to accurately reflect the actual situation of the chip in different operating states. The corrected parameters will be used as input data for subsequent analysis and calculation.

[0035] Perform thermoelectric field coupling calculations on the corrected operating parameters to obtain a nanoscale heat flux distribution map. The key to this step lies in adopting a scientific thermoelectric field coupling model. By substituting the corrected operating parameters into this model, the thermoelectric field distribution of the chip under working conditions is simulated. During the thermoelectric field coupling calculation, it is necessary to consider the thermal conductivity, electrical conductivity of the chip material and their temperature dependencies. Through numerical calculation methods, a nanoscale heat flux distribution map inside the chip can be obtained. This heat flux distribution map shows the heat flux density in different regions of the chip, reflecting how the heat generated during the chip's operation conducts internally.

[0036] Based on the heat flux distribution map, perform an analysis of the tunneling current density in the TVS structure to obtain the leakage current characteristic curve in the subthreshold region. Using the heat flux distribution map, further analyze the tunneling current density in the TVS structure. Specifically, the heat flux distribution map provides temperature information for each region of the chip, and temperature changes will affect the generation and conduction of tunneling current. Therefore, by combining the heat flux distribution map and the tunneling current density model, the tunneling current density distribution of the chip at different temperatures can be obtained. By processing these data, the leakage current characteristic curve in the subthreshold region is plotted, and this curve reflects the leakage characteristics of the chip in the subthreshold state.

[0037] Perform Gaussian orthogonal polynomial fitting on the leakage current characteristic curve in the subthreshold region to obtain a set of target inflection point parameters. Use the Gaussian orthogonal polynomial fitting method to fit the leakage current characteristic curve in the subthreshold region. During the fitting process, it is necessary to select appropriate polynomial orders and weights so that the fitting curve can accurately reflect the trend of the original leakage current characteristic curve. Through fitting, a set of target inflection point parameters is obtained, and these parameters include the coordinates and eigenvalues of the inflection points. The set of target inflection point parameters provides the necessary data support for subsequent calculations.

[0038] Based on the set of target inflection point parameters, perform calculations on the degradation of the carrier mobility in the MOSFET channel to obtain the interface trap distribution function. Through the set of target inflection point parameters, calculate the degradation of the carrier mobility in the MOSFET channel. The degradation of carrier mobility is due to the influence of interface traps, and the distribution of interface traps is deduced through the set of target inflection point parameters. Specifically, establish an interface trap distribution function model and substitute the set of target inflection point parameters into this model to obtain the interface trap distribution function of the chip under different working conditions. The interface trap distribution function reflects the density and distribution of interface traps at different positions and is an important parameter for describing the degradation behavior of the chip.

[0039] The interface trap distribution function and the heat flux distribution map are adaptively grid - fused to obtain the real - time state information of the chip. The interface trap distribution function and the heat flux distribution map are two important parameters describing the chip state. By adaptively grid - fusing these two parameters, the real - time state information of the chip is obtained. The process of adaptive grid fusion includes steps such as grid division, data interpolation, and fusion calculation. First, the chip needs to be divided into several grid units, and the data within each grid unit needs to be interpolated so that the interface trap distribution function and the heat flux distribution map are consistent within the same grid. Then, through the method of fusion calculation, the data of the interface trap distribution function and the heat flux distribution map are synthesized to obtain the real - time state information of the chip. These real - time state information include the temperature distribution, current distribution, and interface trap distribution of the chip under different working states.

[0040] In this embodiment, by analyzing the step - by - step characteristics of TVS - MOSFET for the corrected operating parameters, the real - time state monitoring and evaluation of the chip can be realized, and the reliability of the chip under high - voltage conditions is improved. By performing thermoelectric field coupling calculation on the corrected operating parameters, the obtained nano - scale heat flux distribution map can accurately reflect the heat conduction situation inside the chip, which helps to optimize the heat dissipation design and reduce the risk of chip failure caused by overheating. Based on the heat flux distribution map, the tunneling current density analysis of the TVS structure is carried out, and the obtained leakage characteristic curve in the sub - threshold region can help to identify the leakage behavior of the chip under specific working states, so as to optimize the circuit design and reduce the leakage loss. By fitting the leakage characteristic curve in the sub - threshold region with Gaussian orthogonal polynomials, the target inflection point parameter set is obtained, which can accurately describe the electrical characteristic inflection points of the chip and provide a reliable basis for further carrier mobility degradation calculation. According to the target inflection point parameter set, the carrier mobility degradation calculation of the MOSFET channel is carried out, and the obtained interface trap distribution function can effectively predict the degradation behavior of the chip and extend the service life of the chip. The interface trap distribution function and the heat flux distribution map are adaptively grid - fused to obtain the real - time state information of the chip, which provides a scientific basis for the real - time monitoring and dynamic adjustment of the chip operating state, and helps to improve the operating efficiency and stability of the chip. In summary, this method has significant advantages in chip protection and optimization.

[0041] In one embodiment, the gate charging curve of the ultra - high - voltage silicon carbide start - up control chip is obtained and correlated with the real - time state information of the chip to obtain multi - threshold protection parameters, including: The gate voltage sampling uses a high-precision ADC module to capture the voltage change between the gate and source during the startup phase. The sampling time window covers the complete startup cycle of the chip, and the voltage range covers the operating voltage range of the chip. The preset rules require that the sampling rate meet the Nyquist criterion of the signal bandwidth to ensure the complete capture of the voltage transient characteristics. The original gate voltage data contains a discrete voltage sequence and synchronously recorded operating condition parameters. The data acquisition process follows the signal integrity specification, providing a time-voltage two-dimensional data matrix for subsequent processing.

[0042] The original gate voltage data is passed through a low-pass filter to eliminate high-frequency switching noise. The filtering parameters are set according to the signal characteristic frequency and the maximum allowable distortion rate. The filtered data is reconstructed into a continuous curve using the interpolation method, and the interval between interpolation nodes meets the curve smoothness requirements. The generated gate charging curve exhibits the characteristics of three stages: pre-charging, rapid voltage rise, and steady-state saturation. The curve fitting residual is controlled within the allowable range of the system, meeting the signal fidelity requirements of the TVS-MOSFET cooperative working mode.

[0043] The critical time points of the charging curve stages are determined by the differential extreme value detection algorithm. The preset rules set the threshold of the slope change rate between adjacent stages to mark the state turning points. When the algorithm is executed, the maximum curvature points and slope mutation points of each stage are detected. The extracted segmented charging characteristic parameters include the duration, voltage slope, and steady-state error band of each stage, fully characterizing the dynamic process characteristics of gate charge injection.

[0044] Based on the heat flux distribution data in the real-time state information of the chip, the temperature compensation of the charging characteristic parameters is performed. The compensation coefficient is calculated according to the local junction temperature and the material thermoelectric characteristic model. The normalization process eliminates the timing drift caused by temperature, and the generated curve maintains the stability of the stage parameters within the specified temperature range. The compensation model parameters are derived from the research data of silicon carbide material characteristics, ensuring temperature adaptability.

[0045] The historical safe operation database contains verified gate charging records, and the data cleaning rules eliminate abnormal operating conditions. The normalized charging characteristic curve is dynamically matched with the historical data to calculate the parameter deviation of each stage. The critical safety boundary value is dynamically adjusted according to the statistical principle and the degradation factor in the real-time state information, ensuring that the safety margin covers the normal operating condition range.

[0046] The critical safety boundary value and the real-time state information of the chip generate multi-threshold protection parameters through a multi-objective optimization algorithm. The lower voltage threshold is set comprehensively considering the steady-state voltage characteristics and thermal effects. The overcurrent protection threshold is dynamically adjusted according to the slope safety margin, and the time delay protection threshold is associated with the interface trap distribution state. The set of protection parameters is written into the hardware logic unit to form an adaptive overvoltage, overcurrent, and timing anomaly protection mechanism.

[0047] The gate voltage sampling rate meets the requirements of signal reconstruction theory, and the filtering parameters prevent the loss of effective signal components. The phase critical point detection threshold corresponds to the safety margin of the device's physical limit, and the temperature compensation model is established based on material characteristic data. Historical data analysis uses statistical anomaly detection methods, and the weight assignment of the multi-threshold optimization algorithm conforms to the stability priority of the ultra-high voltage system.

[0048] Among them, the original voltage noise reflects the carrier effect of the device switching process, and the stage characteristics of the charging curve correspond to the physical process of gate capacitance charging and discharging. Temperature compensation eliminates the influence of the temperature variation effect of the material bandgap, and the adjustment of the safety boundary reflects the degradation law of the charge storage capacity caused by interface traps. The multi-threshold parameters are dynamically correlated with the distribution state of the thermal-electric coupling field to ensure that the protection strategy matches the real-time degradation state of the chip.

[0049] In this embodiment, through high-precision sampling and noise cancellation processing of the gate voltage, the transient voltage characteristics of the ultra-high voltage silicon carbide startup control chip are accurately captured, providing a high-fidelity signal basis for subsequent analysis and effectively avoiding misjudgment and missed detection problems. The temperature compensation algorithm based on the heat flow distribution eliminates the influence of environmental and operating condition changes on the charging characteristics, enabling the normalized charging curve to maintain parameter consistency within a wide temperature range and improving the system robustness. By dynamically calculating the multi-threshold protection parameters in combination with historical safety data and real-time status information, the coordinated protection against overvoltage, overcurrent, and timing anomalies is realized, ensuring the operation reliability of the ultra-high voltage silicon carbide chip under complex degradation scenarios such as interface trap accumulation and thermal stress fluctuation. By executing the adaptive protection strategy in real time through the hardware logic unit, the fault response time is significantly shortened, avoiding the lag or false triggering problems existing in the traditional fixed-threshold protection mechanism during sudden changes in operating conditions.

[0050] In one embodiment, the current change data of the ultra-high voltage silicon carbide startup control chip is obtained, and the Miller plateau characteristics of the chip real-time status information are analyzed to obtain the current anomaly trend, including: The current sensor captures the current data in the startup stage at a preset sampling rate, and the sampling window covers the duration of the Miller plateau. The Miller plateau determination is based on the current change rate threshold and the duration rule, and the fluctuation coefficient is calculated using the sliding window standard deviation algorithm, and the window width matches the device switching characteristics. The extracted fluctuation coefficient sequence is processed by the signal decomposition method to reconstruct and generate the Miller plateau current characteristic function. The processing results show the amplitude fluctuation and oscillation frequency characteristics of the characteristic function, which are related to the gate charge redistribution process, providing a dynamic current characteristic benchmark for subsequent analysis.

[0051] The spectral analysis is synchronously performed on the Miller platform current characteristic function and the heat flux distribution data in the real-time state information of the chip, and the harmonic analysis range covers the resonance frequency range of the device parasitic parameters. The temperature compensation factor is introduced in the calculation process to correct the temperature drift effect of the material, and the harmonic distribution map is generated. The abnormal frequency points and their spatial coordinates are marked in the map. The region with abnormal odd harmonic amplitude coincides with the local hot spot position of the chip, reflecting the carrier mobility degradation effect. The frequency domain characteristics of the harmonic distribution map provide input for abnormal current identification.

[0052] The harmonic distribution map separates the nonlinear current components through a nonlinear system identification model, and the order of the kernel function and the memory length are set according to the physical characteristics of the device. The amplitude and time distribution characteristics of the identified nonlinear current components are related to the gate coupling effect. The abnormal current waveform extracts the feature vectors through a pattern matching algorithm, including waveform kurtosis, skewness and zero-crossing rate parameters. The similarity between the feature vectors and the historical fault database quantifies the abnormal level, and the abnormal current feature vectors are output.

[0053] The trend prediction based on the abnormal current feature vectors adopts a time series neural network model, and the input layer fuses the current sequence, interface trap density and heat flux gradient parameters. The model training data covers the historical records under typical working conditions, and the prediction time step matches the driving protection period. The generated predicted current curve marks the potential risk time points and the amplitude change trend, and the curve morphological characteristics reflect the oscillation mode migration caused by the change of parasitic parameters, providing input in the time dimension for abnormal trend determination.

[0054] The deviation coefficient is calculated by the sliding window correlation analysis between the predicted current curve and the actual sampling data, and the threshold is set according to the statistical law of historical data. The abnormal probability is calculated by integrating the harmonic distortion rate, heat flux density gradient and interface trap density parameters, and the abnormal trend data is output. The data set contains fields such as time stamp, abnormal level and spatial coordinates. The coordinates of the abnormal region match the physical defect position of the chip, revealing the correlation mechanism between the Miller platform collapse and the thermoelectric coupling field.

[0055] The abnormal trend data and the nano-scale heat flux distribution map are superimposed and analyzed through a multi-resolution grid registration algorithm, and the grid division accuracy is set according to the device structure characteristics. The high-risk area determination condition generates a composite criterion based on the safety thresholds of current density, temperature and trap density. The analysis result marks the multi-parameter collaborative over-standard area, and its spatial distribution verifies the positive feedback mechanism of trap generation caused by hot electron injection. The finally generated conclusion of the current abnormal trend quantifies the local breakdown risk level and drives the adjustment of the dynamic protection strategy.

[0056] The determination threshold of the Miller platform is derived based on the theoretical relationship between the device Miller capacitance and the driving resistance. The window algorithm parameters match the switching transient response time scale. The harmonic analysis range covers the upper limit of the parasitic parameter resonance frequency. The temperature compensation model is established based on the thermoelectric characteristics of silicon carbide materials. The order of the nonlinear identification kernel function reflects the depth of the memory effect of the gate kickback voltage. The dimension of the input layer of the neural network is designed to meet the requirements of multi-physical field coupling modeling. The deviation coefficient threshold is set through statistical analysis of historical data. The condition parameters of the high-risk area are derived from the material reliability experiment database.

[0057] The oscillation frequency of the characteristic function of the Miller platform current maps the degradation degree of the gate charge storage capacity. There is a spatial correlation between the abnormal frequency points of the harmonic distribution map and the interface trap density. The change in the oscillation mode of the predicted current curve reflects the parasitic capacitance migration caused by gate oxide layer defects. The deviation coefficient over-limit area verifies the distortion effect of the thermally generated carrier transport path. The phenomenon of multi-parameter collaborative over-standard in the fine-grained analysis reveals the thermal-electric-defect coupling mechanism, providing a physical failure warning basis for adaptive protection.

[0058] In this embodiment, through the extraction of the Miller platform fluctuation coefficient and the construction of the current characteristic function, the change of the gate charge storage characteristics is accurately captured, the early identification of current anomalies is realized, and the risk of local breakdown is effectively prevented. Combining the harmonic distribution map analysis with temperature compensation, the abnormal frequency points excited by interface traps are accurately locked, improving the spatial resolution and reliability of fault location. Based on the nonlinear component identification and the neural network prediction model, the current oscillation trend is predicted in advance, providing a time margin for the dynamic protection strategy and avoiding the lag problem of traditional threshold protection. The fine-grained area analysis with multi-parameter collaboration establishes a coupling relationship model of current density, heat flux distribution and interface traps, realizing the accurate positioning and hierarchical disposal of high-risk areas. Through the abnormal trend determination mechanism integrating multi-physical fields, the protection action trigger logic is extended from a single electrical parameter to the dimension of the collaborative evolution of thermoelectric defects, significantly improving the adaptability and robustness of chip protection under ultra-high voltage conditions.

[0059] In one embodiment, temperature control construction is performed on multi-threshold protection parameters and current anomaly trends to obtain an initial control scheme, including: Based on the time-current sequence of the current anomaly trend data set, the sliding time window is used to calculate the current change gradient. The window width matches the device thermal response time constant. The gradient threshold is set according to the temperature rise characteristics of silicon carbide materials. The gradient calculation uses the difference method, and the overlapping rate of adjacent windows is not less than the preset ratio to maintain data continuity. The processing result generates a temperature compensation coefficient, which is linearly related to the real-time junction temperature data. The compensation coefficient mapping rule is established based on the material temperature sensitivity characteristic model. The temperature compensation coefficient is dynamically adjusted according to the temperature rise amplitude of the local hot spot area, reflecting the sensitivity of the current change to the thermal field evolution.

[0060] The temperature compensation coefficient acts on the lower voltage threshold, overcurrent protection threshold, and time delay threshold. The voltage threshold adjustment model introduces a junction temperature compensation factor. The overcurrent threshold is adjusted inversely proportionally according to the temperature compensation coefficient. The time delay threshold establishes a non-linear mapping relationship with the interface trap density and temperature gradient. The adjustment process follows the preset threshold coupling constraint conditions to ensure the consistency of the voltage-current-time collaborative protection logic. The generated set of temperature-corrected thresholds contains upper and lower limit parameters that change dynamically, and the threshold parameters are updated in real time according to the chip thermal state, forming an adaptive protection boundary that matches the heat flux distribution.

[0061] The temperature-corrected thresholds and current anomaly trend data are fused through a multi-dimensional vector space mapping algorithm. The spatial dimensions include four-dimensional coordinates of voltage amplitude, current density, time series, and temperature gradient. The weight coefficients of each dimension are assigned according to the statistical results of historical fault modes. The construction process uses the principal component analysis method for dimensionality reduction, retaining the principal component vectors with a contribution rate exceeding the preset threshold. The generated multi-dimensional protection space presents a non-linear decision boundary, and the boundary shape reflects the combined influence law of the thermo-electric coupling field on the protection threshold, providing a spatial topology basis for zoning optimization.

[0062] The multi-dimensional protection space is divided into temperature-graded protection regions through a clustering algorithm. The number of cluster centers is set according to the number of chip thermally sensitive regions, and the cluster radius is associated with the heat flux gradient threshold. The optimization process performs iterative centroid updates, and the objective function requires that the temperature fluctuation range within the same partition does not exceed the safety margin of the material thermal stress. The partition results are marked with three temperature levels: the core region, the transition region, and the safe region. The core region corresponds to the region with high interface trap density and high current density, and the safe region meets the temperature-current joint safety criterion. The protection thresholds for each partition are dynamically generated according to the cluster center coordinates, forming a stepped temperature response protection mechanism.

[0063] The timing strategy for the temperature-graded protection regions is designed based on the principle of matching the thermal time constant and the circuit response speed. The core region executes millisecond-level rapid derating protection, the transition region enables a second-level periodic threshold recalibration mechanism, and the safe region maintains a conventional monitoring mode. The timing plan introduces a priority scheduling algorithm. When anomalies are triggered in multiple regions simultaneously, the protection instructions for the core region are executed first. The control timing is synchronized with the chip operating cycle to ensure that the protection action is completed within the device thermal inertia time window. The generated dynamic protection strategy contains an instruction sequence with time-space collaborative response, realizing the hierarchical optimization configuration of protection resources.

[0064] Construct a power loss prediction model based on abnormal current trend data. The input variables include current density, voltage deviation, and temperature gradient. The model adopts a method that combines physical mechanism and data-driven approach. It calculates the steady-state heat loss through a thermal resistance network model and predicts the peak value of transient loss by combining with a time series neural network. The prediction results generate a spatio-temporal distribution map of power loss. The high-loss regions in the map coincide with the core regions of temperature hierarchical protection, verifying the coupling relationship of thermoelectric energy conversion. The power loss prediction data quantifies the heat accumulation trend under different protection strategies, providing an energy dimension constraint for control optimization.

[0065] The power loss prediction data corrects the dynamic protection strategy through a multi-objective optimization algorithm. The optimization objective function includes three indicators: peak temperature suppression, minimum energy loss, and protection response speed. The constraint conditions are set as the voltage volatility threshold and the current stability boundary. The genetic algorithm is used in the optimization process to search for the Pareto optimal solution set, and the strategy with the highest comprehensive score is selected as the initial control scheme. The final scheme includes temperature adaptive threshold parameters, hierarchical protection time series instructions, and loss suppression strategies, forming a three-dimensional collaborative protection control system of heat-electricity-time.

[0066] The width of the current gradient analysis window matches the thermal response time constant of the device to ensure the accuracy of transient thermal effect capture. The temperature compensation coefficient mapping rule is established based on the experimental data of the temperature-sensitive characteristics of the carrier mobility in silicon carbide. The contribution rate threshold of the principal component analysis in the dimension space construction is set according to the variance interpretation rate of historical data. The temperature partition clustering radius is related to the thermal expansion coefficient of the material to prevent thermal stress from exceeding the limit. The priority scheduling algorithm for time series planning is sorted according to the fault hazard level, and the parameters of the power loss prediction model are derived from the law of energy conservation and the thermal resistance parameters of the device.

[0067] The current change gradient reflects the rate of Joule heat accumulation, and the temperature compensation coefficient quantifies the drift effect of thermoelectric parameters. The non-linear boundary of the multi-dimensional protection space characterizes the coupling strength of the thermal field and the electric field, and the optimization results of the temperature partition verify the spatial correlation between the heat flow path and the structural defects. The time series planning of the dynamic protection strategy matches the thermal inertia delay characteristics, and the power loss prediction data maps the balance relationship between energy conversion efficiency and heat dissipation capacity. The optimized initial control scheme realizes the collaborative control of thermal runaway prevention and electrical performance stability, providing a multi-physical field collaborative protection mechanism for ultra-high voltage silicon carbide chips.

[0068] In this embodiment, by generating current change gradient analysis and temperature compensation coefficient, the sensitivity difference of the thermal field distribution to current anomalies is dynamically perceived, and the adaptability of protection parameters in the temperature change scenario is improved. Based on the adaptive adjustment mechanism of the temperature correction threshold, the collaborative optimization of the protection boundaries of voltage, current, and time is realized, overcoming the problem of protection failure of traditional fixed thresholds in the thermal-electric coupling scenario. The construction of a multi-dimensional protection space integrates the characteristics of thermal field, electric field, and time evolution, establishes a non-linear decision boundary, and enhances the comprehensive protection ability for anomaly determination under complex working conditions. The division and optimization of the temperature grading protection area realize the accurate positioning and differential control of the chip's thermally sensitive area, reducing the performance loss caused by global temperature control. The timing planning of the dynamic protection strategy matches the thermal inertia characteristics and the circuit response speed, ensuring that the protection action is effectively triggered before the thermal runaway critical point. The joint mechanism of power loss prediction and temperature control optimization balances the relationship between thermal accumulation suppression and energy efficiency, forming a control scheme for the collaborative optimization of thermal stability and electrical performance.

[0069] In one embodiment, a fault self-diagnosis is performed on the real-time status information of the chip to obtain a fault warning message, and a fault prediction is performed with the gate charging curve to obtain a potential fault area, including: Based on the multi-node voltage sampling data in the real-time status information of the chip, the voltage transient values of each functional module are captured by a voltage sensor network at a preset sampling rate. The node voltage threshold is set according to historical safe operation data, and the offset threshold is determined based on the safety margin of the chip design specifications. The threshold offset analysis uses the sliding window difference method, the window width matches the chip clock cycle, and the difference threshold is set as a percentage range of the nominal voltage. The processing result generates a set of node anomaly metric values, including voltage offset amplitude, duration, and spatial distribution coordinates. The anomaly area coordinates match the layout of the chip functional modules, providing an input basis for probability modeling.

[0070] The node anomaly metric values are cumulatively distributed and modeled by the probability density estimation method, and the bandwidth parameter is adaptively adjusted according to the sample distribution characteristics. The distribution calculation covers the dimensions of time, space, and voltage offset, and the generated probability distribution map marks the high-probability anomaly areas. The figure shows that the fault probability in a specific functional area increases significantly, and there is a spatial correlation between the peak area of the probability density and the hot spot position of the real-time heat flow distribution. The resolution of the probability distribution map matches the chip structure characteristics, providing a statistical benchmark for warning parameter fusion.

[0071] The temperature field data and node voltage data in the real-time status information of the chip extract the correlation characteristics through the correlation analysis method, and the width of the sliding time window is set as the proportional value of the thermal dynamic response period. The correlation analysis identifies the coupling relationship between specific node voltage offsets and local temperature increases, and the extracted temperature-voltage coupling coefficient is incorporated into the early warning parameter set. The fault early warning parameter set integrates the probability distribution value, the temperature-voltage coupling coefficient, and the historical fault characteristics, and generates a comprehensive early warning level through the weighted fusion algorithm. The spatial distribution characteristics of the parameter set are consistent with the trend of the interface trap density gradient, verifying the effectiveness of the parameters.

[0072] The preset fault type table contains typical fault modes and their characteristic parameter threshold intervals, and each type of fault corresponds to a combination of electrical, thermal, and material characteristic parameters. The early warning parameter set is matched with the fault type table through the multi-dimensional space similarity algorithm, and the similarity measurement method eliminates the influence of dimensional differences. The matching result generates early warning identification information including the fault type, probability level, and spatial coordinates. The spatial distribution in the identification information coincides with the key structural positions such as the high-voltage nodes and heat dissipation paths of the chip, reflecting the physical relevance of the fault mechanism.

[0073] The fault type early warning identification information is input into the multi-physics field simulation model to calculate the voltage stress distribution in each region of the chip. The model boundary conditions are set according to the dynamic characteristics of the gate charging curve, and the material parameters adopt the physical property database of silicon carbide devices. The calculation result generates a pressure operation interval map, marking the high-risk regions where the voltage stress exceeds the safety threshold. The map shows the stress concentration phenomenon in a specific working stage, and the spatio-temporal distribution characteristics are associated with the degradation trend of parasitic parameters, providing the field distribution input for the critical value prediction.

[0074] The process of calculating the voltage stress distribution in each region of the chip is as follows: The fault type early warning identification information and the time-voltage relationship of the gate charging curve are fused through the spatio-temporal grid mapping algorithm to generate the dynamic voltage field data of each node of the chip. Based on the voltage deviation (the difference between the abnormal voltage value and the nominal voltage) and the dielectric characteristics of the gate oxide layer, the voltage stress distribution is calculated through the electric field stress intensity formula. The calculation process dynamically corrects the steady-state field strength in the Miller plateau stage and the displacement current effect in the voltage transient stage, and sets the safety margin in combination with the silicon carbide breakdown field strength threshold. The finally generated pressure operation interval map marks the high electric field strength regions in the spatio-temporal dimension, and its spatial coordinates overlap with the fault early warning region, and the time window matches the transient process of the charging curve, forming a multi-dimensional risk judgment benchmark.

[0075] Among them, the core formula for calculating the voltage stress distribution is ; : Voltage stress intensity (unit: V / cm); : Fault early warning voltage value (unit: V); : Nominal voltage (unit: V); : Relative dielectric constant of the gate oxide layer; Thickness of the gate oxide layer (unit: cm); x, y: Spatial coordinates of the chip; t represents the time point.

[0076] Based on the multi-field coupling data in the pressure operation range, the critical values of parasitic parameters are calculated through a device physics model. The model introduces the influence mechanism of temperature on material properties, and the critical value prediction formula contains a temperature compensation factor. The prediction results generate data for the avalanche breakdown prediction region, marking the spatio-temporal regions where the electric field strength is close to the material breakdown threshold. The time window of the prediction region is synchronized with the transient process of the gate charging curve, and the spatial distribution corresponds to the layout of the power units in the chip layout, verifying the physical rationality of the prediction model.

[0077] The data of the avalanche breakdown prediction region and the gate charging curve are cross-validated through the spatio-temporal consistency rule. The verification process requires that the change trend of the electric field strength in the prediction region is synchronized with the electrical characteristic events of the charging curve. The processing results mark the potential failure regions that meet the spatio-temporal consistency conditions, and the region boundaries overlap with the chip's thermally sensitive structures and the distribution of high-voltage nodes. The finally determined potential failure regions include a time evolution sequence and spatial sub-regions, providing multi-dimensional inputs for targeted protection strategies.

[0078] The safety margin of the voltage threshold offset is set according to the device reliability experiment standard, and the cumulative probability modeling method follows the statistical distribution theory. The window width of the temperature-voltage correlation analysis matches the thermal conduction time scale, and the multi-dimensional similarity algorithm for fault type matching is based on the pattern recognition theory. The material parameters of the voltage stress model are derived from the physical property database, and the critical value prediction formula of the parasitic parameters is deduced through physical mechanisms. The cross-validation rule ensures the spatio-temporal evolution consistency of multi-field data.

[0079] The node voltage offset reflects the barrier distortion effect caused by charge injection, and the cumulative probability distribution reveals the statistical law of defect evolution. The temperature-voltage correlation verifies the hot carrier excitation mechanism, and the voltage stress concentration region maps the interaction between electric field distortion and material microstructure. The spatio-temporal characteristics of the avalanche breakdown prediction data reflect the coupling relationship between parasitic parameter degradation and switching transients, and the cross-validation results confirm the fault mechanism of the combined action of multiple physical fields. The determination of the potential failure region provides an accurate spatial reference and time window for dynamic protection.

[0080] In this embodiment, through the threshold shift analysis of the chip node voltage, local voltage anomalies are sensed in real time and node anomaly metric values are generated, improving the sensitivity and localization accuracy of early fault detection. Based on the fault probability distribution map calculated from the cumulative probability distribution, the failure risk levels of each region of the chip are quantified, realizing a multi-level early warning system from global to local. The temperature-voltage correlation characteristics extract and fuse the thermal field and electric field data, enhancing the physical correlation of the fault early warning parameter set and overcoming the misjudgment problem of single-parameter diagnosis. The spatio-temporal correlation analysis of the fault type early warning identification information and the gate charging curve accurately locates the high-voltage stress region and the transient risk window, forming a multi-dimensional basis for protection decisions. The cross-validation mechanism for the avalanche breakdown prediction region data, through the physical consistency verification of the electric field strength and voltage characteristics, reduces the false alarm rate and improves the prediction credibility. The construction of the dynamic pressure operating range and the prediction of the parasitic parameter critical values realize the quantitative evaluation and preventive maintenance of the chip degradation state, extending the service life of the device.

[0081] In one embodiment, a clamping-off strategy is constructed for the initial control scheme and the potential fault region to obtain a chip startup protection strategy, including: Data collection and model construction are carried out on parameters such as the breakdown voltage, thermal conductivity, and carrier mobility of the silicon carbide material to form a complete set of material characteristic data. On this basis, a non-linear threshold classification model is constructed according to the material characteristic parameters under different working voltages and temperature conditions, so as to obtain the adaptive voltage protection threshold data. This data can be dynamically adjusted according to the changes in the actual working environment to ensure effective voltage protection under different working conditions.

[0082] Differential feature extraction and analysis of the fluctuation characteristics of the fault precursor signals for the potential fault region are one of the key steps in the protection strategy. High-precision sensors are used to monitor parameters such as current, voltage, and temperature of the potential fault region in real time, and differential algorithms are used to extract the features of the collected signals. By analyzing the fluctuation characteristics of the fault precursor signals, the fault precursor feature vectors are identified. Specifically, the fault precursor feature vectors include information such as voltage fluctuation amplitude, fluctuation frequency, and fluctuation duration, which can reflect the possibility and severity of the chip malfunctioning during startup.

[0083] Based on the obtained adaptive voltage protection threshold data and fault precursor feature vectors, multi-phase response time curve analysis needs to be carried out, and a strategy is constructed to form a dynamic protection response strategy. Multi-phase response time curve analysis monitors the changes in voltage and current at different phases to find the response characteristics at specific time points. Combining the adaptive voltage protection threshold data and fault precursor feature vectors, a set of dynamic protection response strategies is constructed using the multi-phase response time curve analysis method. This strategy can adjust the protection response time according to the actual situation at different starting phases, thereby improving the startup protection effect of the chip.

[0084] After obtaining the dynamic protection response strategy, it is necessary to perform fast and slow double clamped voltage analysis based on a preset second-order damping coefficient regulation algorithm. The second-order damping coefficient regulation algorithm controls the rising and falling rates of voltage by adjusting the damping coefficient of the system. Specifically, in the fast clamped voltage state, the system quickly reduces the voltage to avoid overvoltage damage to the chip; in the slow clamped voltage state, the system gently reduces the voltage to ensure that voltage changes do not cause unnecessary oscillations. Through fast and slow double clamped voltage analysis, a dual-channel clamped control instruction is obtained.

[0085] According to the dual-channel clamped control instruction, variable slope control analysis is performed on the drive circuit to generate an intelligent turn-off control signal. Variable slope control analysis optimizes the startup and shutdown processes of the circuit by adjusting the control slope of the drive circuit. During the high-voltage startup process, the intelligent turn-off control signal can adjust the startup slope of the circuit according to the actual situation to avoid faults caused by too rapid voltage changes. At the same time, the intelligent turn-off control signal can also quickly turn off the circuit when necessary to protect the chip from damage.

[0086] Based on the intelligent turn-off control signal and the dual-channel clamped control instruction, the initial control scheme is optimized for startup protection to form a chip startup protection strategy. By optimizing the initial control scheme, not only can the startup stability of the chip be improved, but also effective protection can be provided when potential faults occur. The chip startup protection strategy can be dynamically adjusted according to the actual working conditions to ensure that the chip can achieve the best protection effect in different startup environments.

[0087] In this embodiment, by introducing a non-linear threshold grading processing technology into the over-high voltage silicon carbide startup control chip protection method, the voltage protection threshold can be dynamically adjusted according to different working voltage and temperature conditions, ensuring reliable voltage protection in various working environments, and significantly improving the adaptability and flexibility of the protection strategy. The differential feature extraction of potential fault areas and the analysis of the fluctuation characteristics of fault precursor signals enable the fault precursor feature vector to accurately reflect the potential fault risks during the chip startup process, so as to take effective preventive measures before the occurrence of faults, enhancing the protection ability of the system. The multi-phase response time curve analysis, combined with the adaptive voltage protection threshold data and the fault precursor feature vector, constructs a dynamic protection response strategy, making the protection response more accurate and efficient, and ensuring that the chip can obtain the best protection under different startup phases. The fast and slow dual clamping voltage analysis based on the second-order damping coefficient regulation algorithm avoids the damage to the chip caused by overvoltage and voltage oscillation by scientifically regulating the voltage change rate, improving the stability and reliability of the system. The variable slope control analysis of the drive circuit and the generation of intelligent shutdown control signals optimize the startup and shutdown processes of the circuit, effectively preventing faults caused by voltage changes while ensuring the circuit performance, and further improving the startup protection effect. The above methods optimize the chip startup protection scheme as a whole, significantly enhancing the stability and reliability of the system.

[0088] Referring to Figure 2 As shown, the present invention also provides an over-high voltage silicon carbide startup control chip protection system, which is applied to the over-high voltage silicon carbide startup control chip protection method of any one of the above, and includes: An acquisition module, which is used to acquire the operating parameters and composite structure characteristic data of the over-high voltage silicon carbide startup control chip, and perform TVS-MOSFET grading characteristic analysis to obtain the real-time state information of the chip; An analysis module, which is used to acquire the gate charging curve of the over-high voltage silicon carbide startup control chip, and perform correlation analysis with the real-time state information of the chip to obtain multi-threshold protection parameters; A correlation module, which is used to acquire the current change data of the over-high voltage silicon carbide startup control chip, and perform Miller platform characteristic analysis on the real-time state information of the chip to obtain the current anomaly trend; A processing module, which is used to construct temperature control for the multi-threshold protection parameters and the current anomaly trend to obtain an initial control scheme; A control module, which is used to perform fault self-diagnosis on the real-time state information of the chip to obtain a fault warning message, and perform fault prediction with the gate charging curve to obtain a potential fault area; An execution module, which is used to construct a clamping shutdown strategy for the initial control scheme and the potential fault area to obtain a chip startup protection strategy.

[0089] A super-high voltage silicon carbide startup control chip protection system provided by the present invention can more accurately evaluate the real-time status information of the chip by comprehensively analyzing the operating parameters and composite structure characteristic data of the startup control chip and combining with the step-by-step characteristic analysis of TVS-MOSFET, thereby improving the accuracy of the chip protection mechanism and providing a more reliable basis for the design and operation of the chip. By correlating the gate charging curve with the real-time status information of the chip, multi-threshold protection parameters are obtained to achieve refined management of the chip under different working conditions, which helps to identify abnormal current trends in advance and avoid damage to the chip caused by sudden abnormal currents during operation. Based on temperature control, an initial control scheme is constructed to ensure that the chip can operate efficiently at different working temperatures, reduce unnecessary energy consumption, and improve the overall operating efficiency of the chip. By performing self-diagnosis of faults on the real-time status information of the chip and combining with the gate charging curve for fault prediction, a more reasonable clamping-off strategy can be formulated, and the optimized startup protection of the chip can be achieved through comprehensive adjustment strategies, thereby effectively extending the chip life, reducing faults, and improving the stability and reliability of the system. By considering the influence of potential fault areas, the protection strategy can be flexibly adjusted according to different working scenarios, making the chip more adaptable to diverse application requirements.

[0090] It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described system and each module can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0091] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A protection method for a super-high voltage silicon carbide startup control chip, characterized in that, Including: Obtain the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide start control chip, and perform TVS-MOSFET step characteristic analysis to obtain the real-time status information of the chip; Obtain the gate charging curve of the ultra-high voltage silicon carbide start control chip, and perform correlation analysis with the real-time status information of the chip to obtain multi-threshold protection parameters; Obtain the current change data of the ultra-high voltage silicon carbide start control chip, and perform Miller plateau characteristic analysis on the real-time status information of the chip to obtain the current anomaly trend; Conduct temperature control construction on the multi-threshold protection parameters and the current anomaly trend to obtain an initial control scheme; Perform fault self-diagnosis on the real-time status information of the chip to obtain fault warning information, and perform fault prediction with the gate charging curve to obtain potential fault areas; Construct a clamping-off strategy for the initial control scheme and the potential fault areas to obtain a chip start protection strategy.

2. The method for protecting an ultra-high voltage silicon carbide startup control chip according to claim 1, wherein The obtaining of the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide start control chip, and performing TVS-MOSFET step characteristic analysis to obtain the real-time status information of the chip includes: Perform power calculation based on the operating parameters, and perform switching frequency analysis to obtain effective frequency data; Extract basic parameters from the operating parameters to obtain the chip basic parameters; Perform data association on the effective frequency data and the chip basic parameters to obtain an effective operating parameter set; Perform coupled calculations of material dielectric constant, interlayer thermal conductivity, and interfacial stress distribution on the composite structure characteristic data to obtain a structure coupling coefficient; Correct the data of the effective operating parameter set according to the structure coupling coefficient to obtain corrected operating parameters; Perform TVS-MOSFET step characteristic analysis on the corrected operating parameters to obtain the real-time status information of the chip.

3. The method for protecting an ultra-high voltage silicon carbide startup control chip according to claim 2, wherein The performing of TVS-MOSFET step characteristic analysis on the corrected operating parameters to obtain the real-time status information of the chip includes: Perform thermoelectric field coupling calculation on the corrected operating parameters to obtain a nano-scale heat flux distribution map; Perform TVS structure tunneling current density analysis based on the heat flux distribution map to obtain a subthreshold region leakage characteristic curve; Perform Gaussian orthogonal polynomial fitting on the subthreshold region leakage characteristic curve to obtain a target inflection point parameter set; Perform MOSFET channel carrier mobility degradation calculation according to the target inflection point parameter set to obtain an interface trap distribution function; Perform adaptive grid fusion on the interface trap distribution function and the heat flux distribution map to obtain the real-time status information of the chip.

4. The method for protecting an ultra-high voltage silicon carbide startup control chip according to claim 1, characterized in that, The obtaining of the gate charging curve of the ultra-high voltage silicon carbide start control chip, and performing correlation analysis with the real-time status information of the chip to obtain multi-threshold protection parameters includes: Perform gate voltage sampling on the ultra-high voltage silicon carbide start control chip to obtain original gate voltage data; Eliminate interference noise from the original gate voltage data and perform curve mapping to obtain the gate charging curve; Perform stage critical time point calculation on the gate charging curve to obtain segmented charging characteristic parameters; Performing temperature compensation calculation on the segmented charging characteristic parameters according to the real-time status information of the chip to obtain a normalized charging characteristic curve; Acquire historical safety operation data of the ultra-high voltage silicon carbide startup control chip, and perform deviation analysis on the normalized charging characteristic curve to obtain a critical safety boundary value; Threshold calculation is performed based on the critical safety boundary value and the real-time status information of the chip to obtain the multi-threshold protection parameter, wherein the multi-threshold protection parameter includes a voltage lower limit threshold, an overcurrent protection threshold and a time delay protection threshold.

5. The overhigh voltage silicon carbide startup control chip protection method according to claim 1, characterized in that The current change data of the ultra-high voltage silicon carbide startup control chip is obtained, and Miller platform characteristic analysis is performed on the real-time status information of the chip to obtain the abnormal current trend, including: Extracting the Miller platform fluctuation coefficient from the current change data to obtain the Miller platform current characteristic function; Calculate the current harmonic components according to the Miller platform current characteristic function and the chip real-time status information to obtain a harmonic distribution spectrum; Identifying nonlinear current components and abnormal current waveforms on the harmonic distribution spectrum to obtain a current abnormality feature vector; Predicting the current change trend according to the current abnormality characteristic vector to obtain a predicted current curve; Calculating the deviation coefficient and abnormal probability of the predicted current curve to obtain abnormal trend data; A Miller platform region fine-grained analysis is performed on the real-time status information of the chip according to the abnormal trend data to obtain the current abnormal trend.

6. The method for protecting an ultra-high voltage silicon carbide startup control chip according to claim 1, wherein The temperature control construction of the multi-threshold protection parameters and the current abnormality trend to obtain an initial control scheme includes: Performing current change gradient analysis on the abnormal current trend to obtain a temperature compensation coefficient; Adaptively adjusting the multi-threshold protection parameter according to the temperature compensation coefficient to obtain a temperature correction threshold; The temperature correction threshold and the current abnormal trend are constructed in a dimensional space to obtain a multi-dimensional protection space; Optimizing the temperature partitioning of the multi-dimensional protection space to obtain temperature graded protection areas; Performing control timing planning on the temperature graded protection areas to obtain a dynamic protection strategy; Performing loss prediction on the abnormal current trend to obtain power loss prediction data; The temperature control of the dynamic protection strategy is optimized according to the power loss prediction data to obtain an initial control scheme.

7. The method for protecting an ultra-high voltage silicon carbide startup control chip according to claim 1, characterized in that, The method of performing fault self-diagnosis on the real-time status information of the chip to obtain fault warning information and performing fault prediction with the gate charging curve to obtain a potential fault area includes: Calculating chip node voltages based on the chip real-time status information and performing threshold offset analysis to obtain node abnormality metrics; Performing cumulative probability distribution calculation on the node abnormality metric value to obtain a fault probability distribution graph; Extracting temperature-voltage correlation characteristics based on the real-time status information of the chip, and performing early warning correlation with the fault probability distribution diagram to obtain a fault early warning parameter set; According to the preset fault type table and the fault warning parameter set, matching is performed to obtain fault type warning identification information; Perform voltage stress distribution calculation on the fault type warning identification information and the gate charging curve to obtain the pressure operation range; Predict the critical value of the chip parasitic parameters according to the pressure operation range to obtain the avalanche breakdown prediction region data; Perform cross-validation on the avalanche breakdown prediction region data and the gate charging curve to obtain the potential fault region.

8. The overvoltage protection method for a silicon carbide startup control chip according to claim 1, wherein The construction of the clamping-off strategy for the initial control scheme and the potential fault region to obtain the chip startup protection strategy includes: Perform non-linear threshold grading on the initial control scheme based on the preset silicon carbide material characteristic data to obtain the adaptive voltage protection threshold data; Extract differential features from the potential fault region and analyze the fluctuation characteristics of the fault precursor signals to obtain the fault precursor feature vector; Perform multi-phase response time curve analysis according to the adaptive voltage protection threshold data and the fault precursor feature vector, and perform strategy construction to obtain the dynamic protection response strategy; Perform fast and slow dual clamping voltage analysis on the dynamic protection response strategy based on the preset second-order damping coefficient regulation algorithm to obtain the dual-channel clamping control instruction; Perform variable slope control analysis on the drive circuit according to the dual-channel clamping control instruction to obtain the intelligent turn-off control signal; Optimize the startup protection of the initial control scheme according to the intelligent turn-off control signal and the dual-channel clamping control instruction to obtain the chip startup protection strategy.

9. A protection system for an ultra-high voltage silicon carbide start control chip, characterized in that, Applied to the protection method of the ultra-high voltage silicon carbide startup control chip described in any one of claims 1-8 above, including: An acquisition module, which is used to obtain the operating parameters and composite structure characteristic data of the ultra-high voltage silicon carbide startup control chip, and perform TVS-MOSFET stage characteristic analysis to obtain the real-time state information of the chip; An analysis module, which is used to obtain the gate charging curve of the ultra-high voltage silicon carbide startup control chip, and perform correlation analysis with the real-time state information of the chip to obtain multi-threshold protection parameters; A correlation module, which is used to obtain the current change data of the ultra-high voltage silicon carbide startup control chip, and perform Miller plateau characteristic analysis on the real-time state information of the chip to obtain the abnormal current trend; A processing module, which is used to construct temperature control for the multi-threshold protection parameters and the abnormal current trend to obtain the initial control scheme; A control module, which is used to perform fault self-diagnosis on the real-time state information of the chip to obtain the fault warning information, and perform fault prediction with the gate charging curve to obtain the potential fault region; An execution module, which is used to construct a clamping-off strategy for the initial control scheme and the potential fault region to obtain the chip startup protection strategy.

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