Controller and storage device

Abstract

The invention discloses a storage device and a controller. In embodiments of the disclosed technology, an occupied logical memory address for loading overlay code stored in memory into a buffer memory is pre-allocated and set, and loading of the overlay code is performed using the occupied logical memory address. Accordingly, the overlay code may be loaded without the need to pre-allocate a buffer area of the buffer memory, so that the buffer memory may be effectively used and the loading of the overlay code may be effectively performed.

Description

[0001] Cross - reference to related applications

[0002] This patent document claims the priority and benefits of a Korean patent application No. 10 - 2023 - 0179399, filed on December 12, 2023, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] Various embodiments of the disclosed technology generally relate to a controller and a storage device. Background art

[0004] A storage device may include memory devices, each memory device including a plurality of memory cells configured to store data. The storage device may include a controller that controls the operation of the memory, such as writing data to the memory device, reading data from the memory device, or erasing data stored in the memory.

[0005] For example, the controller may control the memory by running firmware. In some cases, the firmware may be stored in one or more memory devices included in the storage device. Summary of the invention

[0006] Various embodiments of the disclosed technology are directed to providing measures that can effectively use a buffer area available for use by a controller included in a storage device and improve the operating efficiency of firmware loaded into the buffer area.

[0007] In an embodiment, a storage device may include: a first memory configured to store a plurality of codes including a plurality of overlay codes and a plurality of non - overlay codes, wherein the plurality of non - overlay codes have a higher usage frequency than the plurality of overlay codes; a second memory including a plurality of buffer areas configured to load the plurality of codes; and a controller configured to: pre - allocate at least one occupied logical memory address for loading the plurality of codes; when loading a first overlay code among the plurality of overlay codes, connect a first occupied logical memory address among the at least one occupied logical memory addresses to at least one of the plurality of buffer areas; and load the first overlay code into at least one of the buffer areas connected to the first occupied logical memory address.

[0008] In an embodiment, a controller may include: a buffer memory including a plurality of buffer areas configured to load a plurality of codes; and a processor configured to: pre - allocate at least one occupied logical memory address for loading the plurality of codes in the buffer memory, when loading a first code, connect the first occupied logical memory address to at least one of the plurality of buffer areas, and load the first code into at least one of the buffer areas connected to the first occupied logical memory address.

[0009] In an embodiment, a controller may be configured to: pre-allocate at least one occupied logical memory address for loading a plurality of overlay codes; and when loading at least one of the plurality of overlay codes, load the at least one overlay code into at least one first buffer area connected to the at least one occupied logical memory address, wherein the controller uses the plurality of non-overlay codes more frequently than the plurality of overlay codes.

[0010] In an embodiment, a storage device may include: a first memory configured to store a plurality of codes including a plurality of overlay codes and a plurality of non-overlay codes; a second memory including a plurality of buffer areas for loading the plurality of codes; and a controller configured to set at least one occupied logical memory address pre-allocated for loading the plurality of codes, connect the first occupied logical memory address to at least one of the plurality of buffer areas when loading the first overlay code, and load the first overlay code into at least one buffer area connected to the first occupied logical memory address.

[0011] In an embodiment, a controller may include: a buffer memory including a plurality of buffer areas for loading a plurality of codes; and a processor configured to set at least one occupied logical memory address pre-allocated for loading the plurality of codes, connect the first occupied logical memory address to at least one of the plurality of buffer areas when loading the first code, and load the first code into at least one buffer area connected to the first occupied logical memory address.

[0012] In an embodiment, a controller may be configured to: pre-allocate and set at least one occupied logical memory address for loading a plurality of overlay codes; and when loading at least one of the plurality of overlay codes, load the at least one overlay code into at least one first buffer area connected to the at least one occupied logical memory address.

[0013] According to an embodiment of the disclosed technology, the buffer areas used by the controller can be effectively utilized, and the operating efficiency of the firmware loaded into the buffer areas can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing an example configuration of a storage device based on an embodiment of the disclosed technology.

[0015] Figure 2 is a diagram showing an example of how codes stored in a memory are loaded into a buffer memory of a storage device based on an embodiment of the disclosed technology.

[0016] Figures 3 to 5FIG. is an example diagram showing how overlay code stored in a memory is loaded into a buffer memory of a storage device based on an embodiment of the disclosed technology.

[0017] Figure 6 and Figure 7 FIG. is an example diagram showing how non - overlay code stored in a memory is loaded into a buffer memory of a storage device based on an embodiment of the disclosed technology.

[0018] Figures 8 to 10 FIG. is an example diagram showing how overlay code and non - overlay code stored in a memory are loaded into a buffer memory of a storage device based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0019] When firmware needs to be run, the controller can load the firmware stored in the memory device into the buffer area and run the firmware. However, the controller may not have enough buffer area available, resulting in difficult firmware loading, which has a negative impact on the operating efficiency of the firmware.

[0020] In some embodiments, the disclosed technology can be implemented to solve these problems by effectively using the buffer area of the buffer memory when loading firmware code.

[0021] Figure 1 FIG. is an example configuration diagram of a storage device 100 based on an embodiment of the disclosed technology.

[0022] Referring to Figure 1 , a storage device 100 based on an embodiment of the disclosed technology may include at least one memory 110. The storage device 100 may include a controller 120 that controls the operation of the at least one memory 110 and serves as an interface between the at least one memory 110 and a host device 200, which may be a computer or other computing device.

[0023] The memory 110 may be a non - volatile memory. For example, the memory 110 may be implemented in various types, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory, phase - change random access memory, magnetoresistive random access memory, ferroelectric random access memory, and spin - transfer torque random access memory. The memory 110 may be implemented in a three - dimensional array structure.

[0024] In an embodiment of the disclosed technology, the non-volatile memory may be a flash memory including a charge storage layer. In one example, the charge storage layer may be a floating gate. In another example, the charge storage layer may be an insulating material layer (e.g., an insulating film). In this case, the flash memory may be referred to as a charge-trapping flash memory.

[0025] Memory 110 may operate in response to a control signal from controller 120. Operations of memory 110 may include, for example, a programming operation (also referred to as a “write operation”), an erase operation, and a read operation.

[0026] Controller 120 may control the programming operation, erase operation, read operation, and background operations performed on memory 110. Examples of background operations may include a garbage collection operation, a wear-leveling operation, a read-reclaim operation, and a bad block management operation.

[0027] In an implementation, controller 120 may control the operation of memory 110 according to a request from a device located outside storage device 100. In another implementation, controller 120 may control the operation of memory 110 regardless of requests from the outside.

[0028] For example, controller 120 may control the operation of memory 110 according to a request from host device 200. Storage device 100 and host device 200 may be collectively referred to as a computing system.

[0029] Host device 200 may be a computing device of various configurations. For example, host device 200 may be or may include a computer such as a personal computer (PC), an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, an electronic device configured for a home network, an electronic device configured for a telematics network, a radio frequency identification (RFID) device, a device that can operate under human control or autonomously (e.g., a vehicle, a robot, or a drone). In some implementations, host device 200 may be a virtual / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. In some implementations, host device 200 may be any electronic device that requires a data storage device such as storage device 100 to store data.

[0030] The host device 200 may include at least one operating system. The operating system may manage and control the overall functions and operations of the host device 200, and may control operations related to the interaction between the host device 200 and the storage device 100. Depending on the mobility of the host device 200, the operating system may be classified into a general operating system and a mobile operating system.

[0031] In an embodiment, the controller 120 and the host device 200 may be separate devices. In another embodiment, the controller 120 and the host device 200 may be integrated into a single device. In some of the embodiments discussed below, for the sake of convenience of description, it will be described by taking the example that the controller 120 and the host device 200 are separate devices.

[0032] The controller 120 may include a host interface that provides an interface for communicating with the host device 200. The controller 120 may include a memory interface that provides an interface for communicating with the memory 110.

[0033] The controller 120 may include a processor 121 as Figure 1 shown, and the processor 121 controls the overall operations of the controller 120. The processor 121 may include a working memory for the operation of the processor 121, and in some embodiments, may optionally include an error detection and correction circuit. Optionally, the working memory may be located outside the processor 121.

[0034] The processor 121 may communicate with the host device 200 through the host interface, and may communicate with the memory 110 through the memory interface.

[0035] The processor 121 may interpret commands from the host device 200 and / or transmit commands to the memory 110.

[0036] For example, the processor 121 may include a flash translation layer or may correspond to a flash translation layer. The processor 121 may convert a logical block address provided by the host device 200 into a physical block address. The processor 121 may receive a logical block address and use a mapping table to convert the logical block address into a physical block address.

[0037] The processor 121 may control the operations of the controller 120 by running, for example, firmware. The operations of the storage device 100 according to the embodiments of the disclosed technology may be implemented in such a way that the processor 121 runs firmware that defines the corresponding operations.

[0038] In some embodiments, the firmware is a program that runs in the storage device 100 to drive or operate the storage device 100, and may include various functional layers corresponding to the processor 121 described above. For example, the firmware may include binary data that defines the code for running each functional layer.

[0039] For example, the firmware may be loaded from the memory 110 or a separate non-volatile memory located outside the memory 110 (e.g., ROM or NOR flash memory) into the working memory. When performing a startup operation after power-on, the processor 121 may first load all or part of the firmware into the working memory.

[0040] To control the overall operation of the controller 120, the processor 121 may execute the logical operations defined in the firmware loaded into the working memory. According to the results of executing the logical operations defined in the firmware, the processor 121 may control the controller 120 to generate commands or signals. When a part of the firmware that defines the logical operations to be executed is not loaded into the working memory, the processor 121 may generate an event (e.g., an interrupt) for loading the corresponding part of the firmware into the working memory.

[0041] The working memory may store the firmware, program code, commands, or data required to drive the controller 120. The working memory may be located inside or outside the controller 120.

[0042] In some embodiments, the working memory may be located both inside and outside the controller 120.

[0043] The working memory may be Figure 1 the buffer memory 122 shown. Optionally, the working memory may be separately provided from Figure 1 the buffer memory 122 shown. Figure 1 An example is shown where the buffer memory 122 is located inside the controller 120, but in some embodiments, the buffer memory 122 may be located outside the controller 120.

[0044] In some embodiments, the working memory or the buffer memory 122 may be a volatile memory, such as SRAM (static RAM), DRAM (dynamic RAM), and SDRAM (synchronous DRAM).

[0045] Figure 2 is a diagram showing an example of how the code stored in the memory 110 is loaded into the buffer memory 122 of the storage device 100 based on an embodiment of the disclosed technology.

[0046] Referring to Figure 2, the memory 110 included in the storage device 100 may include multiple memory regions. Some of the memory regions included in the memory 110 may be designated as regions for storing firmware. The firmware may be stored in the form of binary data and, for example, may be defined in the form of code.

[0047] For example, the first firmware code may be stored in the first memory region mem1 and the second memory region mem2. The second firmware code may be stored in the third memory region mem3 and the fourth memory region mem4. The third firmware code may be stored in the fifth memory region mem5 and the sixth memory region mem6.

[0048] In some embodiments, the processor 121 may load the code stored in the memory 110 into the buffer memory 122 included in the controller 120. In some embodiments of the disclosed technology, the memory 110 may be referred to as the first memory, and the buffer memory 122 may be referred to as the second memory.

[0049] The buffer memory 122 may include multiple buffer regions, Figure 2 An example showing 10 buffer regions buf1, ……, buf10 is presented.

[0050] For example, when it is necessary to load the first firmware code, buffer regions of the buffer memory 122 may be allocated to the processor 121. For example, the sixth buffer region buf6 and the seventh buffer region buf7 included in the buffer memory 122 may be allocated to the processor 121.

[0051] The processor 121 may load the first firmware code stored in the first memory region mem1 and the second memory region mem2 of the memory 110 into the sixth buffer region buf6 and the seventh buffer region buf7 of the buffer memory 122. The processor 121 may control the operation of the memory 110 or the storage device 100 by running the first firmware code loaded into the buffer memory 122.

[0052] When the processor 121 finishes using the first firmware code, the sixth buffer region buf6 and the seventh buffer region buf7 loaded with the first firmware code may be deallocated or released. The sixth buffer region buf6 and the seventh buffer region buf7 may be used to load other data.

[0053] The buffer regions of the buffer memory 122 may be used to load data other than firmware code. In some embodiments, the disclosed technology may be implemented to improve the running efficiency of the firmware by effectively using the buffer regions of the buffer memory 122 when loading the firmware code.

[0054] Figures 3 to 5FIG. is an example diagram showing how the overlay code stored in the memory 110 is loaded into the buffer memory 122 of the storage device 100 based on an embodiment of the disclosed technology.

[0055] Referring Figure 3 , when allocating a buffer area for loading firmware code, the controller 120 may use a logical memory address to allocate a buffer area of the buffer memory 122. In some embodiments, the disclosed technology may be implemented to apply to the case of loading firmware code into the buffer memory 122, or the case of loading data other than firmware code by allocating a buffer area of the buffer memory 122.

[0056] The firmware code may be stored in some of the memory areas of the memory 110 included in the storage device 100. Figure 3 As an example, the case where the firmware code is stored in six memory areas is shown.

[0057] The buffer memory 122 included in the controller 120 of the storage device 100 may provide a plurality of buffer areas. In some embodiments, the buffer memory 122 is located outside the controller 120.

[0058] In some embodiments, a buffer area for loading firmware code may be allocated to the processor 121 included in the controller 120 of the storage device 100 using a logical memory address. The processor 121 may classify the firmware code according to the type or usage frequency of the firmware code, and may control the setting of the logical memory address differently for different firmware codes.

[0059] In some embodiments, the processor 121 may classify the firmware code into overlay code and non-overlay code. In some embodiments, the term "overlay code" may be used to indicate firmware code that is not frequently used. In some embodiments, the term "non-overlay code" may be used to indicate firmware code that is frequently used.

[0060] In some embodiments, the non-overlay code may be firmware code that is loaded into the buffer memory 122 when the storage device 100 is started. In some embodiments, the non-overlay code may be firmware code that is continuously loaded into the buffer memory 122 during the operation of the storage device 100. In some embodiments, the non-overlay code may be firmware code that is loaded into the buffer memory 122 during the operation of the storage device 100 with a period or frequency longer or higher than a predetermined value.

[0061] In some embodiments, the overwrite code may be firmware code having a shorter or lower usage period or frequency than the non-overwrite code. In some embodiments, the overwrite code may be firmware code having a shorter or lower period or frequency than a predetermined value and loaded into the buffer memory 122 during the operation of the storage device 100.

[0062] The processor 121 of the controller 120 may pre-allocate logical memory addresses for loading the overwrite code into the buffer memory 122. For example, the processor 121 may pre-allocate at least one occupied logical memory address lma and set at least one occupied logical memory address lma as the logical memory address for loading the overwrite code.

[0063] The occupied logical memory address lma may be a fixed logical memory address. The occupied logical memory address lma may be the logical memory address for loading the overwrite code and may be used for loading each of a plurality of overwrite codes.

[0064] For example, referring to Figure 3 , the processor 121 may pre-allocate a first occupied logical memory address lma1 and a second occupied logical memory address lma2 as the logical memory addresses for loading the overwrite code. The occupied logical memory address lma may be set in different ways according to the size of the firmware code, Figure 3 An example of allocating two occupied logical memory addresses lma for loading one firmware code is shown.

[0065] In some embodiments, the first occupied logical memory address lma1 and the second occupied logical memory address lma2 are not connected to the buffer areas included in the buffer memory 122. Although the first occupied logical memory address lma1 and the second occupied logical memory address lma2 are pre-allocated, since they are not connected to the buffer areas of the buffer memory 122, the buffer areas of the buffer memory 122 may not be allocated for loading the firmware code.

[0066] When a situation occurs where it is necessary to load the first firmware code among the overlay codes, the processor 121 may allocate buffer areas of the buffer memory 122 for the first occupied logical memory address lma1 and the second occupied logical memory address lma2. The buffer areas allocated for the first occupied logical memory address lma1 and the second occupied logical memory address lma2 may be continuous or discontinuous. The buffer areas allocated for the first occupied logical memory address lma1 and the second occupied logical memory address lma2 can be represented by, for example, buffer IDs. Optionally, the buffer areas allocated for the first occupied logical memory address lma1 and the second occupied logical memory address lma2 can be represented by buffer IDs and a plurality of slots included in each buffer ID. For example, one buffer ID and a plurality of slots can be allocated to one occupied logical memory address lma, but the disclosed technology is not limited thereto.

[0067] For example, the second buffer area buf2 and the fourth buffer area buf4 included in the buffer memory 122 can be allocated to the first occupied logical memory address lma1 and the second occupied logical memory address lma2.

[0068] The processor 121 can connect the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to the second buffer area buf2 and the fourth buffer area buf4 respectively.

[0069] The processor 121 can load the first firmware code for the overlay code into the second buffer area buf2 connected to the first occupied logical memory address lma1 and the fourth buffer area buf4 connected to the second occupied logical memory address lma2.

[0070] Since the usage period or frequency of the overlay code is not relatively long or frequent, the processor 121 can load the overlay code only using the pre-allocated occupied logical memory address lma. The overlay code can be loaded into the buffer area connected to the occupied logical memory address lma through the occupied logical memory address lma. In this way, the loading of multiple overlay codes can be effectively managed.

[0071] Since the occupied logical memory address lma is not connected to the buffer area included in the buffer memory 122 before loading the overlay code, the buffer memory 122 may not pre-allocate a buffer area for loading the overlay code. In this way, the allocation of the buffer areas included in the buffer memory 122 can be effectively managed.

[0072] When the use of the first firmware code loaded into the buffer memory 122 via the first occupied logical memory address lma1 and the second occupied logical memory address lma2 is completed, the processor 121 may release the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area.

[0073] For example, with reference to Figure 4 , the connection between the first occupied logical memory address lma1 and the second buffer area buf2 may be released. The connection between the second occupied logical memory address lma2 and the fourth buffer area buf4 may be released.

[0074] The second buffer area buf2 and the fourth buffer area buf4 may be managed as areas loaded with invalid data, and the first firmware code may be deleted from the second buffer area buf2 and the fourth buffer area buf4.

[0075] When a situation occurs where a second firmware code needs to be loaded as another overlay code after the use of the first firmware code is completed, the processor 121 may use the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to load the second firmware code.

[0076] The processor 121 may connect each of the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to a buffer area included in the buffer memory 122. For example, the processor 121 may connect the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to the sixth buffer area buf6 and the ninth buffer area buf9 included in the buffer memory 122, respectively. The processor 121 may load the second firmware code into the sixth buffer area buf6 and the ninth buffer area buf9.

[0077] Since the overlay code is loaded into the buffer area of the buffer memory 122 via the pre-allocated occupied logical memory address lma, the size of the buffer area in the buffer memory 122 where the overlay code is loaded may be maintained to be equal to or less than a predetermined size. In this way, the overlay code may be loaded by effectively using the buffer area of the buffer memory 122, and the impact on loading other data may be minimized.

[0078] To load the overlay code, only the occupied logical memory address lma is pre-allocated, and the buffer area is not pre-allocated, so the buffer area for loading the overlay code may vary according to the time point.

[0079] For example, as Figure 4As shown, the buffer area for loading the first firmware code and the buffer area for loading the second firmware code can be different. When the first firmware code is loaded into the buffer area again after being used in the buffer area, the buffer area for loading the first firmware code at the first time point and the buffer area for loading the first firmware code at the second time point can be different.

[0080] The occupied logical memory address lma can be fixed, and the buffer area connected to the occupied logical memory address lma can change according to the usage status of the buffer memory 122.

[0081] To load the overlay code, only the occupied logical memory address lma is pre-allocated and fixed, and the buffer area of the buffer memory 122 is variably connected. Therefore, the buffer area of the buffer memory 122 can be effectively used.

[0082] Since the pre-allocated occupied logical memory address lma is provided for loading the overlay code, and the overlay code is loaded into the buffer area of the buffer memory 122 through the occupied logical memory address lma, the usage efficiency of the buffer area can be improved according to the loading of the overlay code with a lower usage frequency.

[0083] Since the overlay code is loaded into the buffer area through the occupied logical memory address lma, in some embodiments, the processor 121 can maintain the connection between the occupied logical memory address lma and the buffer area after the use of the overlay code is completed.

[0084] For example, referring to Figure 5 , to Figure 3 The state after the first firmware code is loaded into the buffer area of the buffer memory 122 and the use of the first firmware code is completed is taken as an example for illustration.

[0085] After the use of the first firmware code is completed, in some embodiments, the processor 121 can maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area without releasing it.

[0086] For example, when the remaining capacity of the buffer area in the buffer memory 122 is equal to or greater than a preset value, the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area can be maintained. For example, the connection between the first occupied logical memory address lma1 and the second buffer area buf2 and the connection between the second occupied logical memory address lma2 and the fourth buffer area buf4 can be maintained.

[0087] When a situation occurs where the second firmware code for another overlay code needs to be used after the use of the first firmware code is completed, the processor 121 may load the second firmware code into the second buffer area buf2 and the fourth buffer area buf4 connected to the first occupied logical memory address lma1 and the second occupied logical memory address lma2.

[0088] The processor 121 can effectively use the buffer area by loading the overlay code using the occupied logical memory address lma. When there is space in the buffer area, the connection between the occupied logical memory address lma and the buffer area can be maintained, and the buffer area connected to the occupied logical memory address lma can be used as a buffer area for loading the overlay code.

[0089] Since the processor 121 pre-allocates and sets the occupied logical memory address lma and uses the occupied logical memory address lma to load the overlay code, the buffer areas included in the buffer memory 122 can be effectively used, the loading of the overlay code can be effectively performed, and the performance of the operation of running the firmware code can be improved.

[0090] Since the processor 121 pre-allocates and uses the occupied logical memory address lma to load the overlay code, the processor 121 can use a logical memory address other than the occupied logical memory address lma to load the non-overlay code.

[0091] Figure 6 and Figure 7 FIG. is a diagram showing an example of how the non-overlay code stored in the memory 110 is loaded into the buffer memory 122 in the storage device 100 based on an embodiment of the disclosed technology.

[0092] Figure 6 An example situation is shown where the first firmware code, the second firmware code for the overlay code, and the third firmware code for the non-overlay code are stored in the memory areas included in the memory 110.

[0093] When the first firmware code for the overlay code needs to be loaded, the processor 121 of the controller 120 can use the pre-allocated first occupied logical memory address lma1 and the second occupied logical memory address lma2 to load the overlay code.

[0094] For example, the processor 121 can connect the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to the second buffer area buf2 and the fourth buffer area buf4 among the buffer areas included in the buffer memory 122. The processor 121 can load the first firmware code into the second buffer area buf2 and the fourth buffer area buf4 and use the first firmware code.

[0095] When it is necessary to load the third firmware code as non-overwrite code, the processor 121 can allocate an unoccupied logical memory address nma to load the non-overwrite code. The unoccupied logical memory address nma can be a logical memory address other than the pre-allocated occupied logical memory address lma.

[0096] For example, in order to load the third firmware code as non-overwrite code, the processor 121 can allocate a first unoccupied logical memory address nma1 and a second unoccupied logical memory address nma2. The processor 121 can connect the first unoccupied logical memory address nma1 and the second unoccupied logical memory address nma2 to buffer areas included in the buffer memory 122. For example, the first unoccupied logical memory address nma1 and the second unoccupied logical memory address nma2 can be connected to the sixth buffer area buf6 and the eighth buffer area buf8 included in the buffer memory 122, respectively.

[0097] The processor 121 can load the third firmware code into the sixth buffer area buf6 and the eighth buffer area buf8 connected to the first unoccupied logical memory address nma1 and the second unoccupied logical memory address nma2, and can use the third firmware code.

[0098] Since the occupied logical memory address lma is pre-allocated for overwrite code, the processor 121 can allocate a logical memory address other than the occupied logical memory address lma and can use the logical memory address to load non-overwrite code.

[0099] When the use of the overwrite code or non-overwrite code loaded into the buffer memory 122 is completed, the processor 121 can release the connection between the logical memory address and the buffer area.

[0100] For example, referring to Figure 7 , when the use of the first firmware code is completed, the processor 121 can release the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. When the use of the third firmware code is completed, the processor 121 can release the connection between the first unoccupied logical memory address nma1 and the second unoccupied logical memory address nma2 and the buffer area.

[0101] The buffer area where the connection with the logical memory address is released can be managed as having invalid data loaded, or the data loaded into the corresponding buffer area can be deleted.

[0102] After the connection between the occupied logical memory address lma and the buffer area is released, the processor 121 may maintain the setting of the occupied logical memory address lma. The processor 121 may maintain the setting of the occupied logical memory address lma. Thereafter, when a situation where an overlay code needs to be loaded occurs, the processor 121 may use the occupied logical memory address lma to load the overlay code.

[0103] After the connection between the unoccupied logical memory address nma and the buffer area is released, the processor 121 may release the allocation of the unoccupied logical memory address nma. After the use of data such as non-overlay code is completed, the processor 121 may release the allocation of the unoccupied logical memory address nma for allocating the corresponding data.

[0104] In an embodiment of the disclosed technology, by using a fixed occupied logical memory address lma, the loading of the overlay code can be effectively performed, and as a logical memory address for loading data other than the overlay code, logical memory addresses other than the occupied logical memory address lma can be used without prior allocation. Therefore, the buffer memory 122 can be effectively accessed through the logical memory address.

[0105] In addition, in an embodiment of the disclosed technology, logical memory addresses are used to manage the area for loading data through consecutive addresses, and buffer areas corresponding to consecutive or non-consecutive addresses are used in the buffer memory 122 that provides physical storage space. Therefore, the buffer area can be effectively used according to the usage state of the buffer memory 122.

[0106] In an embodiment of the disclosed technology, since logical memory addresses are used to perform the loading of the overlay code, the loading of the overlay code can be effectively performed using multiple logical memory addresses without degrading the usage efficiency of the buffer memory 122.

[0107] Figures 8 to 10 is a diagram showing an example of how the overlay code and non-overlay code stored in the memory 110 are loaded into the buffer memory 122 of the storage device 100 based on an embodiment of the disclosed technology.

[0108] Refer to Figure 8 and the processor 121 of the controller 120 may pre-allocate two or more occupied logical memory addresses lma for loading the overlay code.

[0109] For example, the processor 121 may pre-allocate a first occupied logical memory address lma1 and a second occupied logical memory address lma2 for loading an overlay code. The processor 121 may pre-allocate a third occupied logical memory address lma3 and a fourth occupied logical memory address lma4 for loading another overlay code.

[0110] Two occupied logical memory addresses lma may be pre-allocated for loading an overlay code.

[0111] In some embodiments, before loading the overlay code, the occupied logical memory address lma may not be connected to the buffer area of the buffer memory 122. Only the occupied logical memory address lma may be pre-allocated, and the buffer area of the buffer memory 122 may not be pre-allocated.

[0112] When the first firmware code to be loaded as an overlay code is needed, the processor 121 may connect the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to the second buffer area buf2 and the fourth buffer area buf4 included in the buffer memory 122, respectively.

[0113] The first firmware code may be loaded into the second buffer area buf2 and the fourth buffer area buf4.

[0114] When the use of the first firmware code is completed, the processor 121 may release the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. In some embodiments, when the use of the first firmware code is completed, the processor 121 may maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area.

[0115] In addition to the first occupied logical memory address lma1 and the second occupied logical memory address lma2, the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 are pre-allocated for loading the overlay code. Therefore, even after the use of the first firmware code is completed, the processor 121 may still maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area.

[0116] For example, referring to Figure 9 , when the second firmware code needs to be loaded after the first firmware code is loaded, the processor 121 may connect the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 to the sixth buffer area buf6 and the ninth buffer area buf9, respectively.

[0117] The processor 121 may load the second firmware code into the sixth buffer region buf6 and the ninth buffer region buf9 connected to the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4.

[0118] For example, when it is necessary to load the second firmware code while the first firmware code is already loaded and in use, the processor 121 may use the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 to load the second firmware code into the buffer memory 122.

[0119] Since the occupied logical memory address lma can be pre-allocated without being connected to a buffer region, by pre-allocating multiple occupied logical memory addresses lma and using multiple occupied logical memory addresses lma when loading the overlay code, the loading efficiency of the overlay code can be improved.

[0120] The processor 121 may determine whether to use the occupied logical memory address lma when loading the second firmware code based on the remaining capacity of the buffer region included in the buffer memory 122.

[0121] For example, when the remaining capacity of the buffer region is equal to or greater than a preset value, the processor 121 may use the above-mentioned third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 to load the second firmware code.

[0122] Optionally, when the remaining capacity of the buffer region is less than the preset value, the second firmware code may be loaded after the use of the first firmware code is completed. In this case, the loading of the second firmware code may be performed using the first occupied logical memory address lma1 and the second occupied logical memory address lma2, or may be performed using the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4.

[0123] In some embodiments, when it is necessary to load the second firmware code in a state where the use of the first firmware code is completed after the first firmware code is loaded, the processor 121 may use the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 to load the second firmware code into the buffer memory 122.

[0124] After the use of the first firmware code is completed, the processor 121 may maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. Thereafter, when the need to use the first firmware code arises again, the processor 121 may use the first firmware code loaded into the buffer area connected to the first occupied logical memory address lma1 and the second occupied logical memory address lma2. The operation of reading the first firmware code from the memory 110 to load the first firmware code may not be performed.

[0125] In some embodiments, the processor 121 may determine whether to maintain the connection between the buffer area loaded with the first firmware code and the occupied logical memory address lma based on the remaining capacity of the buffer area included in the buffer memory 122.

[0126] For example, when the remaining capacity of the buffer area is equal to or greater than a preset value, the processor 121 may maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area after the use of the first firmware code is completed. When the remaining capacity of the buffer area is less than the preset value, the processor 121 may release the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. The buffer area loaded with the first firmware code may be used to load other data.

[0127] In this way, by using multiple occupied logical memory addresses lma to load the overlay code, the loading efficiency of the overlay code can be improved, and since whether to maintain the connection between the multiple occupied logical memory addresses lma and the buffer area can vary according to the remaining capacity of the buffer area, the buffer area can be effectively used.

[0128] When using multiple occupied logical memory addresses lma to load the overlay code, an unoccupied logical memory address nma may be used to perform the loading of non-overlay code.

[0129] For example, Figure 10 shows the completion of the use of the first firmware code loaded into the buffer area using the first occupied logical memory address lma1 and the second occupied logical memory address lma2, and the second firmware code loaded into the buffer area using the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 is in use.

[0130] When non-overlay code needs to be loaded, the processor 121 may allocate an unoccupied logical memory address nma other than the above-mentioned occupied logical memory address lma to load the non-overlay code.

[0131] For example, the processor 121 may allocate a first unoccupied logical memory address nma1 and a second unoccupied logical memory address nma2. The first unoccupied logical memory address nma1 and the second unoccupied logical memory address nma2 may be connected to the eighth buffer region buf8 and the tenth buffer region buf10 of the buffer memory 122, respectively. The third firmware code for non-overwrite code may be loaded into the eighth buffer region buf8 and the tenth buffer region buf10.

[0132] When loading the non-overwrite code after the use of the first firmware code for overwrite code is completed, it is possible to control whether to maintain the buffer region in which the first firmware code is loaded according to the remaining capacity of the buffer region.

[0133] As Figure 10 shown, when the remaining capacity of the buffer region is less than a preset value when loading the third firmware code, the processor 121 may release the connection between the buffer region in which the first firmware code is loaded and the occupied logical memory address lma. The processor 121 may delete the first firmware code loaded into the buffer region or mark the first firmware code as invalid data.

[0134] When the remaining capacity of the buffer region is equal to or greater than the preset value, the processor 121 may maintain the connection between the buffer region in which the first firmware code is loaded and the occupied logical memory address lma. When it is necessary to reuse the overwrite code, without affecting the loading of other data into the buffer memory 122, the loading of the overwrite code may be executed without repeating the reading from the memory 110.

[0135] Only a few embodiments and examples are described. Enhancements and variations can be made to the disclosed embodiments and other embodiments based on what is described and illustrated in this patent document.

Claims

1. A storage device, comprising: A first memory storing a plurality of codes including a plurality of covering codes and a plurality of non-covering codes, wherein the usage frequency of the plurality of non-covering codes is higher than that of the plurality of covering codes; A second memory including a plurality of buffer areas, wherein the plurality of buffer areas are loaded with a plurality of codes; and A controller pre-allocates at least one occupied logical memory address to load the multiple codes, connects a first occupied logical memory address of the at least one occupied logical memory address to at least one buffer area of ​​the multiple buffer areas when loading a first overlay code of the multiple overlay codes, and loads the first overlay code into at least one buffer area connected to the first occupied logical memory address.

2. The storage device according to claim 1, wherein: When use of the first overlay code is completed, the controller releases a connection between the first occupied logical memory address and the at least one buffer area.

3. The storage device according to claim 2, wherein: When loading the second overlay code after the use of the first overlay code is completed, the controller connects the first occupied logical memory address to at least one buffer area among the multiple buffer areas, and loads the second overlay code into the at least one buffer area connected to the first occupied logical memory address.

4. The storage device according to claim 3, wherein: At least one buffer area into which the first coverage code is loaded is different from at least one buffer area into which the second coverage code is loaded.

5. The storage device according to claim 2, wherein: After releasing the connection between the first occupied logical memory address and the at least one buffer area, the controller maintains the setting of the first occupied logical memory address.

6. The storage device according to claim 1, wherein: The controller maintains a connection between the first occupied logical memory address and the at least one buffer area after use of the first overlay code is completed.

7. The storage device according to claim 6, wherein: When loading the second overlay code, the controller loads the second overlay code into at least one buffer area connected to the first occupied logical memory address.

8. The storage device according to claim 6, wherein: In a case where remaining capacities of the plurality of buffer areas in the second memory are less than a preset value, the controller releases a connection between the first occupied logical memory address and the at least one buffer area.

9. The storage device according to claim 1, wherein: When loading a second overlay code during use of the first overlay code, the controller connects a second occupied logical memory address to at least one buffer area among the plurality of buffer areas and loads the second overlay code into the at least one buffer area connected to the second occupied logical memory address.

10. The storage device according to claim 9, wherein: When the use of the first overlay code is completed and the second overlay code is in use and the remaining capacity of the multiple buffer areas is equal to or greater than a preset value, the controller maintains the connection between the first occupied logical memory address and the at least one buffer area.

11. The storage device according to claim 1, wherein: When loading at least one non-cover code among the multiple non-cover codes, the controller allocates an unoccupied logical memory address other than the at least one occupied logical memory address, connects the unoccupied logical memory address to at least one buffer area among the multiple buffer areas, and loads the at least one non-cover code into at least one buffer area connected to the unoccupied logical memory address.

12. The storage device according to claim 11, wherein: The occupied logical memory address is fixed, and the unoccupied logical memory address is variable.

13. The storage device according to claim 1, wherein: At least one buffer region into which the first coverage code is loaded at a first point in time is different from at least one buffer region into which the first coverage code is loaded at a second point in time.

14. A controller comprising: a buffer memory including a plurality of buffer areas for loading a plurality of codes; as well as A processor pre-allocates at least one occupied logical memory address in the buffer memory to load the multiple codes, connects the first occupied logical memory address to at least one buffer area among the multiple buffer areas when loading a first code, and loads the first code into the at least one buffer area connected to the first occupied logical memory address.

15. The controller according to claim 14, wherein: When loading a second code after use of the first code is completed, the processor loads the second code into at least one buffer area connected to the first occupied logical memory address.

16. The controller according to claim 14, wherein: When loading the second code during use of the first code, the processor connects a second occupied logical memory address to at least one buffer area among the plurality of buffer areas, and loads the second code into the at least one buffer area connected to the second occupied logical memory address.

17. The controller according to claim 14, wherein: When loading the third code, the processor connects unoccupied logical memory addresses other than the at least one occupied logical memory address to at least one buffer area among the multiple buffer areas, and loads the third code into the at least one buffer area connected to the at least one unoccupied logical memory address.

18. The controller according to claim 14, wherein: The first occupied logical memory address for loading the first code is fixed, and at least one buffer area for loading the first code is variable.

19. A controller, wherein: pre-allocating at least one occupied logical memory address for loading a plurality of coverage codes; and When loading at least one of the plurality of coverage codes, the at least one coverage code is loaded into at least one first buffer area connected to the at least one occupied logical memory address, in, The controller uses the plurality of non-cover codes more frequently than the plurality of cover codes.

20. The controller according to claim 19, wherein: When loading the non-cover code, the controller uses an unoccupied logical memory address other than the at least one occupied logical memory address and loads the non-cover code into at least one second buffer area connected to the unoccupied logical memory address.

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