Start control method and device, computer equipment and storage medium

Abstract

The invention relates to a starting control method and device, computer equipment and a storage medium. The method comprises the following steps: in response to receiving a reset position and a release signal, controlling an XIP module to start instruction fetching operation; determining a starting stage according to the instruction fetching operation, and controlling a multi-chip selection module to obtain an overtime threshold value corresponding to the starting stage through a system control module; and when the starting stages are not normally operated, receiving a reset position and a release signal generated by the multiple chip selection modules based on the overtime threshold value, and controlling the XIP module to fetch instructions again based on the reset position and the release signal until all the starting stages are normally operated, thereby finishing starting. By adopting the method, XIP starting can be flexibly and efficiently completed.

Description

Technical Field

[0001] The present application relates to the field of computer technologies, and particularly to a startup control method, apparatus, computer device, and storage medium. Background Art

[0002] A system bootloader is a small program that runs in advance before the CPU runs the operating system kernel, so as to enable the CPU to initialize hardware devices and establish a mapping diagram of the memory space, thereby bringing the software and hardware environment of the system to a suitable state, so as to prepare a correct environment for the CPU to finally call the operating system kernel.

[0003] In existing practical applications, the system bootloader is usually stored on a non-volatile storage device that supports Execute In Place (XIP) operations. The CPU can access the non-volatile storage device in the same way as accessing memory, so as to directly execute the system bootloader stored in the non-volatile storage device. Therefore, the XIP technology has a wide range of application fields, including but not limited to industrial control, transportation management, robotics, national defense and military, medical instruments, and aerospace, etc.

[0004] In the process of conceiving and implementing the present application, the inventors found that there are at least the following problems: The access speed of non-volatile memory is usually lower than that of random access memory (RAM), resulting in a decrease in execution efficiency; the access mode and data consistency requirements for memory during the XIP startup process are relatively high. If used improperly, it may cause system instability or data corruption; existing XIP startup implementations often lack flexibility and are difficult to meet the requirements of different application scenarios.

[0005] The foregoing description is for the purpose of providing general background information and does not necessarily constitute prior art. Summary of the Invention

[0006] Based on this, in view of the above technical problems, it is necessary to provide a startup control method, apparatus, computer device, and storage medium that can efficiently and flexibly utilize XIP startup.

[0007] In a first aspect, the present application provides a startup control method, which is applied to a central processing unit. The central processing unit is respectively connected to a system control module and an XIP module, the XIP module is connected to a multi-chip selection module, and the system control module is connected to the multi-chip selection module. The method includes: S11, in response to receiving a reset and release signal, controlling the XIP module to start the instruction fetch operation; S12, determining a startup stage according to the instruction fetch operation, and controlling the multi-chip selection module to obtain a timeout threshold corresponding to the startup stage through the system control module; S13. When the startup phase does not run properly, receive the reset - set and release signals generated by the multi - chip - select module based on the timeout threshold, and control the XIP module to re - fetch instructions based on the reset - set and release signals until all the startup phases run properly and the startup is completed.

[0008] In one embodiment, the timeout threshold includes a first timeout and a second timeout. The step of S12 includes: When the startup phase is a preset initial startup phase, enable the switching function enable in the multi - chip - select module through the system control module to obtain the first timeout pre - configured by the switching function. When the startup phase is a preset non - initial startup phase, disable the switching function enable in the multi - chip - select module through the system control module, and send the second timeout corresponding to the chip - select function to the multi - chip - select module.

[0009] In one embodiment, before S12, it includes: Pre - divide multiple startup phases in the startup process according to the instruction - fetch operation. In one embodiment, the multiple startup phases include: The BOOTROM phase of directly fetching instructions from the flash memory and actively moving the program from the flash memory to the internal static memory. The UBOOT phase of verifying the moved program. The KERNEL phase where the pointer jumps to a new address to execute the moved program.

[0010] In a second aspect, the present application provides a startup control method applied to a multi - chip - select module. The multi - chip - select module is connected to a system control module and an XIP module. The system control module is connected to a central processing unit, and the XIP module is connected to the central processing unit. The method includes: S21. In response to triggering the reset - set and release signals, re - time to obtain timing data and obtain the timeout threshold. S22. When the timing data is greater than the timeout threshold, configure the chip - select data for the next instruction - fetch operation in a preset order, and generate a new reset - set and release signal to be managed by reset through the system control module, so that the central processing unit controls the XIP module to re - fetch instructions until the instruction - fetch operation is completed.

[0011] In one embodiment, the timeout threshold includes a first timeout and a second timeout. The step of obtaining the timeout threshold includes: Enable the switching function enable in the multi - chip - select module based on the system control module to obtain the first timeout pre - configured by the switching function. Based on the system control module, disable the switching function enable in the multi-chip selection module, and receive the second timeout sent by the central processing unit through the system control module.

[0012] In one embodiment, when the timing data is greater than the timeout threshold, configuring the chip selection data for the next fetch operation in a preset order includes: Determine whether the preset switching function is enabled. If the switching function is enabled, compare the timing data with the first timeout. When the timing data is greater than the first timeout, configure the chip selection data for the next fetch operation according to the chip selection and configuration order; If the switching function is disabled, compare the timing data with the second timeout. When the timing data is greater than the second timeout, configure the chip selection data for the next fetch operation according to the chip selection order.

[0013] In one embodiment, the step of configuring the chip selection data for the next fetch operation in a preset order includes: Determine the chip selection data of the current fetch operation; When the switching function is enabled and the timing data is greater than the first timeout, determine the configuration value and / or chip selection value of the chip selection data required for the next fetch operation; Alternatively, when the switching function is disabled and the timing data is greater than the second timeout, determine the chip selection value of the chip selection data required for the next fetch operation.

[0014] In one embodiment, the step of determining the configuration value and / or chip selection value of the chip selection data for the next fetch operation includes: Determine whether the chip selection data is the last configuration value of the current chip selection. If so, continue to determine whether the chip selection data is the last chip selection value. If so, read the abnormal state of the multi-chip selection module through the system control module; If the chip selection data is not the last configuration value of the current chip selection, determine the configuration value of the next chip selection and trigger a new reset-set and release signal; If the chip selection data is not the last chip selection value, determine the chip selection value of the next chip selection and trigger a new reset-set and release signal.

[0015] In a third aspect, the present application provides a startup control device, which includes: a signal receiving module, a threshold sending module, and a fetch control module, where The signal receiving module is used to control the XIP module to start the fetch operation in response to receiving the reset-set and release signal; A threshold sending module, configured to determine a startup phase according to the fetch operation, and control the multi-chip selection module to obtain a timeout threshold corresponding to the startup phase through the system control module; A fetch control module, configured to obtain a reset and release signal generated by the multi-chip selection module based on the timeout threshold when the startup phase does not run properly, so as to control the XIP module to re-fetch instructions based on the reset and release signals until all the startup phases run properly.

[0016] In a fourth aspect, the present application provides a startup control device, where the device includes: a data acquisition module and a chip selection configuration module, where The data acquisition module is configured to re-time to obtain timing data in response to a trigger reset and release signal, and obtain a timeout threshold; The chip selection configuration module is configured to, when the timing data is greater than the timeout threshold, configure chip selection data for the next fetch operation in a preset order, and generate a new reset and release signal to be reset and managed through the system control module, so that a central processing unit controls the XIP module to re-fetch instructions until the fetch operation is completed.

[0017] In a fifth aspect, the present application provides a computer device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented: S11, in response to receiving a reset and release signal, control the XIP module to start a fetch operation; S13, determine a startup phase according to the fetch operation, and control the multi-chip selection module to obtain a timeout threshold corresponding to the startup phase through the system control module; S13, when the startup phase does not run properly, receive a reset and release signal generated by the multi-chip selection module based on the timeout threshold, and control the XIP module to re-fetch instructions based on the reset and release signals until all the startup phases run properly and the startup is completed; Alternatively, when the processor executes the computer program, the following steps are implemented: S21, in response to a trigger reset and release signal, re-time to obtain timing data, and obtain a timeout threshold; S22, when the timing data is greater than the timeout threshold, configure chip selection data for the next fetch operation in a preset order, and generate a new reset and release signal to be reset and managed through the system control module, so that a central processing unit controls the XIP module to re-fetch instructions until the fetch operation is completed.

[0018] In a sixth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: S11. In response to receiving a reset set and release signal, control the XIP module to start an instruction fetch operation; S13. Determine a startup phase according to the instruction fetch operation, and control the multi-chip selection module to obtain a timeout threshold corresponding to the startup phase through the system control module; S13. When the startup phase does not operate normally, receive the reset set and release signal generated by the multi-chip selection module based on the timeout threshold, and control the XIP module to re-fetch instructions based on the reset set and release signal until all the startup phases operate normally and the startup is completed; Alternatively, when the computer program is executed by a processor, the following steps are implemented S21. In response to triggering a reset set and release signal, re-time to obtain timing data and obtain a timeout threshold; S22. When the timing data is greater than the timeout threshold, configure chip selection data for the next instruction fetch operation in a preset order, and generate a new reset set and release signal to be reset and managed through the system control module, so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetch operation is completed.

[0019] The above-mentioned startup control method, device, computer equipment and storage medium can support accessing non-volatile memory using a multi-chip select module based on the XIP module to complete the startup process, reduce the probability of startup failure caused by damage to the existing non-volatile memory, and through multi-chip select design, traverse the configuration parameters as much as possible and reasonably for each non-volatile memory to ensure that the non-volatile memory can read data, so as to implement flexible and efficient use of XIP startup. By connecting the central processing unit to the system control module and the XIP module, the XIP module to the multi-chip select module, and the system control module to the multi-chip select module, it supports efficient and concise communication and interaction between the central processing unit and the hardware. In different startup stages, configure the switching function enable / disable in the multi-chip select module, and configure the selection threshold of the switching function and the chip select function to prevent unexpected central processing unit problems in each startup stage, such as hanging and running away. Use the multi-chip select module to automatically generate reset and release signals based on the fetch timeout caused by abnormal fetch operations. The central processing unit quickly ends the current failed startup process and re-enters a new startup process to start fetching instructions again according to the reset and release signals generated by the multi-chip select module. Use the multi-chip select module to cooperate with the XIP module to access non-volatile memory to perform fetch operations, so as to improve the success rate of XIP startup, adapt to the reading of different types of non-volatile memory, and avoid the risk of system hanging caused by abnormalities of the central processing unit in each startup stage, thereby improving the reliability of the entire system startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. is a startup control system diagram of the startup control method in the first embodiment; Figure 2 FIG. is a flowchart of the startup control method in the second embodiment; Figure 3 FIG. is a schematic diagram of the address arrangement in the storage space in the second embodiment; Figure 4 FIG. is a schematic diagram of the processing flow of multiple startup stages in the second embodiment; Figure 5 FIG. is a flowchart of the startup control method in the third embodiment; Figure 6 FIG. is a schematic diagram of the configured chip select process of the multi-chip select module in the third embodiment; Figure 7 FIG. is a structural block diagram of the startup control device in the fourth embodiment; Figure 8 FIG. is a structural block diagram of the startup control device in the fifth embodiment; Figure 9 FIG. is an internal structure diagram of a computer device in one embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0022] It should be noted that in this document, the terms "including", "comprising", or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, method, article, or device. Without further limitation, an element defined by the phrase "including one..." does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0023] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this document, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "upon" or "in response to determining". Furthermore, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising", "including" indicate the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following" used in the present application may be interpreted inclusively, or mean any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C", and again, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C". An exception to this definition occurs only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0024] It should be understood that although the steps in the flowcharts in the embodiments of the present application are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and they can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and their execution order is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0025] Depending on the context, as used herein, the words "if", "when" can be interpreted as "when...", "when...", "in response to determining", or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" can be interpreted as "when determined", "in response to determining", "when detecting (stated condition or event)", or "in response to detecting (stated condition or event)".

[0026] It should be noted that in this article, step codes such as S1, S2, etc. are used. The purpose is to more clearly and briefly express the corresponding content and do not constitute a substantial limitation in order. Those skilled in the art may execute S2 first and then S1, etc. during specific implementation, but these should all be within the protection scope of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. In subsequent descriptions, suffixes such as "module", "component", or "unit" used to represent elements are only for the convenience of explaining the present application and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0027] The first embodiment The startup control method provided by the present application can be referred to in the startup control system as shown in Figure 1 The startup control system includes: a central processing unit 110, an XIP module 120, a system control module 130, a multi-chip selection module 140, and a non-volatile memory 150. The central processing unit 110 is respectively connected to the XIP module 120 and the system control module 130. The XIP module 120 is connected to the multi-chip selection module 140 and the non-volatile memory 150. The system control module 130 is connected to the multi-chip selection module 140. Among them, the central processing unit 110, the XIP module 120, the system control module 130, and the multi-chip selection module 140 are integrated on the same SOC chip.

[0028] The system control module 130 is responsible for coordinating and managing system-level configuration and control functions, such as clock gating and exception reset control. The system control module in this embodiment serves as a bridge for connecting the central processor 110 and the multi-chip select module 140. The interaction between the system control module 130 and the multi-chip select module 140 in this embodiment is relatively simple and does not require additional use of the amba bus for communication.

[0029] The XIP module 120 uses a simplified QSPI / SPI controller and has a read function. The XIP module 120 adopts the XIP technology to directly execute code on the non-volatile memory 150, eliminating the need to copy the code to the RAM, thereby reducing the startup time, memory footprint, improving the operating efficiency of the system, reducing the system cost and power consumption. The XIP module 120 and the central processor 110 can communicate and interact using any bus, such as the AXI (Advanced eXtensible Interface) bus, the AHB (Advanced High Performance Bus) bus, or the APB (Advanced Peripheral Bus) bus. Thus, the central processor 110 can access the XIP module 120 through any bus. The XIP module 120 converts the read request access of the central processor 110 into a QSPI bus waveform to communicate with the off-chip non-volatile memory 150 and receives the chip select configuration of the multi-chip select module to change the QSPI bus request form in real time. Optionally, the XIP module 120 reads the chip select data of the multi-chip select module 140 according to the instruction fetch of the central processor 110 and directly executes the instruction fetch operation on the non-volatile memory 150. Optionally, the central processor 110 generates an instruction fetch instruction based on the reset and release signals. Optionally, when the central processor 110 receives the reset and release signals generated by an external start key operation, the chip select data received by the XIP module 120 from the multi-chip select module 140 is the initial chip select data, such as chip select 0_configuration 0; when the central processor 110 receives the reset and release signals generated by the internal multi-chip select module, the chip select data received by the XIP module 120 from the multi-chip select module 140 is the chip select data configured by the multi-chip select module 140 based on the timeout threshold.

[0030] The non-volatile memory 150 uses a group of NorFlash chips. The clock and data lines are shared, and the chip selects are independent (in the non-volatile memory, the selected state of each storage chip is independently controlled through the chip select signal (Chip Select, abbreviated as CS). The chip select signal is a low-level effective control signal used to indicate which storage chip is selected for data read and write operations). Different NorFlash chips may be from different manufacturers and have different specific parameters, such as supporting 16-bit, 24-bit, or 32-bit addresses, for example, only supporting mode0, mode1 clock / phase polarities, and so on.

[0031] The central processing unit 110 can be a general-purpose processor, a digital signal processor, or any other conventional processor. The central processing unit 110 interacts with the XIP module 120 to control the XIP module 120 to perform an instruction fetch operation; the central processing unit 110 interacts with the multi-chip select module 140 through the system control module 130, can turn off or enable the switching function enable, send a timeout threshold to the multi-chip select module 140, send a stop command to the multi-chip select module 140 to control the multi-chip select module 140 to stop timing and stop working, and use the reset management of the system control module 130 to receive the reset set and release signals generated by the multi-chip select module 140, so that the central processing unit 110 controls the XIP module 120 to fetch instructions from zero according to the reset set and release signals.

[0032] Optionally, after the central processing unit 110 receives an external start key operation or a reset set and release signal generated by the internal multi-chip select module, it controls the XIP module 120 to read the current chip select data of the multi-chip select module 140 and then perform an instruction fetch operation on the non-volatile memory 150. When the instruction fetch is successful or fails, a stop command is sent to the multi-chip select module 140 through the system control module 130 to control the multi-chip select module 140 to stop working. Optionally, when the reset set and release signal comes from the outside, the chip select data of the multi-chip select module 140 is initialized through the system control module 130. Optionally, the central processing unit 110 sends an instruction fetch instruction to the XIP module 120 according to the reset set and release signal to control the XIP module 120 to perform an instruction fetch operation starting from zero. Optionally, the central processing unit 110 controls the multi-chip select module 140 to turn off / enable the switching function enable through the system control module 130. Optionally, the central processing unit 110 sends a timeout threshold corresponding to the chip select function to the multi-chip select module 140 through the system control module 130.

[0033] The multi-chip select module 140 can use a general-purpose processor and is configured with a timing clock, a reset design, and a multi-chip select design. The multi-chip select design includes several chip select parameters and configuration parameters. When the multi-chip select module generates a reset, set, and release signal, the timing of its internal clock is cleared to start timing again. In this embodiment, the reset, set, and release signal generated by the multi-chip select module is a type of reset, set, and release signal. Optionally, after the multi-chip select module 140 generates a new reset, set, and release signal, the timing data is automatically cleared and starts timing again. When the timing data is greater than the currently obtained timeout threshold, the chip select data for the next instruction fetch operation is determined.

[0034] The startup control method adopted by the above startup control system supports accessing non-volatile memory using the multi-chip select module under the XIP module to complete the startup process, reduces the probability of startup failure due to damage to the non-volatile memory, supports efficient and concise communication interaction between the central processing unit and the hardware. At different startup stages of the software, based on the timeout threshold transmitted by the central processing unit to the multi-chip select module, the chip select data required for the instruction fetch operation is configured to prevent unexpected central processing unit problems during each startup stage, such as hanging, runaway, etc. After the multi-chip select module times out, it automatically configures the chip select data for the next instruction fetch and generates a reset, set, and release signal to feedback to the central processing unit, so that the central processing unit can quickly end the current failed startup process and re-enter the startup process; uses the multi-chip select module to assist the instruction fetch operation of the XIP module, improves the startup success rate of the XIP module, adapts to the reading of different types of non-volatile memory, and avoids the risk of system hanging caused by abnormalities of the central processing unit during each startup stage, thereby improving the reliability of the entire system startup.

[0035] Second Embodiment In one embodiment, as Figure 2 shown, a startup control method is provided. Taking the central processing unit in Figure 1 as an example for illustration, the central processing unit is respectively connected to the system control module and the XIP module, the XIP module is connected to the multi-chip select module, and the system control module is connected to the multi-chip select module. The startup control method provided in this embodiment includes: S11, in response to receiving a reset, set, and release signal, control the XIP module to start the instruction fetch operation; S12, determine the startup stage according to the instruction fetch operation, and control the multi-chip select module to obtain the timeout threshold corresponding to the startup stage through the system control module; S13, when the startup stage does not run normally, receive the reset, set, and release signal generated by the multi-chip select module based on the timeout threshold, and control the XIP module to re-fetch instructions based on the reset, set, and release signal until all startup stages run normally and the startup is completed.

[0036] Optionally, reset and release refers to the operation of restoring the state of certain hardware facilities or software programs to their initial states in a computer system. In short, reset and release is to restart certain devices to ensure normal operation. Reset and release are necessary steps to help solve system failures or ensure the normal operation of the system. The main functions of reset and release include: solving system failures and initializing hardware devices. For example, due to long-term operation, software bugs, hardware failures, etc., some devices or programs may enter an abnormal state or deadlock, and reset and release can force them to restore their original state, thus eliminating the failure. Another example is that in some application environments, reset and release can be used to initialize hardware devices or clear certain temporary data to accelerate the system response speed. The implementation methods of reset and release usually include: system commands, software programming, and physical switches. System commands refer to implementing reset and release through system commands issued by the operating system or hardware drivers. Software programming refers to implementing the reset and release operation through specific codes in software programming. Physical switches mean that at the hardware level, some devices implement the reset operation through physical switches. Since the startup control method in this embodiment is described by taking the central processing unit as an example, when the received reset and release signal comes from the outside, one of the methods of system command, software programming, and physical switch can trigger the reset and release signal. When the received reset and release signal comes from the inside, it can be a preset trigger condition, such as exceeding a predetermined time.

[0037] Optionally, the instruction fetch operation refers to the process of fetching an instruction from a non-volatile memory into an instruction register. In this embodiment, the instruction fetch operation of the XIP module is to determine the position of the instruction in the non-volatile memory by using the chip select data transmitted by the multi-chip select module, and then read and execute the instruction from the non-volatile memory.

[0038] Optionally, the timeout threshold includes a first timeout and a second timeout. The first timeout is used to control the switching function to obtain chip select data, and the second timeout is used to control the chip select function to obtain chip select data.

[0039] Optionally, the step of controlling the multi-chip select module by the system control module in step S12 to obtain the timeout threshold corresponding to the startup stage includes: S121, when the startup stage is a preset initial startup stage, enable the switching function enable in the multi-chip select module through the system control module to obtain the first timeout pre-configured by the switching function; S122, when the startup stage is a preset non-initial startup stage, disable the switching function enable in the multi-chip select module through the system control module and send the second timeout corresponding to the chip select function to the multi-chip select module.

[0040] Among them, the switching function is pre-configured with a first timeout. When the switching function is enabled, a reset set and release signal is generated based on the first timeout of the switching function; the chip select function dynamically configures a second timeout. At different startup stages, the central processing unit allocates corresponding second timeouts to the chip select function of the multi-chip select module through the system control module, so that when the switching function is disabled, a reset set and release signal is generated based on the second timeout of the chip select function. Optionally, the priority of the switching function is higher than that of the chip select function. When both the switching function and the chip select function are in the enabled state, the switching function is given priority. When the switching function is disabled, the chip select function is considered.

[0041] Optionally, before step S11, it includes: pre-dividing multiple startup stages in the startup process according to the instruction fetch operation. Optionally, the multiple startup stages include: the BOOTROM stage, the UBOOT stage, and the KERNEL stage. Optionally, the multiple startup stages include: the BOOTROM stage of directly fetching instructions from the flash memory and actively moving the program from the flash memory to the internal static memory; the UBOOT stage of verifying the moved program; the KERNEL stage where the pointer jumps to a new address to execute the moved program.

[0042] Optionally, in this embodiment, different timeout thresholds are sent to the multi-chip select module through the system control module at different startup stages. For example, the first timeout of 1 s in the BOOTROM stage, the second timeout of 3 s in the UBOOT stage, and the second timeout of 10 s in the KERNEL stage. Further, when the instruction fetch operation in the BOOTROM stage does not run properly, that is, after the instruction fetch operation fails, a new reset set and release signal transmitted by the multi-chip select module is received, and a new instruction fetch operation is started. Optionally, the first timeout is preset to 1 second or a shorter time to end the current startup process as soon as possible. If the instruction fetch operation in the BOOTROM stage is successfully completed, the instruction fetch operation will enter the uboot stage. Further, in the uboot stage, the switching function enable is turned off through the system control module (that is, the switching function is disabled and the first timeout cannot be used), and the second timeout corresponding to the uboot stage is sent to the multi-chip select module through the system control module. Optionally, if a timeout occurs due to verification failure or other exceptions in the uboot stage, a reset set and release signal transmitted by the multi-chip select module is received to end the current startup process; if the instruction fetch operation in the uboot stage is successfully executed, the instruction fetch operation will enter the kernel stage. Further, in the kernel stage, the second timeout corresponding to the kernel stage is sent to the multi-chip select module through the system control module. Optionally, if a timeout occurs due to an error in the execution of the moved program or other exceptions in the kernel stage, a reset set and release signal transmitted by the multi-chip select module is received to end the current startup process.

[0043] Optionally, at any startup stage, when the central processing unit no longer needs the reset and release signals generated by the multi-chip select module, a stop command will be sent to the multi-chip select module through the system control module to control the multi-chip select module to stop timing and stop working.

[0044] Optionally, all non-volatile memories need to be pre-cured with bin files. Refer to the attached Figure 3 shown in the schematic diagram of the address arrangement in the storage space. The BOOTROM is placed at the beginning of address 0, and the uboot, kernel codes and checksums are arranged in sequence afterwards.

[0045] Optionally, in this embodiment, for each startup stage, the enable states of the switching function and the chip select function, the switching function, and the timeout threshold of the chip select function are preset. Optionally, in the BOOTROM stage, the switching function enable is enabled. When the instruction fetch operation fails to run normally after the timeout threshold, the reset and release signals transmitted by the multi-chip select module will be received. At the same time, the timeout threshold of the next startup stage (UBOOT stage or KERNEL stage) will be sent to the multi-chip select module through the system control module, and the switching function enable will be turned off. In this embodiment, the BOOTROM stage is used as the initial startup stage, and the UBOOT stage and KERNEL stage are used as non-initial startup stages. Optionally, in practical applications, more startup stages can be further divided.

[0046] In one embodiment, refer to the attached Figure 4 shown in the schematic diagram of the instruction fetch operation process of multiple startup stages of the central processing unit.

[0047] S101, receive the reset and release signals, control the XIP module to start the instruction fetch operation, and enter the BOOTROM stage. Optionally, the XIP module performs the instruction fetch operation on the non-volatile memory after reading the chip select data of the multi-chip select module; among them, when the reset and release signals come from the outside, the chip select data of the multi-chip select module is initialized through the system control module; the switching function enable of the multi-chip select module is enabled through the system control module, so that the multi-chip select module obtains the first timeout of the switching function, so as to obtain a new reset and release signal generated by the multi-chip select module based on the first timeout.

[0048] S102, determine whether the instruction fetch operation in the BOOTROM stage runs normally. If so, the switching function enable of the multi-chip select module is turned off through the system control module, and the second timeout of the next startup stage (UBOOT stage) is sent to the multi-chip select module through the system control module, and enter the UBOOT stage; if not, after the first timeout, receive the new reset and release signals generated by the multi-chip select module to control the XIP module to re-fetch instructions; S103. Determine whether the instruction fetch operation in the UBOOT stage is running normally. If so, send the second timeout for the next startup stage (KERNEL stage) to the multi-chip select module through the system control module and enter the KERNEL stage. If not, after the second timeout, receive the reset, set, and release signals newly generated by the multi-chip select module to control the XIP module to fetch instructions again. S104. Determine whether the instruction fetch operation in the KERNEL stage is running normally. If so, send a stop command to the multi-chip select module through the system control module. If not, after the second timeout occurs, receive the reset, set, and release signals newly generated by the multi-chip select module to control the XIP module to fetch instructions again. Optionally, when the preset timeout situation is exceeded, read the abnormal status of the multi-chip select module through the system control module so that the central processing unit can trigger a reminder for the implementer to debug and view according to the abnormal status.

[0049] In one embodiment, in the UBOOT stage, set the second timeout of the chip select function to 3 seconds. In the KERNEL stage, set the second timeout of the chip select function to 10 seconds. When the instruction fetch operation in the BOOTROM stage is completed, disable the switching function. Based on the next startup stage being the UBOOT stage, configure the second timeout of 3 seconds. When the instruction fetch operation in the UBOOT stage is executed normally, update the configured second timeout of 3 seconds to 10 seconds in the KERNEL stage, and then perform the multi-chip select instruction fetch operation based on the second timeout of 10 seconds.

[0050] Optionally, when the reset, set, and release signals come from the outside, the multi-chip select module receives the externally triggered reset, set, and release signals and feeds them back to the system control module. The system control module controls the global reset according to the reset signal to release the external reset, the multi-chip select module reset, the system control module itself reset, the SOC bus reset, the central processing unit reset, and the XIP module reset. The central processing unit controls the XIP module to start the instruction fetch operation based on the global reset triggered by the system control module.

[0051] The above startup control method is applied to a central processing unit. In response to receiving a reset-set and release signal, it controls the XIP module to start the instruction fetch operation. It determines the startup phase based on the instruction fetch operation and sends a timeout threshold corresponding to the startup phase to the multi-chip select module through the system control module. When the startup phase does not run properly, it receives the reset-set and release signal generated by the multi-chip select module based on the timeout threshold, and controls the XIP module to refetch instructions based on the reset-set and release signal until all the startup phases run properly and the startup is completed. It can support using the multi-chip select module to access non-volatile memory based on the XIP module to complete the startup process, reduce the probability of startup failure caused by damage to the existing non-volatile memory, and through the multi-chip select design, traverse and configure parameters for each non-volatile memory as much as possible and reasonably to ensure that the non-volatile memory can read data, so as to implement flexible and efficient use of XIP startup. Through the connection between the central processing unit, the system control module, and the XIP module, and the connection between the XIP module and the multi-chip select module, and the connection between the system control module and the multi-chip select module, it supports efficient and concise communication and interaction between the central processing unit and the hardware. In different startup phases, the switching function in the multi-chip select module is disabled / enabled, and the chip select threshold for the switching function and the chip select function is configured to prevent problems of the central processing unit that may occur unexpectedly in each startup phase, such as hanging and running away. The multi-chip select module automatically generates a reset-set and release signal based on the instruction fetch timeout caused by an abnormal instruction fetch operation. The central processing unit quickly ends the current failed startup process based on the reset-set and release signal generated by the multi-chip select module and re-enters a new startup process to start fetching instructions again. Using the multi-chip select module to cooperate with the XIP module to access non-volatile memory to perform the instruction fetch operation, thereby improving the success rate of XIP startup, adapting to the reading of different types of non-volatile memory, and avoiding the risk of system hanging caused by abnormalities of the central processing unit in each startup phase, thus improving the reliability of the entire system startup.

[0052] The third embodiment In one embodiment, as Figure 5 shown, a startup control method is provided. Taking the multi-chip select module in Figure 1 as an example for illustration, the multi-chip select module is connected to the system control module and the XIP module, the system control module is connected to the central processing unit, and the XIP module is connected to the central processing unit.

[0053] S21, in response to triggering a reset-set and release signal, re-time to obtain timing data and obtain a timeout threshold; S22. When the timing data is greater than the timeout threshold, configure the chip select data for the next fetch operation in a preset order, and generate new reset, set, and release signals, which are fed back to the central processing unit through the system control module, so that the central processing unit controls the XIP module to fetch instructions again until the fetch operation is completed.

[0054] Optionally, when the reset, set, and release signals come from the outside, step S21 further includes: resetting the chip select data to initialize the chip select data.

[0055] Optionally, the timeout threshold in step S21 includes a first timeout and a second timeout; in step S21, the steps of obtaining the timeout threshold include: Enabling the switching function enable in the multi-chip select module based on the system control module to obtain the first timeout pre-configured for the switching function; Disabling the switching function enable in the multi-chip select module based on the system control module and receiving the second timeout sent by the central processing unit through the system control module.

[0056] Optionally, after the multi-chip select module generates the reset, set, and release signals, the timeout threshold automatically returns to the first timeout.

[0057] Optionally, the timing data in step S21 is the data after the counter counting operation. This embodiment is used to measure the mechanism to be triggered. The timing data is compared with the timeout threshold to reserve a time as long as the timeout threshold for the fetch operation. If the fetch operation does not run properly within the timeout threshold duration, it means the fetch fails, and the chip select data required for the next fetch operation is configured for the XIP module to read, and new reset, set, and release signals are generated and fed back to the central processing unit after being reset and managed by the system control module. Optionally, each time the central processing unit receives the reset, set, and release signals, it controls the XIP module to start fetching instructions from zero.

[0058] Optionally, the switching function and the chip select function are involved in step S22. The switching function in the multi-chip select module is pre-configured with a first timeout. After the multi-chip select module generates the reset, set, and release signals, the timeout threshold returns to the first timeout. When the fetch operation of the XIP module fails and the timing data reaches the first timeout, the multi-chip select module generates new reset, set, and release signals and determines the chip select data for the next fetch operation. Further explanation, traverse the multi-chip select module and modify the chip select value and / or configuration value in the chip select data for the next fetch operation in order.

[0059] Further explanation: The priority of the switching function is higher than that of the chip select function. When the switching function is enabled, the chip select data is configured using the switching function. When the switching function is disabled, the chip select data is configured using the chip select function. The switching function of the multi-chip select module includes multiple chip select values, and each chip select value includes multiple configuration values. Optionally, the chip select data of the multi-chip select module includes {chip select_0 configuration_0, chip select_0 configuration_1, chip select_0 configuration_2, chip select_1 configuration_0, chip select_1 configuration_1, chip select_1 configuration_2, chip select_2 configuration_0, chip select_2 configuration_1, chip select_2 configuration_2}. When traversing the multi-chip select module, from chip select_0 configuration_0 to chip select_2 configuration_2, the configured chip select data is sent to the XIP module so that the XIP module performs an instruction fetch operation according to the chip select data.

[0060] Receive the second timeout configured by the central processing unit for the chip select function. After the instruction fetch operation of the XIP module fails and the timing data reaches the second timeout, the multi-chip select module generates new reset and release signals and determines the chip select data for the next instruction fetch operation. Further explanation: Traverse the multi-chip select module and modify the chip select value of the chip select data for the next instruction fetch operation in sequence. Optionally, the chip select data of the multi-chip select module includes { chip select_0 configuration_0, chip select_0 configuration_1, chip select_0 configuration_2, chip select_1 configuration_0, chip select_1 configuration_1, chip select_1 configuration_2, chip select_2 configuration_0, chip select_2 configuration_1, chip select_2 configuration_2}. When traversing the multi-chip select module, from chip select_0 configuration_0 to chip select_2 configuration_0, modify the chip select value and provide the configured chip select data for the XIP module to read so that the XIP module performs an instruction fetch operation on the non-volatile memory according to the chip select data.

[0061] Optionally, in step S22, when the timing data is greater than the timeout threshold, configuring the chip select data for the next instruction fetch operation in a preset order includes: S221, determine whether the preset switching function is enabled. If the switching function is enabled, compare the timing data with the first timeout. When the timing data is greater than the first timeout, configure the chip select data for the next instruction fetch operation according to the chip select and configuration order; S222, if the switching function is disabled, compare the timing data with the second timeout. When the timing data is greater than the second timeout, configure the chip select data for the next instruction fetch operation according to the chip select order.

[0062] Optionally, in step S221, the step of configuring the chip select data for the next instruction fetch operation in a preset order includes: Determine the chip select data of the current instruction fetch operation; When the switching function is enabled and the timing data is greater than the first timeout, determine the configuration value and / or chip select value of the chip select data for the next instruction fetch operation; Alternatively, when the switching function is disabled and the timing data is greater than the second timeout, determine the chip select value of the chip select data required for the next fetch operation.

[0063] Wherein, when the reset set and release signals come from outside, the chip select data of the fetch operation is the initial chip select data. For example, chip select 0 - configuration 0.

[0064] Wherein, the step of determining the configuration value and / or chip select value of the chip select data for the next fetch operation includes: Determine whether the chip select data is the last configuration value of the current chip select. If so, continue to determine whether the chip select data is the last chip select value. If so, read the abnormal state of the multi-chip select module through the system control module; if the chip select data is not the last configuration value of the current chip select, determine the configuration value of the next chip select and trigger a new reset set and release signal; if the chip select data is not the last chip select value, determine the chip select value of the next chip select and trigger a new reset set and release signal.

[0065] Optionally, refer to the Figure 6 schematic diagram of the operation process of the multi-chip select module as shown.

[0066] S41, generate a new reset set and release signal, clear the count, re-count, and obtain the timing data; wherein, when the reset set and release signals of the fetch operation come from outside, initialize the chip select data; S42, determine whether the switching function is disabled. If so, go to S43; if not, go to S44; S43, determine whether the timing data is greater than the first timeout. If so, go to S45; if not, go to S41; S44, determine whether the timing data is greater than the second timeout. If so, go to S46; if not, go to S41; S45, determine whether the chip select data is the last configuration value of the current chip select. If so, go to S49; if not, go to S48; S46, determine whether the chip select data is the last chip select value. If so, go to S47; if not, go to S49; S47, control the multi-chip select module to stop abnormally; S48, determine the configuration value of the next chip select and go to S41; S49, determine the chip select value of the next chip select and go to S41.

[0067] Optionally, for the central processing unit, each time it receives the reset and release signals, it is a new starting point and will execute the instruction fetch operation from scratch. When the central processing unit receives the reset and release signals from the outside, it starts the instruction fetch operation through the XIP module, and controls the multi-chip selection module to initialize the chip selection data through the system control module, so that the XIP module can read the initial chip selection data to start the instruction fetch operation. Optionally, the initial chip selection data is the first configuration of the first chip selection. When the reset and release signals come from the outside, the system control module controls the multi-chip selection module to initialize the chip selection data. The initial chip selection data is Chip Selection 0_Configuration 0. When the reset and release signals come from the inside, that is, the instruction fetch operation fails and times out, at this time the multi-chip selection module generates new reset and release signals and feeds them back to the central processing unit due to the timeout, and configures the chip selection data for the next instruction fetch operation for the XIP module to read.

[0068] Optionally, when the switching function is enabled, when the timing data exceeds the first timeout, the multi-chip selection module generates new reset and release signals for the central processing unit. The central processing unit receives the reset and release signals generated by the multi-chip selection module and executes the instruction fetch operation from scratch. For example, when configuring the chip selection data for the next instruction fetch operation, if the current chip selection data (assuming the chip selection data includes: Chip Selection (0, 1, 2)_Configuration (0, 1, 2)) is the last configuration of the current chip selection, then it will switch to the next chip selection (for example, the next chip selection after Chip Selection 0_Configuration 2 is: Chip Selection 1_Configuration 0), otherwise it will switch to the next configuration (for example, the next configuration after Chip Selection 1_Configuration 0 is: Chip Selection 1_Configuration 1).

[0069] Optionally, when the switching function is disabled, when the timing data exceeds the second timeout, the multi-chip selection module generates reset and release signals for the central processing unit. The central processing unit executes the instruction fetch operation from scratch according to the reset and release signals generated by the multi-chip selection module. For example, assuming that the current chip selection data is the last chip selection value, since there is no chip selection value available, no new reset and release signals will be generated, otherwise the next chip selection value will be determined.

[0070] Optionally, after the XIP module completes all the instruction fetch operations in the startup phase, the central processing unit will send a stop command to the multi-chip selection module through the system control module. The multi-chip selection will stop counting under any circumstances and will no longer generate new reset and release signals. When the multi-chip selection module times out when the chip selection data is the last chip selection value and the last configuration value, the counting will stop at this time, and no reset and release signals will be generated, and the current state will be maintained so that the central processing unit / system can generate corresponding reminders for the implementers to debug and view.

[0071] Optionally, when the reset and release signals come from the inside, that is, the reset and release signals generated by the multi-chip select module, at this time, the timing data of the multi-chip select module reaches the timeout threshold; the system control module receives the reset and release signals of the multi-chip select module and controls the preset global reset, so that the Soc bus, the multi-chip select module, the central processing unit, and the XIP module enter the reset state according to the reset and release signals; the timing of the multi-chip select module is cleared and re-timed; the central processing unit controls the XIP module to fetch instructions again.

[0072] In the above startup control method, it is applied to the multi-chip select module, responds to the trigger reset and release signals, re-times to obtain the timing data, and receives the timeout threshold transmitted by the central processing unit through the system control module; when the timing data is greater than the timeout threshold, configure the chip select data for the next instruction fetch operation in a preset order, and generate new reset and release signals to be reset and managed through the system control module, so that the central processing unit controls the XIP module to fetch instructions again until the instruction fetch operation is completed. It can support accessing non-volatile memory based on the XIP module using the multi-chip select module to complete the startup process, reduce the probability of startup failure caused by damage to the existing non-volatile memory, and through the multi-chip select design, traverse the configuration parameters as much as possible and reasonably for each non-volatile memory to ensure that the non-volatile memory can read data, so as to implement the flexible and efficient use of XIP startup. By connecting the central processing unit with the system control module and the XIP module, the XIP module with the multi-chip select module, and the system control module with the multi-chip select module, it supports efficient and concise communication and interaction between the central processing unit and the hardware. In different startup stages, configure the switching function disable / enable in the multi-chip select module, and configure the chip select threshold for the switching function and the chip select function to prevent problems of the central processing unit that may occur accidentally in each startup stage, such as hanging and running away. Utilize the multi-chip select module to automatically generate reset and release signals based on the instruction fetch timeout caused by abnormal instruction fetch operations. The central processing unit quickly ends the current failed startup process according to the reset and release signals generated by the multi-chip select module and re-enters a new startup process to start fetching instructions again. Utilize the multi-chip select module to cooperate with the XIP module to access non-volatile memory to execute the instruction fetch operation, so as to improve the success rate of XIP startup, adapt to the reading of different types of non-volatile memory, and avoid the risk of system hanging caused by abnormalities of the central processing unit in each startup stage, thereby improving the reliability of the entire system startup.

[0073] The Fourth Embodiment In one embodiment, as Figure 7 shown, a startup control device is provided, including: a signal receiving module 110, a threshold sending module 120, and an instruction fetch control module 130, where: The signal receiving module 110 is configured to control the XIP module to start the instruction fetching operation in response to receiving the complex reset and release signals; The threshold sending module 120 is configured to determine the startup phase according to the instruction fetching operation, and control the multi-chip selection module to obtain the timeout threshold corresponding to the startup phase through the system control module; The instruction fetching control module 130 is configured to, when the startup phase does not run normally, obtain the complex reset and release signals generated by the multi-chip selection module based on the timeout threshold, so as to control the XIP module to re-fetch instructions based on the complex reset and release signals until all the startup phases run normally.

[0074] The fifth embodiment In one embodiment, as Figure 8 shown, a startup control device is provided, including: a data acquisition module 210 and a chip selection configuration module 220, wherein: The data acquisition module 210 is configured to re-time to obtain timing data and obtain a timeout threshold in response to triggering the complex reset and release signals; The chip selection configuration module 220 is configured to, when the timing data is greater than the timeout threshold, configure the chip selection data for the next instruction fetching operation in a preset order, and generate a new complex reset and release signal to be reset and managed by the XIP module, so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetching operation is completed.

[0075] For the specific limitations of the startup control device, reference may be made to the limitations on the startup control method in the foregoing text, which will not be elaborated here. Each module in the foregoing startup control device may be implemented in whole or in part by software, hardware, and their combination. The foregoing modules may be embedded in or independent of the processor in the computer device in the form of hardware, or may be stored in the memory in the computer device in the form of software, so as to facilitate the processor to call and execute the operations corresponding to the foregoing modules.

[0076] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as Figure 7 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store startup control data. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program, when executed by the processor, implements a startup control method.

[0077] Those skilled in the art can understand that Figure 7 the structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0078] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented: In response to receiving the reset and release signal, control the XIP module to start the instruction fetch operation; determine the startup phase according to the instruction fetch operation, and control the multi-chip select module to obtain the timeout threshold corresponding to the startup phase through the system control module; when the startup phase does not run normally, receive the reset and release signal generated by the multi-chip select module based on the timeout threshold, and control the XIP module to re-fetch instructions based on the reset and release signal until all the startup phases run normally and the startup is completed; Alternatively, when the processor executes the computer program, the following steps are implemented: In response to triggering the reset and release signal, re-time to obtain timing data, and obtain the timeout threshold; when the timing data is greater than the timeout threshold, configure the chip select data for the next instruction fetch operation in a preset order, and generate a new reset and release signal to be reset and managed through the system control module, so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetch operation is completed.

[0079] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: In response to receiving the reset and release signal, control the XIP module to start the instruction fetch operation; determine the startup phase according to the instruction fetch operation, and control the multi-chip select module to obtain the timeout threshold corresponding to the startup phase through the system control module; when the startup phase does not run normally, receive the reset and release signal generated by the multi-chip select module based on the timeout threshold, and control the XIP module to re-fetch instructions based on the reset and release signal until all the startup phases run normally and the startup is completed; Alternatively, when the computer program is executed by a processor, the following steps are implemented: In response to triggering a reset-set and release signal, re-time to obtain timing data and obtain a timeout threshold; when the timing data is greater than the timeout threshold, configure chip select data for the next instruction fetch operation in a preset order, and generate a new reset-set and release signal to reset and manage through the system control module, so that the central processing unit controls the XIP module to fetch instructions again until the instruction fetch operation is completed. Those of ordinary skill in the art can understand that all or part of the processes in the above-described embodiment methods can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-described method embodiments. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0080] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0081] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A startup control method, applied to a central processing unit, wherein the central processing unit is connected to a system control module and an XIP module respectively, the XIP module is connected to a multi-chip select module, and the system control module is connected to the multi-chip select module, characterized in that: The method comprises: S11, in response to receiving a reset position and a release signal, controlling the XIP module to start an instruction fetch operation; S12, determining a startup phase according to the instruction fetch operation, and controlling the multi-chip selection module through the system control module to obtain a timeout threshold corresponding to the startup phase; S13, when the startup phase does not operate normally, receiving the reset position and release signal generated by the multi-chip select module based on the timeout threshold, and controlling the XIP module to re-fetch instructions based on the reset position and release signal, until all the startup phases operate normally and the startup is completed.

2. The method according to claim 1, characterized in that The timeout threshold includes a first timeout and a second timeout, and the step S12 includes: When the startup phase is a preset initial startup phase, enabling the switching function in the multi-chip selection module through the system control module to obtain the first timeout pre-configured by the switching function; When the startup phase is a preset non-initial startup phase, the system control module turns off the switching function enable in the multi-chip selection module, and sends the second timeout corresponding to the chip selection function to the multi-chip selection module.

3. The method according to claim 1, characterized in that The S12 and above include: A plurality of startup phases in the startup process are pre-divided according to the instruction fetch operation.

4. The method according to claim 3, characterized in that The multiple startup phases include: Directly fetch instructions from the flash memory and actively move the program from the flash memory to the internal static memory in the BOOTROM stage; UBOOT stage to verify the moved program; The pointer will jump to the new address and execute the KERNEL stage of the moved program.

5. A startup control method, applied to a multi-chip select module, wherein the multi-chip select module is connected to a system control module and an XIP module, wherein the system control module is connected to a central processing unit, and the XIP module is connected to the central processing unit, wherein: The method comprises: S21, in response to the trigger reset position and the release signal, re-timing to obtain timing data, and obtaining a timeout threshold; S22, when the timing data is greater than the timeout threshold, the chip select data for the next instruction fetch operation is configured in a preset order, and a new reset position and release signal are generated to reset the management through the system control module so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetch operation is completed.

6. The method according to claim 5, characterized in that The timeout threshold includes a first timeout and a second timeout; and the step of obtaining the timeout threshold includes: Enabling the switching function in the multi-chip selection module based on the system control module to obtain a first timeout preconfigured for the switching function; Based on the system control module, the switching function in the multi-chip selection module is disabled, and the second timeout sent by the central processing unit through the system control module is received.

7. The method according to claim 6, characterized in that When the timing data is greater than the timeout threshold, configuring chip select data for the next instruction fetch operation in a preset order includes: Determine whether a preset switching function is enabled, and if the switching function is enabled, compare the timing data with the first timeout, and when the timing data is greater than the first timeout, configure the chip select data of the next instruction fetch operation according to the chip select and configuration sequence; If the switching function is disabled, the timing data is compared with the second timeout, and when the timing data is greater than the second timeout, the chip select data for the next instruction fetch operation is configured according to the chip select sequence.

8. The method according to claim 7, characterized in that The step of configuring the chip select data for the next instruction fetch operation in a preset order includes: Determine the chip select data of the current instruction fetch operation; When the switching function is enabled and the timing data is greater than the first timeout, determining a configuration value and / or a chip select value of the chip select data required for a next instruction fetch operation; Alternatively, when the switching function is disabled and the timing data is greater than the second timeout, a chip select value of the chip select data required for a next instruction fetch operation is determined.

9. The method according to claim 8, characterized in that The step of determining the configuration value and / or chip select value of the chip select data for the next instruction fetch operation includes: Determine whether the chip select data is the last configuration value of the current chip select, if so, continue to determine whether the chip select data is the last chip select value, if so, read the abnormal state of the multi-chip select module through the system control module; If the chip select data is not the last configuration value of the current chip select, then determine the configuration value of the next chip select, and trigger a new reset position and release signal; If the chip select data is not the last chip select value, the chip select value of the next chip select is determined, and a new reset position and release signal are triggered.

10. A startup control device, characterized in that: The device comprises: A signal receiving module, used for controlling the XIP module to start an instruction fetch operation in response to receiving a reset position and a release signal; A threshold sending module, used for determining a startup phase according to the instruction fetch operation, and controlling the multi-chip selection module through the system control module to obtain a timeout threshold corresponding to the startup phase; The instruction fetch control module is used to obtain the reset position and release signal generated by the multi-chip select module based on the timeout threshold when the startup phase does not operate normally, so as to control the XIP module to re-fetch instructions based on the reset position and release signal until all the startup phases operate normally.

11. A startup control device, characterized in that: The device comprises: A data acquisition module, for retiming to acquire timing data in response to a trigger reset position and a release signal, and acquiring a timeout threshold; The chip select configuration module is used to configure the chip select data for the next instruction fetch operation in a preset order when the timing data is greater than the timeout threshold, and generate a new reset position and release signal to reset the management through the system control module so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetch operation is completed.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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