Apparatus for die-to-die system

Abstract

An apparatus for a die-to-die system may include a die including at least one circuit configured to: receive a first byte, the first byte being mapped to a first channel of two or more channels of the die-to-die system; receiving a second byte, the second byte being mapped to a second channel of the two or more channels of the die-to-die system; transmitting a portion of the first byte using one of the two or more channels of the die-to-die system; and transmitting a portion of the second byte using the one of the two or more channels of the die-to-die system. The one of the two or more channels of the die-to-die system may be a first channel of the two or more channels of the die-to-die system. The one of the two or more channels of the die-to-die system may be a third channel of the two or more channels of the die-to-die system.

Description

[0001] This application claims the priority and benefit of U.S. Provisional Patent Application No. 63 / 608,819, filed on Dec. 11, 2023, and U.S. Patent Application No. 18 / 963,357, filed on Nov. 27, 2024, which are hereby incorporated by reference. Technical Field

[0002] This disclosure generally relates to die-to-die systems, and more particularly, to systems, methods, and devices for die-to-die systems with channel interleaving and error correction coding with retry. Background Art

[0003] Die-to-die (D2D) systems can be used to transfer data between integrated circuit dies. In some embodiments, a D2D system can be implemented with a system including one or more layers that can transfer data between dies using one or more channels, perform error detection, error correction, and / or retry operations, and / or implement one or more communication protocols, etc. In some embodiments, a D2D system can include one or more modules to implement one or more links with one or more channels between dies.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background of the principles of the invention, and thus it may contain information that does not constitute the prior art. Summary of the Invention

[0005] An apparatus may include: a die including at least one circuit configured to: receive a first byte mapped to a first channel of two or more channels of a die-to-die system; receive a second byte mapped to a second channel of the two or more channels of the die-to-die system; use one of the two or more channels of the die-to-die system to transmit a portion of the first byte; and use the one of the two or more channels of the die-to-die system to transmit a portion of the second byte. The one of the two or more channels of the die-to-die system may be the first channel of the two or more channels of the die-to-die system. The one of the two or more channels of the die-to-die system may be a third channel of the two or more channels of the die-to-die system. The portion of the first byte may be a first portion of the first byte, the portion of the second byte may be a first portion of the second byte, the one of the two or more channels of the die-to-die system may be a first one of the two or more channels of the die-to-die system, and the at least one circuit may be configured to: generate a fourth byte including a second portion of the first byte and a second portion of the second byte; and use a second one of the two or more channels of the die-to-die system to transmit the fourth byte. The second one of the two or more channels of the die-to-die system may be the second channel of the two or more channels of the die-to-die system. The second one of the two or more channels of the die-to-die system may be a third channel of the two or more channels of the die-to-die system. The at least one circuit may be configured to: generate error correction information for the portion of the first byte and the portion of the second byte; and use a channel of the die-to-die system to transmit at least a portion of the error correction information. The at least one circuit may be configured to generate the error correction information using variable rate coding.

[0006] An apparatus may include: a die including at least one circuit configured to: receive data to be transmitted using a die-to-die system; generate error correction information for the data; encode the data and the error correction information to generate encoded information; and use the die-to-die system to transmit at least a portion of the encoded information. The at least one circuit may be configured to generate the error correction information using variable rate coding. The at least one circuit may be configured to generate the error correction information using an error correction code.

[0007] An apparatus may include: a die including at least one circuit configured to: receive data to be transmitted using a die-to-die system; generate error correction information for the data; perform a first transmission operation including transmitting the data using the die-to-die system; receive a request based on the first transmission operation; and perform a second transmission operation based on the request, the second transmission operation including transmitting a portion of the error correction information. The portion of the error correction information may be a first portion of the error correction information, the request may be a first request, and the at least one circuit may further be configured to: receive a second request based on the second transmission operation; and perform a third transmission operation based on the second request, the third transmission operation including transmitting a second portion of the error correction information. The portion of the error correction information may be a first portion of the error correction information, and wherein the first transmission operation may include transmitting a second portion of the error correction information. The at least one circuit may be configured to determine the first portion of the error correction information based on a coding rate. The at least one circuit may be configured to generate the error correction information using variable rate coding. The at least one circuit may be configured to generate the error correction information using a convolutional code. The at least one circuit may be configured to generate the error correction information using a turbo code. The at least one circuit may be configured to determine the portion of the error correction information based on a coding rate. The at least one circuit may include a buffer configured to store at least a portion of the error correction information. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings are not necessarily to scale, and throughout the drawings, for illustrative purposes, elements or portions of elements of similar structure or function may generally be represented by reference indicators that end and / or include the same numerals and / or letters, etc. The drawings are only intended to facilitate the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the drawings from becoming obscured, not all components and connections, etc. may be shown, and not all components may have reference numerals. However, the pattern of component configurations can be readily apparent from the drawings. The drawings, together with the specification, illustrate example embodiments of the present disclosure and are used together with the specification to explain the principles of the present disclosure.

[0009] Figure 1 An embodiment of an architecture for a D2D system according to an example embodiment of the disclosure is shown.

[0010] Figure 2 An embodiment of a bit arrangement within a byte transfer on one or more channels according to an example embodiment of the disclosure is shown.

[0011] Figure 3 An embodiment of a byte-to-channel mapping according to an example embodiment of the disclosure is shown.

[0012] Figure 4 An embodiment of an interface architecture for a D2D system according to an exemplary embodiment disclosed is shown.

[0013] Figure 5 An embodiment of a D2D system having a channel interleaving scheme according to an exemplary embodiment disclosed is shown.

[0014] Figure 6 An embodiment of an interleaving scheme according to an exemplary embodiment disclosed is shown.

[0015] Figure 7 An embodiment of an interface architecture for a D2D system having interleaving and error correction according to an exemplary embodiment disclosed is shown.

[0016] Figure 8 An embodiment of a retry scheme for a D2D system having error correction according to an exemplary embodiment disclosed is shown.

[0017] Figure 9 An exemplary embodiment of one or more operations of a buffer for a retry operation according to an exemplary embodiment disclosed is shown.

[0018] Figure 10 Another embodiment of an interface architecture for a D2D system having interleaving and error correction according to an exemplary embodiment disclosed is shown.

[0019] Figure 11 An exemplary embodiment of CRC information in data information and parity check information according to an exemplary embodiment disclosed is shown.

[0020] Figure 12 An embodiment of a method for transmitting information using a D2D system according to an exemplary embodiment disclosed is shown.

[0021] Figure 13 An embodiment of a method for receiving information using a D2D system according to an exemplary embodiment disclosed is shown. Detailed Description

[0022] A die-to-die (D2D) interconnect system (which may be referred to as a D2D system) can be used to transfer data between integrated circuit (IC) dies (which may also be referred to as chips). The D2D system can enable multiple dies to be assembled in a package (e.g., as a system-in-package (SIP)). This can enable different relatively small dies (which may be referred to as dielets and / or chiplets) to be adapted to perform different dedicated functions (e.g., processing, input and / or output (I / O), memory, etc.), which, depending on the implementation details, can improve performance, cost, and / or reliability compared to integrating multiple functions on a single larger die. In some embodiments, the D2D system can be used to transfer data between dies in one package and dies in a different package (or other components), for example, by using retiming circuits.

[0023] Data transferred using the D2D system can have an error rate (e.g., bit error rate (BER)) that can be caused, for example, by noise, interference, distortion, and / or attenuation in the physical (PHY) layer and / or electrical connections, etc., used for the D2D system. One type of error mode that the D2D system may encounter is a burst error mode, in which multiple symbols (e.g., bits) with errors can be associated with physical and / or logical structures such as channels, lanes, bytes, blocks, packets, and / or streams, etc. For example, in a burst error, multiple bits that may be adjacent or relatively close to each other during transmission (e.g., within a byte transmitted over a channel) may have errors.

[0024] Another type of error mode that the D2D system may encounter is a random error mode, in which symbols (e.g., bits) with errors (e.g., single-bit errors within a channel, byte, and / or stream, etc.) can be randomly scattered across uncorrelated physical and / or logical structures. Errors from burst errors and / or random errors, etc., can contribute to the overall BER for the D2D system.

[0025] An interleaving scheme for a D2D system according to an exemplary disclosed embodiment may use a first channel to transmit a first portion (e.g., the first bit) of a transmission unit (e.g., a byte) and a second channel to transmit a second portion (e.g., the second bit) of the transmission unit. According to implementation details, such a channel interleaving scheme may improve the operation of an error correction scheme. For example, a particular convolutional code may be relatively effective in correcting random errors but less effective in correcting burst errors. However, a bit and / or channel interleaving scheme according to an exemplary disclosed embodiment may spread individual errors within a burst error across multiple channels, thereby transforming the burst error pattern into an error pattern that can be characterized as a random error pattern. Thus, according to implementation details, a convolutional code may effectively correct some or all of the errors that may otherwise be more difficult to correct as part of a burst error. The interleaving scheme may be implemented, for example, with a link layer and / or other logic associated with the D2D system.

[0026] An encoding scheme for a D2D system according to an exemplary disclosed embodiment may apply an error correction scheme to data received through a link layer interface. The encoding scheme may generate encoded information (or encoded data), which may include error correction information (e.g., parity information) that can be used to correct one or more errors. The encoded data may be transmitted to the physical layer of the D2D system through a physical layer interface. The encoding scheme may be implemented, for example, with a link layer and / or other logic associated with the D2D system. According to implementation details, the encoding scheme may improve the bit error rate of data transmitted by the physical layer, for example, by enabling a receiving device to correct one or more errors in the encoded data.

[0027] A retry scheme for a D2D system according to an exemplary disclosed embodiment may transmit less data information and / or more error correction information based on receiving a repeat request (e.g., a retry request). For example, in some embodiments, in a first transmission, logic on the transmitting side of the D2D system may transmit data information (e.g., a data payload) with a first amount of error correction information to a receiving device. For example, the first amount of error correction information may not include parity information for the data information or may include a first portion of the parity information for the data information. The receiving device may, for example, send a repeat request to the transmitting side based on "the receiving device is unable to correct one or more errors in the data information based on the first amount of error correction information included with the first transmission."

[0028] Based on receiving a duplicate request, the logic on the sending side may perform a second transmission, in which the logic on the sending side may send less data information (e.g., no data payload) along with more error correction information to the receiving device. For example, if the first transmission does not include parity information, the second transmission may include a first part of the parity information, or if the first transmission includes a first part of the parity information, the second transmission may include a second part of the parity information. The receiving device may combine the error correction information sent together with the second transmission with the error correction information (if any) sent together with the first transmission to correct one or more errors in the data information.

[0029] Based on the ability of the receiving device to adequately correct one or more errors in the data information using the error correction information included with the second transmission, the receiving device may send one or more additional duplicate requests, and the logic on the sending side may perform one or more additional transmissions including additional error correction information (e.g., one or more additional parts of the parity information for the data information).

[0030] According to implementation details, while reducing or minimizing the amount of error correction information that can be sent (e.g., initially sending little or no parity information and progressively sending more parity information based on retry requests until the receiving device has enough parity information to adequately correct one or more errors in the data information), the retry scheme according to the disclosed example embodiments may reduce the total amount of information involved in sending the data information (e.g., by reducing the number of times some or all of the data information is re-sent (e.g., not sending the data information based on retry requests)). According to implementation details, this may reduce the latency of the D2D system, reduce the overhead of the D2D system, increase the throughput of the D2D system, and / or increase the bandwidth of the D2D system, etc.

[0031] This disclosure encompasses many aspects related to D2D systems. The aspects disclosed herein may have independent utility and may be implemented separately, and not every embodiment may utilize every aspect. Additionally, the aspects may also be implemented in various combinations, and some of the various combinations may synergistically amplify some of the benefits of the individual aspects.

[0032] For illustrative purposes, some embodiments may be described in the context of some specific implementation details such as protocols, error detection and / or correction algorithms, interconnection standards, the number and / or type of components, and / or byte-based data processing, etc. However, the disclosed aspects are not limited to these or any other implementation details. Although some embodiments may be described in the context of D2D systems, some aspects may be applicable to other types of interconnections. Additionally, terms such as die, bare die, chip, and / or chiplet, etc. may be used interchangeably to denote any type of integrated circuit device. Thus, the systems, methods, devices, and / or all related principles disclosed herein may be applied to the interconnection between any type of integrated circuit device (regardless of any type of package, lack of package, substrate, interposer, semiconductor bridge, and / or via, etc.), and may be referred to interchangeably as D2D, chip-to-chip (C2C), and / or die-to-chip, etc.

[0033] Multiple instances of elements identified with the same base number and different suffixes may be represented by the base number alone and / or jointly. For example, Figure 4 one or more of the protocols 416T-1, 416T-2, 416T-3, and / or 416T-4 shown in may be referred to as 416T alone and / or jointly. As another example, Figure 4 one or more of the protocols 416T-1, 416T-2, 416T-3, 416T-4, 416R-1, 416R-2, 416R-3, and / or 416R-4 shown in may be referred to as 416 alone and / or jointly.

[0034] Figure 1 An embodiment showing an architecture for a D2D system according to the disclosed example embodiments is shown. Figure 1 The D2D system 101 shown in may include a transaction layer 102, a link layer 104, and / or a physical layer 106. The transaction layer 102 and the link layer 104 may interact via a link layer interface 103. The link layer 104 and the physical layer 106 may interact via a physical layer interface 105. The physical layer 106 may send and / or receive information via link 107.

[0035] For illustrative purposes, Figure 1Some descriptions of the D2D system 101 shown may be based on an embodiment of "each layer and / or interface" having one, however, other embodiments may have multiple "one or more components", and / or one or more components may be omitted. Thus, a reference to the transaction layer 102 may represent one or more transaction layers 102, a reference to the link layer interface 103 may represent one or more link layer interfaces 103, a reference to the link layer 104 may represent one or more link layers 104, a reference to the physical layer interface 105 may represent one or more physical layer interfaces 105, and / or a reference to the physical layer 106 may represent one or more physical layers 106. Additionally, generally, within this disclosure, a reference to an element or the element may represent one or more of the element.

[0036] Although Figure 1 The D2D system 101 shown is not limited to any particular implementation details, but in some embodiments, the D2D system 101 may be implemented at least in part with Universal Chiplet Interconnect Express (UCIe) components. In such embodiments, the transaction layer 102, the link layer interface 103, the link layer 104, the physical layer interface 105, and / or the physical layer 106 may be implemented, for example, at least in part with a protocol layer, a flit-aware D2D interface (FDI), an adapter, a raw D2D interface (RDI), and / or a physical layer, respectively. Other examples of D2D protocols and / or standards that may be implemented with or used to implement the D2D system 101 may include any generation and / or version, etc., of the Advanced Interface Bus (AIB), Interlaken, Bundle of Wires (BOW), and / or Open High Bandwidth Interconnect (OpenHBI), etc., or combinations thereof.

[0037] In some embodiments, and depending on the context, some or all of the transaction layer 102, the link layer 104, the physical layer 106, the link layer interface 103, the physical layer interface 105, and / or the link 107 may be collectively referred to as a D2D system, a chip-to-chip system, a D2D interconnect, and / or a D2D interconnect system. Additionally or alternatively, and depending on the context, Figure 1 Some or all of the components shown may be collectively referred to as interconnects, interconnect interfaces, stacks, interconnect stacks, architecture stacks, interconnect logic, partners (e.g., from the perspective of a remote link partner of another D2D system that can communicate with the D2D system 101 through one or more links 107 that may be referred to as die-to-die links, D2D wires, and / or die links), the transmit or transmitter end of the link 107 (e.g., when the D2D system 101 is configured and / or operated to transmit information), the receive or receiver end of the link 107 (e.g., when the D2D system 101 is configured and / or operated to receive information), and / or one or more other terms that may be clear from the context. In some embodiments, and depending on the implementation details,Figure 1 One or more of the components shown in Figure 1 or portions thereof may be integrated into additional logical and / or physical components. For example, some or all of the transaction layer 102 may be application specific (e.g., application software layer) and / or implemented by an application (e.g., application software layer). In such an embodiment, some or all of the transaction layer 102 may overlap with the application. In such an embodiment, and depending on the implementation details and / or context, the D2D system 101 may be characterized as excluding some or all of the transaction layer 102.

[0038] In some embodiments, a first D2D system (e.g., a first instance of the D2D system 101) may be implemented on a first die or chip, and a second D2D system (e.g., a second instance of the D2D system 101) may be implemented on a second die or chip. The first interface and the second interface may be connected using one or more connectors (e.g., electrical connectors and / or optical connectors, etc.) implemented using one or more contacts, solder joints, conductors, and / or transmission lines, etc., to support one or more communication links 107 between the first interface and the second interface. For example, the first interface and the second interface may be connected by one or more conductors (e.g., conductive traces configured as transmission lines that may have a characteristic impedance), which pass through one or more substrates, interposers, and / or bridges, etc., and extend over and / or along one or more substrates, interposers, and / or bridges, etc. In some embodiments, and depending on the implementation details and / or context, one or more connectors (e.g., electrical connectors, optical connectors, etc.) between D2D systems may be referred to as interconnects, channels, and / or interconnect channels, etc.

[0039] The transaction layer 102 may implement one or more protocols that may be used to transfer data using the physical layer 106. Examples of protocols that may be implemented by the transaction layer 102 may include Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Advanced eXtensible Interface (AXI), Coherent Hub Interface (CHI), Cache Coherent Interconnect for Accelerators (CCIX), and / or CCIX Stream Interface (CXS), etc. Additionally or alternatively, the transaction layer 102 may implement one or more modes and / or formats, etc. (e.g., stream mode, general mode, and / or raw format, etc.) that may support one or more user-configured (e.g., user-defined) protocols.

[0040] According to the disclosed example embodiments, the link layer 104 may implement one or more of a variety of functions, operations, and / or features, etc. For example, the link layer 104 may coordinate one or more operations of the transaction layer 102 and / or the physical layer 106 to transfer data across one or more links 107 implemented by the physical layer 106. As another example, the link layer 104 may implement cyclic redundancy check (CRC) to detect errors and / or implement a retry mechanism to retransmit data. The link layer 104 may be requested and / or configured, etc., to implement CRC and / or the retry mechanism, for example, through the transaction layer 102 and / or an application that may implement part or all of the transaction layer 102 in some embodiments.

[0041] As a further example, if the link layer 104 is configured to support more than one protocol and / or instance of a protocol (e.g., using one or more protocol stacks), the link layer 104 may implement arbitration (ARB) and / or multiplexing (MUX) functions. As yet another example, the link layer 104 may implement a scheme for detecting link health (e.g., by periodically injecting one or more parity bytes into the data stream (e.g., as part of a data transfer operation (which may be referred to as a runtime operation in some embodiments))). Additional examples may include link state management and / or parameter negotiation for one or more links 107 that may be implemented by the physical layer 106 (e.g., between one or more D2D systems 101 and / or one or more of their components), etc.

[0042] The physical layer 106 may include devices for implementing one or more links 107 between D2D systems and / or between a D2D system and one or more other devices (e.g., off-die devices). The link 107 may include a group of one or more channels. In some embodiments, the link 107 may include a main band portion (e.g., 16 data channels (x16 data) or 64 data channels (x64 data)) and / or a side band portion (e.g., 2 side band channels (x2 side band)). Some links 107 may be implemented with one or more modules, each of which may include one or more channels of one or more types (e.g., 16 main band channels and 2 side band channels per module, and / or 64 main band channels and 2 side band channels per module, etc.). In some embodiments, the link 107 may be characterized as having an N-byte data path, where N may indicate the total number of data channels in the link 107. For example, a link implemented with four modules each having 16 data channels may have a 64-byte data path, and a link implemented with two modules each having 64 data channels may have a 128-byte data path.

[0043] In some embodiments, the physical layer 106 may be implemented with one or more sub-layers (e.g., a logical physical layer (logical PHY), and / or an electrical layer that may include and / or be referred to as an analog front end (AFE)).

[0044] The electrical layer may include one or more transmitters and / or receivers, etc. for implementing one or more channels. A channel may be implemented with a transmitter and a receiver (e.g., to implement a pair of a transmitted signal and a received signal). The transmitter may include one or more components (such as, a buffer (e.g., a first-in first-out (FIFO) buffer), a serializer for converting parallel data to serial data, one or more drivers for driving an electrical signal on a channel, a de-skew circuit, a phase differentiator, and / or a clock circuit (e.g., a clock forwarding circuit), etc.). The receiver may include one or more components (such as, one or more amplifiers and / or sampling circuits (such as, flip-flops (e.g., for receiving a data signal and / or a clock signal, etc.)), a de-skew circuit, a buffer, a deserialization circuit, and / or a clock circuit (e.g., phase generation), etc.).

[0045] The logical physical layer may coordinate and / or manage one or more operations of the electrical layer (e.g., initialization, sequencing, transmission, and / or reception, etc.). For example, the logical physical layer may implement a byte-to-lane mapping, in which data packets may be transmitted by bytes, and one or more bytes are transmitted on separate channels (e.g., byte byte 0 may be transmitted on channel Lane 0, byte byte 1 may be transmitted on channel Lane 1, and so on). A byte may be transmitted during eight consecutive unit intervals (UI), such that each bit of the byte may be transmitted on the same channel during the corresponding UI.

[0046] Figure 2 An embodiment showing a bit arrangement within a byte transmission on one or more channels according to an exemplary embodiment disclosed. In Figure 2 the embodiment shown, data of one byte indicated as B0, B1,... may be transmitted on corresponding channels indicated as channel Lane 0, Lane 1,... based on a clock signal Clock and / or a valid signal Valid. Bits 0 to 7 of byte B0 may be indicated as B0[0], B0[1],..., B0[7] respectively. Similarly, bits 0 to 7 of byte B1 may be indicated as B1[0], B1[1],..., B1[7] respectively. Each bit transmission may occupy one UI, and thus, a byte transmission may occupy 8 UIs. In Figure 2In the example embodiments shown, a byte may be considered a transfer unit, and thus, the transfer interval may be 8 UIs. However, in other embodiments, other transfer units (e.g., 4-bit nibbles, 16-bit words, 32-bit words, and / or 64-bit words, etc. to which the physical layer may be mapped to channels) may be used.

[0047] Figure 3 An embodiment showing byte-to-channel mapping according to the disclosed example embodiments. In Figure 3 the example shown, a 256-byte transaction is performed in a 16-byte portion (e.g., to use a 16-channel (e.g., x16) module). In some embodiments, an operation of sending one byte on each data channel in a link having N data channels (which may be referred to as an N-channel link) may be referred to as a transfer, data transfer, or N-byte transfer (e.g., a 16-byte transfer on a link having 16 data channels). Thus, in some embodiments, the number of bytes in an N-byte transfer may correspond to the number of channels in the data path of the link.

[0048] In addition to Figure 3 the byte-to-channel mapping shown, other byte-to-channel mappings may be used. For example, in some embodiments, information may be transferred in groups of any number of bytes, and / or a set of groups may be transferred over any number (not just 16, 64, etc.) of channels per link (e.g., transferred in multiples of any number, not just 256). In some embodiments, the number of bytes per transferred group may be different from the number of channels in the link. Thus, one or more channels may not be used for the transfer of a group of bytes (e.g., for data).

[0049] Referring again to Figure 1 , as another example of a logical physical layer feature, the logical physical layer may implement a scrambling and / or descrambling scheme in which the sequence of bits to be sent on a channel may be reordered such that the bits are on the same channel but sent in a different sequence. For example, referring to Figure 2 , the sequence in which bits B0[0], B0[1], ……, B0[7] are sent may be reordered, but the bits within byte 0 are still sent on Lane 0. A linear feedback shift register (LFSR) may be used, for example, to reorder the bit sequence of a channel. In some embodiments, each channel may use a separate LFSR and a different seed value to reorder the sequence of bits of the channel.

[0050] Further examples of functions that may be performed by the logical physical layer may include coordinating the link state machine and / or initialization, coordinating protocol option and / or parameter exchange (e.g., with another D2D system (remote link partner) at the other end of the link), link training, channel repair, channel inversion, sideband initialization, and / or transfer, etc.

[0051] The link layer interface 103 can be implemented, for example, with one or more signals (e.g., digital electrical signals) that can facilitate the transfer of information between the transaction layer 102 and the link layer 104. Examples of signals used by the link layer interface 103 can include one or more (e.g., 8, 16, 32, etc.) data signals for transferring data from the transaction layer 102 to the link layer 104, one or more (e.g., 8, 16, 32, etc.) data signals for transferring data from the link layer 104 to the transaction layer 102, one or more clock signals that can be used to time one or more (e.g., all) other signals, one or more signals for implementing a sideband interface, and one or more signals for performing functions such as configuration, control, and / or status for the link layer interface 103. Examples of configuration functions can include a flow identifier (flow ID) that can be used for data transfer to and / or from the link layer 104, the number of data signals used by the link layer interface 103, and / or the link speed, etc. In some embodiments, the flow ID can be mapped to a stack and / or protocol (e.g., PCIe, CXL.io, CXL.cache, CXL.mem, CXL.cachemem, a flow protocol, and / or a raw format, etc.). Examples of control functions can include requesting a status change and / or requesting a data transfer, etc. Examples of status functions can include indicating the status of the link layer interface 103, indicating that data is available, indicating a negotiated protocol, indicating that the link 107 may be training, and / or indicating an error, etc.

[0052] The physical layer interface 105 can be implemented, for example, with one or more signals (e.g., digital electrical signals) that can facilitate the transfer of information between the link layer 104 and the physical layer 106. Examples of signals used by the physical layer interface 105 can include one or more (e.g., 8, 16, 32, etc.) data signals for transferring data from the link layer 104 to the physical layer 106, one or more (e.g., 8, 16, 32, etc.) data signals for transferring data from the physical layer 106 to the link layer 104, one or more clock signals that can be used to time one or more (e.g., all) other signals, and / or one or more signals for performing functions such as configuration, control, and / or status for the physical layer interface 105. Examples of configuration functions can include the number of data signals used by the physical layer interface 105 and / or the link speed, etc. Examples of control functions can include requesting a status change and / or requesting a data transfer, etc. Examples of status functions can include indicating the status of the physical layer interface 105, indicating that data is available, and / or indicating an error, etc.

[0053] In some embodiments, the physical layer interface 105 may be characterized as a raw interface and / or a raw die-to-die interface, etc. For example, depending on the implementation details, the physical layer interface 105 may be used to implement a raw format for transmission from the link layer 104 to the physical layer 106. In some embodiments, the physical layer interface 105 may be implemented at least in part using a state machine that can be queried, controlled, configured, and / or reset, etc., using one or more of the above signals. In some embodiments, the raw format may mean that the physical layer interface 105 may cause the physical layer 106 to transmit (e.g., for each transmission) any N bytes passed by the link layer 104 through the physical layer interface 105, regardless of what is in the N bytes. Additionally or alternatively, the link layer 104 may use the byte-to-channel mapping implemented by the physical layer 106, and the link layer 104 (other than knowing to send each byte using a separate channel) may not know about the byte-to-channel mapping.

[0054] In some embodiments, Figure 1 one or more components of the D2D system shown in (e.g., the link layer 104 and / or the physical layer 106) may be used to implement and / or replace, etc., one or more parts of a protocol. For example, in some embodiments, some or all of the link layer 104 and / or the physical layer 106 may be used to replace some or all of the serializer / deserializer (SERDES or SerDes) part of the physical layer of the PCIe protocol and / or some or all of the logical physical (LogPHY) part of the physical layer of the PCIe protocol and / or the CXL protocol. Depending on the implementation details, such a configuration may improve the performance (e.g., bandwidth, latency, and / or power efficiency, etc.) and / or cost, etc., of the protocol.

[0055] In some embodiments, one or more components of the D2D system 101 and / or one or more of its parts may be configured to operate at least in part based on one or more modes, operation formats (e.g., raw format and / or flow control unit (flit) format, etc.), or a combination thereof.

[0056] The mode may be based on, for example, the protocol implemented by the transaction layer 102. Examples of the mode may include PCIe flit mode, PCIe non-flit mode, CXL 68-byte (68B) flit mode, CXL 256-byte (256B) flit mode, and / or flow mode (which may also be referred to as a flow protocol), etc.

[0057] The operation format can be based on techniques such as: the link layer 104 can be used to arrange (e.g., rearrange) the data information received from the transaction layer 102 into one or more transmissions (e.g., N-byte transmissions) that are "sent by the link layer 104 (e.g., using the physical layer interface 105) to the physical layer 106 for transmission over the data path of the link 107". Examples of operation formats can include the raw format, the 68B microslice format, and / or the 256B microslice format, etc.

[0058] Some modes can be used (e.g., implemented) with one or more operation formats. For example, the CXL 68B microslice mode can be used with the 68B microslice format (and in some embodiments may be used only with the 68B microslice format), while the streaming mode can operate with the raw format, the 68B microslice format, and / or the 256B microslice format, etc.

[0059] In some embodiments, a mode, an operation format, or a combination thereof can implement an error detection mechanism and / or a retry mechanism, etc., at the transaction layer 102, the link layer 104, or a combination thereof. For example, some protocols can implement an error detection mechanism and / or a retry mechanism at the transaction layer 102 and thus may not rely on the error detection mechanism and / or the retry mechanism at the link layer 104. As another example, some protocols can rely on the error detection mechanism and / or the retry mechanism at the link layer 104 and thus may not implement an error detection mechanism and / or a retry mechanism at the transaction layer 102. As another example, in some embodiments, a first error detection mechanism and / or a retry mechanism can be implemented at the transaction layer 102, and a second (e.g., independent) error detection mechanism and / or a retry mechanism can be implemented at the link layer 104.

[0060] In a first example configuration of protocol modes and operation formats, the transaction layer 102 and the link layer 104 can be configured to implement the protocol using the 256B microslice format (e.g., the PCIe microslice mode and / or the CXL 256B microslice mode, etc.). In such a configuration, the link layer 104 can receive one or more data bytes from the transaction layer 102, calculate a checksum (e.g., a CRC code) for the data bytes, and arrange the data bytes, the checksum, and / or one or more header bytes, etc., into one or more groups of bytes that can be transmitted to the physical layer 106 for transmission over the link 107. In some embodiments, a group of bytes can include a number of bytes corresponding to the number of bytes in the data path of the link 107. The link layer of another D2D system (e.g., a remote link partner) at the other end of the link 107 can receive the group of bytes, use the checksum to verify errors in the data bytes, and based on a successful transmission, transmit the data bytes to the transaction layer at the other D2D system. In some embodiments, in addition to some or all of the data bytes, the checksum calculation can also include one or more header bytes and / or other types of information.

[0061] In a first example configuration, the link layer 104 may additionally or optionally implement a retry mechanism. For example, the link layer 104 may include retry logic with a retry buffer that may store information (e.g., one or more microtiles and / or one or more groups of bytes, etc.) that has been transmitted to the physical layer 106 for transmission on the link 107. The retry logic may retransmit the information stored in the retry buffer based on, for example, receiving a retry message from the link layer of another D2D system at the other end of the link 107. The retry message may be based on, for example, an error detected at the receiving link layer.

[0062] In a second example configuration of the protocol mode and operation format, the transaction layer 102 and the link layer 104 may be configured to implement a flow protocol using the raw format. In such a configuration, the link layer 104 may receive one or more data bytes from the transaction layer 102 and transmit the data bytes to the physical layer 106 with little or no modification. For example, in some embodiments, the link layer 104 may allow the transaction layer 102 to directly fill one or more groups of bytes that can be transmitted to the physical layer 106 for transmission on the link 107. In such a configuration, the transaction layer 102 may implement an error detection mechanism and / or a retry mechanism, etc. (if any).

[0063] Figure 4 An embodiment of an interface architecture for a D2D system according to the disclosed example embodiments is shown. Figure 4 The embodiment shown may include a first D2D system 401T and a second D2D system 401R connected to one or more links (e.g., D2D links) 407. The first D2D system 401T may be located at a first die (Die 0) 408, the second D2D system 401R may be located at a second die (Die 1) 409, and the one or more links 407 may be implemented using, for example, one or more conductors on and / or in one or more substrates, interposers, and / or bridges, etc. Either or both of the first die 408 and / or the second die 409 may be implemented using one or more dies (chips), cores, and / or any other type of integrated circuit device.

[0064] For illustrative purposes, the first D2D system 401T and the second D2D system 401R may be respectively configured and / or operated as a transmitting (TX) D2D system and a receiving (RX) D2D system. However, either or both of the first D2D system 401T and the second D2D system 401R may be capable of transmitting and / or receiving data across one or more links 407.

[0065] The first D2D system 401T (which may also be referred to as a transmitting D2D system or a transmitting interface) may include a transaction layer 402T, a link layer 404T, and / or a physical layer (Phy) 406T. The transaction layer 402T and the link layer 404T may communicate using a link layer interface 403T. The link layer 404T and the physical layer 406T may communicate using a physical layer interface 405T.

[0066] The second D2D system 401R (which may also be referred to as a receiving D2D system or a receiving interface) may include a transaction layer 402R, a link layer 404R, and / or a physical layer 406R. The transaction layer 402R and the link layer 404R may communicate using a link layer interface 403R. The link layer 404R and the physical layer 406R may communicate using a physical layer interface 405R.

[0067] The transaction layer 402T at the transmitting interface 401T and / or the transaction layer 402R at the receiving interface 401R may implement one or more protocols and / or their modes. In Figure 4 the example shown, the transaction layer 402T may implement a first streaming protocol 416T-0 indicated as Streaming 0 (e.g., using a first on-die (OD) interface port OD0 (e.g., an AXI port)), a second streaming protocol 416T-1 indicated as Streaming 1 (e.g., using a second OD interface port OD1 (e.g., a CHI port)), and / or a third streaming protocol 416T-2 indicated as Streaming 2 (e.g., using a third OD interface port OD2 (e.g., a CXS port)). Additionally or alternatively, the transaction layer 402T may implement a protocol 416T-3, which may implement a protocol transaction layer that can send and / or receive transaction layer packets (TLPs) (e.g., PCIe and / or CXL, etc.) or be implemented with a protocol transaction layer that can send and / or receive transaction layer packets (TLPs) (e.g., PCIe and / or CXL, etc.). One or more of the protocols 416T-0, 416T-1, 416T-2, and / or 416T-3 (which may be referred to individually and / or collectively as 416T) may be implemented with one or more corresponding stacks (e.g., one or more hardware and / or software stacks), e.g., one stack per protocol. In some embodiments, one or more of the protocols 416T may implement a protocol layer with an interface (e.g., to access the protocol).

[0068] In some embodiments, the link layer 404T may include multiplexing logic (or multiplexer logic) (Mux) 420 (which may include arbitration logic), retry logic 417, CRC logic 418, and / or parity check logic 419.

[0069] The arbitration and / or multiplexing logic 420 may be configured to multiplex two or more protocols, two or more protocol stacks, and / or two or more protocols within a stack, etc. onto the physical layer 406T and / or the link 407, etc. For example, in some embodiments, and depending on implementation details, the arbitration and / or multiplexing logic 420 may multiplex two or more protocols, two or more protocol stacks, two or more protocols within a stack, etc. onto the physical layer 406T and / or the link 407, etc., such that they may share the bandwidth of the link 407.

[0070] The retry logic 417 may implement a retry scheme in which the link layer 404T may store information (e.g., one or more microtiles or portions thereof, and / or groups of bytes, etc.) that has been transmitted to the physical layer 406T for transmission on the link 407 for retransmission. The retry logic 417 may include a retry buffer 421 and / or a retry multiplexer 422. The retry buffer 421 is used to store information for retransmission, and the retry multiplexer 422 may switch between transmitting information about a first attempt (e.g., from the arbitration and / or multiplexing logic 420) and retransmitting information from the retry buffer 421. The retry logic 417 may retransmit information (e.g., one or more microtiles or portions thereof, groups of bytes, etc.) based on, for example, a retry message received from the link layer of another D2D system at the other end of the link 407. The retry message may be based on, for example, error detection at the receiving link layer (e.g., using CRC information).

[0071] The retry scheme may be selected and / or enabled by the protocol 416T, by the link layer 404T, or a combination thereof. In some embodiments, the retry scheme may be automatically enabled based on the protocol 416T and / or the operation format configuration. For example, in some embodiments, when the transaction layer 402T and / or the link layer 404T are configured to use the protocol in the microtile mode using the microtile format, the retry scheme may be automatically enabled. As another example, when the transaction layer 402T and / or the link layer 404T are configured to use the raw format, the retry scheme may be automatically disabled.

[0072] The CRC logic 418 may include the function of inserting error detection information into one or more microtiles or portions thereof, groups of bytes, sets of groups of bytes, etc. For example, the CRC logic 418 may include a CRC generator polynomial circuit configured to generate a CRC code, and the CRC code may be inserted into one or more microtiles or portions thereof and / or groups of bytes, etc. that can be transmitted from the physical layer 406T to the physical layer 406R.

[0073] When applicable, the parity logic 419 may include the function of inserting parity information in one or more microchips or portions thereof, groups of bytes, and / or collections of groups of bytes, etc. For example, when the transaction layer 402T implements a specific protocol using a parity scheme, the parity logic 419 may be used to insert parity information. The parity logic 419 may include a multiplexer 425, and the multiplexer 425 may be used to insert the parity information generated by the parity generator 424 into the data that can be transmitted from the link layer 404T to the physical layer 406T for transmission on the link 407.

[0074] The physical layer 406T may include devices for implementing the link 407 between the transmitting D2D system 401T and the receiving D2D system 401R. The physical layer 406T may implement any of the structures and / or functions, etc. described in the embodiments shown above regarding a group of one or more channels that may have a main band portion (e.g., one or more data channels) and / or a side band portion (e.g., one or more side band channels), any or all of which may be implemented as modules, one or more sub-layers (e.g., a logical physical layer and / or an electrical layer, etc.), an analog front end, one or more transmitters and / or receivers, etc., using any byte-to-channel mapping (such as the byte-to-channel mapping described above). Figure 1 Any of the structures and / or functions, etc. described in the embodiments shown above regarding a group of one or more channels that may have a main band portion (e.g., one or more data channels) and / or a side band portion (e.g., one or more side band channels), any or all of which may be implemented as modules, one or more sub-layers (e.g., a logical physical layer and / or an electrical layer, etc.), an analog front end, one or more transmitters and / or receivers, etc., using any byte-to-channel mapping (such as the byte-to-channel mapping described above).

[0075] One or more components of the receiving D2D system 401R may implement a receiving version of the transmission function that may be implemented by the transmitting D2D system 401T. As an example, the physical layer 406R may receive, in the form of bits, information that "can be deserialized into bytes based on the byte-to-channel mapping shown above and transmitted to the link layer 404R" on one or more channels of the link 407 during eight consecutive UIs. Figure 3 Any of the structures and / or functions, etc. described in the embodiments shown above regarding a group of one or more channels that may have a main band portion (e.g., one or more data channels) and / or a side band portion (e.g., one or more side band channels), any or all of which may be implemented as modules, one or more sub-layers (e.g., a logical physical layer and / or an electrical layer, etc.), an analog front end, one or more transmitters and / or receivers, etc., using any byte-to-channel mapping (such as the byte-to-channel mapping described above).

[0076] As another example, the link layer 404R may include parity logic (or parity) 426, and the parity logic 426 may use the parity information generated by the parity generator 424 in the parity logic 419 to detect one or more errors in the data that "can be transmitted from the link layer 404T to the physical layer 406T for transmission on the link 407".

[0077] As a further example, the link layer 404R may include CRC check logic (or CRC check) 427. The CRC check logic 427 may use error detection information generated by the CRC logic 418 and inserted in one or more microtiles, byte groups, and / or sets of byte groups, etc., to check for errors in the information received at the second D2D system 401R. In some embodiments, the CRC check logic 427 may use the result of the error detection operation to initiate a retry operation. For example, the CRC check logic 427 may use the detection information (such as one or more of bytes CRC0 to CRC3) to detect errors in one or more of the header bytes and / or data bytes, etc., in the microtile format described herein. Based on the detected error, the CRC check logic 427 may send a retry request to the retry logic 417 of the link layer 404T to request a retransmission of the microtile, byte group, and / or set of byte groups, etc. (e.g., using a sequence number to identify the information to be retransmitted).

[0078] As an additional example, the link layer 404R may include arbitration and / or demultiplexing logic (or demultiplexer logic) (De-Mux) 428. The arbitration and / or demultiplexing logic 428 may be configured to demultiplex two or more protocols, two or more protocol stacks, and / or two or more protocols within a stack, etc., that may have been multiplexed onto the link 407 by the arbitration and / or multiplexing logic 420 at the transmitting D2D system 401T back to their individual forms from the link 407.

[0079] As yet another example, the transaction layer 402R at the receiving D2D system 401R may implement one or more protocols 416R-0, 416R-1, 416R-2, and / or 416R-3 corresponding to one or more protocols 416T-0, 416T-1, 416T-2, 416T-3 implemented at the transaction layer 402T at the transmitting D2D system 401T, respectively. Specifically, the first streaming protocol 416R-0 indicated as Streaming 0 may be implemented using an AXI port, for example, the second streaming protocol 416R-1 indicated as Streaming 1 may be implemented using a CHI port, and / or the third streaming protocol 416R-2 indicated as Streaming 2 may be implemented using a CXS port, for example. Additionally or alternatively, the transaction layer 402R may implement the protocol 416R-3, and the protocol 416R-3 may implement a transaction layer that can send and / or receive TLPs (such as PCIe and / or CXL, etc.) or be implemented using a transaction layer that can send and / or receive TLPs (such as PCIe and / or CXL, etc.).

[0080] Figure 5 An embodiment of a D2D system with a channel interleaving scheme according to the disclosed example embodiments is shown. Figure 5The embodiments shown may include one or more elements, and the one or more elements may be similar to the elements shown in other figures including Figure 1 wherein similar elements may be indicated by reference numerals that end with the same numbers and / or letters, etc. and / or include the same numbers and / or letters, etc.

[0081] Figure 5 The D2D system 501 shown in may include a link layer 504, and the link layer 504 may communicate with a transaction layer 502 using a link layer interface 503 and / or communicate with a physical layer 506 using a physical layer interface 505.

[0082] The link layer 504 may include channel interleaving logic 510, and the channel interleaving logic 510 may implement a channel interleaving scheme according to the disclosed example embodiments. For example, in an embodiment where a byte-to-channel mapping of "wherein the first byte of a transaction may be sent using a first channel and the second byte of the transaction may be sent using a second channel" may be implemented in the physical layer 506, the channel interleaving logic 510 may rearrange one or more portions of the first byte and / or one or more portions of the second byte such that a portion of the first byte and a portion of the second byte may be sent using the same channel. Thus, portions of bytes mapped to separate channels may be sent using the same channel. The channel on which a portion of the first byte and a portion of the second byte are sent may or may not be one of the first channel and the second channel. For example, a third channel may be used to send a portion of the first byte and a portion of the second byte.

[0083] Additionally or alternatively, the channel interleaving logic 510 may rearrange one or more portions of the first byte such that a first portion of the first byte may be sent using a first channel while a second portion of the first byte may be sent using a second channel. Thus, different channels may be used to send portions of a byte mapped to one channel.

[0084] In some embodiments, Figure 5 an instance of the D2D system 501 shown in may be implemented at a first die, while a second instance of the D2D system 501 (but with deinterleaving logic) may be implemented at a second die that may communicate with the first instance of the D2D system 501. The deinterleaving logic may rearrange one or more portions of the first byte and / or the second byte back to their original arrangement.

[0085] According to implementation details, a channel interleaving scheme according to the disclosed example embodiments can improve one or more of BER, effective BER, bandwidth, latency, and / or power consumption, etc. For example, in some embodiments, the channel interleaving logic 510 can implement bit interleaving (or sub-byte interleaving), which can transform the pattern of burst errors that may occur on one channel into a pattern of random errors spread across multiple channels (which can also represent an error pattern that may be similar to a random error pattern, e.g., a quasi-random error pattern). This can enable the detection and / or correction of errors using one or more error detection and / or correction techniques that may otherwise be ineffective or less effective in correcting burst errors. For example, in some embodiments, one or more convolutional codes, turbo codes, low density parity check (LDPC) codes, and / or linear block codes, etc., can be used to detect and / or correct one or more errors in one or more bytes spread across multiple channels.

[0086] In some embodiments, and according to implementation details, a byte can represent any data unit that the physical layer can map to a channel. Thus, a byte can represent an 8-bit byte (which can also be referred to as an octet), a 4-bit nibble, a 16-bit word, a 32-bit word, and / or a 64-bit word, etc., that the physical layer can map to a channel.

[0087] Figure 6 An embodiment showing an interleaving scheme according to the disclosed example embodiments. Figure 6 The embodiment shown in can be implemented using, for example, Figure 5 the channel interleaving logic 510 shown in and / or any other interleaving scheme disclosed herein, or can be used to implement, for example, Figure 5 the channel interleaving logic 510 shown in and / or any other interleaving scheme disclosed herein.

[0088] In Figure 6 the embodiment shown in, four byte mappers 611-0, 611-1, 611-2, and / or 611-3 can map bytes to channels 612-0, 612-1, 612-2, and / or 612-3, respectively. As shown in Figure 6 each byte of the byte mapper 611 can have its bits arranged in order from 0 to 7. For example, bits 0 to 7 of the byte mapper 611-0 can be respectively indicated as B0[0], B0[1], ……, B0[7]. Similarly, bits 0 to 7 of the byte mapper 611-1 can be respectively indicated as B1[0], B1[1], ……, B1[7].

[0089] The channel 612 can be implemented as a part of any D2D link disclosed herein, such as Figure 1 the link 107 shown in and / or Figure 4 the link 407 shown in.

[0090] In some embodiments, mapping the byte mapper 611-0 to channel 612-0 may represent that the physical layer may receive bytes from the byte mapper 611-0 via the physical layer interface and transmit the bits of the bytes from the byte mapper 611-0 on channel 612-0 (e.g., in the bit arrangement within the byte transfer as shown in Figure 2 ).

[0091] However, in the interleaving scheme shown in Figure 6 , the bytes from the byte mapper 611 may be input into the interleaving function 613, and the interleaving function 613 may generate remapped bytes 614-0, 614-1, 614-2, and / or 614-3 with a modified bit map as shown in Figure 6 . For example, bit 0 and bit 4 from the byte mapper 611-0, 611-1, 611-2, and / or 611-3 may be combined in the remapped byte 614-0. Similarly, bit 1 and bit 5 may be combined in the remapped byte 614-1.

[0092] Any type of interleaving function 613 may be used (e.g., random or pseudo-random sequence generator, linear feedback shift register (LFSR), and / or polynomial, etc.). In some example embodiments, the interleaving function 613 may be implemented as follows: (Equation 1) and (Equation 2) where represents an index (e.g., a memory index), represents a channel selection decision, and represents a bit position decision within the channel. The mapper index may be a channel-based index (e.g., the logical physical layer may have multiple mappers), and y represents an index. If the result of Equation 2 is negative, then may be used as the final result.

[0093] The remapped bytes 614 may be transmitted by the physical layer via the corresponding channel 612 to another die where the D2D system may implement a deinterleaving function, and the deinterleaving function may restore the interleaved bits to their original arrangement in the byte mapper 611.

[0094] Referring to remapped byte 614-0, if a burst error occurs on channel Lane 0 during the transmission of remapped byte 614-0 on channel 612-0, individual bit errors can be spread across bits from four different bytes (e.g., bits 0 and / or bit 4 of byte mappers 611-0, 611-1, 611-2, and / or 611-3). Thus, when the individual bits are restored to their original bytes, the bits of the burst error can be spread across four different bytes. Depending on the implementation details, this can enable an error correction scheme to correct individual bit errors that might otherwise be difficult to correct as a burst error on a single byte.

[0095] In some embodiments, the interleaving function 613 can be implemented with little or no contention. For example, in some contention-free implementation scenarios, there may be no duplication of transmitted data (e.g., there may be no duplication of channels until the interleaving has gone through all channels). In some embodiments, duplicated transmitted data and / or channels can lead to contention.

[0096] For illustrative purposes, Figure 6 the embodiments shown in have four byte mappers 611 and four channels 612, but any number of byte mappers and / or any number of channels can be used.

[0097] Figure 7 An embodiment of an interface architecture for a D2D system with interleaving and error correction according to an exemplary embodiment disclosed is shown. Figure 7 The embodiments shown in may include one or more elements similar to those shown in other figures including Figure 4 and Figure 5 wherein similar elements may be indicated by reference numerals ending with the same numbers and / or letters, etc. and / or including the same numbers and / or letters, etc.

[0098] In Figure 7 the embodiments shown, the first D2D system 701T on the first die 708 may include a link layer 704T having channel interleaving logic (or channel interleaving) 710, encoding logic (or encoding) 730, a retry buffer 732, and / or a retry multiplexer 733. The second D2D system on the second die 709 may include channel deinterleaving logic (or channel deinterleaving) 715, channel decoding logic (or decoding logic, or decoding) 731, and / or a BER monitor 734.

[0099] The encoding logic 730 may implement an error correction scheme to encode the protocol data 735 received from the transaction layer 702T to generate encoded information 738, which in some embodiments may include parity information. The encoding logic 730 is not limited to any particular encoding scheme. However, in some embodiments, it may be beneficial to use any type of encoding in which the coding rate can be modified. For example, some error correction codes may have a basic coding rate or mother coding rate that can be modified (e.g., using a puncturing method) to provide an effective coding rate and / or an actual coding rate, etc. Some examples may include convolutional codes, turbo codes, trellis codes, Hamming codes, Reed-Solomon (RS) codes, LDPC codes, and / or linear block codes (or linear block codes), etc.

[0100] The retry buffer 732 may store protocol data 735, error correction information (e.g., parity information) for the protocol data 735, encoded information 738 (which may include an encoded version of the protocol data 735 and / or the error correction information), etc. The retry multiplexer 733 may select the output of the encoding logic 730 and / or the output of the retry buffer 732 to provide input information 740 (e.g., one or more flits or portions thereof, bytes, byte groups, and / or byte streams, etc.) to the channel interleaving logic 710.

[0101] At the receiving D2D system 701R, the channel decoding logic 731 may use the error correction information in the encoded information 738A arriving at the channel decoding logic 731 to correct one or more errors that may have occurred in the data information when the data information was sent from the first die 708 to the second die 709 (e.g., in one or both of the physical layer 706 and / or the link 707, etc.). Examples of decoding techniques may include a Viterbi algorithm (which may decode information encoded, for example, with a convolutional code and / or a trellis code, etc.) and / or a Fano algorithm, etc. In some embodiments, if the channel decoding logic 731 cannot correctly decode the data information (e.g., the recovery protocol data 735) in the encoded information 738A, the channel decoding logic 731 may send a retry request 737 to the retry multiplexer 733 and / or the encoding logic 730.

[0102] In some embodiments, the retry buffer 732, the retry multiplexer 733, and / or the encoding logic 730 may implement an encoding and / or retry scheme 739 with a retry feature, in which less than all of the encoded information 738 may be resent in response to receiving a retry request 737 from the receiving D2D system 701R. For example, in some embodiments, the encoding logic 730 may implement an error correction code that "generates multiple parts of parity information for a specific amount of data information". The encoding and / or retry scheme 739 may send only the first part of the parity information in response to the retry request 737, rather than resending the entire encoded information 738. Depending on the implementation details, this may enable the channel decoding logic 731 at the receiving D2D system 701R to correctly decode the data information while reducing the amount of error correction information transmitted over the link 707.

[0103] The channel interleaving logic 710 may implement an interleaving scheme in which the link layer 704T may rearrange the information within a byte mapped to one or more channels of the link 707. In some embodiments, the channel interleaving logic 710 may implement an interleaving scheme (such as the interleaving scheme shown and described with respect to Figure 6 ). For example, the channel interleaving logic 710 may rearrange the information in the input information 740 to generate interleaved information 741 (e.g., a byte with remapped bits) that "enables the bits of a byte mapped to a specific channel of the link 707 to span more than one channel". Additionally or alternatively, the interleaved information 741 may enable the bits of multiple bytes mapped to multiple channels to be sent on one channel of the link 707.

[0104] At the receiving D2D system 701R, the channel deinterleaving logic 715 may apply a reverse interleaving function to the interleaved information 741A that arrives at the deinterleaving logic 715. In some embodiments, the interleaved information 741A may be the same as the interleaved information 741 applied to the channel interleaving logic 710, but may include one or more errors (e.g., introduced by one or both of the physical layer 706, the link 707, etc.). However, in the deinterleaved information 738A output from the channel deinterleaving logic 715, one or more burst errors (if any) that may have been concentrated in a byte mapped to a channel may have been transformed into one or more random errors that are spread across multiple bytes mapped to multiple channels. Depending on the implementation details, this may enable Figure 7 the architecture shown in to correct more errors and thus improve the overall BER of the D2D system 701.

[0105] In some embodiments, the link layer 704R at the receiving D2D system 701R may include a BER monitor 734 that may monitor errors in the recovered protocol data 735 and / or provide feedback information to one or more components (e.g., channel decoding logic 731, and / or an encoding and / or retry scheme 739, etc.). For example, if the BER monitor 734 detects an increase in the BER and / or a decrease in throughput caused by an increase in retry requests, the BER monitor 734 may send a request (e.g., via the channel decoding logic 731) to the encoding and / or retry scheme 739 to increase the data encoding rate used with the encoding scheme. This may be achieved, for example, by increasing the amount of error correction information (e.g., parity information) sent with the first transmission attempt.

[0106] Figure 8 FIG. shows an embodiment of a retry scheme for a D2D system with error correction according to the disclosed example embodiments. Figure 8 The embodiments shown in FIG. may be used to implement any one of the error correction and / or retry schemes for a D2D system disclosed herein, and / or may be implemented using any one of the error correction and / or retry schemes for a D2D system disclosed herein, which include, for example Figure 7 the encoding and / or retry scheme 739 and / or decoding logic 731 shown in FIG.

[0107] Figure 9 FIG. shows an example embodiment of one or more operations of a buffer for retry operations according to the disclosed example embodiments. Figure 9 The embodiments shown in FIG. may be used, for example, in conjunction with Figure 8 the embodiment of the retry scheme shown in FIG.

[0108] Referring to Figure 8 and Figure 9 FIG., an error correction coding algorithm may be used to generate one or more portions of parity information Parity 0, Parity 1, …, Parity P−1 for data information (or data) 835 having a size K (which may be referred to as the block size or block length). The data information 835 may be received, for example, from the transaction layer 702T. The portions of parity information Parity 0, Parity1, …, Parity P−1 (which may be denoted as 842-0, 842-1, …, 842-P−1, respectively) may be collectively referred to as parity information 842 having a size P (which may be referred to as the parity size) and may be generated, for example, by the encoding logic 730. For illustrative purposes, Figure 8 and Figure 9 the embodiments shown in FIG. may use a convolutional code, but other coding algorithms may be used.

[0109] The number and / or size of the portions of the parity check information may be determined based on, for example, the target BER of the D2D system, the expected amount of noise or other error sources in one or more physical layers and / or links, etc., the target bandwidth, the coding overhead, and / or the coding rate, etc. In some embodiments, the number and / or size of the portions of the parity check information may be based on one or more parameter tradeoffs. For example, in some embodiments, increasing the size of the portions of the parity check information may reduce the number of retry requests, but increase the error correction overhead.

[0110] Referring to Figure 8 , portions of the data information (or data) 835A and / or the parity check information Parity 0, Parity 1, ……, Parity m-1 (which may be respectively denoted as 842A-0, 842A-1, ……, 842A-P-1) may be collectively referred to as parity check information 842A having a size of m. The data information 835 and / or the parity check information 842 may be sent, for example, from the D2D system 701T to the D2D system 701R, where the data information 835 and / or the parity check information 842 may arrive as the data information 835A and / or the parity check information 842A, and either or both of the data information 835A and / or the parity check information 842A may include one or more errors.

[0111] In some embodiments, the parity check information 842A may be gradually accumulated (e.g., in a buffer at the decoding logic 731 in the D2D system 701R) (e.g., by being sent incrementally based on one or more retry requests).

[0112] Referring to Figure 9 , at operation (0), the buffer 944 at the decoding logic 731 may initially be empty. The encoding logic 730 may generate parity check information 842 having a size of P for the data information 835 (including parity check information Parity 0, Parity 1, ……, Parity P-1), and place the data information 835 and / or the parity check information 842 in the retry buffer 843. At operation (1), the encoding logic 730 may send the data information 835 and the first portion 842-0 of the parity check information (parity check information Parity 0) as a first transmission attempt to the decoding logic 731, where the data information 835 and the first portion 842-0 of the parity check information may arrive and be placed in the buffer 944 as the data information 835A and the parity check information 842A-0 (either or both of which may include one or more errors).

[0113] If the decoding logic 731 successfully decodes the data information 835A using the parity check information 842A-0, the retry operation may end. However, if the decoding logic 731 cannot decode the data information 835A, in operation (2), the decoding logic 731 may send a first retry request to the encoding logic 730. In operation (3), the encoding logic 730 may respond to the first retry request by sending a second part 842-1 (Parity 1) of the parity check information to the decoding logic 731, where the second part 842-1 may arrive as the parity check information 842A-1 (possibly having one or more errors) and be placed in the buffer 944.

[0114] If the additional part of the parity check information 842-1 enables the decoding logic 731 to decode the data information 835A, the retry operation may end. However, if the decoding logic 731 cannot decode the data information 835A using the first and second parts of the parity check information 842A-0 and 842A-1, in operation (4), the decoding logic 731 may send a second retry request to the encoding logic 730. In operation (5), the encoding logic 730 may respond to the second retry request by sending a third part 842-2 (Parity 2) of the parity check information to the decoding logic 731, where the third part 842-2 may arrive as the parity check information 842A-2 (possibly having one or more errors) and be placed in the buffer 944.

[0115] In some embodiments, Figure 9 the process shown in may continue (e.g., until the decoding logic 731 can decode the data information 835A and / or until all the information 842 of size P is sent to the decoding logic 731). In some embodiments, if the decoding logic 731 still cannot decode the data information 835A after all the parity check information 842 is sent, the retry process may start again at operation (0).

[0116] Referring to Figure 8 , the retry buffer 843 may be used to store some or all of the data information 835 and / or the parity check information 842 for one or more retry operations. In some embodiments, Figure 8 the retry scheme shown in may include a retry controller 845 that may control access to the retry buffer 843. For example, the retry controller 845 may provide a read address and / or an address pointer 846, etc. to access the retry buffer 843. In some embodiments, the retry controller 845 may be implemented as a loop controller or an iterative controller because it may loop or iterate through buffer addresses and / or retry operations, etc.

[0117] In some embodiments, the coding rate (e.g., the maximum coding rate and / or the available coding rate, etc.) can be determined by the size K of the data information 835 (which can be referred to as the block size or block length) and / or the size P of the parity information 842. For example, in some embodiments, the coding rate (e.g., the available coding rate) can be expressed as K / (K + P).

[0118] In some embodiments, the effective coding rate (e.g., the actual coding rate) can be determined by the size K of the data information 835 sent to the receiving D2D system and / or the size m of the parity information Parity 0, Parity 1, ……, Parity m-1 (which can be respectively indicated as 842A-0, 842A-1, ……, 842A-m-1) (which can be referred to as the received parity size). For example, in some embodiments, the effective coding rate (e.g., the actual coding rate) can be expressed as K / (K + m) (e.g., in the case where m << P).

[0119] In some embodiments, the amount of the sent parity information m can be less than the amount of the generated parity information P. This may be especially the case (e.g., using a relatively powerful error coding (such as a convolutional code) that "can enable the decoder to successfully correct one or more errors in the data information using a relatively small amount of parity information"), and thus, only a relatively small portion of the parity information 842 and / or a relatively small number of retries can be used. Depending on the implementation details, this can improve the performance of the D2D system, for example, by providing error correction with a relatively low coding overhead.

[0120] In some embodiments, it can be beneficial to use an error coding with a variable coding rate (e.g., a convolutional code) (e.g., because a variable number of portions of the parity information 842A-0, 842A-1, ……, 842A-M-1 can be used to decode the data information 835A).

[0121] In some embodiments, the parity information 842 may not be calculated at the beginning of the sending and / or retry operation, but one or more portions of the parity information 842-0, 842-1, ……, 842-p-1 can be calculated (e.g., as needed) while the retry operation is in progress.

[0122] In some embodiments, the encoding logic 730 may send more or less than one additional portion of the parity information 842-0, 842-1, …, 842-p-1 based on a received retry request. For example, in some embodiments, the encoding logic 730 may adaptively send more than one additional portion of the parity information 842-0, 842-1, …, 842-p-1 in response to a retry request (e.g., based on information included in the retry request and / or information provided by the BER monitor 734, etc.).

[0123] In some embodiments, the first transmission of the data information 835 may not include any parity information (e.g., the first portion of the parity information 842-0). Instead, if requested by a first retry request, the first portion of the parity information 842-0 may be sent.

[0124] In some embodiments, the retry controller 845 may operate based on the coding rate signal 847. For example, in some embodiments, the coding rate signal 847 may be used to set the actual coding rate (e.g., K / (K+m)). In some embodiments, the coding rate signal 847 may be determined at least in part based on the BER determined by the BER monitor 734 (e.g., the actual BER and / or the target BER, etc.).

[0125] Figure 10 Another embodiment of an interface architecture for a D2D system with interleaving and error correction according to an example embodiment disclosed is shown. Figure 10 The embodiment shown in may include one or more elements that may be similar to Figure 7 the elements shown in, where similar elements may be indicated by reference numerals that end with the same numbers and / or letters, etc. and / or contain the same numbers and / or letters, etc.

[0126] In Figure 10 the embodiment shown in, the link layer 1004T may include CRC0 insertion logic (or CRC0 insertion) 1048 and / or CRC1 insertion logic (or CRC1 insertion) 1049. Additionally or alternatively, the link layer 1004R may include CRC0 check logic (or CRC0 check) 1050 and / or CRC1 check logic (or CRC1 check) 1051.

[0127] In some embodiments, the CRC0 insertion logic 1048 and / or the CRC0 check logic 1050 may insert and / or check CRC information (such as Figure 11 the CRC0 in or for the data information 1135 shown in Figure 11 An example embodiment of CRC information in data information and parity information according to an example embodiment disclosed is shown.

[0128] In some embodiments, the CRC1 insertion logic 1049 and / or the CRC1 verification logic 1051 may insert and / or verify CRC information in the parity check information (such as the CRC1 in the parity check information 1142 shown in Figure 11 or for the parity check information 1142).

[0129] In Figure 10 the embodiment shown in, the link layer 1004T may include a multiplexer logic 1020, and the multiplexer logic 1020 may be configured to multiplex two or more protocols, two or more protocol stacks, and / or two or more protocols within the stack, etc. in a manner similar to the multiplexer logic 420 shown in Figure 4 . Additionally or alternatively, the link layer 1004R may include a demultiplexer logic 1028, and the demultiplexer logic 1028 may be configured to demultiplex two or more protocols, two or more protocol stacks, and / or two or more protocols within the stack, etc. in a manner similar to the demultiplexer logic 428 shown in Figure 4 .

[0130] Figure 12 An embodiment showing a method for using a D2D system to transmit information according to an exemplary embodiment disclosed. Figure 12 The embodiment shown in can be implemented using any D2D system described herein, or used to implement any D2D system described herein. For illustrative purposes, it can be described in the context of the architecture shown in Figure 10 the method shown in Figure 12 .

[0131] In operation 1252-1, the method may start, where the method may receive one or more protocol data inputs. For example, one or more in protocol 1016T may provide one or more protocol data inputs to the link layer 1004T using the link layer interface 1003T.

[0132] In operation 1252-2, the one or more protocol data inputs may be multiplexed to select a single source of the protocol data for transmission. For example, the multiplexer logic 1020 may select an input from one of the protocols 1016T for transmission using the D2D system 1001T.

[0133] In operation 1252-3, the method may determine whether a first CRC feature (e.g., CRC0) is enabled. If the first CRC feature is not enabled, the method may proceed to operation 1252-5. However, if the first CRC feature is enabled, in operation 1252-4, the method may insert a first CRC code into the protocol data. For example, as Figure 11As shown, CRC0 logic 1048 can insert CRC0 information into data message 1135. In some embodiments, the first CRC information can be generated, for example, on a per-protocol basis. The method can proceed to operation 1252-5.

[0134] At operation 1252-5, the method can encode the data message using one or more error coding schemes. For example, encoding logic 1030 can generate encoded message 138, as Figure 8 shown, the encoded message 138 can include data message 835 and / or parity information 842.

[0135] At operation 1252-6, the method can determine whether the retry operation is enabled. If the retry operation is not enabled, the method can proceed to operation 1252-8. However, if the retry operation is enabled, at operation 1252-7, the method can save the encoded message in a retry buffer. For example, error correction scheme 1039 can save the encoded message 1038 (as Figure 8 shown, the encoded message 1038 can include data message 835 and / or parity information 842) in retry buffer 1032. The method can proceed to operation 1252-8.

[0136] At operation 1252-8, the method can determine whether a second CRC feature (e.g., CRC1) is enabled. If the second CRC feature is not enabled, the method can proceed to operation 1252-10. However, if the second CRC feature is enabled, at operation 1252-9, the method can insert a second CRC code into the parity information. For example, as Figure 11 shown, CRC1 logic 1049 can insert CRC1 information into parity information 1142. In some embodiments, the second CRC information can be generated, for example, by the encoding logic. The method can proceed to operation 1252-10.

[0137] At operation 1252-10, the method can perform an interleaving operation on the data to be transmitted. For example, channel interleaving logic 1010 can use techniques such as those Figure 6 shown to interleave the information mapped to one or more channels of link 1007.

[0138] At operation 1252-11, the method can use the physical layer of the D2D system to transmit the interleaved information. For example, physical layer 1006T can use link 1007 to transmit the interleaved information 104l. The method can end based on the transmission of the interleaved information.

[0139] Figure 13 An embodiment of a method for receiving information using a D2D system according to an exemplary embodiment disclosed is shown.Figure 13 The embodiments shown herein can be implemented with any D2D system described herein, or used to implement any D2D system described herein. For illustrative purposes, it can be described in the context of the architecture shown in Figure 10 the method shown in Figure 13 shown herein.

[0140] In operation 1354-1, the method can start, where the method can use the physical layer of the D2D system to receive the interleaved information. For example, the physical layer 1006R can receive the interleaved information 1041A using the link 1007.

[0141] In operation 1354-2, the method can perform a deinterleaving operation on the received information. For example, the channel deinterleaving logic 1015 can deinterleave the information 1041A mapped to one or more channels of the link 1007 using a process opposite to the process shown in, for example, Figure 6 shown herein.

[0142] In operation 1354-3, the method can determine whether a second CRC feature (e.g., CRC1) is enabled. If the second CRC feature is not enabled, the method can proceed to operation 13545. However, if the second CRC feature is enabled, then in operation 1354-4, the method can use the second CRC code to verify the information. For example, the CRC1 verification logic 1051 can use the CRC1 information to verify the parity information 1142A, as Figure 11 shown. If the CRC verification determines that there are one or more (e.g., an unacceptable level of) errors in the parity information 1142A, the method can send a retry request. If the CRC verification is successful, the method can proceed to operation 1354-5.

[0143] In operation 1354-5, the method can use one or more error decoding algorithms to decode the encoded information. For example, the decoding logic 1031 can use the parity information (such as the parity information 842A shown in Figure 8 shown herein) to decode the encoded information 1038A to decode the data information 835A shown in Figure 8 shown herein.

[0144] At operation 1354-6, the method can determine whether a first CRC feature (e.g., CRC0) is enabled. If the first CRC feature is not enabled, the method can proceed to operation 1354-8. However, if the first CRC feature is enabled, then in operation 1354-7, the method can use the first CRC code to verify the information. For example, as Figure 11As shown, the CRC0 check logic 1050 can use the CRC0 information to check the data information 1135A. If the CRC check determines that there is one or more (e.g., an unacceptable level of) errors in the data information 1135A, the method can send a retry request. If the CRC check is successful, the method can proceed to operation 1354-8.

[0145] In operation 1354-8, the method can demultiplex the decoded data information into one or more protocols. For example, the demultiplexer logic 1028 can use the link layer interface 1003R to select one of the multiple outputs.

[0146] In operation 1354-9, the method can provide the decoded data information to the selected protocol at the transaction layer. For example, the demultiplexer logic 1028 can provide the decoded data information to one of the protocols 1016R. The method can end based on providing the decoded data information as an output to the selected protocol.

[0147] Any functions and / or components disclosed herein (including any interfaces, layers, interleaving logic, control circuits, error detection logic, error correction logic, encoding and / or decoding logic, etc.) can be implemented using circuits such as combinational logic, sequential logic, gate arrays, timers, counters, registers, buffers, state machines, accelerators, embedded processors, processing units (e.g., central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), and / or digital signal processor (DSP), etc.) or combinations thereof, some of which can execute instructions stored in any type of memory and / or implement any type of execution environment, etc.

[0148] Some of the embodiments disclosed above have been described in the context of details of various implementations, but the principles of the present disclosure are not limited to these or any other specific details. For example, some functions have been described as being implemented by specific components, but in other embodiments, the functions may be distributed among different systems and components in different locations and have various interfaces. Specific embodiments have been described as having specific processing, operations, etc., but these terms also cover embodiments in which the specific processing, operations, etc. may be implemented by multiple processing, operations, etc., or embodiments in which multiple processing, operations, etc. may be integrated into a single processing, step, etc. A reference to a component or element may refer only to a part of the component or element. For example, a reference to a block may refer to the entire block or one or more sub-blocks. Unless clear from the context, terms such as "first" and "second" used in the present disclosure and the claims may be used only for the purpose of distinguishing the elements they modify and may not indicate any spatial or temporal order. In some embodiments, a reference to an element may refer to at least a part of the element, e.g., "based on" may mean "at least partially based on", etc. A reference to a first element does not imply the existence of a second element. The principles disclosed herein have independent utility and may be embodied separately, and not every embodiment may utilize every principle. However, these principles may also be embodied in various combinations, some of which may amplify the benefits of the individual principles in a synergistic manner. The various details and embodiments described above may be combined to produce additional embodiments in accordance with the inventive principles of the present patent disclosure.

[0149] In some embodiments, a part of an element may represent less than the entire element or all of the elements. A first part of an element and a second part of the element may represent the same part of the element. The first part of the element and the second part of the element may overlap (e.g., a part of the first part may be the same as a part of the second part).

[0150] Since the inventive principles of the present patent disclosure may be modified in arrangement and details without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. An apparatus for a die-to-die system, comprising: A die comprising at least one circuit, wherein the at least one circuit is configured to: receiving a first byte, the first byte being mapped to a first channel of two or more channels of a die-to-die system; receiving a second byte, the second byte being mapped to a second channel of the two or more channels of the die-to-die system; transmitting a portion of a first byte using one of the two or more channels of the die-to-die system; and A portion of a second byte is transmitted using the one channel of the two or more channels of the die-to-die system.

2. The device according to claim 1, wherein: The one channel of the two or more channels of the die-to-die system is a first channel of the two or more channels of the die-to-die system.

3. The device of claim 1, wherein: The one channel of the two or more channels of the die-to-die system is a third channel of the two or more channels of the die-to-die system.

4. The device of claim 1, wherein: The portion of the first byte is a first portion of the first byte, the portion of the second byte is a first portion of the second byte, and the at least one circuit is configured to: generating a fourth byte, the fourth byte including the second portion of the first byte and the second portion of the second byte; and A fourth byte is sent using another channel of the two or more channels of the die-to-die system that is different from the one channel.

5. The device of claim 4, wherein: The another channel of the two or more channels of the die-to-die system is a second channel of the two or more channels of the die-to-die system.

6. The device of claim 4, wherein: The other channel of the two or more channels of the die-to-die system is Die-to-die systems A third channel of two or more channels.

7. The device according to any one of claims 1 to 6, wherein: The at least one circuit is configured to: generating error correction information for the portion of the first byte and the portion of the second byte; and At least a portion of the error correction information is sent using a channel of the die-to-die system.

8. The device of claim 7, wherein: The at least one circuit is configured to generate error correction information using variable rate coding.

9. An apparatus for a die-to-die system, comprising: A die comprising at least one circuit, wherein the at least one circuit is configured to: receiving data to be transmitted using a die-to-die system; generating error correction information for the data; encoding the data and the error correction information to generate encoded information; and At least a portion of the encoded information is transmitted using a die-to-die system.

10. The device of claim 9, wherein: The at least one circuit is configured to generate error correction information using variable rate coding.

11. The device according to claim 9 or 10, wherein: The at least one circuit is configured to generate error correction information using an error correction code.

12. An apparatus for a die-to-die system, comprising: A die comprising at least one circuit, wherein the at least one circuit is configured to: receiving data to be transmitted using a die-to-die system; generating error correction information for the data; performing a first sending operation, the first sending operation comprising sending the data using a die-to-die system; receiving a request based on a first send operation; and A second sending operation is performed based on the request, the second sending operation including sending a portion of the error correction information.

13. The apparatus of claim 12, wherein: The portion of the error correction information is a first portion of the error correction information, the request is a first request, and the at least one circuit is further configured to: receiving a second request based on the second send operation; and A third sending operation is performed based on the second request, the third sending operation including sending a second portion of the error correction information.

14. The apparatus of claim 12, wherein: The portion of error correction information is a first portion of error correction information, and wherein: The first sending operation also includes sending a second portion of the error correction information.

15. The apparatus of claim 14, wherein: The at least one circuit is configured to determine a first portion of the error correction information based on a coding rate.

16. The apparatus of claim 12, wherein: The at least one circuit is configured to generate error correction information using variable rate coding.

17. The apparatus of claim 12, wherein: The at least one circuit is configured to generate error correction information using a convolutional code.

18. The apparatus of claim 12, wherein: The at least one circuit is configured to generate error correction information using a turbo code.

19. The apparatus of claim 12, wherein: The at least one circuit is configured to determine the portion of the error correction information based on a coding rate.

20. The apparatus of any one of claims 12 to 19, wherein: The at least one circuit includes a buffer configured to store at least a portion of the error correction information.

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