Computing method and device for realizing Fourier transform of parallel circuit

Abstract

The invention discloses a calculation method and device for realizing Fourier transform by a parallel circuit. The method comprises the following steps: acquiring an input signal sequence of an input signal; based on a preset degree of parallelism, performing serial-parallel conversion on the input signal sequence by using a parallel circuit to obtain a signal transformation matrix; obtaining an original Fourier transform matrix according to the input signal sequence, and transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the degree of parallelism; and performing vector inner product operation on the row vectors of the parallel Fourier transformation matrix and the signal transformation matrix in sequence to obtain a Fourier transformation result of the input signal sequence. During calculation, it is not required that the length of an input signal sequence must be N power of 2 or 4, and it is not required that the input signal sequence must be uniformly sampled, but a Fourier transform result can be obtained by sequentially carrying out vector inner product operation on row vectors of the parallel Fourier transform matrix and the signal transform matrix, so that the calculation efficiency is improved, and the calculation cost is reduced. And the waste of computing resources is avoided.

Description

Technical Field

[0001] The present invention belongs to the field of digital signal processing, and particularly relates to a method and device for implementing Fourier transform calculation by a parallel circuit. Background Art

[0002] The Fourier transform is a core tool for signal analysis and is widely used in fields such as digital signal processing, wireless communication, radar signal processing, and image processing. Through the Fourier transform, a signal can be converted from the time domain to the frequency domain to facilitate the analysis of its spectral characteristics. Currently, with the high parallel processing capabilities and excellent energy efficiency ratios of FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits), they are widely used in mobile and low-power platforms, especially performing excellently in real-time signal processing and large-scale data operations. In practical engineering, the Fast Fourier Transform (FFT) is a commonly used Fourier transform algorithm that efficiently processes large-point signal sequences through butterfly operations. Traditional FFT algorithms are usually based on a radix of 2 or 4, requiring the input sequence to be uniformly sampled in both the time domain and the frequency domain, and the length to be a power of 2 or a power of 4. However, in many practical application scenarios, the signal sequence length is short, and the sampling points may not be uniformly distributed in the time domain or the frequency domain, which poses challenges to the application of FFT.

[0003] To address the above problems, the existing solutions are as follows: For a signal sequence with a length that does not conform to a power of 2, such as a 96-point sequence, traditional FFT algorithms generally require zero-padding the input signal to extend the signal length to a power of 2, for example, extending it to 128 points. Another approach is to use a mixed-radix FFT algorithm, such as a mixed-radix scheme of radix 2 and radix 3. This method uses different radix combinations to process signal sequences with lengths that are not powers of 2, avoiding the need for zero-padding. However, since the mixed-radix FFT requires multiple FFT processing units with different radixes, it increases the complexity of hardware implementation. When implemented on an FPGA or ASIC platform, more logic units, storage resources, and data recombination resources are required, resulting in higher resource occupancy. In addition, for a non-uniform sampling sequence, the non-uniform Fourier transform (NUFFT) actually uses interpolation operations to map non-uniform sampling data into a uniform data sequence, then samples the standard FFT algorithm, and finally performs inverse interpolation to recover the frequency domain information corresponding to the non-uniform sampling points.

[0004] However, existing calculation methods all have different defects: for signal sequences with a length that is not a power of 2, although padding with zeros can meet the requirements of FFT operations, it increases the redundant computational amount, resulting in waste of resources and reduced computational efficiency, and is not suitable for applications with high real-time requirements. Although the mixed-radix FFT can avoid padding with zeros, it is necessary to select an appropriate radix combination according to the signal length and merge the results through specific mapping and recombination steps, consuming a large amount of logic units, storage, and data recombination resources when implemented on an FPGA or ASIC. For non-uniform sampling sequences, the interpolation and anti-interpolation steps of the NUFFT require frequent data transfer and consume a large number of multipliers and adders, making it difficult to meet the real-time processing requirements.

[0005] Therefore, there is an urgent need for a calculation method of Fourier transform with low computational complexity and high computational efficiency. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a calculation method and device for implementing Fourier transform by a parallel circuit.

[0007] The technical problems to be solved by the present invention are realized through the following technical solutions:

[0008] In a first aspect, the present invention provides a calculation method for implementing Fourier transform by a parallel circuit, and the calculation method includes:

[0009] Obtain an input signal sequence of an input signal;

[0010] Based on a preset parallelism, use a parallel circuit to perform serial-to-parallel conversion on the input signal sequence to obtain a signal transformation matrix;

[0011] Obtain an original Fourier transform matrix according to the input signal sequence, and transform the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism;

[0012] Perform vector inner product operations on the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain the Fourier transform result of the input signal sequence.

[0013] Optionally, the preset parallelism is M; the parallel circuit includes M calculation units; each calculation unit includes sub-calculation units; the output end of each sub-calculation unit is connected to a total adder; each sub-calculation unit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a first accumulator, a second accumulator, and a third accumulator;

[0014] The output ends of the first multiplier and the second multiplier are connected to the first accumulator; the output ends of the third multiplier and the fourth multiplier are connected to the second accumulator; the output ends of the first accumulator and the second accumulator are connected to the third accumulator.

[0015] Optionally, obtaining the Fourier transform result by performing vector inner product operations on the row vectors of the parallel Fourier transform matrix and the signal transform matrix in sequence, includes:

[0016]

[0017] wherein, A(n) represents the nth frequency component of the Fourier transform result; represents the parallel Fourier transform matrix; represents the signal transform matrix; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism; represents the weighted Fourier transform factor of the input data of the ith sub-computation unit of a computation unit when calculating the nth frequency component of the Fourier transform result; represents the input data of the ith sub-computation unit.

[0018] Optionally, the input signal sequence includes N time-domain sampling points; the preset parallelism is M;

[0019] Based on the preset parallelism, performing serial-to-parallel conversion on the input signal sequence by using a parallel circuit to obtain a signal transform matrix, includes:

[0020] Using a parallel circuit to extract the input signal sequence with every M time-domain sampling points as a subsequence, to obtain parallel sequences;

[0021] Combining parallel sequences into a signal transform matrix with M rows and N / M columns.

[0022] Optionally, the signal transform matrix is:

[0023]

[0024] wherein, the kth element in the signal transform matrix is represented by x(k); k = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism.

[0025] Optionally, the parallel Fourier transform matrix is:

[0026]

[0027] Among them, the transformation factor of the p-th time-domain sampling point to the q-th frequency component in the parallel Fourier transform matrix is represented by W p,q ; p = 1, 2,..., N - 1; q = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the degree of parallelism.

[0028] Optionally, the calculation method further includes: after transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the degree of parallelism, storing the parallel Fourier transform matrix in the form of a look-up table in a ROM or a static register file.

[0029] In a second aspect, the present invention provides a computing device for implementing Fourier transform by a parallel circuit, and the computing device includes:

[0030] An acquisition module, configured to acquire an input signal sequence of an input signal;

[0031] A serial-to-parallel conversion module, configured to perform serial-to-parallel conversion on the input signal sequence by using a parallel circuit based on a preset degree of parallelism to obtain a signal transformation matrix;

[0032] A matrix transformation module, configured to obtain an original Fourier transform matrix according to the input signal sequence, and transform the original Fourier transform matrix into a parallel Fourier transform matrix based on the degree of parallelism;

[0033] An operation module, configured to perform vector inner product operations on the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain a Fourier transform result of the input signal sequence.

[0034] Optionally, the preset degree of parallelism is M; the parallel circuit includes M computing units; each computing unit includes sub-computing units; the output end of each sub-computing unit is connected to a total adder; each sub-computing unit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a first accumulator, a second accumulator, and a third accumulator;

[0035] The output ends of the first multiplier and the second multiplier are connected to the first accumulator; the output ends of the third multiplier and the fourth multiplier are connected to the second accumulator; the output ends of the first accumulator and the second accumulator are connected to the third accumulator.

[0036] Optionally, the operation module is specifically configured to perform the following calculations:

[0037]

[0038] Among them, A(n) represents the n-th frequency component of the Fourier transform result; represents the parallel Fourier transform matrix; represents the signal transformation matrix; N represents the total number of time-domain sampling points of the input signal sequence; M represents the degree of parallelism; When calculating the n-th frequency component of the Fourier transform result, it represents the weighted Fourier transform factor of the input data of the i-th sub-computation unit of a computing unit; represents the input data of the i-th sub-computation unit.

[0039] Optionally, the input signal sequence includes N time-domain sampling points; the preset degree of parallelism is M; the serial-to-parallel conversion module is specifically used for:

[0040] Using a parallel circuit, extract the input signal sequence with every M time-domain sampling points as a subsequence to obtain parallel sequences; and combine parallel sequences into a signal transformation matrix with M rows and N columns.

[0041] Optionally, the signal transformation matrix is:

[0042]

[0043] Among them, the k-th element in the signal transformation matrix is represented by x(k); k = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the degree of parallelism.

[0044] Optionally, the parallel Fourier transform matrix is:

[0045]

[0046] Among them, the transformation factor of the p-th time-domain sampling point to the q-th frequency component in the parallel Fourier transform matrix is represented by W p,q ; p = 1, 2,..., N - 1; q = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the degree of parallelism.

[0047] Optionally, the computing device further includes a storage module, which is specifically used for storing the parallel Fourier transform matrix in the form of a look-up table in a ROM or a static register file after transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the degree of parallelism.

[0048] A calculation method for implementing Fourier transform by a parallel circuit provided by the present invention first performs serial-to-parallel conversion on an input signal sequence using the parallel circuit based on a preset parallelism degree to obtain a signal transformation matrix. Then, an original Fourier transform matrix is obtained according to the input signal sequence, and the original Fourier transform matrix is transformed into a parallel Fourier transform matrix based on the parallelism degree. Furthermore, the Fourier transform result of the input signal sequence can be obtained by performing vector inner product operations between the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence. When calculating, it is not required that the length of the input signal sequence must be a power of 2 or 4, nor is it required that the input signal sequence must be uniformly sampled. Instead, the Fourier transform result can be obtained by performing vector inner product operations between the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence, thereby improving the calculation efficiency, without introducing additional calculation steps, and avoiding waste of computing resources.

[0049] The following will further describe the present invention in detail with reference to the accompanying drawings. Description of the Drawings

[0050] Figure 1 is a flowchart of a calculation method for implementing Fourier transform by a parallel circuit provided by an embodiment of the present invention;

[0051] Figure 2 is a schematic diagram of a parallel circuit provided by an embodiment of the present invention;

[0052] Figure 3 is a schematic diagram of the result comparison of calculating the Fourier transform of a 128-point signal sequence by using the calculation method for implementing Fourier transform by a parallel circuit and the uniform FFT calculation method;

[0053] Figure 4 is a schematic diagram of the comparison of the amplitude and phase absolute errors of calculating the Fourier transform of a 128-point signal sequence by using the calculation method for implementing Fourier transform by a parallel circuit and the uniform FFT calculation method;

[0054] Figure 5 is a time-domain diagram of a 502-point non-uniform input sequence;

[0055] Figure 6 is a schematic diagram of the frequency-domain comparison of the calculation results for a non-uniform input sequence by using the calculation method for implementing Fourier transform by a parallel circuit and the conventional NUFFT calculation method;

[0056] Figure 7 is a schematic diagram of the comparison of the amplitude and phase absolute errors of the calculation results for a non-uniform input sequence by using the calculation method for implementing Fourier transform by a parallel circuit and the conventional NUFFT calculation method;

[0057] Figure 8It is a schematic diagram of the frequency domain comparison of the calculation results of the Fourier transform implemented by the parallel circuit and the conventional zero-padding calculation method for input sequences that are not integer powers of 2.

[0058] Figure 9 It is a schematic structural diagram of a calculation device for implementing the Fourier transform by a parallel circuit provided in an embodiment of the present invention. Detailed implementation manners

[0059] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0060] To solve the problems that the existing calculation methods for implementing the Fourier transform have high calculation complexity and low calculation efficiency, an embodiment of the present invention provides a calculation method for implementing the Fourier transform by a parallel circuit. Refer to Figure 1 , Figure 1 It is a schematic flowchart of a calculation method for implementing the Fourier transform by a parallel circuit provided in an embodiment of the present invention, which specifically includes the following steps:

[0061] Step S101: Obtain the input signal sequence of the input signal.

[0062] In the embodiment of the present invention, the sensor collects the input signal, and then samples the input signal into a discrete input signal sequence X. The length of X is N, that is, X includes N time-domain sampling points, X = [x(0) x(1) … x(N - 1)] T . Among them, the k-th time-domain sampling value in X is represented by x(k), k = 1, 2,..., N - 1; T represents the transpose operation of the sequence.

[0063] Among them, the input signal sequence can be a uniformly sampled sequence or a non-uniformly sampled sequence.

[0064] Step S102: Based on the preset parallelism, use the parallel circuit to perform serial-to-parallel conversion on the input signal sequence to obtain a signal transformation matrix.

[0065] In the embodiment of the present invention, the preset parallelism is the parallelism M of the parallel circuit applying the calculation method provided in the embodiment of the present invention.

[0066] In the embodiment of the present invention, for the input signal sequence X including N time-domain sampling points, based on the preset parallelism M, using the parallel circuit to perform serial-to-parallel conversion on the input signal sequence to obtain a signal transformation matrix, including:

[0067] Using the parallel circuit, extract the input signal sequence with every M time-domain sampling points as a subsequence to obtain parallel sequences;

[0068] Put M rows are obtained by merging several parallel sequences signal transformation matrix of columns

[0069] In an embodiment of the present invention, by extracting the input signal sequence X with every M time-domain sampling points as a subsequence, several subsequences can be obtained based on the input signal sequence X, which are called parallel sequences. Based on the parallel sequences and the parallelism, they are merged to obtain a signal transformation matrix in the matrix form of M rows and columns

[0070] In an embodiment of the present invention, the signal transformation matrix is as follows

[0071]

[0072] wherein, the k-th element in the signal transformation matrix is represented by x(k); k = 1, 2,..., N - 1; M represents the parallelism

[0073] For example, taking the input signal sequence as a 96-point serial input signal sequence X 96 as an example

[0074] X 96 = [x(0) x(1)... x(95)] T ;

[0075] wherein, the k-th time-domain sampling point of X 96 is represented by x(k); k = 0, 1,..., 95; the total number of time-domain sampling points corresponding to X 96 is 96; the superscript T represents the transpose operation of the sequence

[0076] Assume that the parallelism of the parallel circuit is 24. Based on the parallelism, the signal transformation matrix obtained by performing serial-parallel conversion on X 96 includes

[0077]

[0078] wherein, is the signal transformation matrix obtained by performing serial-parallel conversion on X 96

[0079] In an embodiment of the present invention, by using the parallelism, the input signal is converted from the sequence form to the matrix form

[0080] Step S103, obtaining an original Fourier transform matrix according to the input signal sequence, and transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism

[0081] ​In an embodiment of the present invention, the number of frequency points of the input signal sequence can be obtained according to the input signal sequence. Therefore, according to the input signal sequence, the time-domain signal can be converted into a frequency-domain signal to construct an original Fourier transform matrix.

[0082] Specifically, the original Fourier transform matrix F is:

[0083]

[0084] Among them, the transformation factor of the p-th time-domain sampling point to the q-th frequency component in the original Fourier transform matrix F is represented by W' p,q where p = 1, 2,..., N - 1; q = 1, 2,..., N - 1.

[0085] In an embodiment of the present invention, based on the parallelism, the original Fourier transform matrix can be transformed into a parallel Fourier transform matrix, including converting the original Fourier transform matrix into a parallel Fourier transform matrix with M rows columns based on the parallelism.

[0086] Specifically, the parallel Fourier transform matrix is:

[0087]

[0088] Among them, the transformation factor of the p-th time-domain sampling point to the q-th frequency component in the parallel Fourier transform matrix is represented by W p,q where p = 1, 2,..., N - 1; q = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism.

[0089] Step S104, perform a vector inner product operation on the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain the Fourier transform result of the input signal sequence.

[0090] In an embodiment of the present invention, since the circuit parallelism is M, the input sequence is actually split into parallel sequences. When performing the inner product operation, all these parallel sequences need to be considered. Therefore, the row vectors of the parallel Fourier transform matrix need to be sequentially subjected to a vector inner product operation with the signal transformation matrix.

[0091] The first row vector of the parallel Fourier transform matrix is composed of all the elements corresponding to the first row in the parallel Fourier transform matrix. For W 0,q , when q = 1, 2,..., N - 1, the process of performing the inner product operation includes:

[0092] temp1 = W 0,0 ×x(0)+W 0,1×x(1)+…+W 0,M-1 ×x(M - 1);

[0093] temp2 = W 0,M ×x(M)+W 0,M+1 ×x(M + 1)+…+W 0,2M-1 ×x(2M - 1);

[0094] Until the calculation reaches:

[0095]

[0096] Complete the inner product operation related to W 0,q Perform the inner product operation for each frequency point in sequence, that is, for W p,q After performing the above operations, merge the operation results to obtain the Fourier transform result at each frequency point.

[0097] For example, taking the above input signal sequence as a 96 - point serial input signal sequence X 96 as an example, with a preset parallelism of 24, taking the first frequency point as an example, the vector inner product operation process is as follows:

[0098] temp1 = W 0,0 ×x(0)+W 0,1 ×x(1)+…+W 0,23 ×x(23);

[0099] temp2 = W 0,24 ×x(24)+W 0,25 ×x(25)+…+W 0,47 ×x(47);

[0100] temp3 = W 0,48 ×x(48)+W 0,49 ×x(49)+…+W 0,71 ×x(71);

[0101] temp4 = W 0,72 ×x(72)+W 0,73 ×x(73)+…+W 0,95 ×x(95);

[0102] X F X(0)=temp1 + temp2 + temp3 + temp4;

[0103] Among them, X F (0) is the result at the first frequency point in the Fourier transform result.

[0104] In an embodiment of the present invention, first, based on a preset parallelism degree, a parallel circuit is used to perform serial-to-parallel conversion on an input signal sequence to obtain a signal transformation matrix. Then, an original Fourier transform matrix is obtained according to the input signal sequence, and the original Fourier transform matrix is transformed into a parallel Fourier transform matrix based on the parallelism degree. Furthermore, the Fourier transform result of the input signal sequence can be obtained by performing vector inner product operations between the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence. When calculating, it is not necessary to require that the length of the input signal sequence must be a power of 2 or 4, nor is it necessary to require that the input signal sequence must be uniformly sampled. Instead, the Fourier transform result can be obtained by performing vector inner product operations between the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence, thereby improving the calculation efficiency, without introducing additional calculation steps, and avoiding waste of computing resources.

[0105] In one implementation, after transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism degree, the parallel Fourier transform matrix is stored in a ROM (Read-Only Memory) or a static register file in the form of a look-up table.

[0106] In an embodiment of the present invention, converting the parallel Fourier transform matrix into a look-up table form and storing it in a ROM manner or a static register file manner can achieve fast data access to save the calculation time for subsequent inner product operation processing. When using a look-up table, during parallel calculation, data can be directly read through the look-up table without having to recalculate each time, significantly reducing the calculation complexity and improving the processing speed, and effectively reducing latency and resource consumption.

[0107] In one implementation, performing vector inner product operations between the row vectors of the parallel Fourier transform matrix and the input signal sequence in sequence to obtain the Fourier transform result can be implemented by a parallel circuit, and the preset parallelism degree is M; the parallel circuit includes M calculation units; each calculation unit includes sub-calculation units; the output end of each sub-calculation unit is connected to a total adder; each sub-calculation unit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a first accumulator, a second accumulator, and a third accumulator; the output ends of the first multiplier and the second multiplier are connected to the first accumulator; the output ends of the third multiplier and the fourth multiplier are connected to the second accumulator; the output ends of the first accumulator and the second accumulator are connected to the third accumulator. Refer to Figure 2 , Figure 2It is a schematic diagram of a parallel circuit provided by an embodiment of the present invention. Each frequency point corresponds to an independent multiplier, and the calculation result is directly written into the corresponding storage unit. Among them, the sub-calculation unit includes a multiplier and an accumulator. If the parallelism is 24, 24 independent calculation units are instantiated, and the input of each calculation unit is connected to an independent address of the BRAM (Block RAM, block random access memory):

[0108] X(0) → BRAM0

[0109] X(1) → BRAM1;

[0110] ……

[0111] Among them, BRAM0 represents the BRAM connected to the first calculation unit; BRAM1 represents the BRAM connected to the second calculation unit.

[0112] In one implementation, the row vectors of the parallel Fourier transform matrix are successively subjected to vector inner product operations with the signal transform matrix to obtain the Fourier transform result, including:

[0113]

[0114] Among them, A(n) represents the nth frequency component of the Fourier transform result; represents the parallel Fourier transform matrix; represents the signal transform matrix; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism; represents the weighted Fourier transform factor of the input data of the ith sub-calculation unit of a calculation unit when calculating the nth frequency component of the Fourier transform result; represents the input data of the ith sub-calculation unit.

[0115] Specifically, taking M = 24 ， N = 96 as an example:

[0116] In the first clock cycle, units 0 to 23 calculate A(0), A(1) … A(23);

[0117] In the second clock cycle, units 0 to 23 calculate A(24), A(25) … A(47);

[0118] In the third clock cycle, units 0 to 23 calculate A(48), A(49) … A(71);

[0119] In the fourth clock cycle, units 0 to 23 calculate A(72), A(73) … A(95);

[0120] Among them, A(k - 1) represents the kth point of the Fourier transform result.

[0121] The simulation experiment of the calculation method for implementing Fourier transform using the parallel circuit provided by the embodiments of the present invention is as follows:

[0122] Refer to Figure 3 , Figure 3 , which is a schematic diagram comparing the results of calculating the Fourier transform of a 128-point signal sequence using the calculation method for implementing Fourier transform with a parallel circuit and the uniform FFT calculation method. Among them, the X-axis represents the number of data points, and the Y-axis represents the amplitude. For the uniform input signal sequence of 128 points, the real and imaginary parts of the Fourier calculation results based on the calculation method for implementing Fourier transform with a parallel circuit are very close to those of the traditional radix-2 FFT operation. The spectral curves of the two methods almost overlap, indicating a high degree of consistency in their frequency-domain characteristics and verifying the accuracy and feasibility of the calculation method for implementing Fourier transform with a parallel circuit provided by the embodiments of the present invention when processing a uniform input sequence.

[0123] Refer to Figure 4 , Figure 4 , which is a schematic diagram comparing the absolute errors of the amplitude and phase of the Fourier transform of a 128-point signal sequence calculated using the calculation method for implementing Fourier transform with a parallel circuit and the uniform FFT calculation method. Among them, the X-axis represents the number of data points, and the Y-axis represents the amplitude. The results of the two methods are highly consistent in the main frequency components and details, with almost no significant deviation, further verifying the feasibility and accuracy of the calculation method for implementing Fourier transform with a parallel circuit provided by the embodiments of the present invention.

[0124] Refer to Figure 5 , Figure 5 is the time-domain diagram of a 502-point non-uniform input sequence; among them, the X-axis represents the number of points, and the Y-axis represents the amplitude. Refer to Figure 6 , Figure 6 , which is a schematic diagram comparing the frequency-domain results of calculating a non-uniform input sequence using the calculation method for implementing Fourier transform with a parallel circuit and the conventional NUFFT calculation method. Among them, the X-axis represents the number of data points, and the Y-axis represents the amplitude value. It can be seen that for Figure 5 the provided non-uniform input sequence, the frequency-domain curves of the two are almost overlapping, and the main frequency components and the frequency-domain energy distribution are consistent, fully verifying the feasibility and accuracy of the calculation method for implementing Fourier transform with a parallel circuit provided by the embodiments of the present invention for non-uniform input sequences. The calculation method for implementing Fourier transform with a parallel circuit provided by the embodiments of the present invention not only rivals the NUFFT method in terms of accuracy but also can optimize the processing complexity, providing a more efficient and practical solution for the frequency-domain analysis of non-uniform signals. This result shows that the calculation method provided by the embodiments of the present invention can effectively process non-uniformly sampled data, thus ensuring the accuracy and stability of signal analysis.

[0125] Refer toFigure 7 , Figure 7 is a schematic diagram comparing the absolute errors of the amplitude and phase of the calculation results of the Fourier transform calculation method implemented by a parallel circuit and the conventional NUFFT calculation method for non-uniform input sequences. Among them, the X-axis of the error curve represents the number of data points, and the Y-axis represents the error amplitude. This result further verifies the correctness and effectiveness of the calculation method provided by the embodiments of the present invention when processing non-uniform input sequences, indicating that the calculation method provided by the embodiments of the present invention also has good robustness and is applicable to a wider range of signal analysis scenarios.

[0126] See Figure 8 , Figure 8 is a schematic diagram comparing the frequency domains of the calculation results of the Fourier transform calculation method implemented by a parallel circuit and the conventional zero-padding calculation method for non-integer power-of-two input sequences. Among them, the X-axis represents the frequency, and the Y-axis represents the amplitude. It can be seen that compared with the conventional zero-padding method, the frequency-domain energy of the spectrum calculated by using the calculation method provided by the embodiments of the present invention is more concentrated, the main frequency component is clearer, the side-lobe suppression effect is better, and the influence of frequency-domain leakage on signal analysis is reduced. In addition, the calculation method provided by the embodiments of the present invention can maintain the original number of points of the input signal, avoid the additional calculation burden introduced by zero-padding, and improve the accuracy and efficiency of spectrum calculation. While this direct transformation method has a relatively low computational complexity, it also ensures a higher spectrum resolution and accuracy.

[0127] In the embodiments of the present invention, through serial-parallel conversion combined with vector inner product operations, the positive-order input and positive-order output of non-uniform and non-integer power-of-two length input sequences are realized. The hardware implementation only depends on multipliers and adders, without a complex butterfly operation structure. Pipeline processing is adopted in the design process, with a configurable parallelism, and there is no cross in the logical connection, significantly simplifying the complexity of the hardware implementation. Taking a 96-point input sequence as an example, the number of multipliers (complex multiplication) required for the implementation of a new calculation method is: 24, the number of adders (complex addition) is: 23, and the processing clock cycle is: 384 clock cycles (384 clock cycles are for complex sequences, and real sequences require 192 clock cycles (only calculate half of its Fourier transform). When the resources are doubled, the number of clock cycles is halved. Theoretically, when the parallelism is fully expanded, the new calculation method can complete the Fourier transform of 96-point data in 1 clock cycle.

[0128] In the embodiments of the present invention, through serial-parallel conversion, a new Fourier transform implemented by relying on vector inner product is proposed, which can be used for the efficient calculation of the Fourier transform in parallel on FPGA or ASIC, can effectively solve the Fourier transform problem of non-uniform or non-standard length signals, provides a reliable hardware implementation solution for complex signal analysis, is applicable to signal sequences of any length, and effectively solves the Fourier transform problem of non-uniform or non-standard signals.

[0129] Based on the same inventive concept, an embodiment of the present invention further provides a computing device for implementing Fourier transform by a parallel circuit. Refer to Figure 9 , Figure 9 which is a schematic structural diagram of a computing device for implementing Fourier transform by a parallel circuit provided by an embodiment of the present invention. The computing device includes:

[0130] An acquisition module 901, configured to acquire an input signal sequence of an input signal;

[0131] A serial-to-parallel conversion module 902, configured to perform serial-to-parallel conversion on the input signal sequence by using a parallel circuit based on a preset parallelism degree to obtain a signal transformation matrix;

[0132] A matrix transformation module 903, configured to obtain an original Fourier transform matrix according to the input signal sequence, and transform the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism degree;

[0133] An operation module 904, configured to perform vector inner product operations on row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain a Fourier transform result of the input signal sequence.

[0134] In an embodiment of the present invention, first, based on a preset parallelism degree, a parallel circuit is used to perform serial-to-parallel conversion on an input signal sequence to obtain a signal transformation matrix. Then, an original Fourier transform matrix is obtained according to the input signal sequence, and the original Fourier transform matrix is transformed into a parallel Fourier transform matrix based on the parallelism degree. Furthermore, vector inner product operations are performed on row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain a Fourier transform result of the input signal sequence. When calculating, it is not required that the length of the input signal sequence must be an Nth power of 2 or 4, nor is it required that the input signal sequence must be uniformly sampled. Instead, vector inner product operations can be performed on row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain a Fourier transform result, thereby improving the calculation efficiency, without introducing additional calculation steps, and avoiding waste of computing resources.

[0135] Optionally, the preset parallelism degree is M; the parallel circuit includes M computing units; each computing unit includes sub-computing units; the output end of each sub-computing unit is connected to a total adder; each sub-computing unit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a first accumulator, a second accumulator, and a third accumulator;

[0136] The output terminals of the first multiplier and the second multiplier are connected to the first accumulator; the output terminals of the third multiplier and the fourth multiplier are connected to the second accumulator; the output terminals of the first accumulator and the second accumulator are connected to the third accumulator.

[0137] Optionally, the operation module is specifically configured to perform the following calculations:

[0138]

[0139] where A(n) represents the nth frequency component of the Fourier transform result; represents the parallel Fourier transform matrix; represents the signal transformation matrix; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism; represents the weighted Fourier transform factor of the input data of the ith sub-computation unit of a computation unit when calculating the nth frequency component of the Fourier transform result; represents the input data of the ith sub-computation unit.

[0140] Optionally, the input signal sequence includes N time-domain sampling points; the preset parallelism is M; the serial-to-parallel conversion module is specifically configured to:

[0141] Use a parallel circuit to extract the input signal sequence with every M time-domain sampling points as a subsequence, obtaining parallel sequences; and merge parallel sequences into a signal transformation matrix with M rows and N columns.

[0142] Optionally, the signal transformation matrix is:

[0143]

[0144] where the kth element in the signal transformation matrix is represented by x(k); k = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism.

[0145] Optionally, the parallel Fourier transform matrix is:

[0146]

[0147] where the transformation factor of the pth time-domain sampling point to the qth frequency component in the parallel Fourier transform matrix is represented by W p,qIt is represented that: p = 1, 2,..., N - 1; q = 1, 2,..., N - 1; N represents the total number of time-domain sampling points of the input signal sequence; M represents the parallelism degree.

[0148] Optionally, the computing device further includes a storage module, which is specifically configured to store the parallel Fourier transform matrix in the form of a look-up table in a ROM or a static register file after transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism degree.

[0149] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are only examples of devices and methods consistent with some aspects of the present invention.

[0150] In the description of this specification, the description referring to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0151] Although the present invention has been described in conjunction with various embodiments herein, however, in the process of implementing the claimed present invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "including" does not exclude other components or steps, the term "a" or "one" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0152] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiments.

[0153] It should be noted that the device in the embodiments of the present invention is a device for implementing the calculation method of Fourier transform using the above-mentioned parallel circuit. Therefore, all embodiments of the above-mentioned calculation method of implementing Fourier transform using a parallel circuit are applicable to this device, and all can achieve the same or similar beneficial effects.

[0154] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for calculating Fourier transform using parallel circuits, characterized in that: The calculation method includes: obtaining an input signal sequence of an input signal; Based on a preset parallelism, using a parallel circuit to perform serial-to-parallel conversion on the input signal sequence to obtain a signal conversion matrix; Acquire an original Fourier transform matrix according to the input signal sequence, and transform the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism; The row vectors of the parallel Fourier transform matrix are sequentially subjected to vector inner product operations with the signal transform matrix to obtain the Fourier transform result of the input signal sequence.

2. The calculation method according to claim 1, characterized in that: The preset parallelism is M; the parallel circuit includes M computing units; each computing unit includes sub-computing units; the output end of each sub-computing unit is connected to the total adder; each sub-computing unit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a first accumulator, a second accumulator and a third accumulator; The output ends of the first multiplier and the second multiplier are connected to the first accumulator; the output ends of the third multiplier and the fourth multiplier are connected to the second accumulator; and the output ends of the first accumulator and the second accumulator are connected to the third accumulator.

3. The calculation method according to claim 2, characterized in that: Performing vector inner product operations on the row vectors of the parallel Fourier transform matrix and the signal transform matrix in sequence to obtain a Fourier transform result, including: Wherein, A(n) represents the nth frequency component of the Fourier transform result; represents the parallel Fourier transform matrix; represents the signal transformation matrix; N represents the total number of time domain sampling points of the input signal sequence; M represents the parallelism; represents a weighted Fourier transform factor of input data of an i-th sub-computational unit of a calculation unit when calculating the n-th frequency component of the Fourier transform result; Represents the input data of the i-th sub-computation unit.

4. The calculation method according to claim 1, characterized in that: The input signal sequence includes N time domain sampling points; the preset parallelism is M; Based on a preset parallelism, a parallel circuit is used to perform serial-to-parallel conversion on the input signal sequence to obtain a signal conversion matrix, including: By using a parallel circuit, the input signal sequence is extracted with each M time domain sampling points as a subsequence to obtain parallel sequences; Will parallel sequences are merged into M rows The signal transformation matrix of the columns.

5. The calculation method according to claim 4, characterized in that: The signal transformation matrix is: The kth element in the signal transformation matrix is ​​represented by x(k); k=1, 2, ..., N-1; N represents the total number of time domain sampling points of the input signal sequence; and M represents the parallelism.

6. The calculation method according to claim 1, characterized in that: The parallel Fourier transform matrix is: The transformation factor of the p-th time domain sampling point to the q-th frequency component in the parallel Fourier transform matrix is ​​W p,q Indicates; p = 1, 2, ..., N-1; q = 1, 2, ..., N-1; N represents the total number of time domain sampling points of the input signal sequence; M represents the parallelism.

7. The calculation method according to claim 1, characterized in that: The calculation method further includes: after transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism, storing the parallel Fourier transform matrix in a ROM or a static register file in the form of a lookup table.

8. A computing device for implementing Fourier transform using parallel circuits, characterized in that: The computing device comprises: An acquisition module, used for acquiring an input signal sequence of an input signal; A serial-to-parallel conversion module, used for performing serial-to-parallel conversion on the input signal sequence using a parallel circuit based on a preset parallelism to obtain a signal conversion matrix; A matrix transformation module, used for obtaining an original Fourier transform matrix according to the input signal sequence, and transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the parallelism; The operation module is used to perform vector inner product operations on the row vectors of the parallel Fourier transform matrix and the signal transformation matrix in sequence to obtain the Fourier transform result of the input signal sequence.

9. The computing device according to claim 8, characterized in that The preset parallelism is M; the parallel circuit includes M computing units; each computing unit includes sub-computing units; the output end of each sub-computing unit is connected to the total adder; each sub-computing unit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a first accumulator, a second accumulator and a third accumulator; The output ends of the first multiplier and the second multiplier are connected to the first accumulator; the output ends of the third multiplier and the fourth multiplier are connected to the second accumulator; and the output ends of the first accumulator and the second accumulator are connected to the third accumulator.

10. The computing device according to claim 8, characterized in that The computing module is specifically used to perform the following calculations: Wherein, A(n) represents the nth frequency component of the Fourier transform result; represents the parallel Fourier transform matrix; represents the signal transformation matrix; N represents the total number of time domain sampling points of the input signal sequence; M represents the parallelism; represents a weighted Fourier transform factor of input data of an i-th sub-computational unit of a calculation unit when calculating the n-th frequency component of the Fourier transform result; Represents the input data of the i-th sub-computation unit.

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