Model Order Reduction Method, System, Device and Medium of Grid-Connected Converter Based on Optimal Hankel Norm Approximation

Abstract

The present invention belongs to the technical field of mathematical modeling of grid-forming converters, and discloses a method, system, device and medium for reducing the order of a grid-forming converter model based on optimal Hankel norm approximation, so as to solve the applicability problem of the grid-forming converter model under high short-circuit ratio conditions. The method of the present invention is based on a full-order model, and includes S1 current loop order reduction processing, S2 voltage loop Hankel approximation order reduction, and S3 construction of a ninth-order model. The present invention reduces the full-order system to a ninth-order model through dq decoupling, feedforward cancellation, and optimal Hankel norm approximation, greatly reducing the computational complexity while ensuring control accuracy. The present invention considers the filter for filtering active and reactive high-frequency components and the line resistance and inductance equations to construct a ninth-order model of the grid-forming converter, effectively improving the model accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of mathematical modeling of grid-connected converters, and in particular relates to a grid-connected converter model order reduction method, system, device and medium based on optimal Hankel norm approximation. Background Art

[0002] As a new energy power electronic device, the core function of the grid-connected converter is to simulate the characteristics of a synchronous generator. It can effectively support the voltage and frequency of the power grid, thereby significantly enhancing the overall stability of the power system. Especially in the scenario of new energy grid connection, the grid-connected converter has greatly improved the reliability of weak power grids or island power supply with its powerful grid connection capability, and further improved the operational resilience of the power system. Virtual Synchronous Generator (VSG) technology is the key technology for the grid-connected converter to simulate the characteristics of synchronous generators. By simulating the operating mechanism of synchronous generators, VSG technology gives new energy power generation equipment inertia and damping characteristics, enabling it to actively support the frequency and voltage of the power grid like a synchronous generator, providing solid technical support for the stable operation of the power system.

[0003] At present, in the field of modeling and simulation of grid-connected converters, a variety of models have been realized. In particular, in the modeling of grid-connected converters using VSG control technology, there are mainly two mainstream models: full-order model and third-order reduced-order model. The full-order model retains all control links of the grid-connected converter and provides a comprehensive description of the system behavior. However, due to its high complexity, it leads to a huge amount of calculation and high performance requirements for computing equipment, which is not conducive to the application of real-time simulation and online analysis. In order to simplify the calculation, the third-order reduced-order model obtains the reduced-order model by truncating the eigenvalues of the full-order model. Although the third-order reduced-order model is simple in form and easy to solve, its accuracy is challenged in the case of high short-circuit ratio. Because the third-order reduced-order model ignores key parts such as voltage and current loop control and inductance transient in the filter, it is considered that the power outer loop directly controls the capacitor voltage, which may cause the model to fail to accurately reflect the actual behavior of the system in the high short-circuit ratio scenario.

[0004] In summary, the applicability of current grid-connected converter models in high short-circuit ratio situations has significant problems. These models are difficult to balance the calculation speed and efficiency while ensuring accuracy, which limits their effective application in specific scenarios. Summary of the invention

[0005] Based on the above-mentioned disadvantages and deficiencies in the prior art, one of the objectives of the present invention is to at least solve one or more of the above-mentioned problems existing in the prior art. In other words, one of the objectives of the present invention is to provide a method, system, device, and medium for reducing the order of the grid-forming converter model based on the optimal Hankel norm approximation that meet one or more of the foregoing requirements, so as to solve the applicability problem of the grid-forming converter model under high short-circuit ratio conditions, ensure that the model accuracy is within an acceptable range, accurately reflect the system characteristics, and at the same time ensure high calculation speed and improve operation efficiency.

[0006] To achieve the above-mentioned invention objectives, the present invention adopts the following technical solutions:

[0007] In the first aspect, the present invention provides a method for reducing the order of the grid-forming converter model based on the optimal Hankel norm approximation. Based on the full-order model, it includes S1 current loop order reduction processing, S2 voltage loop Hankel approximation order reduction, and S3 constructing a ninth-order model:

[0008] The S1 current loop order reduction processing includes:

[0009] Perform dq decoupling on the mathematical model of the current loop control circuit in the full-order model, and eliminate the cross-coupling term through feedforward compensation;

[0010] Set the inverter proportional coefficient , and simplify the current loop closed-loop transfer function;

[0011] Adjust the PI controller parameters to approximately cancel the zero and pole, so that the current inner loop control is equivalent to a unit proportional link;

[0012] The S2 voltage loop Hankel approximation order reduction includes:

[0013] Based on the unit proportional simplification result obtained in S1, perform dq decoupling on the voltage loop control circuit in the full-order model;

[0014] Convert the second-order transfer function formula of the voltage loop into a state-space model formula, solve and decompose it, retain the states corresponding to the dominant Hankel singular value , and truncate the states corresponding to the minor singular value , so as to obtain a first-order approximation link for the voltage outer loop;

[0015] The S3 constructing a ninth-order model includes:

[0016] Based on the power measurement link in the full-order model, and set the cut-off frequency Filter out the high-frequency components to obtain a power measurement filtering link;

[0017] Retain the dq-axis coupling characteristics of the line resistance and inductance link in the full-order model;

[0018] Combine the current inner-loop unit proportional link obtained in S1, the voltage outer-loop first-order approximation link obtained in S2, the power measurement filtering link, and the line resistance and inductance link to obtain a ninth-order reduced-order model.

[0019] As a preferred solution, the inverter proportional coefficient takes the value of 1.

[0020] As a preferred solution, the expression of the current inner-loop unit proportional link is:

[0021] ,

[0022] wherein, and are respectively the integral parameter and the proportional parameter of the current PI control, and are respectively the filter inductor and resistor, and s is the complex variable of the Laplace transform.

[0023] As a preferred solution, the second-order transfer function formula of the voltage loop is:

[0024] ,

[0025] wherein, and are respectively the integral parameter and the proportional parameter of the voltage loop PI control, is the filter capacitor.

[0026] As a preferred solution, the state space model formula is:

[0027] ,

[0028] wherein, , , , .

[0029] As a preferred solution, the expression of the voltage outer-loop first-order approximation link is:

[0030] ,

[0031] wherein, , , are matrix constants, , are intermediate variables, , are respectively , derivatives, and are the d - axis and q - axis components of the filter capacitor voltage respectively, and are the d - axis and q - axis reference values of the filter capacitor voltage respectively.

[0032] As a preferred solution, the expression of the ninth - order reduced - order model is:

[0033] ,

[0034] wherein, is the inertia of the virtual synchronous machine, , are the active and reactive droop coefficients respectively, , , , are the set values of angular velocity, active power, reactive power, d axis voltage respectively, , are the measured active and reactive powers respectively, , are the d - axis and q - axis components of the line current respectively, is the power angle of the system, and is the angular frequency of the system, , are the line inductance and resistance respectively, , are the d - axis and q - axis components of the grid voltage respectively, is the time constant of the direct - axis voltage in the control loop of the grid - forming converter, is the cut - off frequency of the filter.

[0035] In the second aspect, the present invention provides a grid - forming converter model reduction system based on optimal Hankel norm approximation, which is used to implement the grid - forming converter model reduction method as described in the first aspect.

[0036] In the third aspect, the present invention provides an electronic device, where the computer device includes a memory, a processor, and a computer program, and the computer program, when executed by the processor, implements the grid - forming converter model reduction method as described in the first aspect.

[0037] In the fourth aspect, the present invention provides a computer - readable storage medium, on which a computer program is stored, and the computer program, when executed by the processor, implements the grid - forming converter model reduction method as described in the first aspect.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. The present invention reduces the full-order system to a ninth-order model through dq decoupling, feedforward cancellation, and optimal Hankel norm approximation, significantly reducing the computational complexity while ensuring control accuracy.

[0040] 2. The present invention constructs a ninth-order model of the grid-forming converter by considering the active and reactive high-frequency component filtering links of the filter and the line resistance-inductance equation, effectively improving the model accuracy.

[0041] Further or more detailed beneficial effects will be described in conjunction with specific embodiments in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic diagram of the application scenario of the grid-forming converter model reduction method described in the embodiments of the present invention.

[0044] Figure 2 It is a schematic diagram of the voltage and current control loops described in the embodiments of the present invention.

[0045] Figure 3 It is a schematic diagram of the distribution of the characteristic roots of the third-order reduced-order model described in the embodiments of the present invention.

[0046] Figure 4 It is a schematic diagram of the distribution of the characteristic roots of the full-order reduced-order model described in the embodiments of the present invention.

[0047] Figure 5 It is a comparison diagram of the change trajectories of the characteristic roots of the third-order reduced-order model and the full-order model described in the embodiments of the present invention.

[0048] Figure 6 It is a schematic diagram of the time-domain simulation results of the third-order reduced-order model and the full-order model described in the embodiments of the present invention.

[0049] Figure 7 It is a flowchart of the grid-forming converter model reduction method described in the embodiments of the present invention.

[0050] Figure 8 It is an equivalent diagram of the current loop described in the embodiments of the present invention.

[0051] Figure 9 It is an equivalent diagram of the voltage loop described in the embodiments of the present invention.

[0052] Figure 10It is the root locus change diagram of the ninth-order model obtained by the network-forming converter model order reduction method described in the embodiments of the present invention.

[0053] Figure 11 It is the structural diagram of the electronic device described in the embodiments of the present invention.

[0054] Reference numerals in the drawings:

[0055] 1100, electronic device;

[0056] 1101, processor; 1102, communication bus; 1103, user interface; 1104, network interface; 1105, memory. Detailed implementation manners

[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0058] In the following introduction, multiple embodiments of the present invention are provided, and different embodiments can be replaced or combined. Therefore, the present invention can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then the present invention should also be considered to include embodiments containing one or more all other possible combinations of A, B, C, and D, although such embodiments may not be explicitly described in the following content.

[0059] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes can be made to the functions and arrangements of the described elements without departing from the scope of the content of the present invention. Each example can appropriately omit, substitute, or add various processes or components. For example, the described method can be executed in a different order than the described order, and various steps can be added, omitted, or combined. In addition, the features described in some examples can be combined into other examples.

[0060] To facilitate a better understanding of the embodiments of the present invention, before explaining the detailed implementation manners of the present invention in detail, its application scenarios will be described first.

[0061] Please refer to Figure 1 , Figure 1 which shows a schematic diagram of the application scenario of the network-forming converter model order reduction method.

[0062] There are already many existing models that can realize the modeling and simulation of network-forming converters. For example Figure 1Shown is a grid-forming converter and its control structure. After collecting the voltage on the filter capacitor and the inductor current at the converter ports, on the one hand, it is fed into the inner loop through abc / dg transformation, and on the other hand, it is input into the outer loop of grid-forming control through a power calculation link to generate the amplitude and phase of the external reference voltage of the filter and feed them into the inner loop. The inner loop includes a voltage feedback loop and a current feedback loop, and outputs the dq components of the converter reference voltage, which are transformed into three-phase reference voltage e abc , which is modulated into a gate signal through the PWM link to drive the converter. Note that the phase angles used in the dq transformation and inverse transformation are autonomously generated by the grid-forming control and do not require a traditional phase-locked loop to provide.

[0063] In the control loop, the outer loop of the grid-forming has forms such as virtual synchronous generator (VSG) and droop control. The voltage and current control loops are as Figure 2 shown. Currently, for VSG control, mainly two models are used for grid-forming converter modeling regarding whether to ignore the voltage and current loops. One is the full-order model, and the other is the third-order reduced-order model.

[0064] The full-order model retains all the control links of the converter, and the differential equations of each link are as follows:

[0065] 1. Outer loop power control

[0066] (1)

[0067] In Equation (1), is the inertia of the virtual synchronous generator, are the active and reactive droop coefficients respectively, are the angular velocity, active power, reactive power, d the axis voltage set values, are the voltage and current reference values respectively, is the system power angle, is the system angular frequency, generally designed as , are the measured active and reactive powers respectively. Assuming that the system uses a filter with a cut-off frequency of to filter out the high-frequency components of active and reactive powers, then the following equation holds:

[0068] (2)

[0069] In Equation (2), are the dq-axis components of the filter capacitor voltage respectively, are the dq-axis components of the line current respectively.

[0070] 2. Outer loop voltage control

[0071] The voltage loop is controlled by PI, and the mathematical model is as follows:

[0072] (3)

[0073] In Equation (3), is an intermediate variable, are respectively the integral parameter and the proportional parameter of the voltage loop PI control, are respectively the dq-axis current reference values.

[0074] 3. Inner-loop current control

[0075] The current loop is controlled by PI, and its mathematical model is shown as the following equation:

[0076] (4)

[0077] In Equation (4), are respectively the dq-axis components of the filter inductor current, is an intermediate variable, are respectively the integral parameter and the proportional parameter of the current PI control, are respectively the dq-axis component reference values of the inverter port voltage.

[0078] 4. Inverter

[0079] Assuming that the high-order harmonics are filtered by the filter, the inverter can be represented by a proportional link:

[0080] (5)

[0081] In Equation (5), are respectively the dq-axis components of the inverter port voltage, is the proportional coefficient.

[0082] 5. Filter inductor

[0083] (6)

[0084] In Equation (6), are respectively the filter inductor and the resistor.

[0085] 6. Filter capacitor

[0086] (7)

[0087] In Equation (7), is the filter capacitor.

[0088] 7. Line resistance and inductance

[0089] (8)

[0090] In Equation (8), are respectively the line inductance and the resistor, is the dq-axis component of the grid voltage.

[0091] As can be seen from the above, the full-order model of the inverter is of 15th order, with a relatively high order. When there are multiple grid-forming converters in the system, the system solution speed becomes slower. Therefore, in the first embodiment, the full-order model is reduced in order to ensure that the model accuracy is within an acceptable range, accurately reflect the system characteristics, and at the same time ensure high calculation speed and improve the operation efficiency.

[0092] The third-order reduced-order model is obtained by truncating the eigenvalues of the full-order model. This model ignores three parts of the full-order model: one is the voltage-current loop control, the transient of the inductor in the filter, etc., and it is considered that the power outer loop directly controls the capacitor voltage, that is ; the second is the power measurement filter; the third is the line electromagnetic transient. Its mathematical model equation is as follows:

[0093] (9)

[0094] Where is obtained from the following non-linear equation set:

[0095] (10)

[0096] When , where X s is the line power frequency reactance. Ignoring R g , and transforming the third-order reduced-order model into the abc coordinate system, a more concise form can be obtained as follows:

[0097] (11)

[0098] In formula (11), is the grid voltage. This reduced-order model has only three orders. Compared with the full-order model, it has a simple form and is convenient to solve. However, in the case of a high short-circuit ratio, there is a problem of inaccurate model.

[0099] The above first model (full-order model) includes multiple links such as power calculation, power control, voltage-current control, coordinate transformation, and filtering, which makes the model calculation amount huge and requires high performance of the calculation device. In real-time simulation and online analysis scenarios, the timeliness of analysis and control may be affected due to the calculation time consumption.

[0100] For the second model above (third-order reduced-order model), it is necessary to truncate the eigenvalues of the full-order model. Since less original spatial information is retained, some details and dynamic characteristics will be lost. As time goes by, the error of the numerical solution may gradually increase, making it difficult to accurately describe the complex dynamic behavior of the grid-connected converter. When analyzing some characteristics that are sensitive to details, the accuracy of the results will be affected. In particular, when the actual operating conditions change significantly, such as an increase in grid strength (increase in short-circuit ratio), load characteristics, ambient temperature, etc., the applicability of the model may decrease, and it cannot accurately reflect the performance of the converter in different scenarios.

[0101] Now, through small-signal analysis, the reduced applicability of the third-order reduced-order model under high short-circuit ratio is further explained.

[0102] For the third-order reduced-order model, through small-signal analysis, its characteristic root distribution is as Figure 3 shown. Comparing with the characteristic root distribution of the full-order model ( Figure 4 ), it can be seen that the third-order reduced-order model ignores some poles and only selects the three poles caused by the power loop. It should be noted that because the influence of other loops is ignored, these three poles do not completely coincide in the third-order reduced-order model and the full-order model.

[0103] When the short-circuit ratio is increased from 1.2 to 24, the change trajectories of the characteristic roots of the third-order reduced-order model and the full-order model are as Figure 5 shown, where blue represents the third-order reduced-order model and red represents the full-order model. From Figure 5 , it can be seen that when the short-circuit ratio changes from 1.2 to 24, all the characteristic roots of the third-order reduced-order model are still in the negative half-plane, and the system is not unstable. When the SCR changes from 1.2 to 2.8, the characteristic roots of the full-order model have crossed the real axis and come to the positive half-plane, and the system loses stability. The corresponding time-domain results are as Figure 6 shown. Under high short-circuit ratio, the third-order reduced-order model is still stable, while the full-order model experiences subsynchronous oscillation, and the oscillation frequency is about 3HZ.

[0104] It can be seen from this that under high short-circuit ratio, the third-order reduced-order model does not experience subsynchronous oscillation, while the full-order model shows subsynchronous oscillation. In fact, even when the short-circuit ratio is increased again, the third-order reduced-order model still will not show subsynchronous oscillation. Next, a simple proof is given that when the short-circuit ratio is infinite ( ), the third-order reduced-order model will not show subsynchronous oscillation.

[0105] Conclusion 1: When , the third-order differential equation system has an equilibrium point.

[0106] The derivation process is as follows:

[0107] Assume that the differential equation has an equilibrium point, then it satisfies the following conditions.

[0108] (12)

[0109] In Equation (12), is the reactive power droop coefficient, and are expression symbols, is the power angle of the grid-forming converter. When at this time , and at this time . Take when (k is any positive real number), . At this time . Let we can get , and then get . Therefore, when is , F 2 is greater than 0. When is , is less than 0. Since is continuous, there is a zero crossing, so there must exist a constant . In addition, from the expression, it can be seen that at this time .

[0110] Conclusion 2: When , the characteristic roots of the third-order differential equation system are in the negative half-plane, and the system is stable.

[0111] The derivation process is as follows:

[0112] The characteristic matrix of the third-order differential equation is as follows:

[0113] (13)

[0114] According to , and using the parameter a, b, c, d to represent the corresponding elements of the matrix, we can get:

[0115] (14)

[0116] The matrix Jacobi characteristic equation is deduced to , and after expansion, it is:

[0117] (15)

[0118] In Equation (15), λ represents the characteristic root. The Hurwitz criterion is used to judge the stability. First, all the coefficients of the characteristic equation are greater than 0. Construct the Hurwitz matrix as follows:

[0119] (16)

[0120] The first-order determinant is , satisfying . The second-order determinant is . Since , so . Therefore, the second-order determinant is greater than 0. The third-order determinant is expanded by the third column, and its positive and negative nature is the same as that of the second-order determinant, so it is also greater than 0.

[0121] Therefore, when , the real parts of the eigenvalues of the characteristic matrix are all negative, and the system remains stable.

[0122] In short, in the case of a low short-circuit ratio, the accuracy of the third-order reduced-order model is acceptable. However, in the case of a high short-circuit ratio, the full-order model exhibits subsynchronous oscillation, while the third-order reduced-order model does not. The fundamental reason is that the third-order reduced-order model ignores the control loop, the control of the power measurement loop, and the measurement delay.

[0123] Therefore, the method for reducing the order of the grid-forming converter model described in the embodiments of this specification is applied to processes such as power system stability control, new energy power generation grid connection optimization, and microgrid energy management. In these scenarios, the application of the method for reducing the order of the grid-forming converter model aims to solve the applicability problem of the grid-forming converter model in the case of a high short-circuit ratio, accurately reflect the dynamic characteristics of the grid-forming converter, and provide a more efficient model tool for the microgrid energy management system.

[0124] The following briefly explains the short-circuit ratio and subsynchronous oscillation involved in multiple embodiments of this specification:

[0125] Short-circuit ratio: The short-circuit ratio (SCR) is an index in the power system to measure the strength of a power source (such as a generator) or the power grid, and is equal to the ratio of the short-circuit capacity to the rated capacity.

[0126] Subsynchronous oscillation: Subsynchronous oscillation is an electromagnetic-mechanical oscillation phenomenon in the power system with a frequency lower than the power frequency. The coupling of the converter control parameters and the grid impedance at the subsynchronous frequency (<50 / 60 Hz) causes resonance, which may cause subsynchronous oscillation and lead to converter instability and equipment damage.

[0127] Example 1:

[0128] As Figure 7As shown in the figure, this embodiment provides a method for reducing the order of the grid-forming converter model based on the optimal Hankel norm approximation, which is based on the full-order model. First, according to the feedforward decoupling in the current loop control structure in the full-order model, the current loop is equivalent to a unit proportional link. Then, according to the optimal Hankel norm approximation, the voltage loop is equivalent to a first-order lag link. Finally, considering the filtering link of the power measurement and the line resistance and inductance link, a nine-order grid-forming converter virtual synchronous machine model is obtained. Through simulation analysis, it is found that this model exhibits subsynchronous oscillation phenomenon under high short-circuit ratio conditions, overcoming the problem of model inaccuracy of the third-order reduced-order model under high short-circuit ratio conditions. The method mainly includes three links: current loop approximation, voltage loop approximation, and nine-order model construction, which are specifically as follows:

[0129] 1. Current loop approximation

[0130] The control objective of the inner current loop of the converter is that the current value on the filter inductor is equal to its reference value. This part is mainly composed of the inner loop current control and the circuit resistance and inductance equation. The mathematical model of the current loop control circuit is shown in Equation (4). The difference between the dq-axis current reference value and the dq-axis components of the filter inductor current is used as the control quantity, and a PI controller is used to control the output of the dq-axis reference value of the inverter terminal voltage , as shown in Figure 8 (a). For the inverter link, when the inverter proportional coefficient is set to 1, we can obtain , . The mathematical model of the circuit resistance and inductance equation is shown in Equation (6), and there is cross-coupling between the dq axes, as shown in Figure 8 (b). Therefore, the cross-coupling terms , and the feedforward terms , in the inner current loop control are designed to cancel the corresponding variables in the circuit equation. After cancellation, the circuit and control equations can be simplified to the form of Figure 8 (c). It can be seen that the dq-axis current control realizes decoupling, and the equivalent transfer function of the inner current loop is as follows:

[0131] (17)

[0132] If appropriate parameters are selected for the PI controller so that the zero and poles of the closed-loop transfer function are cancelled as much as possible, the system can be further approximately simplified to a first-order inertial link, as shown in Figure 8 (d). The time constant T is jointly determined by the filter resistance and inductance parameters and the PI controller parameters. Generally speaking, the time constant TFor the outer loop control, it is small, so this first-order inertial system can be approximated as a unity ratio system.

[0133] 2. Voltage loop approximation

[0134] The control objective of the outer voltage loop of the converter is that the voltage value on the filter capacitor is equal to its reference value. This part is mainly composed of the outer voltage control and the circuit capacitor equation. The mathematical model of the voltage loop control circuit is shown in Equation (3), and the difference between the dq-axis voltage reference value and the dq-axis components of the filter capacitor voltage is used as the control quantity, and a PI controller is used to control the output filter capacitor voltage , as shown in Figure 9 (a). The mathematical model of the circuit capacitor equation is shown in Equation (7), and there is cross-coupling between its dq axes, as shown in Figure 9 (b).

[0135] Figure 9 The circuit equation of the filter impedance inductance part and the inner current control part in Figure 8 are the same as Figure 8 and can be represented by (a) and (b), and will not be redrawn here. According to the previous analysis, if the response speed of the current loop and the filter impedance inductance equation is much higher than that of the voltage loop and the filter capacitor equation, then on the time scale of the latter, the former can be regarded as a unity ratio system, that is, it satisfies Figure 9 . At this time, the voltage loop control equation shown in Figure 9 (a) and the filter capacitor equation shown in can be directly connected. Observing its input and output, it can be seen that the overall control objective of the voltage and current double inner loops of the grid-forming converter is that the voltage value on the filter capacitor is equal to its reference value, and this objective is achieved through the PI controller and the current and voltage double-loop feedback. Similar to the current loop, the cross-coupling term and the leading term Figure 9 in the typical voltage loop control are also designed to cancel the corresponding variables in the circuit equation. Therefore, the circuit and control equations after cancellation can be simplified to the form of Figure 9 (c), so that the dq-axis voltage control is decoupled. As shown in (d), it can be further simplified to a system with as the transfer function, and the expression of

[0136] is as follows.

[0137] Next, approximate as a first-order system through the optimal Hankel norm approximation:

[0138] ① State space modeling

[0139] Convert the second-order transfer function into a state-space model:

[0140] (19)

[0141] In Equation (19), , , , .

[0142] ② Balanced realization

[0143] (a) Calculate the controllability / observability matrices:

[0144] Solve the Lyapumov equation

[0145] (20)

[0146] Obtain the controllability matrix P and the observability matrix Q.

[0147] (b) Balanced transformation:

[0148] Perform a singular value decomposition on PQ, , such that , where are the Hankel singular values, are the left and right singular matrices respectively.

[0149] ③ Truncate the low-energy states

[0150] Retain the states corresponding to the dominant Hankel singular value , and truncate the part related to to obtain a first-order approximate system.

[0151] (21)

[0152] In Equation (21), is the matrix (constant) of the first-order system after balanced truncation. Substitute the input and output variables to obtain the first-order Hankel approximation of the voltage loop:

[0153] (22)

[0154] In the equation, is the intermediate variable.

[0155] 3. Nine-order reduced-order model of the grid-forming converter

[0156] The mathematical equation for power measurement is shown in Equation (2). Assume that the system uses a cut-off frequency of The filter filters out the active and reactive high-frequency components. The line resistance-inductance equation is shown in Equation (8), and there is cross-coupling between its dq axes. Both the filter link and the line resistance-inductance equation belong to first-order systems.

[0157] To sum up, the final model is reduced to a ninth-order model, and its mathematical model is as follows:

[0158] .(23)

[0159] This embodiment considers components such as the control link, filter, and line resistance-inductance, and establishes a more accurate ninth-order model, which can overcome the problem of model distortion of the third-order reduced-order model under high short-circuit ratio conditions. Figure 10 shows the root locus of the ninth-order model when SCR changes from 1.2 to 5.3. From Figure 9 it can be seen that the ninth-order model has 9 poles. When SCR changes to 5.3, a pair of conjugate complex roots cross the real-axis safety boundary, indicating that the system has a subsynchronous oscillation.

[0160] Embodiment 2:

[0161] This embodiment provides a grid-forming converter model reduction system based on optimal Hankel norm approximation for implementing the grid-forming converter model reduction method described in Embodiment 1.

[0162] Embodiment 3:

[0163] As Figure 11 shown, this embodiment provides an electronic device, which may include: at least one processor, at least one network interface, a user interface, a memory, and at least one communication bus.

[0164] Among them, the communication bus can be used to realize the connection and communication of the above-mentioned various components.

[0165] Among them, the user interface may include buttons, and the optional user interface may further include a standard wired interface and a wireless interface.

[0166] Among them, the network interface may but is not limited to including a Bluetooth module, an NFC module, a Wi-Fi module, etc.

[0167] Among them, the processor may include one or more processing cores. The processor uses various interfaces and circuits to connect various parts within the entire electronic device. By running or executing instructions, programs, code sets, or instruction sets stored in the memory, and by calling the data stored in the memory, it executes various functions of the electronic device and processes data. Optionally, the processor may be implemented in at least one hardware form of DSP, FPGA, or PLA. The processor may integrate one or a combination of several of CPU, GPU, and modem, etc. Among them, the CPU mainly processes the operating system, user interface, application programs, etc.; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor and can be implemented separately by a single chip.

[0168] Among them, the memory may include RAM and may also include ROM. Optionally, the memory includes a non-transitory computer-readable medium. The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area. Among them, the program storage area can store instructions for implementing the operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area can store the data involved in the above-mentioned various method embodiments. Optionally, the memory may also be at least one storage device located far from the aforementioned processor. The memory, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and a degradation application program. The processor can be used to call the degradation application program stored in the memory and execute the steps of the network-forming converter model degradation method mentioned in the foregoing embodiments.

[0169] Embodiment 4:

[0170] This embodiment provides a computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When they run on a computer or a processor, they cause the computer or the processor to execute one or more steps in the above-mentioned embodiments. If the various component modules of the above-mentioned electronic device are implemented in the form of software functional units and sold or used as independent products, they can be stored in the computer-readable storage medium.

[0171] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this specification are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a Digital Versatile Disc (DVD)), or a semiconductor medium (such as a Solid State Disk (SSD)), etc.

[0172] Those of ordinary skill in the art can understand that all or part of the processes in implementing the method in the above-mentioned first embodiment can be completed by instructing relevant hardware through a computer program. This program can be stored in a computer-readable storage medium. When this program is executed, it can include the processes of the embodiments of the above-mentioned various methods. The foregoing storage media include: various media such as ROM, RAM, magnetic disks, or optical discs that can store program codes. Without conflict, the technical features in this embodiment and the implementation solutions can be combined arbitrarily.

[0173] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0174] In the above embodiments, each embodiment is described with a particular emphasis. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0175] The foregoing are only exemplary embodiments of the present invention, and thus cannot limit the scope of the present invention. That is, any equivalent changes and modifications made in accordance with the teachings of the present invention still fall within the scope covered by the present invention. After considering the specification and practicing the disclosure herein, those skilled in the art will readily conceive of other embodiments of the present invention. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common general knowledge or conventional technical means in the technical field not recorded in the present invention. The specification and examples are only regarded as exemplary, and the scope and spirit of the present invention are defined by the claims.

Claims

1. A method for reducing the order of the grid-connected converter model based on the optimal Hankel norm approximation, characterized in that Based on the full-order model, including S1 current-loop reduced-order processing, S2 voltage-loop Hankel approximation reduced-order, and S3 constructing a ninth-order model: The S1 current-loop reduced-order processing includes: Performing dq decoupling on the mathematical model of the current-loop control loop in the full-order model, and eliminating the cross-coupling terms through feedforward compensation; Set the inverter proportionality coefficient , and simplify the closed-loop transfer function of the current loop; Adjusting the PI controller parameters to approximately cancel the zeros and poles, so that the current inner-loop control is equivalent to a unit proportional link; The S2 voltage-loop Hankel approximation reduced-order includes: Based on the unit proportional simplification result obtained in S1, performing dq decoupling on the voltage-loop control loop in the full-order model; Convert the second-order transfer function of the voltage loop into a state-space model, solve and decompose it, and retain the states corresponding to the dominant Hankel singular values Truncate the states corresponding to the secondary singular values to obtain a first-order approximation link for the outer voltage loop; The S3 constructing a ninth-order model includes: Based on the power measurement link in the full-order model and set the cut-off frequency Filter out high-frequency components to obtain a power measurement filtering link; Retaining the dq-axis coupling characteristics of the line resistance and inductance link in the full-order model; Combining the current inner-loop unit proportional link obtained in S1, the voltage outer-loop first-order approximation link obtained in S2, the power measurement filtering link, and the line resistance and inductance link to obtain a ninth-order reduced-order model; The expression of the ninth-order reduced-order model is ， Wherein, is the inertia of the virtual synchronous machine, , are the active and reactive droop coefficients respectively, , , , are the set values of angular velocity, active power, reactive power, d axis voltage respectively, , are the measured active and reactive powers respectively, , are the dq-axis components of the line current respectively, is the system power angle, and is the system angular frequency, , are the line inductance and resistance respectively, , are the dq-axis components of the grid voltage respectively, is the time constant of the direct-axis voltage in the control loop of the grid-forming converter, is the filter cut-off frequency, , , are matrix constants, , are intermediate variables, and are the dq-axis components of the filter capacitor voltage respectively, and are the dq-axis components of the filter capacitor voltage reference value respectively.

2. The method for reducing the order of the network-forming converter model based on the optimal Hankel norm approximation according to claim 1, wherein: The proportionality coefficient of the inverter has a value of 1.

3. The method for reducing the order of the network-forming converter model based on the optimal Hankel norm approximation according to claim 2, wherein: The expression of the current inner-loop unit proportional link is ， Wherein, and are the integral parameter and the proportional parameter of the current PI control respectively, and are the filter inductor and resistor respectively, and s is the complex variable of the Laplace transform.

4. The method for reducing the order of the network-forming converter model based on the optimal Hankel norm approximation according to claim 3, wherein: The second-order transfer function formula of the voltage loop is ， In the formula, and are the integral parameter and the proportional parameter of the voltage loop PI control respectively, is the filter capacitor.

5. The method for reducing the order of the network-forming converter model based on the optimal Hankel norm approximation according to claim 4, wherein: The state-space model formula is ， In the formula, , , , .

6. The method for reducing the order of the network-forming converter model based on the optimal Hankel norm approximation according to claim 5, wherein: The expression of the voltage outer-loop first-order approximation link is ， Wherein, , , are matrix constants, , are intermediate variables, , are respectively , derivatives, and are respectively the dq-axis components of the filter capacitor voltage, and are respectively the dq-axis components of the filter capacitor voltage reference value.

7. A grid-forming converter model reduction system based on optimal Hankel norm approximation, characterized in that, For implementing the method for reducing the order of the network-forming converter model according to any one of claims 1 to 6.

8. A computer device, the computer device comprising a memory, a processor, and a computer program, characterized in that, When the computer program is executed by a processor, it implements the method for reducing the order of the network-forming converter model according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method for reducing the order of the network-forming converter model according to any one of claims 1 to 6.

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