Verification method and device and electronic equipment

Abstract

The disclosure provides a verification method, comprising: acquiring a test information sequence for a circuit module and result information generated by the circuit module based on the test information sequence, the test information representing to-be-processed data input to the circuit module; inputting the test information sequence into the recurrent neural network model to obtain a model output result; and verifying the result information of the circuit module according to the model output result. The invention further provides a verification device and electronic equipment.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic circuit technologies, and particularly to a verification method, apparatus, and electronic device. Background Art

[0002] When verifying each module in a VIVO (Video In Video Out) system, a reference model is usually used to predict the ideal output parameters of the module, and the actual output of the module is verified and tested. With the change of the circuit module design specifications, the reference model also needs to be updated and maintained accordingly. Especially in an environment where circuit modules are frequently iteratively updated, this will result in a large amount of repetitive work in model maintenance and poor applicability of the code among different protocols. Summary of the Invention

[0003] In view of this, the present disclosure provides a verification method, apparatus, and electronic device.

[0004] One aspect of the present disclosure provides a verification method, including: obtaining a test information sequence for a circuit module and result information generated by the circuit module based on the test information sequence, where the test information characterizes the data to be processed input to the circuit module; inputting the test information sequence into a recurrent neural network model to obtain a model output result; and verifying the result information of the circuit module according to the model output result.

[0005] According to an embodiment of the present disclosure, the test information sequence includes a plurality of test information arranged in time sequence, and the test information sequence is generated based on input parameters and configuration parameters of the circuit module, where the configuration parameters include at least one of data channel information, working mode information, pixel format information, and clock information for the circuit module.

[0006] According to an embodiment of the present disclosure, the recurrent neural network model includes an input layer, a hidden layer, and an output layer connected in sequence; the test information sequence includes N pieces of test information, where N is an integer greater than 1; inputting the test information sequence into the recurrent neural network model to obtain a model output result includes: inputting the nth test information into the input layer to obtain the nth input layer information, where n = 2,..., N; inputting the nth input layer information and the (n - 1)th intermediate result into the hidden layer to obtain the nth intermediate result; and inputting the nth intermediate result into the output layer to obtain the nth output information; where the model output result is determined according to the N pieces of output information.

[0007] According to an embodiment of the present disclosure, inputting the nth test information into the input layer to obtain the nth input layer information includes: processing the nth test information using a first matrix to obtain a first product; inputting the nth input layer information and the (n - 1)th intermediate result into the hidden layer to obtain the nth intermediate result, including: processing the (n - 1)th intermediate result using a second matrix to obtain a second product; and determining the nth intermediate result according to the first product, the second product, and a preset bias parameter.

[0008] According to an embodiment of the present disclosure, inputting the nth intermediate result into the output layer to obtain the nth output information includes: processing the nth intermediate result using a third matrix to obtain the nth output information.

[0009] According to an embodiment of the present disclosure, verifying the result information of the circuit module according to the model output result includes: in response to the result information of the circuit module matching the model output result, determining that the circuit module passes the verification test; in response to the result information of the circuit module not matching the model output result, determining that the circuit module fails the verification test.

[0010] Another aspect of the present disclosure also provides a verification device, including: an acquisition module, configured to acquire a test information sequence for a circuit module and result information generated by the circuit module based on the test information sequence, where the test information represents data to be processed input to the circuit module; an input module, configured to input the test information sequence into a recurrent neural network model to obtain a model output result; and a verification module, configured to verify the result information of the circuit module according to the model output result.

[0011] Another aspect of the present disclosure provides an electronic device, including: one or more processors; a storage device, configured to store one or more programs, where when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the above method.

[0012] Another aspect of the present disclosure also provides a computer-readable storage medium, on which executable instructions are stored, and when the instructions are executed by a processor, the processor is caused to execute the above method.

[0013] Another aspect of the present disclosure also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0014] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. Description of the Drawings

[0015] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent. In the drawings:

[0016] Figure 1 It is a schematic diagram of an exemplary system architecture to which the verification method and apparatus according to an embodiment of the present disclosure can be applied;

[0017] Figure 2 It schematically shows a flowchart of the verification method according to an embodiment of the present disclosure;

[0018] Figure 3 It schematically shows a schematic diagram of the verification method according to an embodiment of the present disclosure;

[0019] Figure 4 It schematically shows a schematic diagram of the structure of a recurrent neural network according to an embodiment of the present disclosure;

[0020] Figure 5 It schematically shows a flowchart of model training according to an embodiment of the present disclosure;

[0021] Figure 6 It schematically shows a structural block diagram of the verification apparatus according to an embodiment of the present disclosure; and

[0022] Figure 7 It schematically shows a schematic block diagram of an electronic device that can be used to implement the verification method according to an embodiment of the present disclosure. Detailed Embodiments

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, descriptions of well-known functions and structures are omitted in the following description for clarity and conciseness.

[0024] In the technical solution of the present disclosure, the processing of the data involved (such as including but not limited to user personal information), such as collection, storage, use, processing, transmission, provision, disclosure, and application, all comply with the provisions of relevant laws and regulations, take necessary confidentiality measures, and do not violate public order and good customs.

[0025] In the UVM (Universal Verification Methodology) platform, the reference model is a component used to predict the ideal output result of a circuit module. Generally, the stimuli of the circuit module to be tested need to be input into the reference model, and the output of the reference model is compared with the output of the circuit module itself to achieve the verification of the circuit module. The reference model can be implemented in languages such as SystemVerilog, C, and C++.

[0026] During the development process of the reference model, the algorithm or logic of the circuit module needs to be described in detail, so the complexity of the reference model is usually high. When developing the reference model using traditional methods, whether using SystemVerilog or C++, a large amount of time and resources are required in the code development stage.

[0027] Based on this, the present disclosure proposes a verification method. By using a trained recurrent neural network model to replace the reference model to achieve the effect of predicting the ideal output of the circuit module, it can reduce the time and cost required for developing reference models based on different chips and different protocols, and greatly improve the verification efficiency of the circuit module.

[0028] Figure 1 It is a schematic diagram of an exemplary system architecture to which the verification method and apparatus according to an embodiment of the present disclosure can be applied. It should be noted that, Figure 1 The illustration is only an example of the system architecture to which the embodiments of the present disclosure can be applied, to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0029] As Figure 1 shown, the system architecture 100 according to this embodiment may include terminal devices 101, 102, 103, a network 104, and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired and / or wireless communication links, etc.

[0030] Users can use the terminal devices 101, 102, 103 to interact with the server 105 through the network 104 to receive or send messages, etc. The terminal devices 101, 102, 103 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, and desktop computers, etc.

[0031] The server 105 may be a verification platform or server equipped with a reference model such as a recurrent neural network model. For example, it verifies the output results of the circuit modules tested by the user using the terminal devices 101, 102, and 103 (only for illustration).

[0032] It should be noted that the verification method provided by the embodiments of the present disclosure can generally be executed by the server 105. Correspondingly, the verification device provided by the embodiments of the present disclosure can generally be set in the server 105. The verification method provided by the embodiments of the present disclosure can also be executed by a server or a server cluster different from the server 105 and capable of communicating with the terminal devices 101, 102, 103 and / or the server 105. Correspondingly, the verification device provided by the embodiments of the present disclosure can also be set in a server or a server cluster different from the server 105 and capable of communicating with the terminal devices 101, 102, 103 and / or the server 105.

[0033] Figure 2 A flowchart of the verification method according to an embodiment of the present disclosure is schematically shown.

[0034] As Figure 2 shown, the verification method of this embodiment includes operation S210 - operation S230.

[0035] In operation S210, a test information sequence for a circuit module and result information generated by the circuit module based on the test information sequence are obtained, where the test information characterizes the data to be processed input to the circuit module.

[0036] In the embodiments of the present disclosure, the circuit module may refer to a device or component that processes input data based on a specified interface protocol. The test information sequence refers to time-series data input to the circuit module. For example, if the test information sequence can be represented in the form of a pulse signal or a level signal, then the test information sequence refers to the sequence of signal values represented by the pulse signal, or the binary data sequence represented by the level signal. The result information refers to the image information output after the circuit module processes the input test information sequence.

[0037] For example, the circuit module may be a CSI (Camera Serial Interface) module. The CSI module can generate processed image pixel data based on a time signal and a data signal.

[0038] In operation S220, the test information sequence is input into the recurrent neural network model to obtain a model output result.

[0039] In an embodiment of the present disclosure, a recurrent neural network introduces a recurrent structure in the time dimension. The intermediate result at each time step depends not only on the current input but also on the intermediate result at the previous time step. The recurrent neural network model can capture the high-dimensional features of the test information sequence in the time dimension. The model output result refers to the output result generated by the recurrent neural network model based on the test time series.

[0040] In operation S230, the result information of the circuit module is verified according to the model output result.

[0041] In an embodiment of the present disclosure, the model output result can be sent to a scoreboard. By comparing the model output result with the result information of the circuit module, it is determined whether the circuit module passes the verification test.

[0042] According to an embodiment of the present disclosure, verifying the result information of the circuit module according to the model output result includes: determining that the circuit module passes the verification test in response to the result information of the circuit module matching the model output result; determining that the circuit module fails the verification test in response to the result information of the circuit module not matching the model output result.

[0043] For example, if the image pixel value generated by the circuit module based on the test sequence information is 1 and the pixel value in the model output result is also 1, it indicates that the circuit module passes the verification test. If the image pixel value generated by the circuit module based on the test sequence information is 1 and the pixel value in the model output result is 5, it indicates that the circuit module fails the verification test.

[0044] According to an embodiment of the present disclosure, by using the trained recurrent neural network model to replace the reference model in the traditional UVM verification platform, the high-dimensional features hidden in the time steps can be mined. The recurrent neural network is suitable for establishing reference models for various input-output protocols, reducing the time and cost of developing reference models between different chips and different protocols, and greatly improving the efficiency of chip verification.

[0045] Figure 3 A schematic diagram of a verification method according to an embodiment of the present disclosure is schematically shown.

[0046] As Figure 3 shown, the recurrent neural network model 310 can generate corresponding result information 304 according to the input test information sequence 303. Among them, the test information sequence 303 may include the information sequences transmitted by the clock channel and at least one data channel.

[0047] For example, the recurrent neural network model can be used to predict the output of the CSI module. According to the CSI protocol, the signal of each channel includes two differential signals P and N.

[0048] According to an embodiment of the present disclosure, the test information sequence 303 includes a plurality of test information arranged in sequence in time. The test information sequence is generated based on the input parameter 301 and the configuration parameter 302 of the circuit module. The configuration parameter 302 may include at least one of data channel information, operating mode information, pixel format information, and clock information for the circuit module.

[0049] For example, when the circuit module is a CSI module, according to the CSI protocol, the signal of each channel includes differential signals P and N. As Figure 3 shown, according to the preset data channel information and clock information, the test information sequence can be obtained to include a clock signal and two channel signals. Among them, the clock signal includes a clock signal P and a clock signal N; the channel signals include a channel signal 0P, a channel signal 0N, a channel signal 1P, and a channel signal 1N.

[0050] Figure 4 Schematically shows a schematic structural diagram of a recurrent neural network according to an embodiment of the present disclosure.

[0051] As Figure 4 shown, according to an embodiment of the present disclosure, the recurrent neural network model 400 includes an input layer 410, a hidden layer 420, and an output layer 430 connected in sequence; the test information sequence includes N test information, where N is an integer greater than 1.

[0052] For example, the test information sequence can be represented as N sets of signal values corresponding to N moments, and each set of signal values includes the level values or signal values of the signals transmitted within multiple channels at the same moment.

[0053] Inputting the test information sequence into the recurrent neural network model 400, the obtained model output result includes: inputting the nth test information into the input layer 410 to obtain the nth input layer information x n , n = 2,..., N; inputting the nth input layer information x n and the (n - 1)th intermediate result s n-1 into the hidden layer 420 to obtain the nth intermediate result s n ; and inputting the nth intermediate result s n into the output layer 430 to obtain the nth output information; among them, the model output result is determined according to the N output information.

[0054] According to an embodiment of the present disclosure, inputting the nth test information into the input layer to obtain the nth input layer information includes: processing the nth test information using a first matrix to obtain a first product; inputting the nth input layer information and the (n - 1)th intermediate result into the hidden layer to obtain the nth intermediate result includes: processing the (n - 1)th intermediate result using a second matrix to obtain a second product; and determining the nth intermediate result according to the first product, the second product, and a preset bias parameter.

[0055] In an embodiment of the present disclosure, the recurrent neural network model includes three parameter matrices. The first matrix is the parameter matrix from the input layer 410 to the hidden layer 420. The second matrix is the parameter matrix from the hidden layer at the previous moment to the hidden layer at the current moment. The intermediate result s at the nth moment n can be obtained through the following formula:

[0056]

[0057] where U is the first matrix, W is the second matrix, and x n is the information of the nth input layer, and s n-1 is the (n - 1)th intermediate result, and b s is a preset bias parameter, and f is an activation function.

[0058] According to an embodiment of the present disclosure, inputting the nth intermediate result into the output layer to obtain the nth output information includes: processing the nth intermediate result with a third matrix to obtain the nth output information. The third matrix is the parameter matrix from the hidden layer 420 to the output layer 430.

[0059] In an embodiment of the present disclosure, the nth output information o n can be obtained through the following formula:

[0060]

[0061] where g is an activation function, V is the third matrix, and b o is a bias parameter.

[0062] According to an embodiment of the present disclosure, by using the trained recurrent neural network model to replace the reference model to achieve the effect of predicting the ideal output of the prediction circuit module, the method of optimizing key hyperparameters such as increasing the number of neurons and reducing the learning rate can be used, and the reference model established based on the recurrent neural network can cover all test cases.

[0063] Figure 5 Schematically shows a flowchart of model training according to an embodiment of the present disclosure.

[0064] As Figure 5 shown, the model training of this embodiment includes operation S501 - operation S504.

[0065] In operation S501, the input and output data of the circuit module are obtained, and a data set is obtained through processing operations such as cleaning, screening, and feature marking.

[0066] Among them, the input data of the circuit module may include: input parameters, data channel information, working mode information, pixel format information, clock information, etc. The output data may include encoded pixel data. The input data and the output data are matched to form data pairs, so as to obtain a data set composed of data pairs. The data set is divided into a training set, a validation set, and a test set according to a certain ratio, and the model is trained.

[0067] In operation S502, the recurrent neural network model is trained using the training set in the data set.

[0068] In operation S503, the parameters of the recurrent neural network model are adjusted using the validation set, and it is monitored whether overfitting occurs.

[0069] In operation S504, the trained recurrent neural network model is tested using the test set to verify the generalization ability of the model.

[0070] According to an embodiment of the present disclosure, after the recurrent neural network model for the CSI module meets the robustness requirements, the input and output data of the circuit module based on other protocols can also be used to form a data set, and different protocols of the circuit module are used as labels to further train the recurrent neural network model until the model can match multiple protocols, improving the generalization of the recurrent neural network model.

[0071] Figure 6 A structural block diagram of a verification device according to an embodiment of the present disclosure is schematically shown.

[0072] As Figure 6 shown, the verification device 600 of this embodiment includes an acquisition module 610, an input module 620, and a verification module 630.

[0073] The acquisition module 610 is configured to acquire a test information sequence for the circuit module and result information generated by the circuit module based on the test information sequence, where the test information represents the data to be processed input to the circuit module. In one embodiment, the acquisition module 610 may be configured to perform the operation S210 described above, which will not be elaborated here.

[0074] The input module 620 is configured to input the test information sequence into the recurrent neural network model to obtain a model output result. In one embodiment, the input module 620 may be configured to perform the operation S220 described above, which will not be elaborated here.

[0075] The verification module 630 is configured to determine the importance of the target node based on the path information and time information of the target node. In one embodiment, the verification module 630 may be configured to perform the operation S230 described above, which will not be elaborated here.

[0076] According to an embodiment of the present disclosure, the test information sequence includes a plurality of test information arranged in sequence in time. The test information sequence is generated based on input parameters and configuration parameters of the circuit module. The configuration parameters include at least one of data channel information, working mode information, pixel format information, and clock information for the circuit module.

[0077] According to an embodiment of the present disclosure, the recurrent neural network model includes an input layer, a hidden layer, and an output layer connected in sequence; the test information sequence includes N test information, where N is an integer greater than 1; the input module 620 includes a first input sub-module, a second input sub-module, and an output sub-module. The first input sub-module is configured to input the nth test information into the input layer to obtain the nth input layer information, where n = 2, ……, N. The second input sub-module is configured to input the nth input layer information and the (n - 1)th intermediate result into the hidden layer to obtain the nth intermediate result. The output sub-module is configured to input the nth intermediate result into the output layer to obtain the nth output information; wherein, the model output result is determined based on the N output information.

[0078] According to an embodiment of the present disclosure, the first input sub-module includes a first product unit. The first product unit is configured to process the nth test information using a first matrix to obtain a first product. The second input sub-module includes a second product unit and a determination unit. The second product unit is configured to process the (n - 1)th intermediate result using a second matrix to obtain a second product. The determination unit is configured to determine the nth intermediate result based on the first product, the second product, and a preset bias parameter.

[0079] According to an embodiment of the present disclosure, the output sub-module includes an output unit configured to process the nth intermediate result using a third matrix to obtain the nth output information.

[0080] According to an embodiment of the present disclosure, the verification module includes a first verification sub-module and a second verification sub-module. The first verification sub-module is configured to determine that the circuit module passes the verification test in response to the result information of the circuit module matching the model output result. The second verification sub-module is configured to determine that the circuit module fails the verification test in response to the result information of the circuit module not matching the model output result.

[0081] Figure 7 A schematic block diagram of an electronic device that can be used to implement the method according to an embodiment of the present disclosure is schematically shown.

[0082] As Figure 7As shown, the electronic device 700 according to an embodiment of the present disclosure includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage section 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (such as a CPU), an instruction set processor, and / or a related chipset, and / or a dedicated microprocessor (such as an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include on-board memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0083] In the RAM 703, various programs and data required for the operation of the electronic device 700 are stored. The processor 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. The processor 701 performs various operations of the method flow according to an embodiment of the present disclosure by executing the programs in the ROM 702 and / or the RAM 703. It should be noted that the program may also be stored in one or more memories other than the ROM 702 and the RAM 703. The processor 701 may also implement the method provided by the embodiments of the present disclosure by executing the programs stored in the one or more memories.

[0084] According to an embodiment of the present disclosure, the electronic device 700 may further include an input / output (I / O) interface 705, and the input / output (I / O) interface 705 is also connected to the bus 704. The electronic device 700 may further include one or more of the following components connected to the I / O interface 705: an input section 706 including a keyboard, a mouse, etc.; an output section 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, a modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A driver 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the driver 710 as needed so that a computer program read from it can be installed into the storage section 708 as needed.

[0085] The present disclosure also provides a computer-readable storage medium, which may be included in the device / device / system described in the above embodiments; or may exist separately and not be assembled into the device / device / system. The above computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the method according to an embodiment of the present disclosure is implemented.

[0086] According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present disclosure, the computer-readable storage medium may include one or more memories other than the above-described ROM 702 and / or RAM 703 and / or ROM 702 and RAM 703.

[0087] An embodiment of the present disclosure further includes a computer program product, which includes a computer program that contains program code for executing the method shown in the flowchart. When the computer program product runs in a computer system, the program code is used to enable the computer system to implement the method provided by the embodiment of the present disclosure.

[0088] When the computer program is executed by the processor 701, the above functions defined in the system / apparatus of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described system, apparatus, module, unit, etc. may be implemented by computer program modules.

[0089] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices and magnetic storage devices. In another embodiment, the computer program may also be transmitted and distributed in the form of a signal on a network medium, and be downloaded and installed through the communication part 709, and / or be installed from the removable medium 711. The program code included in the computer program may be transmitted by any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0090] In such an embodiment, the computer program may be downloaded and installed from the network through the communication part 709, and / or be installed from the removable medium 711. When the computer program is executed by the processor 701, the above functions defined in the system of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described system, device, apparatus, module, unit, etc. may be implemented by computer program modules.

[0091] It should be noted that in the technical solutions of the present disclosure, the collection, storage, use, processing, transmission, provision, disclosure, application and other processing of the user's personal information comply with the provisions of relevant laws and regulations, necessary confidentiality measures are taken, and public order and good customs are not violated. In the technical solutions of the present disclosure, the authorization or consent of the user is obtained before obtaining or collecting the user's personal information.

[0092] According to the embodiments of the present disclosure, the program code for executing the computer programs provided by the embodiments of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level procedures and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages include, but are not limited to, such as Java, C++, Python, "C" language or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, by using an Internet service provider to connect through the Internet).

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above-mentioned module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0094] Those skilled in the art can understand that the features described in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0095] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A verification method, comprising: Acquire a test information sequence for a circuit module and result information generated by the circuit module based on the test information sequence, wherein the test information represents data to be processed input to the circuit module; Inputting the test information sequence into a recurrent neural network model to obtain a model output result; The result information of the circuit module is verified according to the output result of the model.

2. The method according to claim 1, wherein: The test information sequence includes multiple test information arranged in sequence in time, and the test information sequence is generated based on input parameters and configuration parameters of the circuit module, and the configuration parameters include at least one of data channel information, working mode information, pixel format information and clock information for the circuit module.

3. The method according to claim 1, wherein: The recurrent neural network model includes an input layer, a hidden layer and an output layer connected in sequence; the test information sequence includes N test information, where N is an integer greater than 1; the test information sequence is input into the recurrent neural network model to obtain a model output result including: Inputting the nth test information into the input layer to obtain the nth input layer information, where n=2, ..., N; Inputting the nth input layer information and the n-1th intermediate result into the hidden layer to obtain the nth intermediate result; and Inputting the nth intermediate result into the output layer to obtain the nth output information; Wherein, the model output result is determined according to N output information.

4. The method according to claim 3, wherein: The step of inputting the nth test information into the input layer to obtain the nth input layer information comprises: Processing the nth test information using the first matrix to obtain a first product; The step of inputting the nth input layer information and the n-1th intermediate result into the hidden layer to obtain the nth intermediate result comprises: Processing the n-1th intermediate result using a second matrix to obtain a second product; and An nth intermediate result is determined according to the first product, the second product and a preset bias parameter.

5. The method according to claim 3 or 4, wherein: The inputting the nth intermediate result into the output layer to obtain the nth output information comprises: The nth intermediate result is processed using a third matrix to obtain the nth output information.

6. The method according to claim 1, wherein: Verifying the result information of the circuit module according to the model output result includes: In response to the result information of the circuit module matching the model output result, determining that the circuit module passes the verification test; In response to the result information of the circuit module not matching the model output result, it is determined that the circuit module has failed the verification test.

7. A verification device, comprising: An acquisition module, used for acquiring a test information sequence for a circuit module and result information generated by the circuit module based on the test information sequence, wherein the test information represents data to be processed input to the circuit module; An input module, used to input the test information sequence into the recurrent neural network model to obtain a model output result; A verification module is used to verify the result information of the circuit module according to the model output result.

8. An electronic device comprising: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to perform the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, wherein the computer program is stored on at least one of a readable storage medium and an electronic device, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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