Three-level power module graphical automatic layout design method considering mutual inductance effect

Abstract

The invention discloses a three-level power module graphical automatic layout design method considering a mutual inductance effect. The method comprises the following steps: acquiring an input parameter for designing the layout of the three-level power module; determining the type and number of units on the three-level circuit topology according to the circuit topology netlist and the geometric structure diagram of the required functional units; connecting communication paths between corresponding nodes of each unit on the three-level circuit topology by using the path planning model to obtain a grid connection diagram of the power module; according to the obtained grid connection diagram of the power module, scanning to obtain a size definition diagram, and determining the size of the layout; according to an inductance evaluation method in the target evaluation model, determining parasitic inductance of the layout commutation loop; and obtaining an optimal layout scheme of the three-level power module according to multi-objective optimization processing. In the process, a pre-defined manual layout template does not need to be input, and automatic layout design of the power module is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of power module layout design, and particularly relates to a graphical automatic layout design method for a three-level power module considering mutual inductance effects. Background Art

[0002] Silicon carbide devices are renowned for their excellent performance, characterized by fast switching speeds, minimal losses, superior thermal conductivity, and high-temperature tolerance. In the field of power module design, the three-level topology can effectively reduce the voltage stress on switching devices while reducing the harmonic content and electromagnetic interference (EMI) in the output, and has become a key trend. Combined with the inherently low switching losses of the devices, three-level modules can improve the reliability and power density of the system, especially at high frequencies. As the structure of three-level modules becomes increasingly complex, the pursuit of low parasitic inductance in layout design has become an important focus of research and development work. Larger parasitic inductance not only causes current transmission delay but also exacerbates switching losses, thereby undermining the overall efficiency of the system. With the increase in the number of parallel chips, it is difficult to achieve such a significant reduction in loop inductance because traditional layout designs are usually limited by the engineering expertise of designers. Therefore, automated layout design methods have received increasing research attention. However, three-level modules have complex structures and current paths. The complexity of these module current paths greatly increases the difficulty of accurately calculating the parasitic inductance of the loop and further poses a major challenge to the efficiency of automatic design. Summary of the Invention

[0003] Considering the complex electrical connections and numerous limitations within three-level modules, directly designing an overall automatic layout is challenging because it is difficult to simultaneously consider key factors such as parasitic inductance, mutual inductance, and floor area. The present invention proposes a graphical automatic layout design method for three-level modules; the layout design process is divided into the following three progressive stages. Stage one: initial layout generation. The relative positions and connection relationships of layout component units are described using a grid connection diagram. Combining with a path planning model, a preferred layout can be generated without manual template input. Stage two: candidate layout screening. Based on the grid connection diagram of stage one, a size definition diagram is used to describe the layout size. Through an efficient and accurate inductance calculation method considering mutual inductance effects in the target evaluation model, the parasitic inductance of the commutation loop is calculated. Stage three: layout size optimization. Based on the selected candidate layout, the multi-objective optimization algorithm NSGA-II is used to iteratively optimize the layout size parameters, and a compact low-inductance layout can be generated to achieve automatic layout design. The technical solution of the present invention is as follows: Obtain input parameters for designing the layout of a three-level power module, where the input parameters include information on the circuit topology required for the layout design of the power module; According to the information of the circuit topology and the geometric structure diagrams of the functional units required for the layout saved in advance, determine the types of layout units on the circuit topology and the quantity of each type of layout unit. Specifically, it includes: generating a netlist of the three-level circuit topology according to the information of the three-level circuit topology; processing the input netlist of the three-level circuit topology through the geometric structure diagrams of the functional units required for the layout saved in advance, so as to identify each layout unit in the netlist of the circuit topology; calculating how many types of layout units there are on the netlist of the circuit topology and the quantity of each type of layout unit according to the structure diagrams of each type of layout unit saved in advance, providing a basis for generating a grid connection diagram subsequently. The types of the layout units include switch units, diode units, power terminal units, and copper layer line units. In the layout of the three-level module, there are switch units, diode units, and power terminal units. Build a commutation path according to the switch units, diode units, and power terminal units. By constructing each commutation network between the nodes corresponding to the switch units, diode units, and terminal units on the netlist of the circuit topology, then select the shortest path of each commutation network through the path planning model, and connect the optimal commutation paths of each commutation network. Finally, establish the copper layer line nodes and interconnection edges of the commutation path to obtain a grid connection diagram. The path planning model is a combination of the depth-first search algorithm and the integer programming algorithm. In the process of generating the connection graph, in the commutation network between two set nodes, there are generally multiple circulation paths. The path planning model is used to select the circulation path with the shortest path in the commutation network, so that the structure of the entire connection graph of the designed layout scheme is simple, and the manufacturing cost can be reduced. Specifically, it includes: determining at least one commutation network on the netlist of the three-level circuit topology, and at least one connected path and the length and the number of turning points of each connected path in each commutation network. The commutation network refers to the network path between two nodes on the netlist of the circuit topology. The two nodes are one of the two nodes of the switching unit and one of the two nodes of the diode unit, or the two nodes of two different switching units, or the two nodes of one switching unit and one power terminal unit, or the two nodes of one diode unit and one power terminal unit; inputting at least one connected path and the length and the number of turning points of each connected path in each commutation network into the integer programming model to obtain the target optimal path in each commutation network. The optimal path is the path that meets the set length threshold in each commutation network; placing copper layer line nodes on each network node of the target optimal path in each commutation network, and establishing interconnection edges on the target optimal path in each commutation network. The copper layer line nodes are the nodes placed by the copper layer line unit in the grid graph; outputting the non-empty nodes and edges in the grid connection structure to obtain the grid connection graph of the power module. The input parameters further include the design size parameters of the basic layout units; the method further includes: determining the original minimum size of each type of basic layout unit according to the design size parameters; scanning the layout grid connection graph according to the original minimum size of each type of basic layout unit to obtain the size definition graph of the connection graph. The size definition graph is used to describe the sizes of the respective layout units and the sizes of different grid connection graphs when calculating the commutation loop inductance according to the connection graph. Scanning the grid connection graph to obtain the size definition graph of the connection structure specifically includes: scanning the grid connection graph in the horizontal direction to obtain the size definition graph of the connection graph in the horizontal direction; and scanning the grid connection graph in the vertical direction to obtain the size definition graph of the connection graph in the vertical direction. By constructing the size definition graph from two mutually perpendicular directions, the sizes of the layout units and the overall layout can be represented, and the generated template has high quality and no design rule detection is required in the subsequent processing link. The size definition graph includes nodes and edges. The nodes are the grid lines obtained by scanning the grid connection graph, and the edges are the distances between the grid lines, which are used to represent the sizes of the respective layout units. The method further includes: defining a graph according to the grid connection graph and the dimensions of the connection graph, and using a target evaluation model to detect the parasitic inductance of the commutation loop of the geometric layout corresponding to the grid connection graph of the power module and the layout area of the geometric layout of the power module; the parasitic inductance is the self-inductance of the path constituting the commutation loop and the mutual inductance generated between paths. The number and arrangement positions of each layout unit and the position of the commutation path can be determined through the grid connection graph; the dimensions of each layout unit can be determined through the dimension definition graph, and then the dimensions of the commutation path can be determined. The target evaluation model includes detecting the parasitic inductance of the commutation loop in the grid connection graph of the three-level power module and the layout area of the geometric structure layout corresponding to the grid connection graph, and outputting a layout scheme, specifically including: a parasitic inductance evaluation method based on the path segmentation method, segmenting the commutation loop path in the grid connection graph at path turning points and bonding wire connections, respectively calculating the self-inductance of each path segment and the mutual inductance generated between all path segments in the loop, and superimposing them as the loop parasitic inductance in the commutation loop. According to the length parameters of the edges in the dimension definition graph corresponding to the grid connection graph, the weights of the edges in the horizontal direction are superimposed to obtain the total length of the layout, and the weights of the edges in the vertical direction are superimposed to obtain the total width of the layout, so as to obtain the layout area of the geometric structure layout corresponding to the grid connection graph of the three-level power module. The method further includes: inputting the grid connection graph and the dimension definition graph of the layout scheme into an optimization processing model, and outputting a target geometric layout scheme, where the target geometric layout scheme is a geometric layout scheme of the three-level power module that meets the set conditions, and the set conditions are to reduce the parasitic inductance value of the commutation loop in the three-level power module and the overall layout area of the geometric layout reaches the Pareto optimization frontier. The multi-objective optimization processing model specifically includes: taking the minimum parasitic inductance of the commutation loop and the minimum overall layout area of the geometric layout as optimization objectives, the grid connection graph and the dimension definition graph of the three-level power module layout can be input into the optimization processing model constructed by the multi-objective optimization algorithm NSGA-II to search for optimal dimension parameters, so that the two parameters of the minimum parasitic inductance of the commutation loop and the minimum overall layout area of the geometric layout reach the Pareto optimization frontier, serving as the optimal grid connection graph, and then outputting the geometric layout of this structure to obtain the best geometric layout of the power module. Description of the Drawings

[0004] Figure 1 It is a framework schematic diagram of a multi-stage and multi-objective automatic layout design method for a three-level module based on a graphic connection graph technology provided in an embodiment of the present application. Figure 2 It is a schematic diagram of the T-type three-level circuit topology and its network representation in an embodiment of the present invention; Figure 3 Geometric structure diagrams, node representation schematic diagrams, and node attribute definitions of each layout unit provided in the embodiments of the present invention; Figure 4 Flowchart for generating a connection diagram of a T-type three-level power module in the embodiments of the present invention; Figure 5 Schematic diagram of a hierarchical integer programming model for connected paths in a commutation network in the embodiments of the present invention; Figure 6(a) is a layout connection diagram of a T-type three-level power module provided in the embodiments of the present invention; Figure 6(b) is a geometric structure layout constructed based on the connection diagram shown in Figure 6(a) in the embodiments of the present invention; Figure 6(c) is a dimension definition diagram in the horizontal direction and a dimension definition diagram in the vertical direction obtained based on the connection diagram shown in Figure 6(a) in the embodiments of the present invention; Figure 7 Schematic diagram of a parasitic inductance evaluation method considering mutual inductance in the embodiments of the present invention; Figure 8 Corresponding geometric layouts constructed from 5 different layout connection diagrams provided in the embodiments of the present invention; Figure 9 Process flowchart for optimizing layout dimension parameters provided in the embodiments of the present invention; Figure 10 Schematic diagram of the results of each iteration and the Pareto front results provided in the embodiments of the present invention; Detailed implementation manners

[0005] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The present invention will be further described in detail and completely below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments described by combining the technical solutions in the embodiments of the present invention with the accompanying drawings are only illustrative descriptions of the present invention and are not used to limit the present invention. Figure 1 Schematic diagram of the framework of an automated layout design method for a three-level power module based on a graphical connection diagram, multi-stage, and multi-objective considering complex mutual inductance effects provided in the embodiments of the present application. As Figure 1 shown, this method is divided into three stages: initial layout generation, candidate layout screening, and layout dimension optimization. The specific processes of each stage are as follows: In the first stage, it is first necessary to obtain the input parameters for the layout design of the three-level power module, such as the configuration information of the power module, the constraint conditions of the design dimensions, etc. Exemplarily, the input parameters for the layout design of the power module can be, for example, Figure 2 the T-type three-level circuit topology netlist as shown and the parameters shown in Table 1, specifically: Table 1, Input parameters for the layout design of the T-type three-level power module Parameter Value Unit Number of switch chips 4 Number of diode chips 2 Size of switch chip 6.30×4.80 mm Size of diode chip 4.80×4.80 mm Thickness of copper layer 0.30 mm DBC etching 0.70 mm Soldering pitch 1.00 mm Diameter of bonding wire 0.38 mm Size of bonding area ≥1.00 mm Width of copper layer circuit ≥1.00 mm Size of power terminal ≥3.00×3.00 mm Among them, the circuit topology netlist required for the layout design of the power module, and the design dimension parameters include the size of the chip, the size of the diode, the size of the power terminal, the width of the copper layer line, the copper layer spacing, the copper layer thickness, the welding spacing, the bond wire size, and so on. The T-type three-level circuit topology is selected for the circuit topology required for the power module layout design. The number of chips is 4, the number of diodes is 2, the size of the chip is 6.3×4.8 mm, the size of the diode is 4.8×4.8 mm, the size of the terminal is greater than or equal to 3.0×3.0 mm, the width of the copper layer line is greater than or equal to 1.0 mm, the copper layer spacing is 0.7 mm, the copper layer thickness is 0.3 mm, the welding spacing is greater than or equal to 1.0 mm, and the size of the bonding area is greater than or equal to 1.0 mm. This application is only an example here and is not a limitation of this application. According to the information of the circuit topology required for the power module layout design, a netlist of the circuit topology is generated, and in combination with the geometric structure diagrams of each layout unit, the types of layout units existing on the netlist of the circuit topology and the number of each type of layout unit are determined. Among them, the circuit topology, also known as the graph of the circuit, is a set obtained by re-abstracting the circuit diagram and consisting only of branches and nodes, that is, the connection relationship between branches and nodes. In this application, such as Figure 2 the netlist of the T-type three-level circuit topology includes the name of the component, the number of the component, the port node numbers of the component, the connectivity information of the port nodes, etc. By processing the input netlist of the three-level circuit topology, each layout unit in the netlist of this circuit topology can be recognized; through Figure 3 the geometric structure diagrams of the functional units required for layout predefined in, the types of layout units on the netlist of the circuit topology and the number of each type of layout unit can be calculated. The node graph representing the layout unit is composed of nodes and edges and is used to generate a connection graph. The information of the layout units required in the layout design of the T-type three-level power module is specifically introduced below. Each type of layout unit exists in the minimum size, specifically: The geometric structure diagram of the switch unit includes one chip and three copper layers. Among them, the chip is arranged on one copper layer, and the chip is arranged according to the design conditions such as the minimum copper layer line width, the minimum copper layer spacing, and the minimum welding spacing. Through the interconnect structure on its top, the gate on the surface of the chip is connected to a copper layer with a bond wire, and the source on the surface of the chip is connected to a copper layer through a bond wire. And Figure 3Corresponding to the geometric structure diagram of the switch unit in , in the graph node representation of the switch unit, it includes two adjacent nodes and an edge. Among them, the two adjacent nodes indicate that the switch unit occupies two adjacent nodes in the circuit topology, and the edge between the nodes indicates the current flow path in the switch unit. The diode unit includes a chip and two copper layers. Among them, the diode chip is arranged on one copper layer and is connected to the other copper layer through bonding wires. Figure 3 Corresponding to the geometric structure diagram of the diode unit shown in , in the graph node representation of the diode unit, the diode unit includes two adjacent nodes and an interconnecting edge. Among them, the two adjacent nodes indicate that the diode unit occupies two adjacent nodes in the circuit topology, and the edge between the nodes indicates the current flow path in the diode unit. The power terminal unit includes a chip and a copper layer. Among them, the chip is composed of one or more power terminal elements, and there are power output terminals such as positive, negative, AC, neutral point, etc. on the power terminal elements. The output terminals on each terminal element are arranged in the middle position of a copper layer. Figure 3 Corresponding to the geometric structure diagram of the power terminal unit in , in the graph node representation of the power terminal unit, the terminal unit includes a node indicating that the terminal unit occupies one node in the circuit topology. The copper layer line unit is composed of a copper layer. Figure 3 Corresponding to the geometric structure diagram of the copper layer line unit in , in the graph node representation of the copper layer line unit, the copper layer line unit includes a node indicating that the copper layer line unit occupies one node in the circuit topology. In the embodiment of the present invention, when designing the layout scheme of the power module, after processing the input parameters, the geometric structure diagram, graph node representation, and node attributes of the layout units constituting the power module are obtained, providing a basis for subsequent construction of the connection graph and optimization of the size of the designed power module layout. The number of switch units determined according to the information in the input T-type three-level circuit topology netlist is 4. An orthogonal grid with a size not exceeding 8×8 is generated to represent the module layout. Then, the graph nodes of the switch unit, diode unit, and power terminal unit are randomly placed in the grid. Next, the loop connection path that satisfies the electrical connectivity of the circuit topology is found through the path planning model, and the nodes in the path are set as the nodes of the copper layer line unit. The electrical connection between the path nodes is set as an edge. Finally, the grid connection graph and its corresponding geometric layout template are output. As Figure 4 shown, the process of generating the grid connection graph of the T-type three-level power module through the path planning model is specifically implemented as follows: Step S401: Determine at least one commutation loop formed by the circuit topology, as well as at least one connected path of each commutation network in each commutation loop, and the length and number of turning points of each connected path. Here, the commutation network refers to the network path between two nodes on the netlist of the circuit topology. Specifically: The loops formed by the T-type three-level circuit topology shown in the figure are two loops from the positive pole to the neutral point and from the neutral point to the negative pole. Its netlist includes nodes Q1.1 and Q1.2 in switch unit Q1, nodes Q2.1 and Q2.2 in switch unit Q2, nodes Q3.1 and Q3.2 in switch unit Q3, nodes Q4.1 and Q4.2 in switch unit Q4, and nodes D2.1 and D2.2 in diode unit D2 anti-parallel to switch unit Q2, diode unit D3 anti-parallel to switch unit Q3, and nodes DC+, DC-, DC0, AC in four power terminal units. Each commutation network in the commutation loop from the positive pole to the neutral point is specifically the power terminal node DC+ and the switch node Q1.1, the switch node Q1.2 and the switch node Q3.1, the switch node Q3.2 and the diode node D2.2, and the diode node D2.1 and the power terminal node DC0. Each commutation network in the commutation loop from the neutral point to the negative pole is specifically the power terminal node DC0 and the switch node Q2.1, the switch node Q2.2 and the diode node D3.2, the diode node D3.1 and the switch node Q4.2, and the switch node Q4.1 and the power terminal node DC0. Step S402: For each commutation network in the commutation loop, find all its possible connected paths, which refers to the switch unit component nodes, diode unit component nodes, and power terminal unit component nodes at any grid position in the circuit topology netlist. Using the depth-first search algorithm, obtain all k connected paths between two nodes among all the nodes of the layout unit, as well as their path lengths and the number of turning points. The path length refers to the number of nodes in the path, and the turning point refers to the node where the direction changes in the path. Exemplarily, as shown in the figure, there are 3 connected paths in commutation network A, 3 connected paths in commutation network B, and 4 connected paths in commutation network C. Step S403: Construct a hierarchical integer programming model Before establishing the integer programming model, first define each connected path as an integer variable x k,net,loop , indicating whether path k is selected in the network net of the commutation loop loop, that is

[0006] Determine that the optimization objective is to minimize the total path length and the number of path turning points, that is

[0007] wherein l k : the total length of path k; P k : path the number of inflection points; w : weight coefficient. The constraint conditions for establishing the integer programming model are defined as: Unique path constraint: Only one path can be selected for each commutation network to ensure path independence.

[0008] Node exclusive constraint: Each grid node can be occupied by at most one path of a network to avoid path conflicts.

[0009] Then, by way of example, taking FIGS. (a) and (b) as examples, according to the integer variables, optimization objectives, constraint condition ① and constraint condition ②, an integer programming model is obtained. Step S404, input all possible connected paths in all commutation networks in each commutation loop and the length and number of inflection points of each connected path into the integer programming model to obtain the target commutation path in each network of each commutation loop. Among them, the target commutation path is the commutation path with the shortest path in each commutation network. Step S405, place copper layer line nodes on each network node of the target commutation path in the commutation networks in each loop, and establish edges between the target commutation path nodes in the networks belonging to two commutation loops. Among them, the copper layer line nodes are the nodes where the copper layer line units are arranged in the connection diagram. Step S406, output the layout grid connection diagram. The second stage is candidate layout screening. Based on the grid connection diagram in the first stage, the layout size is described by defining the size definition diagram and the overall layout area is calculated. Then, through the efficient and accurate inductance calculation method considering the mutual inductance effect in the target evaluation model, the parasitic inductance of the commutation loop is calculated. Specifically: According to the design size parameters, the original minimum size of each layout unit is determined, that is, the minimum sizes of the switch unit, diode unit, power terminal unit and copper layer line unit. The grid connection diagram is scanned in the horizontal and vertical directions to obtain the size definition diagram in the horizontal direction and the size definition diagram in the vertical direction respectively. In the size definition schematic diagram, the nodes represent grid lines, and the edges represent the length or width of the area between adjacent grid lines. According to the physical sizes of the nodes in each grid area, by assigning values to the edges in the size definition diagram, the size of the grid diagram can be determined, and these edge weights are used as the lower bounds of the layout size design. Exemplarily, according to the grid connection diagram shown in Fig. 6(a), a geometric structure diagram of the layout shown in Fig. 6(b) is generated. The layout includes four switch units, two diode units, four power terminal units, and 12 line units. Among them, two switch units, two absorption units, and four power terminal units are arranged in the connection line manner shown in Fig. 6(a), and 12 line units are filled in other positions to form a complete layout, and the overall layout shape is rectangular. As shown in Fig. 6(c), in the horizontal dimension definition diagram, there are nodes x1, x2, x3, x4, and x5 from left to right. There is an edge w1 between node x1 and node x2, an edge w2 between node x2 and node x3, an edge w3 between node x3 and node x4, and an edge w4 between node x4 and node x5. Among them, the width of edge w1 is related to the width of the copper layer in the line unit, the width of the copper layer in the terminal unit, and the width of the copper layer in the switch unit. Edge w2 is related to the width of the copper layer in the switch unit and the width of the copper layer in the terminal unit. The width of edge w3 is related to the width of the copper layer in the switch unit, the width of the copper layer in the terminal unit, and the width of the copper layer in the line unit. In the vertical dimension definition diagram, there are nodes y1 to y8 from bottom to top. Similarly, the edges between the nodes are h1 to h7, and the length of the edges is also related to the copper layer length of the layout unit. The overall layout area is obtained by multiplying the sum of the edge weights in the horizontal dimension definition diagram by the sum of the edge weights in the vertical dimension definition diagram. The target evaluation model is used to calculate the parasitic inductance of the commutation loop of the layout connection diagram. Based on Figure 7 the proposed efficient and accurate inductance calculation method considering the mutual inductance effect, the parasitic inductance of the two commutation loops is calculated. When the parasitic inductance of the commutation loop is less than the first threshold and the geometric layout area is less than the second threshold, the grid connection diagram and its geometric layout of the power module are output. When the parasitic inductance of the commutation loop is not less than the first threshold and the geometric layout area is not less than the second threshold, a new connection diagram is regenerated. Specifically: The commutation loop path in the grid connection diagram is input, and the path is divided into multiple rectangular segments for calculation, that is, the direction of the path node sequence is determined, and the segments are divided at the turning points of the path node directions. Based on the path segments after the above segmentation, it is judged whether there is a bonding wire. If there is a bonding wire, further segmentation is performed at the bonding wire connection. After the segmentation is completed, the self-inductance of each rectangular path is calculated:

[0010]

[0011] Where L is the parasitic inductance value of the conductor in henries (H); l is the length of the conductor in meters (m); g is the equivalent radius of the conductor; 𝜇 represents the magnetic permeability in a vacuum; w is the width of the conductor, and h is the height of the conductor, both in meters (m). Calculate the mutual inductance generated between all path segments in the loop. Specifically: divide each rectangle into q segments for representation. The mutual inductance value between any two segments in the copper layers represented by two rectangles can be approximately calculated using the following formula:

[0012] Where, l k is the length of the k-th segment, and d kp is the distance between two segments. Thus, the mutual inductance between other segments can also be obtained. By calculating the mutual inductance between all segments of two rectangular conductors, the overall mutual inductance between the two conductors can be obtained as:

[0013] The self-inductance of the path segments and the mutual inductance between the path segments are superimposed to form the loop parasitic inductance in the commutation loop. Determine whether the parasitic inductance of the connection diagram is less than the first threshold and whether the geometric layout area is less than the second threshold, and output the connection diagram that meets the set conditions and its size definition diagram. The 6 connection diagrams shown in the figure, and their corresponding geometric layouts. The third stage is to optimize the size of the layout unit. Based on the above-generated optimal layout, use the multi-objective optimization algorithm NSGA-II to iteratively optimize the layout size parameters, reduce the parasitic inductance value of the commutation loop of the layout and reduce the geometric layout area value of the layout to reach the Pareto optimization frontier, and then generate a compact low-inductance layout. Specifically: use the edge weights of the size definition diagram corresponding to the connection diagram as the design variables, and the minimum size of the layout unit as the design constraint, input them into the multi-objective optimization calculation model for optimization processing, and output the optimal three-level module layout. Multi-objective optimization is used to solve problems with multiple conflicting objective functions. Different from single-objective optimization, multi-objective optimization aims to find a set of solutions that achieve a balance in all objectives, rather than simply optimizing for a single objective. The multi-objective optimization algorithm finds a set of non-dominated solutions through an iterative search process, and these solutions achieve a balance in all objectives. A non-dominated solution means that no other solution is better than it in all objectives. The non-dominated sorting genetic algorithm II (NSGA-II) is a classic multi-objective optimization algorithm, which maintains the diversity of the population through non-dominated sorting and crowding distance. The specific implementation process is as follows: Step 1, system input: Input the grid connection diagram, size definition diagram, design size parameters, and genetic algorithm parameters, such as population size, number of iterations, crossover / mutation rate, and other parameters. Step 2, Initial Population: According to the dimension definition graph, calculate the DNA of the randomly generated initial population. That is, randomly select multiple groups of length parameters of the edges in the dimension definition graph of w1 - wn and h1 - hm. Here, n represents the number of edges in the dimension definition graph in the horizontal direction, and m represents the number of edges in the dimension definition graph in the vertical direction. Step 3, Fitness Evaluation: According to the length parameters of the edges in the multiple groups of w1 - wn and h1 - hm selected in Step 2 in the dimension definition graph, evaluate the parasitic inductance in the commutation loop and evaluate the overall layout area. Specifically, for the multiple groups of w1 - wn and h1 - hm generated in Step 2, calculate the parasitic inductance to obtain the parasitic inductance in the commutation loop and the overall layout area. Among them, the number of selected groups is related to the input population size. Step 4, Fitness Ranking: Calculate the Pareto rank and crowding degree. Specifically, sort the commutation loops corresponding to each group of dimension parameters according to the minimum loop parasitic inductance and the minimum layout area, and retain the top M layouts of the commutation loops with the minimum parasitic inductance and the minimum layout area. Step 5, Whether the Maximum Generation is Reached: Judge whether the maximum generation is reached. If the maximum generation is not reached, execute Step 6. If the maximum generation is reached, execute Step 8. Step 6, Generate Offspring: According to the M groups of parents screened by sorting, generate offspring DNA through crossover and mutation to generate a new population. Specifically, modify the length parameters of the edges in the dimension definition graph corresponding to the first M connection graphs to generate length parameters of the edges in the dimension definition graph with M different values. Exemplarily, modify the length of the edges in the dimension definition graph in one direction, such as increasing the length parameters of the edges in the M groups or decreasing the length parameters of the edges in the M groups. Step 7, Increment the Generation by One and then Execute Step 3. Step 8, Design Output: Output the global Pareto front design set and the design sets of all generations. In the present invention, the connection graph input into the genetic algorithm is Figure 9 the 6 connection graphs shown in [Figure], select the initial population size as 50 and the maximum number of iterations as 100, and then perform iterative optimization according to the steps shown in [Figure]. The results of each iteration and the finally obtained Pareto front are shown in [Figure], which is the relationship between the parasitic inductance and the layout area of the commutation loops corresponding to six different layouts. In the embodiments of the present application, after constructing the grid connection diagram and its size definition diagram, with the minimum parasitic inductance of the commutation loop and the minimum layout area as the optimization objectives, the grid connection diagram and its size definition diagram can be input into the multi-objective genetic calculation model constructed by the genetic algorithm for optimization search, to obtain the grid connection diagram of the power module and its geometric structure layout under two critical states with the minimum parasitic inductance of the commutation loop and the minimum layout area, as the optimal geometric layout, and then output the geometric layout to obtain the best layout of the T-type three-level power module. In order to verify whether the power module layout scheme designed in the present application has an optimization effect, the present application selects the frontier solution B for simulation verification. Before optimization: L = 23.02 nH, S = 18 cm2, design result of the frontier solution B: L = 16.03 nH, S = 16 cm2, verifying the effectiveness of the substrate design scheme of the power module designed in the present application. In the embodiments of the present application, with the minimum parasitic inductance of the commutation loop and the minimum layout area as the optimization objectives, the genetic algorithm is used to optimize the layout size of the power module, which can realize the automated layout design and has excellent performance.

Claims

1. A graphical automatic layout design method for three-level power modules considering mutual inductance. It is characterized by: include: Acquiring input parameters for designing a layout of a three-level power module, wherein the input parameters include information on a circuit topology required for the layout design of the power module; Determine the type of layout unit on the circuit topology and the number of each layout unit according to the information of the circuit topology and the pre-saved geometric structure diagram of the functional unit required for the layout, wherein the layout unit is the smallest unit constituting the geometric structure diagram of the functional unit required for the power module layout; A path planning model is used to connect the connected paths between the graph nodes corresponding to the geometric structure diagrams of each layout unit on the circuit topology to obtain a grid connection diagram constituting the power module layout, wherein the graph nodes corresponding to the geometric structure of the layout unit are the nodes and edges of the connection graph of the pre-saved layout unit on the circuit topology, and the connected path is a path between two nodes in the graph nodes corresponding to the geometric structure diagram of a layout unit, or between one of the graph nodes corresponding to two layout unit geometric structure diagrams.

2. The method according to claim 1, characterized in that , the type of layout unit on the circuit topology and the number of each layout unit are determined according to the information of the circuit topology and the pre-saved geometric structure diagrams of each layout unit, specifically including: Based on the information of the circuit topology, a netlist of the circuit topology is generated; based on the geometric structure diagram of each layout unit, the types of layout units on the netlist of the circuit topology and the number of each layout unit are calculated, wherein the types of layout units include switch units, diode units, power terminal units and copper layer line units.

3. The method according to claim 1 or 2, characterized in that The path planning model is a combination of a deep optimization search model and an integer programming model. The connection paths between the nodes representing the geometric structures of each layout unit on the circuit topology are connected to obtain a grid connection diagram of the power module layout, which specifically includes: Determine at least one commutation network on the netlist of the three-level circuit topology, and at least one connected path in each commutation network and the length and number of inflection points of each connected path, wherein the commutation network refers to a network path between two nodes on the netlist of the circuit topology, wherein the two nodes are one of two nodes of a switch unit and one of two nodes of a diode unit, or two nodes of two different switch units, or two nodes of a switch unit and a power terminal unit, or two nodes of a diode unit and a power terminal unit; Inputting at least one connected path in each commutation network and the length and number of inflection points of each connected path into the integer programming model to obtain a target optimal path in each commutation network, wherein the optimal path is a path in each commutation network that meets a set length threshold; Placing a copper layer line node on each network node of the target optimal path in each commutation network, and establishing an interconnection edge on the target optimal path in each commutation network; Output the non-empty nodes and edges in the grid connection structure to obtain a grid connection graph of the power module.

4. The method according to any one of claims 1 to 3, characterized in that , the input parameters also include the design size of the layout unit geometry; the method also includes: According to the design size, the minimum size of each layout unit is determined; according to the minimum size of each layout unit, the grid connection diagram of the power module is scanned to obtain a size definition diagram of the connection diagram; the size definition diagram is used to define the size of each layout unit and the size of the grid connection diagram when calculating the commutation loop inductance according to the connection diagram.

5. The method according to claim 4, characterized in that , scanning the grid connection diagram to obtain a dimension definition diagram of the grid connection structure, specifically including: The grid connection diagram is scanned in the horizontal direction to obtain a dimension definition diagram of the connection diagram in the horizontal direction; and the grid connection diagram is scanned in the vertical direction to obtain a dimension definition diagram of the connection diagram in the vertical direction.

6. The method according to claim 4 or 5, characterized in that ,The size definition graph includes nodes and edges, the nodes are grid lines for scanning the grid connection graph, and the edges are the distances between the grid lines, which are used to represent the size of each layout unit.

7. The method according to any one of claims 1 to 6, characterized in that , the method further comprises: According to the grid connection diagram and the dimension definition diagram of the connection structure, the target evaluation model is used to detect the parasitic inductance of the commutation loop of the power module geometric layout and the layout area of ​​the power module geometric layout; the parasitic inductance is the self-inductance of the path constituting the commutation loop and the mutual inductance generated between the paths. When the parasitic inductance of the commutation loop is less than a first threshold value and the geometric layout area of ​​the power module is less than a second threshold value, the grid connection diagram of the power module and its geometric layout are output.

8. The method according to claim 7, characterized in that ,The parasitic inductance evaluation method based on the path segmentation method specifically includes: The commutation loop path in the grid connection diagram is segmented at the path turning points and the bonding wire connections, and the self-inductance of each path segment and the mutual inductance generated between all path segments in the loop are calculated respectively, and the resultant are superimposed as the loop parasitic inductance in the commutation loop.

9. The method according to claims 7-8, characterized in that: A grid connection diagram and a dimension definition diagram of the three-level power module layout are input into a multi-objective optimization processing model, and a target geometric layout is output, where the target geometric layout is a geometric structure diagram that satisfies a set condition, and the set condition is to reduce the parasitic inductance value of the commutation loop and reduce the area value of the geometric layout to reach the Pareto optimization frontier, so as to obtain an optimal geometric layout of the three-level power module.

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