Method and system for checking Dangling line in layout

Abstract

The invention aims to provide a method and a system for checking Dangling lines in a layout. The method comprises the following steps: screening signal lines in the layout to obtain a first screening result; the positions with through holes at the joints of the upper and lower metal layers are screened out to obtain a second screening result; removing a second screening result in the first screening result to obtain a third screening result; calculating a Dangling line screening result according to the second screening result and the third screening result; and carrying out correction on the Dangling line. According to the method, the position of the Dangling line can be visually positioned, manual inspection is not needed, the conditions of false inspection and missing inspection are prevented, and the accuracy and efficiency of layout design are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a method and system for checking Dangling wires in a layout. Background Art

[0002] A Dangling wire, also known as a pendant wire, refers to a wire that is physically connected to a pin or terminal but is not logically connected to any load. Such a wire is in a floating state logically and may cause potential antenna effect problems. In the design of integrated circuits, Dangling wires are usually caused by negligence in the design or wiring process. These dangling wires not only occupy additional wiring resources but also increase the RC delay, affecting the signal transmission speed. In addition, the dangling wire may be connected to other input pins, resulting in unnecessary capacitive effects, thus affecting the performance and stability of the circuit.

[0003] In the layout design of an integrated circuit (IC), Routing is the process of converting the signal connections (Netlist) in a logic circuit into physical metal interconnections, which directly affects the performance, power consumption, and reliability of the chip. In existing IC designs, Routing mainly involves multi-metal analog manual wiring and digital automatic wiring. Design Rule Check (DRC) is a key verification step in integrated circuit design, mainly used to ensure that the design complies with the physical and electrical constraints of the manufacturing process. However, this kind of reliability check generally does not include Dangling wires. Problems with manual design reliability: During the manual wiring process, due to design complexity or human negligence, the signal line often fails to be correctly connected to the target device or the power / ground network. More notably, during the iterative optimization of the design, local circuit modifications may accidentally introduce new Dangling wires, and such errors are often difficult to be detected through conventional design reviews. Limitations of automated tools: When digital Automatic Placement and Routing (APR) tools process special structures, they may generate unexpected Dangling wires due to algorithm limitations. Existing tools lack an intelligent judgment mechanism for such special scenarios. Inherent defects of DRC checks: Traditional Design Rule Check (DRC) systems do not include Dangling wires in the standard check items because: some designs deliberately retain Dangling wires to achieve specific functions such as parasitic capacitance tuning, and it is necessary to manually search for relevant situations. The Dangling wire may become an antenna structure, accumulate charges (antenna effect) during the manufacturing process, cause gate oxide breakdown or transistor threshold voltage drift, and may also introduce unpredictable parasitic capacitance / inductance, which may change the timing of the critical path (such as an increase in clock skew) or cause signal crosstalk. Summary of the Invention

[0004] The object of the present invention is to provide a method and system for checking Dangling lines in a layout. This method can visually locate the positions of Dangling lines, eliminating the need for manual inspection, preventing false inspections and missed inspections, and improving the accuracy and efficiency of layout design.

[0005] A method for checking Dangling lines in a layout, comprising: Screening out the signal lines in the layout to obtain a first screening result; Screening out the positions with vias at the upper and lower layer metal connections to obtain a second screening result; Removing the second screening result from the first screening result to obtain a third screening result; Calculating a Dangling line screening result based on the second screening result and the third screening result; Correcting the Dangling lines.

[0006] Preferably, the calculating the Dangling line screening result based on the second screening result and the third screening result includes: Screening out the polygons with a shared point equal to 1 in the second screening result and the third screening result as a fourth screening result; Calculating the perimeter of the fourth screening result; Dividing the perimeter of the fourth screening result by 2 to obtain the value by which the Dangling line exceeds the second screening result; Comparing the exceeded value with a preset value to obtain the number of Dangling lines that need to be corrected.

[0007] Preferably, the screening out the signal lines in the layout to obtain a first screening result includes: Defining the power supply name; Marking the positions where power supply and ground wires exist and filtering the filling layer; Filtering the power supply and ground wires and screening the signal lines.

[0008] Preferably, the screening out the positions with vias at the upper and lower layer metal connections to obtain a second screening result includes: Finding out the overlapping area at the upper and lower layer signal line metal connections, which is the via position.

[0009] Preferably, the comparing the exceeded value with a preset value to obtain the number of Dangling lines that need to be corrected includes: Calculating the preset amount of the Dangling line according to the parameters of the layout; Comparing the preset amount of the Dangling line with the current number of Dangling lines to obtain the number of Dangling lines that need to be corrected.

[0010] Preferably, the correction of the Dangling wire includes: Locate the Dangling wire according to the coordinates of the screened Dangling wire; Remove or retain the Dangling wire by changing the wiring according to the circuit design requirements.

[0011] Preferably, after the correction of the Dangling wire, it further includes verifying the correction result, specifically: Perform iterative verification on the circuit; If the circuit reports an error, correct the position of the changed wiring until the circuit passes the verification.

[0012] A system for checking Dangling wires in a layout, including: A signal line screening module, used to screen the signal lines in the layout to obtain a first screening result; A via screening module, used to screen the positions with vias at the upper and lower layer metal connection points to obtain a second screening result; A data processing module, used to remove the second screening result from the first screening result to obtain a third screening result; A Dangling wire screening module, used to calculate the Dangling wire screening result according to the second screening result and the third screening result.

[0013] An electronic device, including: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for checking Dangling wires in a layout.

[0014] A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by the processor of the electronic device, the processor is enabled to execute a method for checking Dangling wires in a layout.

[0015] The beneficial effects of the present invention are as follows: In a complex Routing scenario including various elements such as signal lines, power ground wires, and CMP filling layers, the present invention can accurately locate the specific positions of these Dangling wires. In actual layout design, due to dozens or even hundreds of process layers involved, the wiring complexity increases exponentially, and traditional manual recognition methods face great challenges. The innovative method proposed by the present invention can achieve efficient and accurate positioning of Dangling wires in such a highly complex wiring environment. Description of the Drawings

[0016] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing the embodiments in accordance with the present invention, and are used together with the specification to explain the principles of the present invention.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a flowchart of a method for checking Dangling lines in a layout of the present invention; Figure 2 It is a schematic diagram of the Dangling line of the present invention; Figure 3 It is a schematic diagram of the first screening result of the present invention; Figure 4 It is a schematic diagram of the second screening result of the present invention; Figure 5 It is a schematic diagram of the third screening result of the present invention; Figure 6 It is a schematic diagram of the polygon screening result of the present invention; Figure 7 It is a schematic diagram of the actual layout wiring situation of the present invention; Figure 8 It is a schematic diagram of positioning the position of the Dangling line of the present invention. Detailed implementation manners

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0021] In addition, the descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] In integrated circuit (IC) layout design, Routing is the process of converting the signal connections (Netlist) in a logic circuit into physical metal interconnections, which directly affects the performance, power consumption, and reliability of the chip. In existing IC designs, Routing mainly relies on multi-metal analog manual wiring and digital automatic wiring. Design Rule Check (DRC) is a key verification step in integrated circuit design, mainly used to ensure that the design complies with the physical and electrical constraints of the manufacturing process. However, this kind of reliability check generally does not include Dangling wires. Reliability issues in manual design: During the manual wiring process, due to design complexity or human negligence, it often occurs that signal lines are not correctly connected to the target device or the power / ground network. More notably, during the design iteration and optimization, local circuit modifications may accidentally introduce new Dangling wires, and such errors are often difficult to be detected through conventional design reviews. Limitations of automated tools: Digital Automatic Placement and Routing (APR) tools may generate unexpected Dangling wires due to algorithm limitations when dealing with special structures. Existing tools lack an intelligent judgment mechanism for such special scenarios. Inherent defects of DRC checks: Traditional Design Rule Check (DRC) systems do not include Dangling wires in the standard check items because: some designs deliberately retain Dangling wires to achieve specific functions such as parasitic capacitance tuning, and it is necessary to manually search for relevant situations. Dangling wires may become antenna structures, accumulate charges (antenna effect) during the manufacturing process, resulting in gate oxide breakdown or transistor threshold voltage drift, and may also introduce unpredictable parasitic capacitance / inductance, which may change the timing of the critical path (such as an increase in clock skew) or cause signal crosstalk.

[0023] The present invention can accurately locate the specific positions of these Dangling wires in a complex Routing scenario including various elements such as signal lines, power and ground lines, and CMP filling layers. In actual layout design, due to the involvement of dozens or even hundreds of process layers, the wiring complexity increases exponentially, and traditional manual identification methods face great challenges. The innovative method proposed by the present invention can achieve efficient and accurate positioning of Dangling wires in such a highly complex wiring environment.

[0024] Example 1 A method for checking Dangling lines in a layout, referring to Figure 1 , including: S100, screening out the signal lines in the layout to obtain the first screening result; S200, screening out the positions with vias at the upper and lower metal joints to obtain the second screening result; S300, removing the second screening result from the first screening result to obtain the third screening result; Based on each layer of metal, the rules are as follows. For example, for M2_NON, it is necessary to first merge the lower derivative layer IN_V1_AND and the upper derivative layer IN_V2_AND based on M2 in OUTPUT_B into V1V2_OR, and then remove the merged derivative layer V1V2_OR from M2_NON_SUPPLY in OUTPUT_A. The screened area cluster is output as OUTPUT_C.

[0025] V1_OR = OR IN_V1_AND, V1V2_OR = OR IN_V1_AND IN_V2_AND, V2V3_OR = OR IN_V2_AND IN_V3_AND, V3_OR = OR IN_V3_AND, M1_NON = NOT M1_NON_SUPPLY V1_OR, M2_NON = NOT M2_NON_SUPPLY V1V2_OR, M3_NON = NOT M3_NON_SUPPLY V2V3_OR, M4_NON = NOT M4_NON_SUPPLY V3_OR.

[0026] S400, calculating the Dangling line screening result according to the second screening result and the third screening result; S500, correcting the Dangling lines.

[0027] In the embodiments of the present invention, the positions of signal lines and positions with vias can be screened out through the language in the Standard Verification Rule Format (SVRF) of Calibre DRC. It is mainly used for the rule description of integrated circuit physical verification. After many commands in its language are used to screen out signal lines, for example, after EXPAND TEXT screens out POWER_NET, the signal lines are selected by taking the inverse of NET AREA RATIO. The positions with holes are screened out by using ENCLOSE VIA after using AND for high-level metal and low-level metal.

[0028] Preferably, S400, calculating the Dangling line screening result based on the second screening result and the third screening result includes: S410, screening out the polygons with the shared points equal to 1 in the second screening result and the third screening result as the fourth screening result; Select all the shapes where the shared points of OUTPUT_C and OUTPUT_B are equal to 1 and name the output as OUTPUT_D, as Figure 6 shown.

[0029] TOUCH M1_NON V1_OR ==1, TOUCH M2_NON V1V2_OR ==1, TOUCH M3_NON V2V3_OR ==1, TOUCH M4_NON V3_OR==1.

[0030] S420, calculating the perimeter of the fourth screening result; S430, dividing the perimeter of the fourth screening result by 2 to obtain the value by which the Dangling line exceeds the second screening result; S440, comparing the exceeded value with a preset value to obtain the number of corrections required for the Dangling line.

[0031] Based on the output OUTPUT_D shape, calculate the perimeter of OUTPUT_D, and dividing it by two can obtain the specific value VALUE1 by which the Dangling line exceeds OUTPUT_B. The user can preset the value of VALUE2 according to the actual situation and compare it with VALUE1 and then make modifications.

[0032] Preferably, S100, screening out the signal lines in the layout to obtain the first screening result includes: S110, defining the power supply name; First, define the names of the power grounds required in the project design, such as VDDA, VDDD, VSSA, VSSD, VPPA, VPPD: VARIABLE POWER_GROUND “VDDA” “VDDD” “VSSA” “VSSD” “VPPA” “VPPD”.

[0033] S120, mark the positions where power ground lines exist and filter the fill layer; Then, construct a square layer with a length and width derived from 0.01 at the positions where POWER_GROUND object pins (including multi-layer metals, M1_pin, M2_pin, M3_pin, M4_pin...) exist, and the positions of M1, M2, M3, M4 AND can filter out the CMP fill layer.

[0034] M1_PG_PIN = AND M1 (EXPAND TEXT POWER_GROUND M1_pin BY 0.01 PRIMARYONLY), M2_PG_PIN = AND M2 (EXPAND TEXT POWER_GROUND M2_pin BY 0.01 PRIMARYONLY), M3_PG_PIN = AND M3 (EXPAND TEXT POWER_GROUND M3_pin BY 0.01 PRIMARYONLY), M4_PG_PIN = AND M4 (EXPAND TEXT POWER_GROUND M4_pin BY 0.01 PRIMARYONLY) …… ‌The power ground wire is a wire used to safely introduce current into the ground, usually called the lightning protection wire. Its main function is to quickly conduct the current into the ground when an electrical device leaks electricity, thus ensuring the safety of personnel and equipment. The ground wire plays a crucial role in the electrical system and is an important means of electrical protection‌. The ground wire is a wire connected to the ground, the shell, or a reference potential of zero. In an electrical system or electronic device, the ground wire is usually connected to the shell to prevent electric shock accidents caused by the shell being electrified due to internal insulation damage of the electrical appliance.

[0035] S130, filter the power ground wires and screen the signal wires.

[0036] There are various signal wires, power ground wires, CMP fill layers... in the layout. First, screen out the signal wires in the layout and name them OUTPUT_A, as Figure 3 shown.

[0037] Filter out the lines of M1, M2, M3, and M4 that do not cover M1_PG_PIN, M2_PG_PIN, M3_PG_PIN, and M4_PG_PIN respectively as connection signals, which can filter out power ground wires, and the output result is OUTPUT_A.

[0038] M1_NON_SUPPLY = NET AREA RATIO M1 OVER M1_PG_PIN M2_PG_PIN M3_PG_PINM4_PG_PIN==0, M2_NON_SUPPLY = NET AREA RATIO M2 OVER M1_PG_PIN M2_PG_PIN M3_PG_PINM4_PG_PIN==0, M3_NON_SUPPLY = NET AREA RATIO M3 OVER M1_PG_PIN M2_PG_PIN M3_PG_PINM4_PG_PIN==0, M4_NON_SUPPLY = NET AREA RATIO M4 OVER M1_PG_PIN M2_PG_PIN M3_PG_PINM4_PG_PIN==0.

[0039] The signal lines in the layout refer to the lines used to transmit sensing information and control information in the electrical control circuit. The main function of the signal lines is to ensure the quality and stability of the signal during transmission. Generally, good shielding performance and anti-interference ability are required to reduce the attenuation and distortion of the signal during transmission.

[0040] Preferably, in S200, screening out the positions with vias at the upper and lower layer metal connections to obtain the second screening result includes: Find the overlapping area of the upper and lower layer signal line metal connections, which is the via position.

[0041] Screen out the positions with vias at the upper and lower layer signal line metal connections, and the output result is OUTPUT_B.

[0042] ALL_M1M2_AND=ENCLOSE (AND M1_NON_SUPPLY M2_NON_SUPPLY) V1, ALL_M2M3_AND=ENCLOSE (AND M2_NON_SUPPLY M3_NON_SUPPLY) V2, ALL_M3M4_AND = ENCLOSE (AND M3_NON_SUPPLY M4_NON_SUPPLY) V3, IN_V1_AND = INSIDE V1 ALL_M1M2_AND, IN_V2_AND = INSIDE V2 ALL_M2M3_AND, IN_V3_AND = INSIDE V3 ALL_M3M4_AND。

[0043] Screen out the positions with vias at the upper and lower metal joints and name them OUTPUT_B, as Figure 4 shown. Then remove the area of OUTPUT_B from OUTPUT_A, and the remaining is OUTPUT_C, as Figure 5 shown.

[0044] ‌In a layout, a via refers to a hole that passes through from one side of the circuit board to the other side and can completely penetrate the entire circuit board. Vias are mainly used to connect circuits on different layers, providing electrical connections and mechanical support.‌ A via realizes the electrical connection of the pads on the front and back surfaces through its copper-plated inner wall, and is often used for internal interconnection or as a component positioning hole.‌ Vias also provide mechanical support to help fix the components on the circuit board.‌

[0045] Preferably, S440, comparing the exceeded value with the preset value to obtain the number of Dangling lines that need to be corrected includes: S441, calculating the preset amount of Dangling lines according to the parameters of the layout; In chip layout design, a Dangling line usually refers to a metal line or via that is not correctly connected to the target node or is floating. Dangling lines may cause problems such as short circuits, leakage, or signal integrity, so it is necessary to strictly control their quantity and length. The preset amount is usually determined by the process rules (Design Rule Manual, DRM) or project specifications. The standards include: the maximum allowable length, the maximum allowable number (such as ≤5 lines per metal layer), and prohibition in critical areas (such as not allowed near clock lines and power supply lines). Then, according to the layout parameters (such as metal layer, line width, process node), calculate the electrical impact of the Dangling lines.

[0046] S442, comparing the preset amount of Dangling lines with the current number of Dangling lines to obtain the number of Dangling lines that need to be corrected.

[0047] The selection steps for the selected value of VALUE2 are as follows: First, based on the larger value between the width and height in the actual size in the layout, this value is set as Value_max. In actual operation, the VALUE2 (set value) is shown in Table 1 as follows: Table 1: Set value

[0048] By setting the value of VALUE2 according to the layout situation, errors can be effectively screened out and corrected, and the output result is the area that the engineer needs to correct. Figure 7 It presents a complex Routing scenario including various elements such as signal lines, power and ground lines, and CMP filling layers, among which there is also the problem of Dangling lines in the signal lines; Figure 8 Then it accurately locates the specific positions of these Dangling lines. In actual layout design, due to involving dozens or even hundreds of process layers, the wiring complexity increases exponentially, and traditional manual recognition methods face great challenges. The innovative method proposed in this patent can achieve efficient and accurate positioning of Dangling lines in such a highly complex wiring environment.

[0049] Preferably, for S500, the correction of the Dangling line includes: S510, locating the Dangling line according to the coordinates of the screened-out Dangling line; S520, changing the wiring according to the circuit design requirements to remove or retain the Dangling line.

[0050] After finding the Dangling line, the engineer can directly click to view the position of the Dangling line in the layout and directly make modifications. The present invention can intuitively locate the position of the Dangling line, without the need for manual inspection, preventing the situations of misdetection and missed detection, and improving the accuracy and efficiency of layout design.

[0051] If the Dangling line exceeds the standard, it can also be repaired in the following ways: Connect to a dummy node: Connect the dangling line to a non-functional dummy metal. Delete redundant segments: Remove metal segments without electrical significance. Add jumpers: Connect to other layers through vias to avoid charge accumulation.

[0052] Preferably, after S500, for the correction of the Dangling line, it also includes verifying the correction result, specifically: Performing iterative verification on the circuit; If the circuit reports an error, then correct the position of the changed wiring until the circuit passes the verification.

[0053] In the design of chip layout, to verify whether the dangling lines are qualified, it is necessary to check the unconnected signal lines and check whether the dangling vias affect the circuit performance. Run the circuit to see if it can work properly. If it can work properly, it means that the correction of the dangling lines is completed. If it cannot work properly, modify the wiring position until the circuit passes the verification.

[0054] Embodiment 2 A system for checking dangling lines in a layout, comprising: A signal line screening module for screening out the signal lines in the layout to obtain a first screening result; In the layout, there are many signal lines, power ground lines, CMP filling layers, etc. There may be dangling lines in these lines. Therefore, it is necessary to use the signal line screening module to first screen out the signal lines in the layout. Because the number of signal lines is the largest and they are the easiest to be screened out, and the screening of some other lines also depends on the screening results of the signal lines, so the signal lines should be screened first.

[0055] A via screening module for screening out the positions with vias at the upper and lower layer metal joints to obtain a second screening result; The core role of vias in layout design is to achieve electrical connection between multiple layers of circuits and provide mechanical support. Vias are used to fix plug-in components (such as resistors, capacitors). The pins are inserted into the vias and welded to enhance the physical connection strength between the components and the PCB. Dangling lines are usually interrupted by vias.

[0056] A data processing module for removing the second screening result from the first screening result to obtain a third screening result; When all the signal lines are removed of the vias, what are obtained are various lines. Among these lines, there are dangling lines. Therefore, the next step is to screen out the contained dangling lines from these lines.

[0057] A dangling line screening module for calculating a dangling line screening result according to the second screening result and the third screening result.

[0058] Each different layout has a number of dangling lines that can be allowed to exist. Once the number of allowed dangling lines is exceeded, it will directly affect the performance, power consumption and reliability of the chip, resulting in chip scrapping. Therefore, it is necessary to calculate the number of unqualified dangling lines and screen the positions of the dangling lines for engineers to delete and modify the dangling lines.

[0059] Embodiment 3 An electronic device, comprising: a chip, a processor, and a memory, where the memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for checking Dangling lines in a layout.

[0060] Embodiment 4 A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a method for checking Dangling lines in a layout.

[0061] The present invention can accurately locate the specific positions of these Dangling lines in a complex Routing scenario including various elements such as signal lines, power ground lines, and CMP filling layers. In actual layout design, due to the involvement of dozens or even hundreds of process layers, the wiring complexity increases exponentially, and traditional manual recognition methods face great challenges. The innovative method proposed by the present invention can achieve efficient and accurate positioning of Dangling lines in such a highly complex wiring environment.

[0062] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for checking dangling lines in a layout, characterized in that: include: Filter the signal lines in the publication diagram to obtain the first screening result; Screening out the locations with through holes at the connection between the upper and lower metal layers to obtain a second screening result; The second screening result is removed from the first screening result to obtain a third screening result; The Dangling line screening result is calculated based on the second screening result and the third screening result; Correction of Dangling Line; The Dangling line screening result calculated according to the second screening result and the third screening result includes: Filter out the polygons whose shared points are equal to 1 in the second and third screening results as the fourth screening result; Calculating the perimeter of the fourth screening result; Divide the perimeter of the fourth screening result by 2 to obtain the value of the Dangling line exceeding the second screening result; Compare the exceeded value with the preset value to get the amount of correction required for the Dangling line.

2. A method for checking dangling lines in a layout according to claim 1, characterized in that: The screening of the signal lines in the publication graph to obtain the first screening result comprises: Define the power supply name; Mark the location where the power ground wire exists and filter the filling layer; Filter the power ground line and screen the signal line.

3. The method for checking dangling lines in a layout according to claim 1, characterized in that: The second screening result obtained by screening out the positions with through holes at the connection between the upper and lower metal layers includes: Find the overlapping area where the metal connections of the upper and lower signal lines are connected, which is the location of the through hole.

4. The method for checking dangling lines in a layout according to claim 2, characterized in that: The step of comparing the exceeded value with the preset value to obtain the number of Dangling lines that need to be corrected includes: Calculate the preset amount of Dangling lines according to the parameters of the layout; The preset amount of the Dangling line is compared with the current amount of the Dangling line to obtain the amount of the Dangling line that needs to be corrected.

5. A method for checking dangling lines in a layout according to claim 4, characterized in that: The correction of the Dangling line includes: Locate the Dangling line according to the coordinates of the selected Dangling line; Change the wiring to remove or retain the dangling line according to the circuit design requirements.

6. The method for checking dangling lines in a layout according to claim 1, characterized in that: After the Dangling line is corrected, the correction result is verified, specifically: Iterate and verify the circuit; If the circuit reports an error, correct it by changing the wiring position until the circuit passes verification.

7. A system for checking dangling lines in a layout, applied to a method for checking dangling lines in a layout as claimed in any one of claims 1 to 6, characterized in that: include: A signal line screening module, used to screen the signal lines in the publication diagram to obtain a first screening result; A through-hole screening module is used to screen out the positions with through-holes at the connection between the upper and lower metal layers to obtain a second screening result; A data processing module, used for removing the second screening result from the first screening result to obtain a third screening result; The Dangling line screening module is used to calculate the Dangling line screening result according to the second screening result and the third screening result.

8. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for checking dangling lines in a layout as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a method for checking dangling lines in a layout according to any one of claims 1 to 6.

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