Semiconductor structure preparation method

Abstract

The invention provides a method for preparing a semiconductor structure, which comprises the following steps of: depositing a dielectric substance anti-reflection layer on a semiconductor material layer, carrying out light irradiation on the dielectric substance anti-reflection layer by adopting SiH4-containing gas to break Si-H bonds in the dielectric substance anti-reflection layer so as to obtain the dielectric substance anti-reflection layer. And etching the dielectric substance anti-reflection layer after light irradiation to form a patterned dielectric substance anti-reflection layer, and etching the semiconductor material layer by taking the patterned dielectric substance anti-reflection layer as a mask to form a patterned structure. By performing light irradiation on the dielectric anti-reflection layer, the Si-H bond in the dielectric anti-reflection layer is broken to enhance the compactness and the etching resistance of the film, so that in the process of etching the target material layer and the DARC layer to form the patterned structure, the LES effect is inhibited through the enhanced etching resistance, the patterning precision is improved, and the yield of the patterned structure is improved. And the electrical performance and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Art

[0002] As semiconductor processes progress from 90 nm to 7 nm and below, the miniaturization of feature sizes poses extremely high requirements for the accuracy and reliability of etching processes. In semiconductor manufacturing, a dielectric anti-reflective coating (DARC), as an important dielectric anti-reflective coating, is not only used to reduce the standing wave effect during lithography but also widely serves as a hard mask to protect underlying materials and achieve patterning in various etching scenarios. The application of DARC spans both the front-end-of-line (FEOL, such as MOSFET gate fabrication) and the back-end-of-line (BEOL, such as metal interconnect structures), and its etching resistance directly affects the geometric accuracy of the patterned structure and device performance.

[0003] In the related art, the etching resistance of DARC is insufficient, thereby affecting the performance of semiconductor devices.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] Aiming at the problems in the prior art, the purpose of the present invention is to provide a method for fabricating a semiconductor structure, which overcomes the difficulties of the prior art and can solve the technical problem of insufficient etching resistance of DARC in the related art.

[0006] The first aspect of the present disclosure provides a method for fabricating a semiconductor structure, which includes:

[0007] Providing a semiconductor material layer;

[0008] Depositing a dielectric anti-reflective layer on the semiconductor material layer, wherein the gas used for depositing the dielectric anti-reflective layer includes SiH 4 ;

[0009] Performing light irradiation on the dielectric anti-reflective layer to break the Si-H bonds in the dielectric anti-reflective layer;

[0010] Etching the dielectric anti-reflective layer after light irradiation to form a patterned dielectric anti-reflective layer, and etching the semiconductor material layer using the patterned dielectric anti-reflective layer as a mask to form a patterned structure;

[0011] Removing the patterned dielectric anti-reflective layer.

[0012] In an alternative embodiment, light with a wavelength of 200 - 400 nm is used to irradiate the dielectric antireflection layer.

[0013] In an alternative embodiment, the thickness of the dielectric antireflection layer is

[0014] In an alternative embodiment, the duration of the light irradiation is 90 - 130 s.

[0015] In an alternative embodiment, a plasma enhanced chemical vapor deposition process is used to deposit the dielectric antireflection layer on the semiconductor material layer.

[0016] In an alternative embodiment, the gas used for depositing the dielectric antireflection layer further includes N 2 , NH 3 , N 2 O, and CO 2 or at least one of them.

[0017] In an alternative embodiment, the semiconductor structure manufacturing method is applied to the SRAM manufacturing process, and the semiconductor material layer is used to form the SRAM structure.

[0018] In an alternative embodiment, the semiconductor material layer is a polysilicon layer, and the patterned structure serves as the gate structure of the MOSFET; and / or

[0019] The semiconductor material layer is a dielectric layer, and the patterned structure is a via or a trench, and the via or the trench is used to fill the metal interconnect structure.

[0020] In an alternative embodiment, the semiconductor material layer is a substrate, and the patterned structure is a shallow trench or a Fin structure located in the substrate.

[0021] The semiconductor structure manufacturing method provided by the embodiments of the present disclosure has the following advantages:

[0022] After depositing the dielectric antireflection layer on the semiconductor material layer, the dielectric antireflection layer is irradiated with light to break the Si - H bonds in the dielectric antireflection layer, enhancing the film density and etch resistance. In this way, during the process of etching the target material layer and the DARC layer to form the patterned structure, the LES effect is suppressed through the enhanced etch resistance, improving the patterning accuracy, device electrical performance, and reliability.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0024] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non - limiting embodiments read in conjunction with the accompanying drawings.

[0025] Figure 1 A flowchart showing a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure.

[0026] Figures 2 - 10 Show Figure 1 Schematic diagrams of the semiconductor structure shown at various stages during fabrication;

[0027] Figure 11 A schematic diagram of a control sample of a semiconductor structure without light irradiation. Detailed implementation manners

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments.

[0029] In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0030] In actual MOSFET production, it has been found that there are significant differences in the etching behavior between the end region and the central region of polysilicon lines. The etching of the central region of the line is mainly affected by a single direction, while the end of the line is affected by multi - direction etching, resulting in insufficient etching resistance of DARC in these regions and rapid recession. This recession phenomenon is called Line End Shortness (LES), which directly affects the geometry and dimensional accuracy of the line. For example, in traditional processes, LES causes the shortening of the end length of the line, thereby limiting the further miniaturization of the process dimensions. In addition, LES also causes a series of electrical performance problems, including the threshold voltage shift (Vt shift) of MOSFETs and the mismatch of SRAMs, which are particularly prominent in high - density integrated circuits and directly affect the performance and yield of the devices.

[0031] Upon further research, it was found that the cause of the LES problem lies in the insufficient etching resistance of the DARC film quality. During the traditional DARC deposition process, the film layer formed by using a gas containing SiH 4 often has unreacted Si-H bonds remaining. The presence of these Si-H bonds makes the film quality relatively loose and difficult to effectively resist the bombardment of plasma during the dry etching process, resulting in the rapid consumption of DARC in the end region. Therefore, how to enhance the etching resistance of DARC has become a technical challenge in solving the LES problem.

[0032] Therefore, there is an urgent need for a simple and efficient method to enhance the etching resistance of DARC, suppress the LES effect, and improve the performance and reliability of semiconductor devices without significantly increasing the process complexity.

[0033] The semiconductor structure preparation method proposed in the embodiments of the present disclosure uses light irradiation to break the Si-H bonds in the DARC film layer, making the film quality change from loose to dense, thereby enhancing the etching resistance and optimizing the patterning effect during the etching process. This method is applicable to any scenario where DARC is used as a mask and has broad universality.

[0034] As Figure 1 shown, the semiconductor structure preparation method provided in the embodiments of the present disclosure includes but is not limited to the following steps:

[0035] Step 110: Provide a semiconductor material layer;

[0036] Step 120: Deposit a dielectric antireflection layer on the semiconductor material layer. The gas used for depositing the dielectric antireflection layer includes SiH 4 ;

[0037] Step 130: Perform light irradiation on the dielectric antireflection layer to break the Si-H bonds in the dielectric antireflection layer;

[0038] Step 140: Etch the dielectric antireflection layer after light irradiation to form a patterned dielectric antireflection layer, and use the patterned dielectric antireflection layer as a mask to etch the semiconductor material layer to form a patterned structure;

[0039] Step 150: Remove the patterned dielectric antireflection layer.

[0040] In this embodiment, by performing light irradiation on the DARC layer, the Si-H bonds in the DARC layer are broken, enhancing the film quality density and etching resistance. In this way, during the process of etching the target material layer and the DARC layer to form a patterned structure, the LES effect is suppressed through the enhanced etching resistance, improving the patterning accuracy, and enhancing the electrical performance and reliability of the device.

[0041] The method for fabricating a semiconductor structure according to the embodiments of the present disclosure will be described in detail below with reference to the formation process of a polysilicon (POLY) gate.

[0042] As Figure 2 shown, a substrate 1 is provided, and a polysilicon layer 2 is deposited on the substrate 1. Exemplarily, the polysilicon layer 2 is an implementation of the above-mentioned semiconductor material layer.

[0043] In the embodiments of the present disclosure, the substrate 1 provides a process operation basis for subsequent processes.

[0044] Optionally, the substrate 1 may be a third-generation wide bandgap semiconductor material such as silicon carbide or gallium nitride. In other embodiments, the material of the substrate 1 may also be other materials such as silicon, germanium, silicon germanide, gallium arsenide, or indium gallium, and the substrate 1 may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 1 may be a material suitable for process requirements or easy to integrate.

[0045] In an alternative embodiment, on the substrate 1, a polysilicon layer 2 is deposited by low-pressure chemical vapor deposition (LPCVD) as the semiconductor material layer. The polysilicon layer 2 serves as the main material of the subsequent gate structure. In addition, as the main material of the gate structure, the semiconductor material layer is not limited to polysilicon, and a metal gate material or the like may also be selected. The deposition method of the polysilicon layer 2 is not limited to LPCVD, and other CVD methods may be selected according to actual production.

[0046] In one embodiment, before depositing the polysilicon layer 2, an active area 1a is formed in the substrate 1. Exemplarily, ion implantation is performed in the substrate 1 to adjust the electrical characteristics of the substrate 1 and form the active area 1a. The active area is a key area in MOSFET manufacturing and is also the working area of the MOSFET, providing a channel for current flow.

[0047] As Figure 3 shown, a DARC layer 3 is deposited on the polysilicon layer 2, and the DARC layer 3 is deposited using a gas containing SiH 4 gas.

[0048] Exemplarily, on the polysilicon layer 2, a nitrogen-containing DARC layer 3 is deposited by plasma-enhanced chemical vapor deposition (PECVD), which simultaneously serves as an anti-reflection coating and a hard mask.

[0049] Among them, the PECVD deposition equipment may be a multi-chamber PECVD system, and the reaction gas formula is SiH 4and a nitrogen-containing gas (such as N 2 , NH 3 and N 2 O, etc.), taking N 2 O as an example, the chemical reaction equation is as follows:

[0050] SiH 4 +N 2 +NH 3 +N 2 O→(Plasma heat)SiON+N 2 O+ by-products (H2, N2, etc.).

[0051] The PECVD technology enhances chemical reactions by means of plasma to achieve the process of chemical vapor deposition. In the PECVD system, reaction gases are introduced into the reaction chamber. Then, through the excitation of power sources such as radio frequency (RF) and microwave, the reaction gases are ionized to form plasma. The plasma contains a large number of active particles such as high-energy electrons, ions, and free radicals. These active particles have high chemical activity and can greatly reduce the activation energy required for chemical reactions, enabling chemical reactions that originally required harsh conditions such as high temperature to proceed rapidly at relatively low temperatures.

[0052] Therefore, this embodiment is highly compatible with existing PECVD and etching processes and does not require additional complex equipment.

[0053] In this embodiment, the deposited DARC layer 3 contains a certain amount of Si-H bonds and the film quality is relatively loose.

[0054] In the embodiment of the present disclosure, the thickness of the DARC layer 3 is Within this range, the DARC layer 3 can provide good etching accuracy and etching resistance during the etching process. If the DARC layer 3 is too thick (for example, >310 nm), the sidewall protection is enhanced during the etching process, but due to the change in the etching selectivity ratio, it may cause critical dimension (CD) deviation and etching residues may occur, affecting subsequent processes. However, if the DARC layer 3 is too thin (for example, <210 nm), it cannot provide sufficient etching resistance, may cause premature loss of the mask layer, uneven etching endpoints, and may cause sidewall collapse or exacerbation of the LES effect. Within the range of 210 - 310 nm, the DARC layer 3 can provide etching resistance, ensure line perpendicularity, and improve CD uniformity.

[0055] On the other hand, the thickness of the DARC layer 3 also affects the subsequent light irradiation time, and the light irradiation time affects the final density of the DARC layer 3.

[0056] As Figure 4 shown, the deposited DARC layer 3 is subjected to light irradiation treatment.

[0057] In one embodiment, an irradiation light is provided by irradiating a device with ultraviolet light (UV) having a wavelength of 200 - 400 nm. During the UV irradiation, the photon energy (about 3.1 - 6.2 eV) is sufficient to break the Si - H bond (bond energy about 3.1 eV), decomposing the unreacted Si - H bonds into Si radicals and H atoms. After the H atoms escape, the Si atoms rebond with other atoms to form a denser Si - O or Si - N network structure.

[0058] In this embodiment, a wavelength of 200 - 400 nm can ensure moderate breaking of the Si - H bonds, improve the etch resistance of the DARC layer 3, and optimize the perpendicularity and topography uniformity after etching. For low light (weak ultraviolet, e.g., < 200 nm), the Si - H bonds are not sufficiently broken, the densification of the DARC layer is limited, and the etch resistance is insufficient, which may lead to non - uniform film layers during etching and affect the line integrity. For high light (strong ultraviolet, > 400 nm), it may cause local over - crosslinking of the DARC layer, affect the etching rate, result in non - uniform etching topography, may introduce additional film stress, and cause device process deformation.

[0059] Tests show that the film hardness of the DARC layer after irradiation increases by about 20%, and the density increases by about 15%.

[0060] In an alternative embodiment, the duration of the light irradiation is 90 - 130 s. Research shows that if the duration of the light irradiation is too short (e.g., < 90 s), the Si - H bonds are not sufficiently broken, the densification of the film layer is not fully improved, resulting in low etch resistance. During the etching process, the DARC layer 3 is consumed too quickly, which may cause pattern collapse or non - uniform topography, may lead to etching end - point errors, and affect the control of the final etching depth. If the irradiation time is too long (e.g., > 130 s), it may cause over - crosslinking of the DARC layer, reducing the etching rate, affecting the processing efficiency, may generate additional film stress, affect subsequent device performance such as Vt shift, etc., and may cause local over - photochemical reaction inside the DARC layer, resulting in increased CD loss during the etching process.

[0061] Within the above - mentioned duration range (90 - 130 seconds), it can ensure sufficient breaking of the Si - H bonds, densify the DARC layer 3, improve the etch resistance, control the optical properties of the film layer, and improve the uniformity of subsequent etching. At the same time, this can meet the requirements of different etching processes, ensuring the etch resistance without introducing additional film stress.

[0062] Further considering the influence of the light irradiation duration on the subsequent etching topography, an appropriate light irradiation time is helpful for etching uniformity and improving the critical dimension (CD) consistency. An overly short time will cause the etching rate of the DARC layer to be too fast, affecting the line integrity. An overly long time may reduce the etching rate, resulting in inaccurate control of the etching end point. Additionally, an appropriate light irradiation time can improve the sidewall retention ability of the DARC layer and reduce the occurrence of the LES effect during etching. An overly short time will cause sidewall collapse, and an overly long time may introduce additional stress, making the sidewall structure uneven.

[0063] In addition, a moderate light irradiation time can ensure the stable etching selectivity of the DARC layer 3 and improve the CD control accuracy. An overly short time may cause the DARC layer 3 to be etched too fast, resulting in CD loss, and an overly long time may cause CD expansion, affecting the accuracy of pattern transfer.

[0064] In the above embodiments, the thickness of the DARC layer 3, the duration and wavelength of the light irradiation are comprehensively considered, and the influence of the combination of these parameters on enhancing the densification of the DARC layer 3 and the subsequent etching process is tested to select a suitable parameter combination.

[0065] As Figure 5 and Figure 6 shown, Figure 5 is a cross-sectional view along the gate width direction, while Figure 6 is a top view. After the light irradiation treatment of the DARC layer 3, a photoresist 4 is coated and lithography (GATE PHOTO) is performed to form a line pattern 40.

[0066] As Figure 7 and Figure 8 shown, Figure 7 is a cross-sectional view along the gate width direction, while Figure 8 is a top view. The DARC layer 3 and the polysilicon layer 2 are etched by a dry etching device (such as a CCP type plasma etcher). Optionally, the etching gas can be selected as CF 4 and O 2 .

[0067] During the etching process, the DARC layer 3 acts as a hard mask to protect the polysilicon layer 2. At the same time, after the DARC layer 3 is etched and patterned, the polysilicon layer 2 is continuously etched using the patterned DARC layer as a mask to form a patterned line 20, which, as a part of the patterned structure, forms a gate structure. Due to the enhanced etching resistance of the DARC layer 3, the end retraction length of the patterned line 20 is reduced, and the LES effect is significantly suppressed.

[0068] As Figure 9 and Figure 10 shown, after the patterned line 20 is etched, the DARC layer 3 is removed (as Figure 8As shown). Additionally, it is also possible that during the etching of the patterned line 20, the DARC layer 3 is also etched, and after obtaining the patterned line 20, the DARC layer 3 is exactly etched away.

[0069] In this embodiment, after etching to obtain the patterned line 20, wet etching can be used to remove the remaining DARC layer 3. The cleaning solution is a diluted HF solution, followed by rinsing with deionized water and drying to complete the preparation of the polysilicon line.

[0070] Compared with the control sample without light irradiation, the LES length of this embodiment is reduced. Figure 11 Characterize the control sample without light irradiation. From the left photolithographic pattern to the two-gate structure shown on the right, the LES length is represented by the dashed box L1. And in this embodiment, from Figures 6 - 10 , the LES length is represented by the dashed box L2. By comparison, it can be seen that the LES length is significantly reduced. Experiments show that the LES length is reduced by about 25%, and the dimensional accuracy at the end of the line is improved by about 20%. Electrical tests show that the Vt shift of the MOSFET also decreases, indicating that the stability of the gate structure is significantly improved.

[0071] In this embodiment, after fabricating the gate structure, the source and drain can be deposited subsequently, and finally the MOSFET is obtained.

[0072] The semiconductor structure preparation method of the present disclosure embodiment is applied to the SRAM (Static Random-Access Memory) manufacturing process. At this time, the semiconductor material layer is the material layer for forming the SRAM structure, and the patterned structure is used to form the gate and / or interconnect pattern.

[0073] Different from the preparation of the gate structure, the semiconductor material layer of the SRAM structure includes a polysilicon layer and a silicon oxide layer (as an isolation layer). The polysilicon layer is deposited by LPCVD under the same conditions as in the above embodiment, and the silicon oxide layer can be formed by a thermal oxidation process.

[0074] In this embodiment, a nitrogen-free DARC layer is deposited by PECVD. The reaction gases are SiH 4 and CO 2 , to form a SiOC layer as the nitrogen-free DARC layer. The reaction equation is as follows:

[0075] SiH 4 +CO 2 →(Plasma heat)SiOC + by-products (H 2 , CO, etc.).

[0076] The nitrogen-free process avoids the introduction of nitrogen atoms and reduces the defects in the film layer, but some Si-H bonds still remain.

[0077] After that, after processes such as light irradiation and etching, SRAM patterning is completed. The final patterned structure can be the gate structure, interconnect structure, etc. in SRAM. SRAM patterning is completed.

[0078] The test results show that the LES effect of SRAM is reduced by about 30%, and the mismatch rate of SRAM cells also drops significantly, significantly improving the matching and reliability of memory cells.

[0079] The method for preparing a semiconductor structure according to the embodiments of the present disclosure can also be used in etching scenarios directly using a DARC layer as a mask on a substrate, such as shallow trench isolation or fin (Fin) structures.

[0080] Taking the etching of shallow trenches directly on a silicon substrate as an example, it is used for STI (Shallow Trench Isolation) manufacturing. In this embodiment, a DARC layer is directly deposited on the substrate, and after processes such as light irradiation and etching, shallow trenches are formed in the substrate.

[0081] Experiments show that the perpendicularity of the sidewalls of the shallow trenches is improved, the depth error is reduced, and the STI isolation performance is improved.

[0082] The method for preparing a semiconductor structure according to the embodiments of the present disclosure is used for fabricating the Fin structure in FinFet. It includes depositing fin structure materials by epitaxial growth on a substrate as a semiconductor material layer, and then using processes such as DARC layer deposition, light irradiation, and etching to finally obtain a patterned Fin structure. Finally, the LES of the Fin structure is reduced, and the switching performance of the FinFet device is improved, and the stability is significantly enhanced.

[0083] In modern semiconductor processes, the patterning of metal interconnect structures (such as copper or aluminum wires and vias) and dielectric layers (such as silicon oxide, low-k dielectrics) usually involves photolithography and etching steps. As a versatile material, DARC, in addition to its common use in gate manufacturing, may also be used as a hard mask in the following metal interconnect and dielectric layer related scenarios:

[0084] The semiconductor structure testing method provided by the embodiments of the present disclosure can also be used for preparing metal interconnect structures. In the metal interconnect process, vias or trenches need to be etched in the inter-layer dielectric (Inter-Layer Dielectric, ILD) to embed metals (such as copper dual damascene process).

[0085] In this embodiment, the semiconductor material layer is a dielectric layer (such as SiO 2Or a low-k material), the DARC layer can be deposited on the dielectric layer to reduce the standing wave effect in lithography as an anti-reflection coating, and at the same time act as a hard mask during dry etching to protect the bottom dielectric layer and control the etching profile.

[0086] After processes such as deposition, light irradiation, and etching of the DARC layer, vias or trenches are finally obtained as the patterned structure in the dielectric layer, and the vias or trenches are used to fill the metal interconnect structure. The DARC layer acts as a hard mask in the processing of the metal interconnect structure and the dielectric layer, especially in the etching of the dielectric layer (such as vias or trenches), to improve the etching accuracy and pattern transfer quality. However, its specific uses and process stages are different from those in gate manufacturing: in the gate process, DARC mainly protects polysilicon, while in the interconnect process, the DARC layer protects or patterns the dielectric layer.

[0087] As can be seen from the above, the method for preparing the semiconductor structure of this embodiment has strong universality and is applicable to any dry etching process using the DARC layer as a hard mask, including scenarios such as gate structures, SRAMs, and FinFETs.

[0088] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a semiconductor material layer; Depositing a dielectric anti-reflection layer on the semiconductor material layer, wherein the gas used to deposit the dielectric anti-reflection layer includes SiH4; irradiating the dielectric anti-reflection layer with light to break Si-H bonds in the dielectric anti-reflection layer; Etching the dielectric anti-reflection layer after light irradiation to form a patterned dielectric anti-reflection layer, and etching the semiconductor material layer using the patterned dielectric anti-reflection layer as a mask to form a patterned structure; The patterned dielectric anti-reflective layer is removed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The dielectric anti-reflection layer is irradiated with light having a wavelength of 200-400 nm.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the dielectric anti-reflection layer is 4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The duration of the light irradiation is 90-130s.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The dielectric anti-reflective layer is deposited on the semiconductor material layer using a plasma enhanced chemical vapor deposition process.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The gas used to deposit the dielectric anti-reflection layer further includes at least one of N2, NH3, N2O and CO2.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The semiconductor structure preparation method is applied to the SRAM manufacturing process, and the semiconductor material layer is used to form the SRAM structure.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The semiconductor material layer is a polysilicon layer, and the patterned structure serves as a gate structure of a MOSFET; and / or The semiconductor material layer is a dielectric layer, the patterned structure is a through hole or a groove, and the through hole or the groove is used to fill a metal interconnection structure.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The semiconductor material layer is a substrate, and the patterned structure is a shallow trench or a Fin structure located in the substrate.

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