Semiconductor element with filling layer and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor element comprises a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed within the bottom and on opposite sides of the gate electrode; an isolation layer disposed over the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a plurality of conductive plugs disposed in the isolation layer and electrically coupled to the metal contacts; a contact pad surrounding the conductive plug; and the filling layer is arranged in the isolation layer. The filling layer contains boron carbonitride.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 2024103435437, filed on March 25, 2024, with the invention title of "Semiconductor Element with Filling Layer and Its Manufacturing Method". Application No. 2024103435437 claims the priority and benefits of US Formal Application No. 18 / 534,948, filed on December 11, 2023. The content of this US Formal Application is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a manufacturing method thereof. In particular, it relates to a semiconductor element with a filling layer and a manufacturing method of the semiconductor element with the filling layer. Background Art

[0003] Semiconductor elements are used in different electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor elements is gradually getting smaller to meet the increasing demand for computing power. However, during the process of reducing the size, different problems are increasing, and such problems are still continuously increasing. Therefore, there are still challenges in achieving improved quality, yield, performance, reliability, and reducing complexity.

[0004] The above "Prior Art" description only provides background art and does not admit that the above "Prior Art" description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "Prior Art" should not be taken as any part of this case. Summary of the Invention

[0005] An embodiment of the present disclosure provides a semiconductor element, including a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolation layer disposed above the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a contact pad disposed in the isolation layer; a plurality of conductive plugs disposed in the isolation layer and surrounded by the contact pad, and electrically coupled to the metal contacts; and a filling layer disposed within the isolation layer. The filling layer contains boron carbonitride.

[0006] Another embodiment of the present disclosure provides a semiconductor device, comprising a substrate; a device element disposed on the substrate; a first insulating layer disposed on the substrate and covering the device element; a second insulating layer disposed on the first insulating layer; a plurality of first wires and a plurality of second wires disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer and covering the plurality of first wires and the plurality of second wires; and a filling layer disposed on the second insulating layer and within the third insulating layer. The filling layer comprises boron carbonitride.

[0007] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising providing a substrate; forming a gate electrode above the substrate; forming a source region and a drain region in the substrate; depositing an isolation layer above the substrate and the gate electrode; providing a patterned photoresist above the isolation layer; forming a plurality of contact holes in the isolation layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; forming a contact pad in the contact holes; forming a plurality of conductive plugs in the contact holes, wherein the plurality of conductive plugs are surrounded by the contact pad; and forming a filling layer in the isolation layer. The filling layer comprises boron carbonitride.

[0008] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising forming a first wire including a first protruding portion at a side of the first wire; forming a second wire including a second protruding portion at a side of the second wire, wherein the second protruding portion faces the first protruding portion; and forming a filling layer between the first protruding portion and the second protruding portion, wherein the filling layer comprises boron carbonitride.

[0009] Due to the design of the semiconductor device of the present disclosure, by adopting a filling layer having a low dielectric constant and an air gap, the parasitic capacitance between a conductive structure including a conductive plug and an adjacent conductive structure including another conductive plug can be reduced. As a result, the performance of the semiconductor device can be improved.

[0010] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent structures cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. Description of the Drawings

[0011] When combined with the accompanyingFigure 1 When starting to read, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that according to the standard practices in the industry, the various features are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0012] Figure 1 is a process schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 2 to 20 is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 21 is a process schematic diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 22 is a top-view schematic diagram illustrating an intermediate semiconductor device according to another embodiment of the present disclosure.

[0016] Figure 23 is a cross-sectional schematic diagram illustrating Figure 22 the cross-section along the cutting line A-A' in

[0017] Figure 24 is a top-view schematic diagram illustrating an intermediate semiconductor device according to another embodiment of the present disclosure.

[0018] Figure 25 is a cross-sectional schematic diagram illustrating Figure 24 the cross-section along the cutting line A-A' in

[0019] Figure 26 is a cross-sectional schematic diagram illustrating Figure 24 the cross-section along the cutting line B-B' in

[0020] Figure 27 is a top-view schematic diagram illustrating an intermediate semiconductor device according to another embodiment of the present disclosure.

[0021] Figure 28 is a cross-sectional schematic diagram illustrating Figure 27 the cross-section along the cutting line A-A' in

[0022] Among them, the reference numerals are explained as follows:

[0023] 1A: Semiconductor device

[0024] 1B: Semiconductor device

[0025] 10: Fabrication method

[0026] 10': Fabrication method

[0027] 20: Array region

[0028] 30: Peripheral region

[0029] 101: Substrate

[0030] 103: Device element

[0031] 105: First insulating layer

[0032] 107: Second insulating layer

[0033] 109: Third insulating layer

[0034] 201: First wire

[0035] 201E: End portion

[0036] 201P: First protruding portion

[0037] 201S-1: Side

[0038] 201S-3: Side

[0039] 203: Second wire

[0040] 203P: Second protruding portion

[0041] 203S-1: Side

[0042] 203S-3: Side

[0043] 210: Substrate

[0044] 211: Front surface

[0045] 212: Active region

[0046] 214: Isolation region

[0047] 220: Gate structure

[0048] 222: Gate dielectric

[0049] 223: Sidewall

[0050] 224: Gate electrode

[0051] 225: Sidewall

[0052] 226: Upper surface

[0053] 230: Gate spacer

[0054] 240: Source region

[0055] 242: Drain region

[0056] 250: Metal-oxide-semiconductor (MOS) transistor

[0057] 260: Isolation layer

[0058] 270: Lower dielectric layer

[0059] 272: Upper surface

[0060] 274: Side wall

[0061] 280: Upper dielectric layer

[0062] 281: Lower surface

[0063] 282: Upper surface

[0064] 284: Side wall

[0065] 290: Patterned photoresist

[0066] 300: Contact hole

[0067] 301: Air gap

[0068] 301P: Top

[0069] 310: Metal layer

[0070] 320: Metal contact

[0071] 322: Upper surface

[0072] 324: Upper surface

[0073] 330: Contact pad

[0074] 335: Barrier layer

[0075] 340: Conductive material

[0076] 350: Conductive plug

[0077] 352: End face

[0078] 354: End face

[0079] 400: Filling material layer

[0080] 401: Filling layer

[0081] 402: Filling layer

[0082] 410: Hard mask

[0083] 801: Air gap

[0084] BS: Lower surface

[0085] D1: Distance

[0086] D2: Distance

[0087] E1: Etching process

[0088] P1: Part

[0089] S1: Space

[0090] S11: Step

[0091] S13: Step

[0092] S15: Step

[0093] S17: Step

[0094] S21: Step

[0095] S23: Step

[0096] S25: Step

[0097] VL: Vertical plane

[0098] VL1: Vertical plane

[0099] W1: Width

[0100] W2: Width

[0101] X: Second direction

[0102] Y: First direction

[0103] Z: Direction Detailed implementation manners

[0104] The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include an embodiment where the first and second components are in direct contact, or it may include an embodiment where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of this repetition is to simplify and clarify, and unless otherwise specified in the text, it does not itself represent a specific relationship between various embodiments and / or the configurations discussed.

[0105] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures with another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0106] It should be understood that when a component is "on" another component, "connected to" another component, and / or "coupled to" another component, embodiments may include those where the components are in direct contact, and may also include embodiments where additional components are between the components such that the components are not in direct contact.

[0107] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the inventive concept of progressiveness.

[0108] Unless otherwise indicated in the context, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same", "equal", "planar", or "coplanar" as used herein do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean within acceptable variations, including nearly identical orientation, layout, location, shape, size, amount, or other measure, and for example, such acceptable variations may occur due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar means exactly the same, equal, or planar, or it may be the same, equal, or planar within acceptable variations, and for example, such acceptable variations may occur due to manufacturing processes.

[0109] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0110] It should be understood that in the description of the present disclosure, the direction above (or up) corresponds to the direction of the Z-direction arrow, and the direction below (or down) corresponds to the opposite direction of the Z-direction arrow.

[0111] Figure 1 is a process schematic diagram illustrating a method for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 20 is a cross-sectional schematic diagram illustrating the process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0112] Please refer toFigures 1 to 5 In step S11, a substrate 210 can be provided. A gate structure 220 and a gate spacer 230 can be formed over the substrate 210. A source region 240 and a drain region 242 can be formed in the substrate 210. A lower dielectric layer 270 covering the substrate 210, the gate structure 220 and the gate spacer 230 can be formed, and an upper dielectric layer 280 can be formed over the gate structure 220, the gate spacer 230 and the lower dielectric layer 270.

[0113] Please refer to Figure 2 The substrate 210 can be provided. In some embodiments, the substrate 210 is a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 210 includes a plurality of active regions 212 (only one active region 212 is shown for simplicity) Figure 2 and a plurality of isolation regions 214. In some embodiments, the isolation regions 214 can be formed in the substrate 210 to isolate the active regions 212. In some embodiments, the isolation regions 214 use shallow trench isolation (STI) technology to define and electrically isolate the active regions 212. In some embodiments, the isolation regions 214 are STI regions. In some embodiments, the isolation regions 214 include silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric materials, or combinations thereof. In some embodiments, the formation of the isolation regions 214 includes patterning the substrate 210 by a lithography process, etching one or more trenches 216 in the substrate 210 (e.g., by a dry etching process, a wet etching process, and / or a plasma etching process), and filling the trenches 216 with one or more dielectric materials 218 (e.g., by a chemical vapor deposition process). In some embodiments, the isolation regions 214 are connected to a front surface 211 of the substrate 210.

[0114] In some embodiments, the gate structure 220 and the gate spacer 230 may be formed over the substrate 210. In some embodiments, the gate structure 220 includes a gate dielectric 222 disposed on the front surface 211 and a gate electrode 224 disposed over the gate dielectric 222. In some embodiments, the gate dielectric 222 includes silicon dioxide. In some embodiments, the fabrication technique of the gate dielectric 222 may include chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, thermal oxidation process, or similar processes. In some embodiments, the gate electrode 224 includes polysilicon. In some embodiments, the fabrication technique of the gate electrode 224 may include CVD process, physical vapor deposition (PVD) process, ALD process, or other suitable processes. In some embodiments, the formation of the gate dielectric 222 and the gate electrode 224 includes forming a blanket gate dielectric layer over the substrate 210 and forming a blanket gate electrode layer over the blanket gate dielectric layer, and then performing a patterning process and an etching process to remove some portions of the blanket gate dielectric layer and some portions of the blanket gate electrode layer. Thus, the gate dielectric 222 and the gate electrode 224 can be formed.

[0115] In some embodiments, the gate spacer 230 is disposed on the front surface 211 of the substrate 210, on sidewalls 223 of the gate dielectric 222, and on sidewalls 225 of the gate electrode 224. In some embodiments, the fabrication technique of the gate spacer 230 may include using a CVD process to deposit a dielectric layer to cover the front surface 211, the gate dielectric 222, and the gate electrode 224, and then using an anisotropic etching process to pattern the dielectric layer to remove the horizontal portions of the dielectric layer, while retaining the vertical portions of the dielectric layer on the sidewalls 223 and 225 of the gate dielectric 222 and the gate electrode 224 to form the gate spacer 230. In some embodiments, the gate spacer 230 includes an oxide or a nitride. In some embodiments, the gate spacer 230 includes silicon dioxide or silicon nitride.

[0116] Please refer to Figure 3 , in some embodiments, the source region 240 and the drain region 242 may be formed in the substrate 210. In some embodiments, the source region 240 and the drain region 242 are disposed on opposite sides of the gate electrode 224. In some embodiments, the formation process of the source region 240 and the drain region 242 includes forming a photoresist on the front surface 211, and then performing implantation to form the source region 240 and the drain region 242 in the substrate 210. Thus, a metal oxide semiconductor (MOS) transistor 250 including the gate electrode 224, the source region 240, and the drain region 242 can be formed. In some embodiments, the source region 240 and the drain region 242 are connected to the front surface 211.

[0117] Please refer to Figure 4 , in some embodiments, the lower dielectric layer 270 is deposited over the MOS transistor 250. In some embodiments, the lower dielectric layer 270 covers the substrate 210, the gate structure 220, and the gate spacer 230. In some embodiments, the lower dielectric layer 270 includes an oxide. In some embodiments, the lower dielectric layer 270 is a spin-on dielectric layer using spin-on technology. In some embodiments, a chemical mechanical polishing (CMP) process is used to provide a planar topography such that an upper surface 272 of the lower dielectric layer 270 is substantially coplanar with an upper surface 226 of the gate electrode 224. In some embodiments, the upper surface 226 of the gate electrode 224 is exposed through the lower dielectric layer 270.

[0118] Please refer to Figure 5 , in some embodiments, the upper dielectric layer 280 is deposited over the lower dielectric layer 270. In some embodiments, the upper dielectric layer 280 includes an oxide. In some embodiments, the upper dielectric layer 280 covers the lower dielectric layer 270 and the gate electrode 224. In some embodiments, the fabrication technique of the upper dielectric layer 280 may include a CVD process. In some embodiments, the lower dielectric layer 270 and the upper dielectric layer 280 may be collectively referred to as the isolation layer 260.

[0119] Refer to Figure 1 and Figures 6 to 11 , in step S13, a patterned photoresist 290 may be provided over the upper dielectric layer 280; a plurality of contact holes 300 may be formed to penetrate through the upper dielectric layer 280 and the lower dielectric layer 270; a metal layer 310 is deposited over the lower dielectric layer 270, over the upper dielectric layer 280, and in the contact holes 300; and a plurality of metal contacts 320 may be formed in the source region 240, the drain region 242, and the gate electrode 224.

[0120] Please refer to Figure 6 , in some embodiments, the fabrication technique of the patterned photoresist 290 may include disposing an unpatterned photoresist layer to completely cover the upper dielectric layer 280, and then removing some portions of the unpatterned photoresist layer according to a predetermined pattern, wherein the remaining portions of the unpatterned photoresist layer form the patterned photoresist 290.

[0121] Please refer to Figure 7, a etching process is performed to form a plurality of contact holes 300. In some embodiments, the etching process uses a patterned photoresist 290 to define the areas to be etched and protect other areas of the upper dielectric layer 280 and the lower dielectric layer 270. In some embodiments, after the etching process is performed, only some portions of the upper dielectric layer 280 and the lower dielectric layer 270 remain under the patterned photoresist 290. In some embodiments, the patterned photoresist 290 is used as a mask to etch the unwanted portions of the upper dielectric layer 280 and the lower dielectric layer 270. In some embodiments, the contact holes 300 can be formed to penetrate the upper dielectric layer 280 and the lower dielectric layer 270. In some embodiments, the contact holes 300 can be formed in the active region 212. In some embodiments, some portions of the gate electrode 224 and the front surface 211 connected to the source region 240 and the drain region 242 are exposed to the contact holes 300. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the patterned photoresist 290 is removed after the contact holes 300 are formed, as Figure 8 shown.

[0122] Please refer to Figure 9 , in some embodiments, a metal layer 310 is deposited over the lower dielectric layer 270, over the upper dielectric layer 280, and in the contact holes 300. In some embodiments, the metal layer 310 is disposed on the upper surface 226 of the gate electrode 224, on a sidewall 274 of the lower dielectric layer 270, on a sidewall 284 of the upper dielectric layer 280, and on an upper surface 282 of the upper dielectric layer 280. In some embodiments, the metal layer 310 has a uniform thickness. In some embodiments, the metal layer 310 includes titanium. In some embodiments, the metal layer 310 includes cobalt.

[0123] Please refer to Figure 10 and Figure 11 , a heat treatment is performed to react at least some portions of the metal layer 310 with the gate electrode 224 and the substrate 210 in the source region 240 and the drain region 242 to form a plurality of metal contacts 320. In some embodiments, the metal contacts 320 are metal silicide contacts. In some embodiments, the heat treatment for forming the metal contacts 320 is preferably a rapid thermal annealing (RTA) process. In some embodiments, after the metal contacts 320 are formed, the unreacted portions of the metal layer 310 disposed above the upper surface 282 and on the sidewalls 274 and 284 are removed using a wet etching process, as Figure 11 shown.

[0124] Please refer to Figure 11, in some embodiments, the fabrication technique of the metal contact 320 located in the gate electrode 224 may include reacting the metal layer 310 with the gate electrode 224, and the fabrication technique of the metal contact 320 located in the source region 240 and the drain region 242 may include reacting the metal layer 310 with the substrate 210. In some embodiments, the metal contact 320 includes titanium silicide or cobalt silicide, wherein the contact resistance of cobalt silicide is lower than that of titanium silicide. In some embodiments, an upper surface 322 of the metal contact 320 buried in the gate electrode 224 is coplanar with an upper surface 272 of the lower dielectric layer 270. In some embodiments, each upper surface 324 of the metal contact 320 buried in the source region 240 and the drain region 242 is coplanar with the front surface 211. In some embodiments, at the interfaces between the substrate 210 and the conductive plugs (described below) and between the gate electrode 224 and the conductive plugs, the metal silicide contacts provide greater conductivity than contacts without silicide.

[0125] Please refer to Figure 1 and Figures 12 to 16 , in step S15, a contact pad 330 may be formed in the contact hole 300, a barrier layer 335 may optionally be formed in the contact hole 300, and a plurality of conductive plugs 350 may be formed in the contact hole 300 and surrounded by the contact pad 330.

[0126] Please refer to Figure 12 , in some embodiments, the contact pad 330 is deposited above the upper dielectric layer 280 and in the contact hole 300. In some embodiments, the contact pad 330 is disposed on the upper surface 282 of the upper dielectric layer 280, on the upper surfaces 322 and 324 of the metal contact 320, and on the sidewalls 274 and 284 of the lower dielectric layer 270 and the upper dielectric layer 280. In some embodiments, the contact pad 330 has a uniform thickness. In some embodiments, the contact pad 330 includes a nitride. In some embodiments, the contact pad 330 includes silicon nitride.

[0127] Please refer to Figure 12 and Figure 13, in some embodiments, a portion of the contact pad 330 is removed. In some embodiments, the portions of the contact pad 330 disposed on the upper surface 282 and the metal contact 320 are removed, while the portions of the contact pad 330 disposed on the sidewalls 274 and 284 are left in place. In some embodiments, an anisotropic etching process is used to remove this portion of the contact pad 330. In some embodiments, after performing the etching process, the upper surface 282 and the metal contact 320 are exposed via the contact pad 330. In some embodiments, the remaining portion of the contact pad 330 is used to reduce the diameter of each contact hole 300 to form a conductive plug, as described below. Specifically, the contact hole 300 for depositing the conductive plug is initially formed with a diameter larger than the diameter specified in the design rules or design guidelines to allow for the fabrication of the metal contact 320, and then the contact pad 330 is used to reduce the diameter of the contact hole 300 to meet the requirements of the design rules or design guidelines.

[0128] Please refer to Figure 14 , in some embodiments, the barrier layer 335 is optionally deposited above the upper dielectric layer 280 and in the contact holes 300, where the barrier layer 335 is surrounded by the contact pad 330. In some embodiments, the barrier layer 335 has a uniform thickness. In some embodiments, the barrier layer 335 covers the upper surface 282 of the upper dielectric layer 280 and the contact pad 330. In some embodiments, the barrier layer 335 includes titanium.

[0129] Please refer to Figure 14 and Figure 15 , in some embodiments, a conductive material 340 is deposited above the barrier layer 335 and in the contact holes 300. In some embodiments, the conductive material 340 has a thickness sufficient to fill the contact holes 300. In some embodiments, the conductive material 340 includes tungsten. In some embodiments, the conductive material 340 includes copper. In some embodiments, the conductive material 340 is electrically coupled to the metal contact 320 via the barrier layer 335.

[0130] Please refer to Figure 16 , in some embodiments, a planarization process is performed. In some embodiments, the planarization process is performed to remove the excess portion of the conductive material 340 above the upper surface 282, while the remaining portion of the conductive material 340 forms a plurality of conductive plugs 350 surrounded by the contact pad 330. In some embodiments, one end face 352 of each conductive plug 350 is coplanar with the upper surface 282, and the other end face 354 of each conductive plug 350 is electrically coupled to the metal contact 320 via the barrier layer 335. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0131] Please refer to Figure 1 andFigures 17 to 20 In step S17, a hard mask 410 can be provided, a filling layer 401 can be formed in the upper dielectric layer 280, and an air gap 301 can be formed in the filling layer 401.

[0132] Please refer to Figure 17 In some embodiments, the hard mask 410 can be disposed above the isolation layer 260. In some embodiments, the hard mask 410 is used as an etching mask to perform an etching process E1. In some embodiments, the fabrication technique of the hard mask 410 can include disposing a hard mask material above the upper dielectric layer 280, the contact pad 330, the barrier layer 335, and the conductive plug 350, and then providing a patterned mask (not shown) on the hard mask material, such as a patterned photoresist having a predetermined pattern. Subsequently, a lithography process including an exposure process, a post-bake process, and a development process is performed on the patterned photoresist, and a hard mask etching process is performed on the hard mask material using the developed photoresist as a mask. Thus, the hard mask 410 having a predetermined pattern can be formed. In some embodiments, the hard mask material can be a material having an etching selectivity to the upper dielectric layer 280. In some embodiments, the hard mask material can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. In some embodiments, the patterned mask (i.e., the patterned photoresist) is removed after the hard mask is formed.

[0133] In some embodiments, the hard mask 410 is used as an etching mask to perform the etching process E1. In some embodiments, a portion P1 (indicated by the dashed line in Figure 17 ) of the upper dielectric layer 280 is removed by the etching process E1. In some embodiments, the etching process E1 can be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the hard mask 410 is removed after the etching process E1 is performed.

[0134] Please refer to Figure 18 In some embodiments, a space S1 can be formed after the portion P1 of the upper dielectric layer 280 is removed. In some embodiments, a lower surface BS of the space S1 can be at a higher vertical plane VL than a lower surface 281 of the upper dielectric layer 280.

[0135] Please refer to Figure 19, in some embodiments, a filler material layer 400 may be formed to cover the upper surface 282 of the upper dielectric layer 280 and partially fill the space S1 in the upper dielectric layer 280. The remaining empty portion of the space S1 may be referred to as an air gap 301. For example, the filler material layer 400 may be formed at a relatively high deposition rate near each apex angle of the upper dielectric layer 280 adjacent to the space S1. As a result, the filler material layer 400 near each apex angle of the upper dielectric layer 280 adjacent to the space S1 may be sealed first to create the air gap 301. In some embodiments, a top 301P of the air gap 301 may be at a vertical plane VL1 lower than the upper surface 282 of the upper dielectric layer 280. In some embodiments, the filler material 400 may include boron carbonitride.

[0136] In some embodiments, a pretreatment process may be applied to the space S1 before forming the filler material layer 400. Due to the pretreatment of the surface of the space S1, the adhesiveness of the filler material layer 400 may be improved by creating a favorable interface between the surface of the space S1 (e.g., the exposed surface of the upper dielectric layer 280) and the filler material layer 400. The pretreatment process may be or may include a heat treatment process or a plasma enhanced process. As described below, the processing conditions may be maintained during the formation of the filler material layer 400, which may be beneficial to the formation of the filler material layer 400. In some embodiments, the pretreatment process may include delivering a hydrogen-containing precursor, a nitrogen-containing precursor, or some other precursor. Exemplary precursors may include hydrogen, ammonia, or other hydrogen-containing or nitrogen-containing precursors, and other materials that can be used to pretreat the surface of the space S1.

[0137] In some embodiments, the formation of the filler material layer 400 may include providing a first precursor to the surface of the space S1, generating a capacitively coupled plasma of the first precursor, and forming the filler material layer 400.

[0138] In some embodiments, the first precursor may include boron, carbon, and / or nitrogen. Non-limiting exemplary precursors may be or may include tris(dimethylamino)borane, dimethylamine borane, trimethylamine borane, triethylamine borane, tetra(dimethylamino)diborane, or any other precursor including one or more of boron, carbon, and / or nitrogen. Additional precursors may be included in some embodiments to adjust the atomic ratio. For example, additional hydrogen-containing precursors, carbon-containing precursors such as hydrocarbon molecules, or nitrogen-containing precursors such as nitrogen gas and ammonia may be included together with a carrier gas or an inert gas, such as helium, neon, argon, krypton, xenon, or nitrogen.

[0139] In some embodiments, a co-reactant may be included during the formation of the filler material layer 400. The co-reactant may include carbon dioxide, carbon monoxide, water, methanol, oxygen, ozone, nitrous oxide, or combinations thereof. Such materials can be used as nitriding agents, oxidizing agents, reducing agents, etc. In some embodiments, the co-reactant may be used to adjust the amount of carbon in the filler material layer 400. In certain cases, the co-reactant may be used to adjust the amount of nitrogen or oxygen in the filler material layer 400. In some embodiments, the co-reactant may be introduced together with the first precursor, e.g., without direct exposure to the plasma.

[0140] The plasma power at which this process is performed can affect the growth of the layer (i.e., the filler material layer 400), as well as various properties of the layer. For example, the incorporation of carbon within the layer can allow for a reduction in the dielectric constant by incorporating additional methyl groups within the layer. However, during plasma processing, the methyl moieties can decompose relatively easily, and then the carbon can simply be evacuated from the processing chamber. Additionally, as the plasma power increases, the bombardment of the layer can increase, which can remove pores and densify the layer, and can further increase the dielectric constant of the layer. Thus, in some embodiments, the plasma can be generated at a plasma power of less than or about 500 W, and can be generated at less than or about 450 W, less than or about 400 W, less than or about 350 W, less than or about 300 W, less than or about 250 W, less than or about 200 W, less than or about 150 W, less than or about 100 W, less than or about 50 W, or less.

[0141] Similarly, the pressure at which this process is performed can also affect various aspects of the process. For example, as the pressure increases, the absorption of atmospheric water may increase, which may increase the dielectric constant of the layer. When maintaining a lower pressure, the hydrophobicity of the layer can increase. Thus, in some embodiments, the pressure can be maintained at less than or about 10 Torr to produce a sufficiently low dielectric constant, and the pressure can be maintained at less than or about 9 Torr, less than or about 8 Torr, less than or about 7 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, less than or about 0.5 Torr, or less. However, to maintain plasma parameters to facilitate the formation of the layer, the pressure can be maintained at greater than or about 0.5 Torr, and can be maintained at greater than or about 1 Torr or more.

[0142] In some embodiments, the process temperature during the formation of the filler material layer 400 can be maintained at a temperature below or about 500 °C, and in some embodiments can be maintained at below or about 475 °C, below or about 450 °C, below or about 425 °C, below or about 400 °C, below or about 375 °C, below or about 350 °C, below or about 325 °C, below or about 300 °C, below or about 275 °C, below or about 250 °C, below or about 225 °C, below or about 200 °C, below or about 175 °C, below or about 150 °C, below or about 125 °C, below or about 100 °C, below or about 75 °C, or lower.

[0143] In some embodiments, a boron concentration of the filler material layer 400 can be greater than or about 30%, and can be greater than or about 32%, greater than or about 34%, greater than or about 36%, greater than or about 36%, greater than or about 38%, greater than or about 40%, greater than or about 42%, greater than or about 44%, greater than or about 46%, or greater. Similarly, a carbon concentration of the filler material layer 400 can be greater than or about 12%, and can be greater than or about 14%, greater than or about 16%, greater than or about 18%, greater than or about 20%, greater than or about 22%, greater than or about 24%, greater than or about 26%, greater than or about 28%, greater than or about 30%, or greater. A nitrogen concentration of the filler material layer 400 can be greater than or about 20%, and can be greater than or about 22%, greater than or about 24%, greater than or about 26%, greater than or about 28%, greater than or about 30%, greater than or about 32%, greater than or about 34%, greater than or about 36%, greater than or about 38%, or more. Once exposed to the atmosphere, the filler material layer 400 can include any amount of oxygen incorporation, which can be maintained at less than or about 15%, and can be maintained at less than or about 14%, less than or about 13%, less than or about 12%, less than or about 11%, less than or about 10%, less than or about 9%, less than or about 8%, or less.

[0144] Although carbon or methyl can promote a lower dielectric constant within the filler material layer 400, the boron-nitrogen ratio within the film can affect the hardness and modulus of a layer. Thus, in some embodiments, the boron-nitrogen ratio can be maintained at greater than or about 1:1, and can be maintained at greater than or about 1.2:1, greater than or about 1.4:1, greater than or about 1.6:1, greater than or about 1.8:1, greater than or about 2:1, or greater. The carbon-boron ratio can also be beneficial to the beneficial properties of the filler material layer 400. For example, although the hardness and modulus can be improved when carbon is sufficiently combined with boron based on layer growth characteristics, the incorporation of carbon can have an adverse effect on the layer hardness in general.

[0145] In some embodiments, the dielectric constant of the filler material layer 400 can be less than or about 4.0, less than or about 3.9, less than or about 3.8, less than or about 3.7, less than or about 3.6, less than or about 3.5, less than or about 3.4, less than or about 3.3, less than or about 3.2, less than or about 3.1, less than or about 3.0, less than or about 2.9, less than or about 2.8, or less.

[0146] In some embodiments, the Young's modulus of the filler material layer 400 can be maintained at greater than or about 40 GPa, and can be maintained at greater than or about 42 GPa, greater than or about 44 GPa, greater than or about 46 GPa, greater than or about 48 GPa, greater than or about 50 GPa, greater than or about 52 GPa, greater than or about 54 GPa, greater than or about 56 GPa, greater than or about 58 GPa, greater than or about 60 GPa, greater than or about 62 GPa or greater. In some embodiments, the layer hardness of the filler material layer 400 can be maintained at greater than or about 4.0 GPa, and can be maintained at greater than or about 4.1 GPa, greater than or about 4.2 GPa, greater than or about 4.3 GPa, greater than or about 4.4 GPa, greater than or about 4.5 GPa, greater than or about 4.6 GPa, greater than or about 4.7 GPa, greater than or about 4.8 GPa, or greater. Such properties can be achieved without additional processing (such as ultraviolet irradiation or other processes).

[0147] Please refer to Figure 20 , a planarization process can be performed until the upper surface 282 of the upper dielectric layer 280 is exposed, converting the filler material layer 400 into a filler layer 401 in the upper dielectric layer 280. It should be understood that after the planarization process, the air gap 301 is not exposed. In other words, the air gap 301 is completely surrounded by the filler layer 401.

[0148] In some embodiments, the planarization process can include chemical mechanical polishing. In some embodiments, the planarization process can include an etch-back process. In some embodiments, during the etch-back, the etch rate ratio of the filler material layer 400 to the upper dielectric layer 280 can be between about 100:1 and about 3:1, between about 15:1 and about 3:1, or between about 10:1 and about 5:1.

[0149] Please refer to Figure 20 , a ratio of a width W2 of the filler layer 401 to a width W1 of the air gap 301 can be between about 50 and about 5, between about 40 and about 5, or between about 30 and about 5.

[0150] By employing the filler layer 401 and the air gap 301 with low dielectric constants, the parasitic capacitance between the conductive structure including the conductive plug 350 and the adjacent conductive structure including another conductive plug 350 can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0151] Figure 21 is a process schematic diagram, illustrating a method 10' for manufacturing a semiconductor element 1B according to another embodiment of the present disclosure. Figure 22 is a top view schematic diagram, illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 23 is a cross-sectional schematic diagram, illustrating Figure 22 the cross-section along the cutting line A-A' in. For clarity, Figure 22 some elements of the semiconductor element of the present disclosure are not shown in.

[0152] Please refer to Figures 21 to 23 , in step S21, in some embodiments, a substrate 101 may be provided, and a device element 103, a first insulating layer 105, and a second insulating layer 107 may be formed on the substrate 101. The substrate 101 may include an array region 20 and a peripheral region 30. The array region 20 may be surrounded by the peripheral region 30. The substrate 101 may include, for example, silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, indium arsenide, indium, or other semiconductor materials including group III, group IV, and group V elements. In some embodiments, the substrate 101 may include a silicon-on-insulator structure. For example, the substrate 101 may include a buried oxide layer formed using a process such as oxygen separation by implantation.

[0153] It should be understood that the array region 20 may include a part of the substrate 101 and a space above this part of the substrate 101. Describing an element as being disposed on the array region 20 means that the element is disposed on an upper surface of this part of the substrate 101. Describing an element as being disposed above the array region 20 means that the element is disposed above the upper surface of this part of the substrate 101. In some embodiments, describing an element as being disposed in the array region 20 means that the element is disposed in this part of the substrate 101; however, an upper surface of the element may be flush with the upper surface of this part of the substrate 101. In some embodiments, describing an element as being disposed in the array region 20 means that some parts of the element are disposed in the substrate 101 and other parts of the element are disposed on or above the substrate 101.

[0154] Therefore, the peripheral region 30 may include another part of the substrate 101 and a space above this other part of the substrate 101.

[0155] Please refer to Figure 22 and Figure 23, the device element 103 can be formed on the substrate 101. The device element 103 can be, for example, a bipolar junction transistor, a metal oxide semiconductor field effect transistor, a diode, a flash memory, a dynamic random access memory, a static random access memory, an electrically erasable programmable read-only memory, an image sensor, a microelectromechanical system, an active element or a passive element. The device element 103 can include a plurality of doped regions formed in the substrate 101. The plurality of doped regions can be doped with dopants such as phosphorus, arsenic, antimony or boron. For ease of description, only one device element 103 is described. It should be understood that in most cases, there can be more device elements 103 in the semiconductor element.

[0156] In some embodiments, an isolation layer ( Figure 23 not shown in the figure) can be formed in the substrate 101 and can insulate the plurality of doped regions of the device element 103 from adjacent doped regions. For example, the isolation layer can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate or the like. It should be understood that the silicon oxynitride of the present disclosure refers to a substance containing silicon, nitrogen and oxygen, and in which the proportion of oxygen is greater than that of nitrogen. The silicon nitride oxide is a substance containing silicon, oxygen and nitrogen, in which the proportion of nitrogen is greater than that of oxygen.

[0157] Please refer to Figure 22 and Figure 23 , in some embodiments, the first insulating layer 105 can be formed on the substrate 101 and can cover the device element 103. For example, the first insulating layer 105 can include silicon nitride, silicon oxide, silicon oxynitride, undoped quartz glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass or a combination thereof, but is not limited thereto. The first insulating layer 105 can be referred to as an interlayer dielectric.

[0158] Please refer to Figure 22 and Figure 23 , in some embodiments, the second insulating layer 107 can include a plurality of sub-layers. The plurality of sub-layers can be formed on the first insulating layer 105. Each of the plurality of sub-layers can have a thickness between about 0.5 micrometers and about 3.0 micrometers. For example, the plurality of sub-layers can include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, etc. or a combination thereof. The plurality of sub-layers can include different materials, but is not limited thereto. The low-k dielectric material can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material can have a dielectric constant less than 2.0. The second insulating layer 107 can be referred to as an interconnect layer.

[0159] Figure 24 is a top view schematic diagram illustrating an intermediate semiconductor element of another embodiment of the present disclosure. Figure 25 is a cross-sectional schematic diagram illustratingFigure 24 The cross-section of the center cutting line A-A'. Figure 26 It is a schematic cross-sectional view, illustrating Figure 24 the cross-section of the center cutting line B-B'. For clarity, some components of the semiconductor device of the present disclosure are not shown in Figure 24 it.

[0160] Please refer to Figure 21 and Figures 24 to 26 In step S23, in some embodiments, a plurality of conductive features may be formed above the substrate 101; specifically, a plurality of conductive features may be formed in and on the first insulating layer 105 and the second insulating layer 107. The plurality of conductive features may include, for example, wires, conductive vias, and conductive contacts. The conductive vias may connect adjacent wires along the Z direction. The conductive vias may improve heat dissipation in the semiconductor device and may provide structural support in the first insulating layer 105 and the second insulating layer 107. The device element 103 may be electrically coupled to the plurality of conductive features. For example, the plurality of conductive features may include copper, aluminum, titanium, etc. or a combination thereof. The wires, conductive vias, and conductive contacts may include different materials, but are not limited thereto.

[0161] In some embodiments, the element density of the array region 20 may be greater than the element density of the peripheral region 30. The element density may be a value defined by the number of elements (e.g., wires) formed in the array region 20 or the peripheral region 30 divided by the surface area of the array region 20 or the peripheral region 30 as viewed from a top view. From a cross-sectional view, a larger density may mean a smaller horizontal distance between adjacent elements. In other words, the array region 20 may be regarded as a dense region, while the peripheral region 30 may be regarded as a sparse region. More wires are shown in the figure to emphasize that the array region 20 is a dense region compared to the peripheral region 30.

[0162] For convenience and clarity of description, Figure 28 only the first wire 201 and the second wire 203 are labeled and described in detail in

[0163] Please refer to Figure 24 and Figure 25, the first conductor 201 may be formed on the second insulating layer 107 and may extend along the first direction Y. The first conductor 201 may include two side edges 201S-1, 201S-3 and a plurality of first protruding portions 201P. In some embodiments, the plurality of first protruding portions 201P may be located at the two side edges 201S-1, 201S-3 of the first conductor 201. The plurality of first protruding portions 201P at the side edge 201S-1 may be opposite to the plurality of first protruding portions 201P at the side edge 201S-3. In other words, viewed from a top view, the corresponding first protruding portions 201P on the two side edges 201S-1, 201S-3 may be located on a line parallel to the second direction X. Viewed from a top view, some of the plurality of first protruding portions 201P may be located at the end 201E of the first conductor 201, and some others of the plurality of first protruding portions 201P may be located at the middle of the first conductor 201. In some embodiments, the plurality of first protruding portions 201P located at the side edge 201S-1 may be offset from the plurality of first protruding portions 201P located at the side edge 201S-3. In some embodiments, the plurality of first protruding portions 201P may be provided only at the side edge 201S-3 facing the second conductor 203, as described below.

[0164] Please refer to Figure 24 and Figure 25 , in some embodiments, the second conductor 203 may be formed on the second insulating layer 107. The second conductor 203 may extend along the first direction Y and may be adjacent to the first conductor 201. In some embodiments, only a part of the second conductor 203 may be parallel and adjacent to the first conductor 201. In some embodiments, the second conductor 203 may be parallel and adjacent to only a part of the first conductor 201. The second conductor 203 may include two side edges 203S-1, 203S-3 and a plurality of second protruding portions 203P. In some embodiments, the plurality of second protruding portions 203P may be located at the two side edges 203S-1, 203S-3 of the second conductor 203. The plurality of second protruding portions 203P located at the side edge 203S-1 may respectively face the plurality of first protruding portions 201P located at the side edge 201S-3. The plurality of second protruding portions 203P at the side edge 203S-3 may be opposite to or offset from the plurality of second protruding portions 203P at the side edge 203S-1.

[0165] The space between the multiple first protruding portions 201P at the side 201S-3 and the multiple second protruding portions 203P at the side 203S-1 can be narrower than the space between the side 201S-3 of the first wire 201 and the side 203S-1 of the second wire 203. In other words, when viewed from a top view, the distance D1 between the multiple first protruding portions 201P located at the side 201S-3 and the multiple second protruding portions 203P located at the side 203S-1 can be less than the distance D2 between the side 201S-3 of the first wire 201 and the side 203S-1 of the second wire 203.

[0166] Please refer to Figure 24 and Figure 25 , in some embodiments, the multiple second protruding portions 203P located at the side 203S-1 can be offset from the multiple first protruding portions 201P located at the side 201S-3. The space between the side 201S-3 of the multiple second wires 203 and the multiple first protruding portions 201P at the side 203S-1 and the space between the side 203S-1 of the first wire 201 and the multiple second protruding portions 203P at the side 201S-3 can be narrower than the space between the side 201S-3 of the first wire 201 and the side 203S-1 of the second wire 203.

[0167] It should be understood that the directions of the first wire 201 and the second wire 203 are for illustrative purposes only. For example, the first wire 201 and the second wire 203 can extend along the second direction X. As another example, the first wire 201 and the second wire 203 can extend along a direction diagonal to both the first direction Y and the second direction X. In another example, when viewed from a top view, the first wire 201 and the second wire 203 can both be L-shaped. That is, the first wire 201 and the second wire 203 can extend along both the first direction Y and the second direction X at the same time. In another example, when viewed from a top view, the first wire 201 and the second wire 203 can be U-shaped, T-shaped, or other suitable shapes respectively.

[0168] Figure 27 is a top view schematic diagram illustrating an intermediate semiconductor element of another embodiment of the present disclosure. Figure 28 is a cross-sectional schematic diagram illustrating Figure 27 the cross-section along the cutting line A-A' in Figure 27 . For clarity, some elements of the semiconductor element of the present disclosure are not shown in

[0169] Please refer to Figure 21 and Figures 27 to 28, in step S25, in some embodiments, a third insulating layer 109 may be formed on the second insulating layer 107, a filling layer 402 may be formed in the third insulating layer 109, and a plurality of air gaps 801 may be formed in the filling layer 402.

[0170] Please refer to Figure 28 , the manufacturing technique of the third insulating layer 109 may include depositing an insulating material on the intermediate semiconductor element shown by, for example, a deposition process such as chemical vapor deposition. Figures 24 to 26 Subsequently, a planarization process, such as chemical mechanical polishing, may be performed until the upper surfaces of the first wire 201 and the second wire 203 are exposed, so as to remove the excess material and provide a substantially flat surface for subsequent processing steps. The insulating material may be the same as the material of the second insulating layer 107, but is not limited thereto.

[0171] Please refer to Figure 27 and Figure 28 , in some embodiments, the filling layer 402 may be formed between a plurality of first protruding portions 201P at the side 201S-3 and a plurality of second protruding portions 203P at the side 203S-1. The formation of the filling layer 402 and the plurality of air gaps 801 is similar to or the same as the formation of the filling layer 401 (as shown in Figures 17 to 20 ), and will not be elaborated herein. In some embodiments, the filling layer 402 may include boron carbonitride. It should be understood that after the planarization process, the air gaps 801 are not exposed. In other words, the air gaps 801 are completely surrounded by the filling layer 402.

[0172] An embodiment of the present disclosure provides a semiconductor element, including a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolation layer disposed above the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a contact pad disposed in the isolation layer; a plurality of conductive plugs disposed in the isolation layer and surrounded by the contact pad, and electrically coupled to the metal contacts; and a filling layer disposed in the isolation layer. The filling layer contains boron carbonitride.

[0173] Another embodiment of the present disclosure provides a semiconductor element, including a substrate; a device element disposed on the substrate; a first insulating layer disposed on the substrate and covering the device element; a second insulating layer disposed on the first insulating layer; a plurality of first wires and a plurality of second wires disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer and covering the plurality of first wires and the plurality of second wires; and a filling layer disposed on the second insulating layer and in the third insulating layer. The filling layer contains boron carbonitride.

[0174] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a gate electrode over the substrate; forming a source region and a drain region in the substrate; depositing an isolation layer over the substrate and the gate electrode; providing a patterned photoresist over the isolation layer; forming a plurality of contact holes in the isolation layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; forming a contact liner in the contact holes; forming a plurality of conductive plugs in the contact holes, wherein the plurality of conductive plugs are surrounded by the contact liner; and forming a filling layer in the isolation layer. The filling layer contains boron carbonitride.

[0175] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including forming a first wire including a first protruding portion located at a side of the first wire; forming a second wire including a second protruding portion located at a side of the second wire, wherein the second protruding portion faces the first protruding portion; and forming a filling layer between the first protruding portion and the second protruding portion, wherein the filling layer includes boron carbonitride.

[0176] Due to the design of the semiconductor device of the present disclosure, by adopting a filling layer having a low dielectric constant and an air gap, the parasitic capacitance between a conductive structure including a conductive plug and an adjacent conductive structure including another conductive plug can be reduced. As a result, the performance of the semiconductor device can be improved.

[0177] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0178] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can perform the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, comprising: providing a substrate; forming a gate electrode above the substrate; forming a source region and a drain region in the substrate; depositing an isolation layer over the substrate and the gate electrode; providing a patterned photoresist above the isolation layer; forming a plurality of contact holes in the isolation layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; forming a contact pad in the contact hole; forming a plurality of conductive plugs in the contact hole, wherein the plurality of conductive plugs are surrounded by the contact pad; and forming a filling layer in the isolation layer, The filling layer contains boron carbonitride.

2. The method of claim 1 , wherein forming the plurality of metal contacts in the gate electrode, the source region, and the drain region comprises: depositing a metal layer in the plurality of contact holes; performing a thermal treatment to react portions of the metal layer with the gate electrode and the substrate in the source region and the drain region to form the plurality of metal contacts; and An unreacted portion of the metal layer is removed.

3. The method of claim 1 , wherein forming the contact pad in the contact hole comprises: depositing the contact liner on an upper surface and sidewalls of the isolation layer and over upper surfaces of the metal contacts; and An etching process is performed to remove a portion of the contact pad, wherein the portion of the contact pad is disposed above the upper surface of the isolation layer and above the plurality of upper surfaces of the plurality of metal contacts.

4. The method of claim 1 , wherein depositing the isolation layer over the substrate and the gate electrode comprises: Depositing a dielectric layer over the substrate and the gate electrode; performing a grinding process to expose the gate electrode; and An upper dielectric layer is deposited over the lower dielectric layer and the gate electrode.

5. The preparation method according to claim 1, further comprising: A barrier layer is deposited in the plurality of contact holes, wherein the barrier layer is surrounded by the contact pad before forming the plurality of conductive plugs.

6. The preparation method according to claim 5, wherein forming the filling layer comprises: providing a hard mask over the isolation layer; performing an etching process to remove a portion of the isolation layer; depositing a filling material over the isolation layer, the contact pad, the barrier layer, and the plurality of conductive plugs, and in a space of the portion where the isolation layer is removed; and A planarization process is performed to remove the filling material above an upper surface of the isolation layer.

7. The preparation method according to claim 1, further comprising: Before forming the gate electrode, forming a gate dielectric on the substrate; and A gate spacer is formed on the gate electrode and the sidewalls of the gate dielectric.

8. The preparation method according to claim 1, further comprising: A plurality of isolation regions are formed in the substrate to define and electrically isolate one or more active regions including the gate electrode, the source region and the drain region.

9. The method of claim 8, wherein forming the plurality of isolation regions comprises: etching a plurality of trenches in the substrate; and The plurality of trenches are filled with one or more dielectric materials.

10. The preparation method according to claim 1, further comprising: A plurality of air gaps are formed in the filling layer, wherein each of the plurality of air gaps is surrounded by the filling layer.

11. A method for preparing a semiconductor element, comprising: forming a first conductive line including a first protruding portion located at a side edge of the first conductive line; forming a second conductive line including a second protruding portion located at a side edge of the second conductive line, wherein the second protruding portion faces the first protruding portion; as well as forming a filling layer between the first protruding portion and the second protruding portion, The filling layer includes boron carbonitride.

12. The preparation method according to claim 11, further comprising: An air gap is formed in the filling layer, wherein the air gap is surrounded by the filling layer. 13 . The manufacturing method according to claim 11 , wherein the first protrusion is formed at one end of the first conductive line, and the second protrusion is formed at one end of the second conductive line. 14 . The manufacturing method as claimed in claim 11 , wherein a distance between the first protruding portion and the second protruding portion is smaller than a distance between the first conductive line and the second conductive line. 15 . The manufacturing method of claim 12 , wherein a ratio of a distance between the first protruding portion and the second protruding portion to a width of the air gap is between about 5 and about 50, between about 5 and about 40, or between about 5 and about 30.

Images