Semiconductor device and manufacturing method thereof
By using atomic layer deposition technology and ion implantation process in semiconductor device manufacturing, a polysilicon film layer is formed and titanium azide and tungsten layers are stacked, which solves the problem of trench filling with a large aspect ratio, and achieves ultra-thin, uniform and dense film deposition, improving the performance and reliability of the device.
Patent Information
- Application Number
- CN202510282488.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-06-13
AI Technical Summary
In semiconductor device manufacturing, as the characteristic size of integrated circuits decreases and the problem of trench filling with large depth and aspect ratios is difficult, traditional processes cannot effectively deposit an ultra-thin polysilicon film layer with uniform thickness and good step coverage.
Atomic layer deposition technology combined with ion implantation technology is used to form a polysilicon film layer on the surface of the trench, and a titanium nitride layer and a tungsten layer are formed on its surface in turn to form a gate structure. The process includes steps such as online cleaning, cracking of precursor materials, purge of nitrogen and hydrogen, and online annealing to ensure the density and thickness control of the film layer.
A polysilicon film layer with uniform thickness and high density is deposited in trenches with a depth ratio of more than 10:1, which improves step coverage and conformity and meets the high performance needs of semiconductor devices.
Smart Images
Figure CN120149256A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor device manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] With the continuous reduction of the feature size of integrated circuits, lithography technology has developed to below the 14nm node. The sizes of holes and trenches are getting smaller and smaller, and the aspect ratio is getting larger and larger. The line width of the Shallow Trench Isolation (STI) etching trenches of Buried Channel Array Transistor (BCAT) devices has been as low as 25nm, the depth has reached 250nm, and the aspect ratio is 10:1. A polysilicon layer with a thickness of 1-2nm needs to be filled in the STI etching trenches of BCAT devices as a buffer layer for preparing silicon dioxide by the dry oxygen method later. The filling thickness of the polysilicon film layer in the STI trenches is also getting thinner and thinner, which poses higher requirements for the filling of the polysilicon film layer. It not only requires high thickness uniformity of the polysilicon film layer, but also good step coverage and conformal properties. The low-pressure chemical vapor deposition process cannot prepare a polysilicon film layer with such a thin thickness and cannot meet the filling of trenches with an aspect ratio of 10:1. Although the refractive index of the polysilicon film layer prepared by the physical vapor deposition process meets the requirements, its thickness is not easy to control, and there are also problems of poor step coverage and poor filling ability. Summary of the Invention
[0003] In order to overcome the above deficiencies in the prior art, the present application provides a semiconductor device and a method for manufacturing the same. The method includes:
[0004] Providing a substrate, the substrate including a first surface and a second surface opposite thereto;
[0005] Forming at least one trench on the first surface;
[0006] Using an ion implantation process to form a first source / drain region and a second source / drain region on both sides of the trench;
[0007] Using atomic layer deposition technology to form a polysilicon film layer on the surface of the trench;
[0008] Sequentially forming a titanium nitride layer and a tungsten layer on the surface of the polysilicon film layer, and the three layers are stacked to form a gate structure.
[0009] In some possible embodiments, the method of using atomic layer deposition technology to form a polysilicon film layer on the surface of the trench further includes:
[0010] Placing the substrate into a process chamber and cleaning the surface of the trench using the in-situ cleaning technology of atomic layer deposition technology;
[0011] Introduce a precursor material into the process chamber, and after the precursor material is pyrolyzed, silicon molecular clusters deposited on the trench are obtained;
[0012] Introduce nitrogen, hydrogen, and nitrogen into the process chamber in sequence, and after multiple cycles of purging, silicon atoms deposited on the trench are obtained;
[0013] Adopt the in-situ annealing technology of atomic layer deposition technology to obtain the polysilicon film layer.
[0014] In some possible implementation manners, the method of putting the substrate into the process chamber and cleaning the surface of the trench by using the in-situ cleaning technology of atomic layer deposition technology further includes:
[0015] Put the substrate into the process chamber;
[0016] According to the trench material and the type of oxide layer on its surface, adopt the in-situ plasma cleaning technology to bombard the wafer surface to remove the oxide layer;
[0017] Use an inert gas to purge the trench to remove residues.
[0018] In some possible implementation manners, the method of putting the substrate into the process chamber includes:
[0019] The substrate is transferred into the process chamber through an atomic layer deposition device;
[0020] Raise the temperature of the process chamber to 550°C - 650°C, keep it warm for 10 min - 20 min, and detect that the leak rate of the process chamber does not exceed 1*10 -7 mbar*l / s.
[0021] In some possible implementation manners, the precursor material includes trimethylchlorosilane, diethylaminosilane, or disilane.
[0022] In some possible implementation manners, the time for introducing the precursor material into the process chamber is 5 s - 10 s.
[0023] In some possible implementation manners, the method of introducing nitrogen, hydrogen, and nitrogen into the process chamber in sequence and obtaining silicon atoms deposited on the trench after multiple cycles of purging includes:
[0024] Introduce nitrogen to purge the trench for 2 s - 5 s;
[0025] Introduce hydrogen to reduce for 3 s - 6 s;
[0026] Introduce nitrogen again to purge the trench for 2 s - 5 s;
[0027] Repeat the above steps multiple times to obtain silicon atoms deposited on the trench.
[0028] In some possible embodiments, the method of obtaining a polysilicon film layer by in-situ annealing using atomic layer deposition technology further includes:
[0029] Use atomic layer deposition technology for in-situ annealing, with the annealing temperature being 500°C - 600°C and the annealing time being 20 min - 40 min;
[0030] Obtain the polysilicon film layer deposited on the substrate.
[0031] This application also provides a semiconductor device, which is fabricated using the manufacturing method of any one of the foregoing semiconductor devices. The semiconductor device includes:
[0032] A substrate, including a first source / drain region and a second source / drain region;
[0033] A trench, in the substrate and between the first source / drain region and the second source / drain region, and the first source / drain region is separated from the second source / drain region by the trench;
[0034] A gate electrode, including a polysilicon film layer, a titanium nitride layer, and a tungsten layer sequentially disposed on the surface of the trench.
[0035] In some possible embodiments, the aspect ratio of the trench is 10:1;
[0036] The thickness of the polysilicon film layer is 1 nm - 2 nm.
[0037] Compared with the prior art, this application has the following beneficial effects:
[0038] A semiconductor device and its manufacturing method provided by this application apply atomic layer deposition technology to the preparation of the polysilicon buffer layer of a buried channel array transistor (BCAT). This technology can deposit an ultra-thin and uniform polysilicon film layer, and at the same time achieve precise control of the thickness of the polysilicon buffer film layer; the prepared film layer structure is highly dense, showing excellent step coverage ability and good conformality; at the same time, it can fill trenches with an aspect ratio greater than 10:1. In addition, this technology can also effectively manage the number of particles in the cavity to ensure the cleanliness of the production environment. The traditional low-pressure chemical vapor deposition process cannot meet the filling function of the polysilicon buffer layer; the physical vapor deposition process is not easy to control the film layer thickness, and there are problems of poor step coverage and poor filling ability. This technical solution is more competitive in the preparation of the polysilicon buffer film layer and is an ideal choice for realizing large-scale mass production. Description of the Drawings
[0039] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related accompanying drawings can be obtained based on these drawings without creative efforts.
[0040] Figure 1 Schematic flow chart of the manufacturing method of the semiconductor device provided in this embodiment;
[0041] Figure 2 Schematic structural diagram of the semiconductor device corresponding to step S12 provided in this embodiment;
[0042] Figure 3 Schematic structural diagram of the semiconductor device corresponding to step S13 provided in this embodiment;
[0043] Figure 4 Schematic structural diagram of the semiconductor device corresponding to step S14 provided in this embodiment;
[0044] Figure 5 Schematic structural diagram of the semiconductor device corresponding to step S15 provided in this embodiment;
[0045] Figure 6 Schematic flow chart of step S14 provided in this embodiment;
[0046] Figure 7 Schematic flow chart of step S141 provided in this embodiment;
[0047] Figure 8 Schematic flow chart of step S1411 provided in this embodiment;
[0048] Figure 9 Schematic flow chart of step S143 provided in this embodiment;
[0049] Figure 10 Schematic flow chart of step S144 provided in this embodiment;
[0050] Figure 11 Schematic structural diagram of the trench and polysilicon film layer provided in this embodiment.
[0051] Icons: 10 - semiconductor device; 100 - substrate; 110 - first surface; 120 - second surface; 200 - trench; 310 - first source / drain region; 320 - second source / drain region; 400 - polysilicon film layer; 500 - titanium nitride layer; 600 - tungsten layer. Detailed implementation manners
[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. Usually, the components of the embodiments of this application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.
[0053] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts fall within the scope of protection of this application.
[0054] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0055] In the description of this application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is customarily placed during use. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.
[0056] In addition, the terms "horizontal", "vertical", "overhanging", etc. do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.
[0057] In the description of this application, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0058] The following will describe in detail the specific embodiments of the present application with reference to the accompanying drawings.
[0059] Through the research of the inventors, it is found that as the feature size of integrated circuits continues to shrink, when lithography technology develops below the 14nm node, the sizes of holes and trenches are getting smaller and smaller, the aspect ratio is getting larger and larger. The line width of the etched trench of the Buried Channel Array Transistor (BCAT) has been as low as 25nm, the depth reaches 250nm, and the aspect ratio is 10:1. A layer of polysilicon with a thickness of 1-2nm needs to be filled in the etched trench of the BCAT device to serve as a buffer layer for preparing silicon dioxide by the dry oxidation method later. This poses higher requirements for the filling of the polysilicon film layer, not only requiring high thickness uniformity of the polysilicon film layer, but also requiring good step coverage and good conformality, etc. The traditional low-pressure chemical vapor deposition process cannot prepare a polysilicon film layer with such a thin thickness, and cannot meet the filling of trenches with an aspect ratio of 10:1.
[0060] The present application provides a semiconductor device 10 and a manufacturing method thereof, which are applied to BCAT. Please refer to Figure 1 and the method includes the following steps.
[0061] Step S11, provide a substrate 100, where the substrate 100 includes a first surface 110 and a second surface 120 opposite thereto.
[0062] For example, provide a silicon substrate 100 to ensure that its surface is flat and defect-free, and then uniformly coat a photoresist selected according to the subsequent process requirements thereon. Then, use an ArF immersion lithography machine for exposure, and then put the silicon substrate 100 into a developer to remove the photoresist in the exposed area to form a pattern, preparing for the subsequent process.
[0063] Step S12, please refer to Figure 2 and form at least one trench 200 on the first surface 110.
[0064] For example, according to the patterning requirements, select dry etching to etch the silicon substrate 100 to remove the area not protected by the photoresist to form the required trench 200.
[0065] Step S13, please refer to Figure 3 and form a first source / drain region 310 and a second source / drain region 320 on both sides of the trench 200 by using an ion implantation process. After the ion implantation process is completed, use a remover to remove the remaining photoresist on the silicon substrate 100.
[0066] For example, first, the silicon substrate 100 is cleaned to remove surface impurities and contaminants. Then, an ion implanter is used to implant the required impurity atoms in the form of ions into the designated area of the silicon substrate 100 to form the source / drain regions. The implantation angle and dose should be adjusted according to the process requirements. The implanted silicon substrate 100 is heat-treated to promote the diffusion and activation of the impurity atoms and form the required electrical properties.
[0067] Step S14, please refer to Figure 4 , and a polysilicon film layer 400 is formed on the surface of the trench 200 by using atomic layer deposition technology.
[0068] For example, a polysilicon film layer 400 is deposited on the surface of the trench 200 by using atomic layer deposition technology.
[0069] Step S15, please refer to Figure 5 , a titanium nitride layer 500 and a tungsten layer 600 are sequentially formed on the surface of the polysilicon film layer 400, and the three layers are stacked to form a gate structure.
[0070] For example, a titanium nitride layer 500 and a tungsten layer 600 are sequentially deposited on the polysilicon film layer 400 to form a gate stack structure. The polysilicon film layer 400 serves as the gate material, the titanium nitride layer 500 serves as the barrier layer, and the tungsten layer 600 serves as the conductive layer. Lithography and etching techniques are used to pattern the gate stack structure to form the required gate shape. Finally, contact holes are formed in the gate structure and filled with metal or alloy to form gate contacts. Finally, after a series of processes, BCAT is formed.
[0071] In some possible embodiments, please refer to Figure 6 , step S14 further includes the following steps.
[0072] Step S141, the substrate 100 is placed in a process chamber, and the surface of the trench 200 is cleaned by using the in-situ cleaning technology of atomic layer deposition technology.
[0073] For example, the silicon substrate 100 is transferred into the process chamber through a pre-vacuum chamber, and then the temperature and holding time of the process chamber are set, and the leak rate of the process chamber is detected to meet the requirements. Then, the in-situ cleaning process of the atomic layer deposition equipment is used to remove the oxide layer on the surface, sidewalls and bottom of the trench 200 of the silicon substrate 100 and the particles on the inner wall of the chamber, so as to deposit the polysilicon film layer 400 subsequently and improve the adhesion and film quality of the polysilicon.
[0074] The implementation of this step can improve the surface cleanliness of the substrate 100, removing surface impurities, contaminants, and oxide layers. The in-situ cleaning technology in atomic layer deposition technology does not require the substrate 100 to be removed from the process chamber, reducing contact with the external environment and thus lowering the risk of contamination. The clean surface provides a good substrate for subsequent deposition steps, facilitating the formation of a uniform and dense deposition layer.
[0075] Step S142: Introduce a precursor material into the process chamber. After the precursor material cracks, silicon molecular clusters are deposited on the trench 200.
[0076] In this step, it is necessary to strictly control the introduction time of the precursor source material so that the precursor source material cracks, generating silicon molecular clusters that adsorb on the surface, sidewalls, and bottom of the trench 200.
[0077] Step S143: Sequentially introduce nitrogen, hydrogen, and nitrogen into the process chamber. After multiple cycles of purging, silicon atoms are deposited on the trench 200.
[0078] In this step, nitrogen is introduced as a purge gas, and its introduction time is controlled to carry away some of the unadsorbed precursor source material; then a certain amount of reducing gas hydrogen is introduced to reduce the completely cracked silicon molecular clusters into silicon atoms and adsorb them on the surface, sidewalls, and bottom of the trench 200 of the silicon substrate 100; then nitrogen is introduced again as a purge gas to carry away some of the precursor source molecular clusters or atomic clusters that did not participate in the reaction. The above process is one cycle, and then multiple cycles are carried out according to the above steps. At this time, the formed polysilicon grains are small and the film layer is not dense.
[0079] Step S144: Use the in-situ annealing technology of atomic layer deposition technology to obtain the polysilicon film layer 400.
[0080] In this step, through in-situ annealing, the polysilicon grains grow and the defects of the film layer are eliminated, obtaining a polysilicon film layer 400 with a dense and defect-free film layer structure. The temperature and time of annealing are controlled according to needs in this step.
[0081] In some possible implementation manners, please refer to Figure 7 , the step S141 further includes the following steps.
[0082] Step S1411: Place the substrate 100 into the process chamber.
[0083] Step S1412: According to the material of the trench 200 and the type of oxide layer on its surface, use the in-situ plasma cleaning technology to bombard the surface of the wafer to remove the oxide layer.
[0084] Step S1413: Use an inert gas to purge the trench 200 to remove residues.
[0085] Through the above steps, the cleanliness of the surface of the trench 200 is improved, and an ideal substrate is provided for the subsequent deposition step, thereby contributing to improving the performance and reliability of the entire semiconductor device 10.
[0086] In some possible embodiments, please refer to Figure 8 , the step S1411 further includes the following steps.
[0087] Step S14111, the substrate 100 is transferred into the process chamber through an atomic layer deposition device.
[0088] Step S14112, raise the temperature of the process chamber to 550°C - 650°C, keep it warm for 10 min - 20 min, and detect that the leak rate of the process chamber does not exceed 1*10 -7 mbar*l / s.
[0089] Through the above steps, the residual gases and volatile substances in the chamber are removed, and the preheating of the inner wall of the chamber is promoted, providing a more stable and controllable environment for the subsequent deposition process. At the same time, the leak rate of the process chamber is strictly detected to ensure that it does not exceed the threshold, further ensuring the airtightness of the chamber and the purity of the gas environment, thereby contributing to improving the quality and uniformity of the deposited layer.
[0090] In some possible embodiments, the precursor material includes trimethylchlorosilane, diethylaminosilane or disilane. These materials can generate a certain vapor pressure at a certain temperature, which is beneficial to their uniform distribution and adsorption on the surface of the trench 200. At the same time, the silicon atoms generated after the cracking of these materials have high reactivity and can quickly react with the surface of the trench 200 to form stable chemical bonds, thereby enhancing the bonding force between the deposited layer and the substrate 100.
[0091] In some possible embodiments, the time for introducing the precursor material into the process chamber is 5 s - 10 s to ensure that the precursor source material can be fully cracked and deposited on the surface of the substrate 100, while avoiding unnecessary waste and pollution caused by too long introduction time.
[0092] In some possible embodiments, please refer to Figure 9 , the step S143 also includes the following steps.
[0093] Step S1431, introduce nitrogen to purge the trench 200 for 2 s - 5 s.
[0094] Step S1432, introduce hydrogen to reduce for 3 s - 6 s.
[0095] Step S1433, introduce nitrogen gas again to purge the trench 200 for 2 s - 5 s.
[0096] Step S1434, cycle the above steps multiple times to obtain silicon atoms deposited on the trench 200.
[0097] In this embodiment, by precisely controlling the introduction time and sequence of the precursor source material, nitrogen gas, and hydrogen gas, efficient cleaning and deposition on the surface of the trench 200 are achieved. As a purge gas, nitrogen gas can effectively carry away the unadsorbed or unreacted precursor source material, ensuring the purity of the deposited layer. The introduction of hydrogen gas plays a reduction role, reducing the incompletely cracked silicon molecular clusters into silicon atoms, which are tightly adsorbed on the surface, sidewalls, and bottom of the trench 200, thereby improving the density and uniformity of the deposited layer. Cycling the above steps multiple times can ensure the thickness and uniformity of the deposited layer.
[0098] In some possible implementation manners, please refer to Figure 10 and the following steps are further included in step S144.
[0099] Step S1441, perform in-situ annealing using atomic layer deposition technology. The temperature of the in-situ annealing is 500°C - 600°C. This temperature range can not only ensure that the atoms in the polysilicon film layer 400 are fully migrated and rearranged to form a more stable and dense crystal structure, but also prevent the degradation of the film layer quality or the damage of the substrate 100 due to excessive temperature. The annealing time is 20 min - 40 min, which can ensure the sufficiency and efficiency of the annealing process.
[0100] Step S1442, obtain the polysilicon film layer 400 deposited on the substrate 100.
[0101] After the in-situ annealing treatment, the polysilicon film layer 400 deposited on the substrate 100 is successfully obtained. This polysilicon film layer 400 has high uniformity and density.
[0102] This application also provides a semiconductor device 10, which is applied to BCAT. Please refer to Figure 5 and the semiconductor device 10 is fabricated using the manufacturing method of any one of the foregoing semiconductor devices 10, and includes: a substrate 100, including a first source / drain region 310 and a second source / drain region 320; a trench 200, in the substrate 100 and between the first source / drain region 310 and the second source / drain region 320, and the first source / drain region 310 is spaced apart from the second source / drain region 320 by the trench 200; a gate electrode, including a polysilicon film layer 400, a titanium nitride layer 500, and a tungsten layer 600 sequentially disposed on the surface of the trench 200.
[0103] The semiconductor device 10 in this embodiment includes a substrate 100, a trench 200 that separates two source / drain regions, and a gate electrode composed of a polysilicon film layer 400, a titanium nitride layer 500, and a tungsten layer 600. The polysilicon film layer 400 is prepared by atomic layer deposition technology, ensuring high uniformity and density, and improving the overall performance of the semiconductor device 10.
[0104] In some possible implementation manners, the aspect ratio of the trench 200 is 10:1; the thickness of the polysilicon film layer 400 is 1 nm - 2 nm. Please refer to Figure 11 , any of the foregoing methods can fill the trench 200 with D / W ≥ 10:1, and at the same time can accurately control the thickness T of the polysilicon film layer 400. For example, the depth D of the trench 200 can be 250 nm, the width W can be 25 nm; the thickness T of the polysilicon film layer 400 can be 2 nm.
[0105] In summary, a semiconductor device 10 and a manufacturing method thereof provided by the present application, the method includes: providing a substrate 100, the substrate 100 includes a first surface 110 and a second surface 120 opposite thereto; forming at least one trench 200 on the first surface 110; using an ion implantation process to form a first source / drain region 310 and a second source / drain region 320 on both sides of the trench 200; using atomic layer deposition technology to form a polysilicon film layer 400 on the surface of the trench 200; sequentially forming a titanium nitride layer 500 and a tungsten layer 600 on the surface of the polysilicon film layer 400, and the three layers are stacked to form a gate structure. This solution applies atomic layer deposition technology to the preparation of the polysilicon buffer layer of BCAT. This technology can deposit an ultra-thin and uniform polysilicon film layer 400, and at the same time achieve precise control of the thickness of the polysilicon buffer film layer; the film layer structure prepared by it is highly dense, showing excellent step coverage ability and good conformality; at the same time, it can fill the trench 200 with an aspect ratio greater than 10:1. In addition, this technology can also effectively manage the number of particles in the cavity to ensure the cleanliness of the production environment. Compared with the traditional low-pressure chemical vapor deposition process that cannot meet the filling function of the polysilicon buffer layer; the physical vapor deposition process is not easy to control the film layer thickness, and there are problems of poor step coverage and poor filling ability, this technical solution is more competitive in the preparation of the polysilicon buffer film layer and is an ideal choice for realizing large-scale mass production.
[0106] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a substrate, the substrate comprising a first surface and a second surface opposite thereto; forming at least one groove on the first surface; Using an ion implantation process, a first source / drain region and a second source / drain region are formed on both sides of the trench; A polysilicon film layer is formed on the surface of the groove by using atomic layer deposition technology; A titanium nitride layer and a tungsten layer are sequentially formed on the surface of the polysilicon film layer, and the three layers are stacked to form a gate structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of forming a polysilicon film layer on the surface of the groove by using atomic layer deposition technology also includes: Placing the substrate into a process chamber, and using an online cleaning technique of atomic layer deposition technology to clean the surface of the groove; A precursor material is introduced into the process chamber, and the precursor material is cracked to obtain silicon molecular clusters deposited on the grooves; Introducing nitrogen, hydrogen, and nitrogen into the process chamber in sequence, and obtaining silicon atoms deposited on the grooves after multiple cycles of purging; The polysilicon film layer is obtained by adopting the online annealing technology of atomic layer deposition technology.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: The method of placing the substrate into a process chamber and using an online cleaning technology of an atomic layer deposition technology to clean the surface of the groove also includes: placing the substrate into the process chamber; According to the groove material and the type of oxide layer on the surface thereof, a plasma online cleaning technology is used to bombard the wafer surface to remove the oxide layer; The trench is purged with an inert gas to remove residue.
4. The method for manufacturing a semiconductor device according to claim 3, wherein: The method of placing the substrate into a process chamber comprises: The substrate is transferred into the process chamber through the atomic layer deposition equipment; The temperature of the process chamber is raised to 550°C-650°C and kept at this temperature for 10-20 minutes. The leakage rate of the process chamber is tested to be no more than 1*10 -7 mbar*l / s.
5. The method for manufacturing a semiconductor device according to claim 2, wherein: The precursor material includes trimethylsilyl chloride, diethylaminosilane or disilane.
6. The method for manufacturing a semiconductor device according to claim 2, wherein: The time for the precursor material to be introduced into the process chamber is 5s-10s.
7. The method for manufacturing a semiconductor device according to claim 2, wherein: The method of sequentially introducing nitrogen, hydrogen, and nitrogen into the process chamber and obtaining silicon atoms deposited on the groove after multiple cycles of purging includes: Pass nitrogen gas to purge the groove for 2s-5s; Add hydrogen to reduce for 3s-6s; Introduce nitrogen gas again to purge the groove for 2s-5s; The above steps are repeated multiple times to obtain silicon atoms deposited on the grooves.
8. The method for manufacturing a semiconductor device according to claim 2, wherein: The method of obtaining a polysilicon film layer by online annealing using atomic layer deposition technology also includes: The atomic layer deposition technology is used for online annealing, the online annealing temperature is 500℃-600℃, and the annealing time is 20min-40min; The polysilicon film layer deposited on the substrate is obtained.
9. A semiconductor device, characterized in that: A semiconductor device manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device comprises: a substrate including a first source / drain region and a second source / drain region; a trench in the substrate and between the first source / drain region and the second source / drain region, the first source / drain region being separated from the second source / drain region by the trench; The gate electrode comprises a polysilicon film layer, a titanium nitride layer and a tungsten layer which are sequentially arranged on the surface of the groove.
10. The semiconductor device according to claim 9, characterized in that The depth-to-width ratio of the groove is 10:1; The thickness of the polysilicon film layer is 1nm-2nm.