Formation method of semiconductor device
By forming a patterned mask layer and photoresist layer in the semiconductor manufacturing process and controlling the plasma etching amount, the problem of damage to the silicon oxide layer caused by thin photoresist thickness is solved, and device performance and yield are improved.
Patent Information
- Application Number
- CN202311701402.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-11
- Publication Date
- 2025-06-13
AI Technical Summary
In the existing semiconductor manufacturing process, in the integrated etching process of the rear section through-hole and trench, the photoresist is thinner, causing plasma to penetrate the photoresist, causing damage to the surface of the silicon oxide layer, affecting device performance and yield.
By forming a patterned first mask layer, a second mask layer and a patterned photoresist layer on the substrate, two plasma etchings are used to control the etching amount of the second plasma etching is less than the sum of the thickness of the photoresist layer and the second mask layer to reduce plasma penetration and damage to the silicon oxide layer.
While ensuring the through-hole etching effect, it reduces or avoids surface damage of the silicon oxide layer and improves device performance and yield.
Smart Images
Figure CN120149260A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor device. Background Art
[0002] The integrated via and trench etching process in the back end is a common semiconductor manufacturing process. First, using photoresist as a soft mask, the pattern of the mask is transferred from the soft mask to the hard mask. After removing the photoresist, the pattern is further transferred from the dielectric hard mask to the copper substrate through an etching process. In the integrated via and trench etching in the back end, the degree of surface damage of the silicon oxide layer is one of the indicators for measuring the etching performance. How to accurately control the degree of plasma penetration through the photoresist is the key to ensuring the surface damage of the silicon oxide during the integrated via and trench etching in the back end, and is very important for the performance and yield of the finally manufactured semiconductor device (hereinafter referred to as the device).
[0003] In the existing semiconductor manufacturing process flow, for the integrated via and trench etching process in the back end, the thickness of the photoresist is usually only about 1700 nm. Since the thickness of the spin-coated photoresist is relatively thin, and the integrated via and trench etching process in the back end usually requires multiple etching operations, when the photoresist is consumed to a relatively thin thickness during manufacturing and then etching is performed, the plasma will penetrate through the photoresist, resulting in surface damage to the silicon oxide layer after via etching, which has a greater impact on the device performance and yield. Summary of the Invention
[0004] The technical problem to be solved by the present invention is how to reduce the degree of substrate surface damage while ensuring a good via etching effect.
[0005] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, on which a patterned first mask layer is formed; sequentially forming a second mask layer and a patterned photoresist layer on the first mask layer; using the patterned photoresist layer as a mask to perform a first plasma etching on the second mask layer to obtain a patterned second mask layer, the patterned second mask layer exposing the substrate; using the patterned photoresist layer and the patterned second mask layer as masks to perform a second plasma etching on the substrate; wherein, in the step of performing the second plasma etching on the substrate, the etching amount of the substrate is less than the sum of the thicknesses of the patterned photoresist layer and the patterned second mask layer.
[0006] Optionally, the area of the substrate covered by the patterned first mask layer is smaller than the area of the substrate covered by the patterned second mask layer, and the thickness of the patterned second mask layer is the thickness of the region where the patterned second mask layer directly covers the substrate.
[0007] Optionally, the etching amount is determined according to the etching time and the etching rate, and the etching rate is positively correlated with the bias power. Before the second plasma etching of the substrate, it further includes: determining the etching time and the bias power according to the target etching amount, so that the etching amount of the substrate in the step of performing the second plasma etching on the substrate is not less than the target etching amount.
[0008] Optionally, on the premise of ensuring that the etching amount reaches the target etching amount, the bias power used in the step of performing the second plasma etching on the substrate is less than the lower limit value of the process specification of the standard bias power for etching the substrate.
[0009] Optionally, the lower limit value of the process specification of the standard bias power for etching the substrate is taken from 1700W to 1800W, and the bias power used in the step of performing the second plasma etching on the substrate is taken from 1500W to 1600W.
[0010] Optionally, the bias power used in the step of performing the first plasma etching on the second mask layer is greater than the bias power used in the step of performing the second plasma etching on the substrate.
[0011] Optionally, after the first plasma etching of the second mask layer and before the second plasma etching of the substrate, it further includes: adjusting the bias power of the etching chamber from a first power value to a second power value, where the first power value is the bias power used in the step of performing the first plasma etching on the second mask layer, and the second power value is the bias power used in the step of performing the second plasma etching on the substrate.
[0012] Optionally, the bias power used in the step of performing the first plasma etching on the second mask layer is not less than the lower limit value of the process specification of the standard bias power for etching the second mask layer, and the bias power used in the step of performing the second plasma etching on the substrate is less than the lower limit value of the process specification of the standard bias power for etching the substrate.
[0013] Optionally, the forming of the patterned photoresist layer includes: forming the patterned photoresist layer with a first thickness by a spin coating process.
[0014] Optionally, after the first plasma etching of the second mask layer and before the second plasma etching of the substrate, the method further includes: calculating a second thickness according to the first thickness and the etching amount of the photoresist layer in the step of performing the first plasma etching on the second mask layer, where the second thickness is the remaining thickness of the patterned photoresist layer after the first plasma etching; determining a second power value according to the second thickness, where the second power value is the bias power used in the step of performing the second plasma etching on the substrate; and adjusting the bias power of the etching chamber to the second power value.
[0015] Optionally, the second power value is positively correlated with the second thickness.
[0016] Optionally, the first thickness is greater than the upper limit of the process specification of the standard thickness when the patterned photoresist layer is formed by a spin coating process.
[0017] Optionally, the first thickness is related to the material of the photoresist. Before forming the patterned photoresist layer with the first thickness by a spin coating process, the method further includes: determining a lower limit value of the first thickness according to the bias power used in the step of performing the second plasma etching on the substrate; and selecting the material of the photoresist used in the spin coating process according to the lower limit value of the first thickness.
[0018] Optionally, the first mask layer includes a metal hard mask layer, and / or the second mask layer includes an anti-reflection layer.
[0019] Optionally, after the second plasma etching of the substrate, the method further includes: removing the patterned photoresist layer and the patterned second mask layer; and etching the substrate using the patterned first mask layer as a mask.
[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0021] The embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, on which a patterned first mask layer is formed; sequentially forming a second mask layer and a patterned photoresist layer on the first mask layer; using the patterned photoresist layer as a mask to perform a first plasma etching on the second mask layer to obtain a patterned second mask layer, where the patterned second mask layer exposes the substrate; using the patterned photoresist layer and the patterned second mask layer as masks to perform a second plasma etching on the substrate; where the etching amount of the substrate in the step of performing the second plasma etching on the substrate is less than the sum of the thicknesses of the patterned photoresist layer and the patterned second mask layer.
[0022] In the existing back-end integrated etching technology for through-holes and grooves, due to the thin thickness of the photoresist spin coating, the plasma penetrates the photoresist during the etching process, causing surface damage to the underlying substrate (e.g., the silicon oxide layer of the substrate), resulting in yield loss. In comparison, this embodiment reasonably controls the etching amount in the second plasma etching step to ensure that the plasma does not basically pass through the patterned second mask layer and the patterned photoresist layer under the premise of meeting the process etching requirements, thereby reducing or even avoiding damage to the substrate surface. As a result, while ensuring a good through-hole etching effect, the degree of damage to the substrate surface after etching can be improved, for example, the degree of damage to the surface of the silicon oxide layer caused by the plasma caused by the loss of the patterned photoresist layer during the etching process can be reduced, thereby improving device performance and yield.
[0023] Furthermore, when the thickness increase of the patterned photoresist layer is limited, the etching amount of the substrate in the second plasma etching step is reasonably controlled to ensure a better (eg, lighter) surface damage degree of the silicon oxide layer after TSV etching.
[0024] Furthermore, when the thickness of the patterned photoresist layer can be appropriately increased, the surface damage degree of the silicon oxide layer after the through silicon via etching can be ensured by increasing the thickness. Furthermore, the damage to the surface of the silicon oxide layer caused by etching can be better avoided by combining increasing the thickness with reasonably controlling the etching amount.
[0025] Furthermore, the thickness of the patterned second mask layer specifically refers to the thickness of the region where the patterned second mask layer directly covers the substrate (e.g., silicon oxide layer). By controlling the etching amount in the second plasma etching step, it is possible to avoid the plasma in this step penetrating the patterned photoresist layer and the patterned second mask layer to damage the silicon oxide layer, thereby ensuring a better protection effect on the surface of the silicon oxide layer.
[0026] Furthermore, the etching time and bias power are determined according to the target etching amount, so that the determined etching time and bias power can meet the requirements of the target etching amount, and the etching time and bias power can be flexibly adjusted to improve the production efficiency while ensuring the etching effect. For example, by adjusting the bias power to ensure that the penetration ability of the plasma is sufficient to achieve the target etching amount while not penetrating the patterned photoresist layer and the patterned second mask layer, the etching time is adjusted accordingly according to the bias power, thereby reducing surface damage while ensuring that the etching amount reaches the over-etching amount required for the step.
[0027] Further, performing a second plasma etching on the substrate with a bias power lower than the lower limit of the process specification of the standard bias power can weaken the penetration ability of the plasma, making it not easy to penetrate the patterned second mask layer and the patterned photoresist layer, thereby reducing the degree of damage to the surface of the silicon oxide layer during etching.
[0028] Further, the bias power used in the first plasma etching is greater than that used in the second plasma etching, which can accelerate the etching rate when the photoresist layer is not consumed (or consumed less), improving production efficiency.
[0029] Further, flexibly controlling the switching of the bias power during the first plasma etching and the second plasma etching in the etching chamber is beneficial to improving production efficiency while reducing the damage to the surface of the silicon oxide layer.
[0030] Further, without reducing the bias power of the first plasma etching below the standard bias power, ensuring good etching effect and efficiency. In other words, during the first plasma etching, the bias power is not deliberately reduced, while during the subsequent second plasma etching, the bias power is actively reduced to weaken or even avoid surface damage.
[0031] Further, determining the bias power used in the second plasma etching based on the thickness of the remaining photoresist layer after the first plasma etching (i.e., the second thickness) can more accurately control the penetration ability of the plasma during the second plasma etching, ensuring that the plasma does not penetrate the patterned photoresist layer and the patterned second mask layer. Thus, it is beneficial to reduce the degree of damage to the surface of the silicon oxide layer.
[0032] Further, using a patterned photoresist layer thicker than the standard thickness to ensure that after the first plasma etching with the standard power, the thickness of the remaining photoresist layer can still be maintained within a large value range. Thus, during the subsequent second plasma etching, the surface of the silicon oxide layer can be better protected from being damaged.
[0033] Further, inversely calculating the minimum thickness of the photoresist layer to be formed during spin coating based on the bias power during the second plasma etching, and then selecting a suitable photoresist material to ensure that the spin-coated photoresist layer reaches at least this minimum thickness. Thus, based on the requirement for the thickness of the photoresist layer, the material of the photoresist used to form the photoresist layer can be flexibly selected to meet the bias power configuration during the second plasma etching, with better adaptability. Description of the Drawings
[0034] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device in the existing back-end via and trench integrated etching process;
[0035] Figure 2It is a graph showing the variation of the thickness of the photoresist with the rotation speed in the photolithography spin-coating process;
[0036] Figure 3 It is a flowchart of a method for forming a semiconductor device in an embodiment of the present invention;
[0037] Figures 4 to 6 It is a schematic diagram of the device cross-sectional structure corresponding to each step in the method for forming a semiconductor device according to an embodiment of the present invention;
[0038] Figure 7 It is a flowchart of another method for forming a semiconductor device in an embodiment of the present invention;
[0039] Figure 8 It is a flowchart of yet another method for forming a semiconductor device in an embodiment of the present invention;
[0040] Figures 9 to 10 It is a schematic diagram of the device cross-sectional structure corresponding to each step in the yet another method for forming a semiconductor device according to an embodiment of the present invention. Detailed implementation manner
[0041] As described in the background art, in the existing semiconductor manufacturing process, in the process of etching the via holes and trenches in the back end, the photoresist layer will be damaged during the etching of the soft mask layer, resulting in a thinner photoresist layer. During subsequent further etching, the surface of the silicon oxide layer is bombarded by plasma due to the thinner photoresist layer, resulting in surface damage. This surface damage of the silicon oxide layer generated during etching will affect the device performance and yield.
[0042] See Figure 1 , Figure 1 exemplarily shows the film layers involved in a semiconductor device in the existing back-end via hole and trench integrated etching process. Specifically, the substrate can be, for example, a silicon substrate containing a copper substrate, on which a silicon carbonitride thin film, a low-k dielectric insulating layer, a silicon oxide layer, a titanium nitride mask, an anti-reflection layer, and a patterned photoresist layer are sequentially formed. During the etching process to form silicon vias, the patterned photoresist layer gradually becomes thinner. As the etching progresses further, the etching depth further increases, and the thickness of the photoresist layer and the anti-reflection layer on the silicon oxide layer continue to decrease, and the plasma may penetrate the thinner photoresist layer and anti-reflection layer to reach the silicon oxide layer. Thus, as the etching step progresses, damage as shown in Figure 1 the top view is generated on the surface of the silicon oxide layer. The damage can be, for example, a depression formed by plasma bombarding the surface of the silicon oxide layer, or can also be, for example, a protrusion sputtered by plasma bombardment.
[0043] The inventors of the present application found through analysis that one of the reasons for the above problems is that in the existing integrated etching technology for back-end vias and trenches, the photoresist layer is generally made relatively thin. During the etching process, the plasma will penetrate through the photoresist layer with a relatively thin thickness, causing damage to the surface of the silicon via after etching. Specifically, the photoresist layer is usually prepared by a photolithography spin-coating process, and the thickness of the photoresist layer is related to the rotation speed of the spin-coating. Generally speaking, the thickness of the photoresist layer used in the existing technology is about 1700 nm. In actual use, the 1700-nm photoresist layer is already relatively thin and will inevitably become thinner in the later stage of etching. This leads to the plasma easily penetrating through the remaining photoresist layer after thinning and hitting the silicon oxide layer during the silicon via etching, causing damage to the surface of the silicon oxide layer.
[0044] Figure 2 Yes Figure 1 is a graph showing the variation of the photoresist thickness in the photolithography spin-coating process with the rotation speed. Figure 2 The abscissa is the rotation speed of the photolithography spin-coating (unit: revolutions per minute), and the ordinate is the photoresist thickness (also known as the thickness of the photoresist layer) (unit: nanometer nm). Combining Figure 2 it can be seen that the faster the rotation speed, the thinner the photoresist thickness. The thickness of the photoresist used in the existing process is about 1700 nm, and the corresponding rotation speed is about 1100 revolutions per minute.
[0045] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, on which a patterned first mask layer is formed; sequentially forming a second mask layer and a patterned photoresist layer on the first mask layer; using the patterned photoresist layer as a mask to perform a first plasma etching on the second mask layer to obtain a patterned second mask layer, and the patterned second mask layer exposes the substrate; using the patterned photoresist layer and the patterned second mask layer as masks to perform a second plasma etching on the substrate; wherein, in the step of performing the second plasma etching on the substrate, the etching amount of the substrate is less than the sum of the thicknesses of the patterned photoresist layer and the patterned second mask layer.
[0046] As described above, in this implementation scheme, by increasing the thicknesses of the second mask layer and the patterned photoresist layer, during the etching process, the second mask layer and the patterned photoresist layer will not become too thin, and the plasma is not easy to penetrate through the thickened second mask layer and the patterned photoresist layer. Therefore, the plasma is not easy to cause damage to the surface of the silicon oxide layer. Thus, it is possible to reduce the degree of damage to the surface of the silicon oxide layer caused by the plasma as the thicknesses of the second mask layer and the patterned photoresist layer become thinner during the etching process.
[0047] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.
[0048] Figure 3 It is a flowchart of a method for forming a semiconductor device in an embodiment of the present invention.
[0049] Referring to Figure 3 , the method for forming the semiconductor device may include steps S11 to S14:
[0050] Step S11, providing a substrate, on which a patterned first mask layer is formed;
[0051] Step S12, sequentially forming a second mask layer and a patterned photoresist layer on the first mask layer;
[0052] Step S13, using the patterned photoresist layer as a mask, performing a first plasma etching on the second mask layer to obtain a patterned second mask layer, and the patterned second mask layer exposes the substrate;
[0053] Step S14, using the patterned photoresist layer and the patterned second mask layer as masks, performing a second plasma etching on the substrate; wherein, in the step of performing the second plasma etching on the substrate, the etching amount of the substrate is less than the sum of the thicknesses of the patterned photoresist layer and the patterned second mask layer.
[0054] Specifically, the substrate may be, for example, a silicon substrate, or may also be a semiconductor substrate made of other silicon-containing materials. In practical applications, the substrate may also include, for example, a silicon carbonitride film, a low dielectric insulating layer, and / or a silicon oxide layer, etc.
[0055] In the subsequent integrated process of vias and trenches, the surface of the substrate is usually a silicon oxide layer, and etching damage usually also occurs in the silicon oxide layer. In practical applications, the surface of the substrate may also be other film layers, and this embodiment does not limit this.
[0056] In a specific embodiment, in step S13, the fact that the patterned second mask layer exposes the substrate means that at least a part of the area of the substrate not covered by the patterned first mask layer is exposed.
[0057] Next, in combination with Figures 4 to 6 the above steps will be elaborated in detail.
[0058] Refer to Figure 4, a substrate (not shown) is provided, on which a patterned first mask layer 105 is formed. In some embodiments, the substrate may sequentially include, from bottom to top, a silicon substrate 101 on which a copper substrate 108 is formed, a silicon carbonitride thin film 102, a low dielectric insulating layer 103, and a silicon oxide layer 104. The patterned first mask layer 105 may be formed on the surface of the silicon oxide layer 104.
[0059] Specifically, the first mask layer 105 may include a metal hard mask layer.
[0060] In some embodiments, the first mask layer 105 may be, for example, a titanium nitride TiN mask.
[0061] In some embodiments, the first mask layer 105 may also be formed of other metal-containing materials to form a hard mask layer on the surface of the silicon oxide layer 104. For example, the material of the first mask layer 105 may also include a combination of titanium Ti, TiN, and Ti, etc.
[0062] In some embodiments, at least a part of the silicon oxide layer 104 may be formed with trenches through a previous process. Further, the patterned first mask layer 105 covers the part of the silicon oxide layer 104 except for the trenches.
[0063] In step S12, a second mask layer 106 and a patterned photoresist layer 107 are sequentially formed on the first mask layer 105.
[0064] Specifically, the second mask layer 106 may cover the first mask layer 105 and the area of the silicon oxide layer 104 not covered by the first mask layer 105. In other words, the area of the substrate covered by the patterned first mask layer 105 is smaller than the area of the substrate covered by the patterned second mask layer 106.
[0065] In some embodiments, the second mask layer 106 may be, for example, an anti-reflection layer. For example, the material of the anti-reflection layer may include a dielectric anti-reflection coating (DARC).
[0066] Specifically, the patterned photoresist layer 107 may be formed on the second mask layer 106 by a spin coating process.
[0067] In step S13, using the patterned photoresist layer 107 as a mask, the second mask layer 106 is subjected to a first plasma etching to obtain a patterned second mask layer 106 as shown in Figure 5 . The patterned second mask layer 106 exposes the substrate. The first plasma etching step may also be referred to as an anti-reflection layer etching step.
[0068] Specifically, in this embodiment, the fact that the patterned second mask layer 106 exposes the substrate means that after the first plasma etching, a part of the silicon oxide layer 104 is exposed. For example, at least a part of the area of the silicon oxide layer 104 that is not covered by the patterned first mask layer 105 is exposed.
[0069] In some embodiments, the amount of the first plasma etching can be denoted as A, that is, the etching depth of the second mask layer 106 (for example, an anti-reflection layer).
[0070] In some embodiments, after the first plasma etching, the thickness of the patterned photoresist layer 107 can be denoted as C, the thickness of the patterned second mask layer 106 can be denoted as D, and the sum of the thicknesses of the patterned photoresist layer 107 and the patterned second mask layer 106 can be denoted as C + D. Among them, the thickness D of the patterned second mask layer 106 specifically refers to the thickness of the area where the patterned second mask layer 106 directly covers the substrate (for example, the silicon oxide layer 104).
[0071] Reference Figure 6 , in step S14, using the patterned photoresist layer 107 and the patterned second mask layer 106 as masks, the substrate (for example, the silicon oxide layer 104 and the low dielectric insulating layer 103) is subjected to a second plasma etching. The second plasma etching step can also be called a through-silicon via etching step.
[0072] In some embodiments, the amount of the second plasma etching can be denoted as B, that is, the etching depth of the substrate (for example, the silicon oxide layer 104 and the low dielectric insulating layer 103).
[0073] In some embodiments, in combination with Figure 5 and Figure 6 , in the step of performing the second plasma etching on the substrate, the etching amount of the substrate (for example, the etching amount B) is less than the sum of the thicknesses of the patterned photoresist layer 107 and the patterned second mask layer 106 (for example, C + D).
[0074] During the etching process, by reasonably controlling the etching amount (for example, the etching amount B) in the second plasma etching step, it is ensured that the plasma basically does not pass through the patterned second mask layer 106 and the patterned photoresist layer 107 on the premise of meeting the process etching requirements, thereby reducing or even avoiding damage to the surface of the substrate (for example, the silicon oxide layer 104). Thus, while ensuring a good through-hole etching effect, the degree of surface damage of the substrate after etching can be improved. For example, the degree of damage to the surface of the silicon oxide layer 104 caused by the plasma as the patterned photoresist layer 107 is consumed during the etching process can be reduced, thereby improving the device performance and yield.
[0075] In some embodiments, with continued reference to Figure 5 and Figure 6 , the area of the patterned first mask layer 105 covering the substrate refers to the projected area of the patterned first mask layer 105 on the substrate (e.g., the silicon oxide layer 104). The area of the patterned second mask layer 106 covering the substrate refers to the projected area of the patterned second mask layer 106 on the substrate (e.g., the patterned first mask layer 105 and the silicon oxide layer 104).
[0076] By controlling the thickness D of the patterned second mask layer 106, that is, the thickness of the area where the patterned second mask layer 106 directly covers the substrate (e.g., the silicon oxide layer 104), a better protection effect on the surface of the silicon oxide layer 104 can be ensured.
[0077] In a specific implementation, the etching amount (e.g., etching amount B) is determined according to the etching time and the etching rate. The etching rate is positively correlated with the bias power. Before performing step S14, the method of this embodiment further includes: determining the etching time and the bias power according to the target etching amount, so that the etching amount B of the substrate in the step of performing the second plasma etching on the substrate is not less than the target etching amount.
[0078] Determining the etching time and the bias power according to the target etching amount can ensure that the determined etching time and bias power can meet the requirements of the target etching amount without penetrating the patterned photoresist layer and the patterned second mask layer. The etching time is adjusted accordingly with the bias power, thereby reducing surface damage while ensuring that the etching amount reaches the over-etching amount required for this step. Flexible adjustment of the etching time and the bias power can improve production efficiency while ensuring the etching effect.
[0079] Furthermore, on the premise of ensuring that the etching amount reaches the target etching amount, the bias power used in the step of performing the second plasma etching on the substrate can be less than the lower limit value of the process specification of the standard bias power for etching the substrate.
[0080] Specifically, the standard bias power can refer to the customary bias power for etching the substrate in the existing plasma etching process. This customary bias power can be, for example, a numerical interval, and the lower limit value of the process specification of the standard bias power can be the lower limit value of this numerical interval.
[0081] For example, the standard bias power for etching the substrate is 1700W - 2200W, where 1700W is the lower limit of the process specification. In this embodiment, the bias power for the second plasma etching of the substrate in step S14 can be less than 1700W. The current mature range of the bias power in use is approximately 1700W - 2000W, and it can also be less than 1700W, but the time needs to be increased accordingly.
[0082] For another example, the lower limit value of the process specification of the standard bias power for etching the substrate is taken from 1700W to 1800W. In this example, the bias power used in the step of the second plasma etching of the substrate in step S14 can be taken from 1500W to 1600W.
[0083] Using a bias power lower than the lower limit value of the process specification of the standard bias power for the second plasma etching of the substrate can weaken the penetration ability of the plasma, making it not easy to penetrate the patterned second mask layer and the patterned photoresist layer, thereby reducing the degree of damage to the surface of the silicon oxide layer during etching.
[0084] In a specific implementation, the bias power used in the step of the first plasma etching of the second mask layer can be greater than the bias power used in the step of the second plasma etching of the substrate. That is, the bias power used in step S13 is different from (for example, greater than) the bias power used in step S14.
[0085] Specifically, during the first plasma etching, the patterned photoresist layer has not yet suffered etching loss and thus has a larger thickness. Compared with the second plasma etching when the patterned photoresist layer has been damaged to a certain extent and thus a reduced bias power is required for etching, a relatively higher bias power can be used during the first plasma etching, such as the lower limit value of the process specification of the standard bias power.
[0086] In some embodiments, the bias power used in the step of the first plasma etching of the second mask layer can be, for example, 1700W to 1800W.
[0087] Using a greater bias power for the first plasma etching than for the second plasma etching can accelerate the etching speed and improve production efficiency when the photoresist layer has not been damaged (or has less damage).
[0088] In a specific implementation, after the first plasma etching of the second mask layer and before the second plasma etching of the substrate, this implementation may further include: adjusting the bias power of the etching chamber from a first power value to a second power value, where the first power value is the bias power used in the step of the first plasma etching of the second mask layer, and the second power value is the bias power used in the step of the second plasma etching of the substrate.
[0089] For example, the bias power used in the step of the first plasma etching of the second mask layer, that is, the first power value is 1800 W. After the first plasma etching of the second mask layer, the bias power of the etching chamber is adjusted from 1800 W to 1500 W, that is, after the second power value is adjusted to 1500 W, the substrate is then subjected to the second plasma etching.
[0090] By flexibly controlling the switching of the bias power for the first plasma etching and the second plasma etching in the etching chamber, it can not only ensure that during the first plasma etching, the target etching amount is achieved while reducing the etching time, which is beneficial to improving production efficiency. But also ensure that during the second plasma etching, the damage to the surface of the silicon oxide layer is reduced.
[0091] Furthermore, the bias power used in the step of the first plasma etching of the second mask layer is not less than the lower limit value of the process specification of the standard bias power for etching the second mask layer. And the bias power used in the step of the second plasma etching of the substrate is less than the lower limit value of the process specification of the standard bias power for etching the substrate.
[0092] Specifically, as mentioned above, the process specification range of the standard bias power for etching the second mask layer can be, for example, 1700 W - 2200 W, where 1700 W is the lower limit value of the process specification. Correspondingly, the bias power used in the step of the first plasma etching of the second mask layer is not less than the lower limit value of the process specification of the standard bias power, which can be, for example, not less than 1700 W. The current mature range of the bias power in use is approximately 1700 W - 2000 W. Of course, it can also be less than 1700 W, but the time needs to be increased accordingly.
[0093] When performing the first plasma etching of the second mask layer, the bias power of the first plasma etching is not deliberately reduced, achieving the target etching amount while reducing the etching time, which is beneficial to improving production efficiency.
[0094] In the step of performing the second plasma etching on the substrate, the bias power used is less than the lower limit of the process specification of the standard bias power for etching the substrate. For example, it can be less than 1700 W. By actively reducing the bias power of the second plasma etching, the surface damage to the substrate (such as the silicon oxide layer) can be weakened or even avoided.
[0095] In a specific implementation, the forming of the patterned photoresist layer includes: forming the patterned photoresist layer with a first thickness by using a spin coating process.
[0096] Specifically, in the case of the same photoresist material, the first thickness is determined according to the spin speed (abbreviated as speed) of the spin coating process. The faster the speed, the thinner the first thickness; the slower the speed, the thicker the first thickness, that is, the thicker the thickness of the formed patterned photoresist layer. On the other hand, below the rated maximum speed, the faster the speed, the more consistent the thickness uniformity at the center and edge of the formed patterned photoresist layer.
[0097] Furthermore, the first thickness can be greater than the upper limit of the process specification of the standard thickness when the patterned photoresist layer is formed by using a spin coating process.
[0098] Specifically, the standard thickness can refer to the usual thickness obtained by spin coating in the existing spin coating process for the photoresist layer. This usual thickness can be, for example, a numerical range, and the upper limit of the process specification of the standard thickness can be the upper limit of this numerical range. The thickness uniformity of the photoresist layer formed within this numerical range is acceptable.
[0099] For example, the usual thickness obtained by spin coating by using a spin coating process is 1600 nm - 1700 nm, and 1700 nm is the upper limit of the process specification. In this example, the first thickness of the patterned photoresist layer formed by using a spin coating process can be greater than 1700 nm. It should be noted that the specific value of the first thickness greater than 1700 nm in this example can be determined on the premise that the thickness uniformity of the photoresist layer still remains within an acceptable range.
[0100] Using a patterned photoresist layer thicker than the standard thickness ensures that after the first plasma etching is performed with the standard power, the remaining thickness of the photoresist layer can still be maintained within a relatively large numerical range. Thus, when the second plasma etching is performed subsequently, the surface of the silicon oxide layer can be better protected from being damaged.
[0101] In a specific implementation, referring to Figure 7 , after the first plasma etching of the second mask layer and before the second plasma etching of the substrate, that is Figure 3After step S13 and before step S14 shown in the embodiments, this implementation scheme further includes steps S131 to S133:
[0102] Step S131, calculate a second thickness according to the first thickness and the etching amount of the photoresist layer in the step of performing first plasma etching on the second mask layer, where the second thickness is the remaining thickness of the patterned photoresist layer after the first plasma etching;
[0103] Step S132, determine a second power value according to the second thickness, where the second power value is the bias power used in the step of performing second plasma etching on the substrate;
[0104] Step S133, adjust the bias power of the etching chamber to the second power value.
[0105] For step S131, in combination with Figure 5 , the first thickness may be, for example, thickness M (not shown in the figure), and the etching amount of the photoresist layer 107 in the step of performing first plasma etching on the second mask layer 106 may be, for example, etching amount N (not shown in the figure). The second thickness is calculated based on thickness M and etching amount N, that is, M - N. The second thickness is the remaining thickness of the patterned photoresist layer 107 after the first plasma etching. The second thickness may be, for example, thickness C. That is, the first thickness of the patterned photoresist layer 107 after spin coating is M, the etching amount of the photoresist layer 107 in the step of the first plasma etching is N. After the first plasma etching, the remaining thickness of the patterned photoresist layer 107 is M - N = C, that is, the second thickness.
[0106] In some embodiments, the etching amount N of the photoresist layer 107 in the step of performing first plasma etching on the second mask layer 106 may be substantially equal to the etching amount A of the second mask layer 106.
[0107] In a specific implementation, for step S132, the second power value is positively correlated with the second thickness. That is, the larger the second thickness, the larger the second power value determined based on the second thickness. Specifically, the larger the remaining thickness of the patterned photoresist layer after the first plasma etching, the larger the bias power that can be used during the second plasma etching.
[0108] Since the thickness of the patterned second mask layer covered by the patterned photoresist layer is substantially unchanged before and after the first plasma etching, it can be understood that the second power value and the second thickness are also positively correlated with the sum of the thickness of the patterned second mask layer (for example, thickness C + D).
[0109] In practical applications, at the same rotational speed, the initial thickness of the photoresist layer obtained by spin-coating different photoresist materials (for example, thickness M) is different, and the remaining thickness of the photoresist layer after the first plasma etching (for example, thickness C) will also change accordingly. Therefore, the specific value of the second power value can be flexibly adjusted according to the selected photoresist material, with stronger applicability.
[0110] Since the thickness of the patterned second mask layer remains basically unchanged before and after the first plasma etching, determining the bias power used in the second plasma etching based on the thickness of the remaining photoresist layer after the first plasma etching can more accurately control the intensity of the plasma in the second plasma etching and ensure that the plasma does not penetrate the remaining photoresist layer and the second mask layer. Thus, the degree of damage to the surface of the silicon oxide layer can be reduced.
[0111] In a specific implementation, the first thickness may be related to the photoresist material. Before forming the patterned photoresist layer with the first thickness by spin-coating process, this implementation further includes: determining the lower limit value of the first thickness according to the bias power used in the step of performing the second plasma etching on the substrate; and selecting the photoresist material used in the spin-coating process according to the lower limit value of the first thickness.
[0112] In some embodiments, based on the given bias power (for example, the second power value) used in the step of performing the second plasma etching on the substrate, the remaining thickness (for example, thickness C) of the patterned photoresist layer after the first plasma etching can be determined. Then, based on the etching amount (for example, etching amount N) of the patterned photoresist layer in the first plasma etching step, the initial thickness (for example, thickness M) of the patterned photoresist layer is calculated by reverse deduction. Thus, a suitable photoresist material is selected for the spin-coating process to obtain a patterned photoresist layer with the required initial thickness.
[0113] In some embodiments, based on the initial thickness (for example, thickness M) of the patterned photoresist layer calculated as described above, the rotational speed used in the spin-coating process can be selected to ensure that the initial thickness of the formed patterned photoresist layer meets the requirements.
[0114] In some embodiments, a suitable photoresist material can be selected based on the initial thickness (for example, thickness M) of the patterned photoresist layer calculated as described above. At the same time, based on the characteristics of the selected photoresist material, the rotational speed used in the spin-coating process is selected, so as to better meet the requirements for the initial thickness of the required patterned photoresist layer.
[0115] Thus, in this embodiment, the minimum thickness of the patterned photoresist layer to be formed during the spin coating process is deduced based on the bias power of the second plasma etching, and then a suitable photoresist material and / or spin coating speed is selected to ensure that the spin-coated photoresist layer reaches at least this minimum thickness.
[0116] Through this solution, based on the requirement for the thickness of the photoresist layer, the material of the photoresist used to form the photoresist layer and / or the spin coating speed can be flexibly selected to meet the bias power configuration during the second plasma etching, with better adaptability.
[0117] In a specific implementation, referring to Figure 8 , after the second plasma etching of the substrate, the method for forming the semiconductor device further includes step S21 and step S22:
[0118] Step S21, removing the patterned photoresist layer and the patterned second mask layer;
[0119] Step S22, etching the substrate using the patterned first mask layer as a mask.
[0120] Next, the above steps will be elaborated in detail in conjunction with Figures 9 to 10 the following.
[0121] Referring to Figure 9 , on the basis of obtaining the structure shown in Figure 6 , in step S21, the patterned photoresist layer 107 and the patterned second mask 106 are removed. At this time, the patterned first mask layer 105 and the silicon oxide layer 104 not covered by the first mask layer 105 are exposed.
[0122] Referring to Figure 10 , etching the substrate using the patterned first mask layer 105 as a mask to obtain an integrated silicon through hole and trench.
[0123] In some embodiments, etching the substrate using the patterned first mask layer 105 as a mask specifically means further etching the low dielectric insulating layer 103 and the silicon carbonitride film 102 on the surface of the silicon substrate using the patterned first mask layer 105 as a mask to expose at least a part of the copper substrate 108.
[0124] As described above, by adopting the solution of this embodiment, a method for forming a semiconductor device can be provided. By reasonably controlling the etching amount in the second plasma etching step, it is ensured that the plasma basically does not penetrate through the patterned second mask layer and the patterned photoresist layer on the premise of meeting the process etching requirements, thereby reducing or even avoiding damage to the substrate surface. Thus, while ensuring a good via etching effect, the degree of damage to the substrate surface after etching can be improved. For example, the degree of damage to the surface of the silicon oxide layer caused by the plasma as the patterned photoresist layer is consumed during the etching process can be reduced, thereby improving the device performance and yield.
[0125] Furthermore, in the case where the increase in the thickness of the patterned photoresist layer is limited, by reasonably controlling the etching amount of the substrate in the second plasma etching step, a better (e.g., lighter) degree of surface damage to the silicon oxide layer after the via etching is ensured.
[0126] Furthermore, in the case where the thickness of the patterned photoresist layer can be appropriately increased, a better degree of surface damage to the silicon oxide layer after the via etching is ensured by increasing the thickness. Further, a better way to avoid damage to the surface of the silicon oxide layer caused by etching can be achieved by combining the increase in thickness and the reasonable control of the etching amount.
[0127] It should be understood that the term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.
[0128] The term "a plurality of" appearing in the embodiments of this application refers to two or more.
[0129] The descriptions such as first and second appearing in the embodiments of this application are only for schematic and distinguishing the described objects, without an order, and do not particularly limit the number of devices in the embodiments of this application, and cannot constitute any limitation to the embodiments of this application.
[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor device, characterized in that, comprising: providing a substrate, on which a patterned first mask layer is formed; successively forming a second mask layer and a patterned photoresist layer on the first mask layer; using the patterned photoresist layer as a mask to perform a first plasma etching on the second mask layer to obtain a patterned second mask layer, and the patterned second mask layer exposes the substrate; using the patterned photoresist layer and the patterned second mask layer as masks to perform a second plasma etching on the substrate; wherein, in the step of performing the second plasma etching on the substrate, the etching amount of the substrate is less than the sum of the thicknesses of the patterned photoresist layer and the patterned second mask layer.
2. The method according to claim 1, characterized in that, the area of the substrate covered by the patterned first mask layer is less than the area of the substrate covered by the patterned second mask layer, and the thickness of the patterned second mask layer is the thickness of the region where the patterned second mask layer directly covers the substrate.
3. The method according to claim 1, characterized in that, the etching amount is determined according to the etching time and the etching rate, and the etching rate is positively correlated with the bias power. Before performing the second plasma etching on the substrate, it further includes: determining the etching time and the bias power according to the target etching amount so that the etching amount of the substrate in the step of performing the second plasma etching on the substrate is not less than the target etching amount.
4. The method according to claim 3, characterized in that, on the premise of ensuring that the etching amount reaches the target etching amount, the bias power used in the step of performing the second plasma etching on the substrate is less than the lower limit value of the process specification of the standard bias power for etching the substrate.
5. The method according to claim 4, characterized in that, the lower limit value of the process specification of the standard bias power for etching the substrate is taken from 1700W to 1800W, and the bias power used in the step of performing the second plasma etching on the substrate is taken from 1500W to 1600W.
6. The method according to claim 1, characterized in that, the bias power used in the step of performing the first plasma etching on the second mask layer is greater than the bias power used in the step of performing the second plasma etching on the substrate.
7. The method according to claim 6, characterized in that, after performing the first plasma etching on the second mask layer and before performing the second plasma etching on the substrate, it further includes: adjusting the bias power of the etching chamber from a first power value to a second power value, where the first power value is the bias power used in the step of performing the first plasma etching on the second mask layer, and the second power value is the bias power used in the step of performing the second plasma etching on the substrate.
8. The method according to claim 6, characterized in that, In the step of performing the first plasma etching on the second mask layer, the bias power used is not less than the lower limit of the process specification of the standard bias power for etching the second mask layer, and in the step of performing the second plasma etching on the substrate, the bias power used is less than the lower limit of the process specification of the standard bias power for etching the substrate.
9. The method according to claim 1, wherein, the forming of the patterned photoresist layer includes: forming the patterned photoresist layer with a first thickness by a spin coating process.
10. The method according to claim 9, wherein, after performing the first plasma etching on the second mask layer and before performing the second plasma etching on the substrate, further includes: calculating a second thickness according to the first thickness and the etching amount of the photoresist layer in the step of performing the first plasma etching on the second mask layer, wherein the second thickness is the remaining thickness of the patterned photoresist layer after the first plasma etching; determining a second power value according to the second thickness, wherein the second power value is the bias power used in the step of performing the second plasma etching on the substrate; adjusting the bias power of the etching chamber to the second power value.
11. The method according to claim 10, wherein, the second power value is positively correlated with the second thickness.
12. The method according to claim 9, wherein, the first thickness is greater than the upper limit of the process specification of the standard thickness when the patterned photoresist layer is formed by a spin coating process.
13. The method according to claim 9, wherein, the first thickness is related to the material of the photoresist. Before forming the patterned photoresist layer with the first thickness by a spin coating process, further includes: determining a lower limit value of the first thickness according to the bias power used in the step of performing the second plasma etching on the substrate; selecting the material of the photoresist used in the spin coating process according to the lower limit value of the first thickness.
14. The method according to claim 1, wherein, the first mask layer includes a metal hard mask layer, and / or, the second mask layer includes an anti-reflection layer.
15. The method according to claim 1, wherein, after performing the second plasma etching on the substrate, further includes: removing the patterned photoresist layer and the patterned second mask layer; etching the substrate using the patterned first mask layer as a mask.