Anti-fuse structure and manufacturing method thereof

Abstract

The invention discloses an anti-fuse structure and a manufacturing method thereof. The anti-fuse structure comprises a base material, a shallow trench isolation region, a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer and a conductive layer. The base material is provided with a base material surface; the shallow trench isolation region extends downwardly through the surface of the substrate into the substrate, and the shallow trench isolation region has a top surface and a recessed chamber extending downwardly from the top surface. The first dielectric layer is located above the shallow trench isolation region and covers the top surface of the shallow trench isolation region and a corner formed by the vertical wall of the concave chamber and the top surface of the shallow trench isolation region. A polysilicon layer is over the dielectric layer and covers the corner. The second dielectric layer is over the polysilicon layer and covers the corner. The conductive layer is over the second dielectric layer and covers the corner.

Description

Technical Field

[0001] The present invention relates to a semiconductor device structure and a manufacturing method thereof, and particularly to an anti-fuse structure and a manufacturing method thereof. Background Art

[0002] The manufacture of integrated circuits involves forming millions of electronic components on a single wafer or chip. In the manufacturing process, when detecting that some electronic components are faulty and may cause the failure of the integrated circuit, if the subsequent manufacturing process is aborted and the wafer or chip being processed is discarded, it will result in a waste of cost. The prior art has currently provided fuse / anti-fuse fault tolerance designs, arranging anti-fuses and fuses widely in integrated circuits. By burning out the fuse, the originally conductive circuit path becomes an open circuit; or by burning out the anti-fuse, the originally non-conductive circuit path becomes a short circuit, thereby rearranging the circuit path to exclude the faulty electronic components and maintaining the operating function of the integrated circuit without scrapping the entire wafer or chip.

[0003] However, taking a typical anti-fuse structure as an example, it is composed of an insulator (pattern) separating two conductors (patterns). The prior art uses an additional photomask etching manufacturing process to form the anti-fuse structure by patterning an additional insulating layer, conductor layer, and conductor. This not only significantly increases the manufacturing process steps and the number of photomasks used, but also increases the layout area and thickness dimensions of the integrated circuit, which is not conducive to the miniaturization of the integrated circuit.

[0004] Therefore, it is necessary to provide an advanced anti-fuse structure and a manufacturing method thereof to solve the problems faced by the prior art. Summary of the Invention

[0005] An embodiment of this specification discloses an anti-fuse structure, including: a substrate, a shallow trench isolation (STI) region, a first dielectric layer, a polysilicon layer, a second dielectric layer, and a conductive layer. The substrate has a substrate surface; the shallow trench isolation region extends downward through the substrate surface into the substrate, and the shallow trench isolation region has a top surface and a recess extending downward from the shallow top surface. The first dielectric layer is located above the shallow trench isolation region and covers the top surface and a corner formed by the vertical wall of the recess and the top surface of the shallow trench isolation region. The polysilicon layer is located above the dielectric layer and covers the corner. The second dielectric layer is located above the polysilicon layer and covers the corner. The conductive layer is located above the second dielectric layer and covers the corner.

[0006] Another embodiment of the present specification discloses a method for manufacturing an anti-fuse structure, including the following steps: First, provide a substrate, and form at least one shallow trench isolation region in the substrate, extending downward through the surface of the substrate into the substrate. Then, etch the shallow trench isolation region to form a recess extending downward from the top surface of the shallow trench isolation structure. After that, form a first dielectric layer above the shallow trench isolation region to cover the top surface and a corner formed by the vertical wall and the top surface of the recess; then form a polysilicon layer above the dielectric layer to cover the corner; form a second dielectric layer above the polysilicon layer to cover the corner; and form a conductive layer above the second dielectric layer to cover the corner.

[0007] According to the above embodiment, the present specification provides an anti-fuse structure and a method for manufacturing the same. By using the existing photomasks and manufacturing process steps used in manufacturing other semiconductor components in semiconductor manufacturing processes, first form a recess recessed from the top surface of the shallow trench isolation region in the shallow trench isolation region through an etching manufacturing process, and then sequentially form a first dielectric layer, a polysilicon layer, a second dielectric layer (for example, an interlayer dielectric (ILD)) and a conductive layer (for example, a metal wire layer) to cover the corner formed by the corner of this recess and the top surface of the shallow trench isolation region, so that the first distance between the part of the polysilicon layer corresponding to above the corner and the conductive layer is less than the second distance between other parts of the polysilicon layer and the conductive layer. Furthermore, an anti-fuse structure can be formed above the corner without (or without significantly) increasing the number of photomasks and manufacturing process steps, so as to provide an anti-fuse fault tolerance design in the integrated circuit manufacturing process. Description of the Drawings

[0008] To better understand the above and other aspects of the present specification, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows:

[0009] Figure 1 This is an embodiment of the present specification, showing a flowchart of the method steps for preparing an anti-fuse structure; and

[0010] Figures 2A to 2G This is an embodiment of the present specification, showing a cross-sectional view of the manufacturing process structure of a series of manufacturing process steps for preparing an anti-fuse structure.

[0011] Symbol Description

[0012] 100: Anti-fuse structure

[0013] 201: Semiconductor substrate

[0014] 201A: Component area

[0015] 201B: Anti-fuse area

[0016] 201s: Substrate surface

[0017] 201r: Recess

[0018] 202: Shallow trench isolation region

[0019] 202a: Etched top surface

[0020] 202s: Original top surface

[0021] 202r: Recess

[0022] 202w: Vertical wall

[0023] 202t: Etched top surface

[0024] 203: Patterned photoresist layer

[0025] 204: Corner

[0026] 205: First dielectric layer

[0027] 205G: Gate oxide layer

[0028] 206: Polysilicon layer

[0029] 206G: Gate electrode layer

[0030] 207: Lightly doped drain region

[0031] 208: Spacer

[0032] 209: Source / drain region

[0033] 210: Second dielectric layer

[0034] 210L: Interlayer dielectric layer

[0035] 211a:: Conductive plug

[0036] 211b: Conductive plug

[0037] 212: Conductive layer

[0038] 212M: Metal wire layer

[0039] T1: Transistor element

[0040] H1: First distance

[0041] H2: Second distance

[0042] S102: Provide a semiconductor substrate and form at least one shallow trench isolation region in the substrate, extending downward through the substrate surface into the semiconductor substrate.

[0043] S104: Etch the shallow trench isolation region in the antifuse region to form a recess extending downward from the original top surface of the shallow trench isolation structure.

[0044] S106: Form a first dielectric layer to cover the original top surface of the shallow trench isolation region and cover the corner formed by the sidewall and the original top surface of the etched shallow trench isolation region exposed to the outside.

[0045] S108: Form a polysilicon layer above the dielectric layer to cover the corner.

[0046] S110: Form a second dielectric layer above the polysilicon layer to cover the corner.

[0047] S112: Form a conductive layer above the second dielectric layer to cover the corner. Detailed implementation manners

[0048] This specification provides an antifuse structure and a manufacturing method thereof, which can provide an antifuse fault tolerance design for integrated circuits without (or with little) increasing the number of photomasks and manufacturing process steps. In order to make the above embodiments and other purposes, features and advantages of this specification more obvious and understandable, multiple embodiments are specifically given below and detailed descriptions are made in conjunction with the accompanying drawings.

[0049] However, it must be noted that these specific implementation cases and methods are not used to limit the present invention. The present invention can still be implemented by using other features, elements, methods and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention and are not used to limit the claims of the present invention. Those of ordinary skill in the art can make equal modifications and changes within the spirit of the present invention according to the following description of the specification. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0050] Please refer to Figure 1 , Figure 1 which is a flowchart showing the method steps for fabricating an antifuse structure 100 according to an embodiment of this specification; and Figures 2A to 2F which is a cross-sectional view of the manufacturing process structure showing a series of manufacturing process steps for fabricating an antifuse structure 100 according to an embodiment of this specification.

[0051] First, as described in step S102: Provide a semiconductor substrate 201, and form at least one shallow trench isolation region 202 in the semiconductor substrate 201, extending downward through the substrate surface 201s into the semiconductor substrate 201. In some embodiments of this specification, the semiconductor substrate 201 may be composed of a semiconductor material, such as silicon (Si), germanium (Ge), or a compound semiconductor material, such as gallium arsenide (GaAs). However, in other embodiments, the semiconductor substrate 201 may also be a silicon-on-insulator (SOI) substrate. In this embodiment, the semiconductor substrate 201 is preferably a silicon substrate, such as a silicon wafer.

[0052] Then, pattern the semiconductor substrate 201 through a photolithography etching manufacturing process to form at least one recess (depression) 201r in the semiconductor substrate 201, extending downward from the substrate surface 201s into the semiconductor substrate 201. Next, through a deposition manufacturing process, deposit a dielectric material on the substrate surface 201s for each recess (depression) 201r. Then, adopt a planarization manufacturing process (for example, chemical mechanical polishing (CMP)) to remove the dielectric material located above the substrate surface 201s, and form a shallow trench isolation region 202 in each recess (depression) 201r, extending downward through the substrate surface 201s into the semiconductor substrate 201, for at least dividing the semiconductor substrate 201 into an element region 201A and an antifuse region 201B. In this embodiment, the shallow trench isolation region 202 has an original top surface 202s that is substantially flush with the substrate surface 201s (as Figure 2A shown).

[0053] Next, as described in step S104: Etch the shallow trench isolation region 202 located in the antifuse region 201B to form a recess 202r extending downward from the original top surface 202s of the shallow trench isolation structure 202. For example, in this embodiment, a patterned photoresist layer 203 is covered on the substrate surface 201s, exposing the element region 201A and a part of the original top surface 202s of at least one shallow trench isolation region 202 located in the antifuse region 201B. Then, use the patterned photoresist layer 203 as an etching mask for dry etching, for removing a part of the semiconductor substrate 201 and a part of the shallow trench isolation region 202 located in the element region 201A and the antifuse region 201B, for forming a recess 202r extending downward from the original top surface 202s of the shallow trench isolation structure 202 in the shallow trench isolation region 202 in the antifuse region 201B.

[0054] Specifically, in the etching process using the patterned photoresist layer 203, a part of the shallow trench isolation region 202 in the antifuse region 201B can be removed to form a recess 202r extending downward from the original top surface 202s of the shallow trench isolation structure 202. Among them, a part of the original top surface 202s of the shallow trench isolation region 202 is covered by the patterned photoresist layer 203. Therefore, the etched shallow trench isolation region 202 includes at least one exposed vertical wall 202w and an etched top surface 202t, and the two jointly define the recess 202r. In addition, the exposed vertical wall 202w of the shallow trench isolation region 202 not only serves as the side wall of the recess 202r, but also is connected to the original top surface 202s of the unetched (covered by the patterned photoresist layer 203) shallow trench isolation region 202 and the etched top surface 202t of the shallow trench isolation region 202. And the side wall of the recess 202r (the exposed vertical wall 202w of the shallow trench isolation region 202) and the original top surface 202s of the unetched shallow trench isolation region 202 jointly define a corner 204 at their connection (as shown in Figure 2B shown).

[0055] Subsequently, as described in step S106: a first dielectric layer 205 is formed to cover the original top surface 202s of the shallow trench isolation region 202 and cover a corner 204 formed by the exposed vertical wall 201w and the original top surface 202s of the etched shallow trench isolation region 202. In some embodiments of the present specification, the first dielectric layer 205 can (but is not limited to this) be formed simultaneously with the gate oxide layer 205G on the device region 201A.

[0056] For example, in this embodiment, the formation of the first dielectric layer 205 includes the following steps: First, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material or other suitable dielectric materials is deposited on the substrate surface 201 and the shallow trench isolation region 202 by (for example, chemical vapor deposition (CVD)), and the deposited dielectric material is patterned to form the gate oxide layer 205G on the device region 201A, and at the same time, a first dielectric layer 205 is formed above the etched shallow trench isolation region 202, and the first dielectric layer 20 covers the corner 204 (as shown in Figure 2C shown).

[0057] Then, as described in step S108: a polysilicon layer 206 is formed above the dielectric layer 205 to cover the corner 204. In some embodiments of the present specification, the polysilicon layer 206 can (but is not limited to this) be formed simultaneously with the gate electrode layer 206G on the device region 201A.

[0058] For example, in this embodiment, the formation of the polysilicon layer 206 includes the following steps: First, deposit polysilicon on the device region 201A and the antifuse region 201B by (for example, chemical vapor deposition manufacturing process). And pattern the deposited polysilicon to form a gate electrode layer 206G above the gate oxide layer 205G in the device region 201A, and at the same time form a polysilicon layer 206 above the first dielectric layer 205, and make the polysilicon layer 206 cover above the corner 204 (as Figure 2D shown).

[0059] Subsequently, perform an ion implantation manufacturing process to form a lightly doped drain region 207 and a gate oxide layer 205G in the semiconductor substrate 201 of the device region 201A. Then, form a spacer 208 on the sidewalls of the gate electrode layer 206G and the gate oxide layer 205G, and perform another ion implantation manufacturing process to form a source / drain region 209 in contact with the lightly doped drain region 207 in the semiconductor substrate 201 of the device region 201A. The gate electrode layer 206G, the gate oxide layer 205G, the spacer 208, the lightly doped drain region 207, and the source / drain region 209 together form a transistor element T1 (as Figure 2E shown).

[0060] In another embodiment of this specification, the gate electrode layer 206G and the gate electrode layer 206G made of polysilicon material can be removed, a part of the substrate surface 201s in the device region 201A is exposed, and then through a series of deposition and patterning manufacturing processes, a seed barrier layer, a work function layer, and a metal gate layer (not shown) are sequentially formed on the exposed part of the substrate surface 201s to form a metal gate structure (not shown) to replace the silicon gate structure composed of the gate electrode layer 206G and the gate oxide layer 205G.

[0061] However, it should be noted that the manufacturing process steps performed in the device region 201A are not limited to this. Any manufacturing process steps that are not used to form the antifuse structure 100 of semiconductor components do not depart from the spirit and scope of the present invention.

[0062] Then, as described in step S110: form a second dielectric layer 210 above the polysilicon layer 206 to cover the corner 204. In some embodiments of this specification, the second dielectric layer 210 can be formed simultaneously with the interlayer dielectric layer 210L covering above the transistor element T1.

[0063] For example, in the present embodiment, the formation of the second dielectric layer 210 includes the following steps: First, a dielectric material (such as silicon oxide) is deposited on the device region 201A and the antifuse region 201B by (for example, chemical vapor deposition manufacturing process) to cover the polysilicon layer 206 and the transistor element T1. After planarizing the deposited dielectric material, an etching patterning manufacturing process is performed to form an interlayer dielectric layer 210L in the device region 201A, and at the same time, a second dielectric layer 210 covering the polysilicon layer 206 and the corner 204 is formed in the antifuse region 201B (as Figure 2F shown).

[0064] Then, as described in step S112: A conductive layer 212 is formed above the second dielectric layer 210 to cover the corner 204. In some embodiments of the present specification, the conductive layer 212 can be formed simultaneously with a metal wire layer 212M that is electrically connected to the gate oxide layer 205G and the source / drain region 209 of the transistor element T1, respectively.

[0065] For example, in the present embodiment, before forming the conductive layer 212 and the metal wire layer 212M, conductive plugs 211a and 211b that penetrate the interlayer dielectric layer 210L and are in contact with the gate oxide layer 205G and the source / drain region 209 of the transistor element T1, respectively, are formed in the device region 201A by an interconnect manufacturing process. Then, a metal layer is formed to cover the interlayer dielectric layer 210L in the device region 201A and the second dielectric layer 210 in the antifuse region 201B, for example, by physical vapor deposition (PVD) technology. The metal layer is then patterned by a photolithography etching manufacturing process to form a patterned metal wire layer 212M above the interlayer dielectric layer 210L, which includes a plurality of metal wires that are in contact with the conductive plugs 211a and 211b, respectively, and a conductive layer 212 is formed above the second dielectric layer 210 in the antifuse region 201B to cover the corner 204. A three-layer stack of the polysilicon layer 206, the second dielectric layer 210, and the conductive layer 212 can form an antifuse structure 100 in the antifuse region 201B.

[0066] Specifically, as Figure 2G shown, a first distance H1 between a part of the polysilicon layer 206 located (corresponding) at the corner 204 and the conductive layer 212 is substantially smaller than a second distance H2 between another part of the polysilicon layer 206 away from the corner 204 and the conductive layer 212. In other words, the resistance value (or the so-called initial resistance) of a part of the polysilicon layer 206 located (corresponding) at the corner 204 is substantially smaller than the resistance between another part of the polysilicon layer 206 away from the corner 204 and the conductive layer 212. The antifuse structure 100 is formed on a stacked structure of the polysilicon layer 206, a part of the second dielectric layer 210, and a part of the conductive layer 212 located (corresponding) at the corner 204.

[0067] When a relatively low voltage is applied to the conductive layer 212 and the polysilicon layer 206, no conductive path (i.e., an open circuit) is formed between the conductive layer 212 and the polysilicon layer 206. When a relatively high programming (or write) voltage is applied to the conductive layer 212 and the polysilicon layer 206, a part of the second dielectric layer 210 located at the corner will be melted and broken down due to an increase in the leakage current between the conductive layer 212 and the polysilicon layer 206, resulting in a thermal runaway state. This causes a conductive filament to form between a part of the polysilicon layer 206 located at the corner 204 and the conductive layer 212, leading to a short circuit between the two. As a result, a permanent conductive path can be formed in the second dielectric layer 210 to provide an anti-fuse fault tolerance design in semiconductor manufacturing processes. At this time, a part of the polysilicon layer 206 located at the corner 204 has a programming resistance that is much smaller than the initial resistance (for example, the programming resistance is 0). In some examples of this specification, the programming voltage can substantially range between -3.3V and 7.5V.

[0068] According to the above embodiments, this specification provides an anti-fuse structure and a manufacturing method thereof. By using the existing photomasks and manufacturing process steps used in semiconductor manufacturing processes for manufacturing other semiconductor components, first, an etching manufacturing process is used to form a recess in the top surface of the shallow trench isolation region in the shallow trench isolation region. Then, a first dielectric layer, a polysilicon layer, a second dielectric layer (e.g., an interlayer dielectric layer), and a conductive layer (e.g., a metal wire layer) are sequentially formed to cover the corner formed by the recess in the corner of the shallow trench isolation region and the top surface of the shallow trench isolation region, such that the first distance between the part of the polysilicon layer corresponding to the corner above and the conductive layer is less than the second distance between other parts of the polysilicon layer and the conductive layer. Thus, an anti-fuse structure can be formed above the corner without (or with little) increasing the number of photomasks and manufacturing process steps, to provide an anti-fuse fault tolerance design in integrated circuit manufacturing processes.

[0069] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art in this technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. An anti-fuse structure, comprising: a substrate having a substrate surface; a Shallow Trench Isolation (STI) region that extends downward through the substrate surface into the substrate, and the shallow trench isolation has a top surface and a recess extending downward from the top surface; a first dielectric layer located above the shallow trench isolation region and covering the top surface and the corner formed by the vertical wall of the recess and the top surface; a polysilicon layer located above the dielectric layer and covering the corner; a second dielectric layer located above the polysilicon layer and covering the corner; and a conductive layer located above the second dielectric layer and covering the corner.

2. The anti-fuse structure according to claim 1, wherein a first distance exists between a part of the polysilicon layer corresponding to the corner and the conductive layer; another part of the polysilicon layer away from the corner has a second distance from the conductive layer, and the first distance is less than the second distance.

3. The anti-fuse structure according to claim 1, wherein the part of the polysilicon layer corresponding to the corner has an initial resistance; after applying a programming voltage to the conductive layer, the part of the polysilicon layer corresponding to the corner has a programming resistance, and the programming resistance is substantially less than the initial resistance.

4. The anti-fuse structure according to claim 3, wherein the programming voltage is substantially between -3.3V and 7.5V.

5. The anti-fuse structure according to claim 1, wherein the first dielectric layer is a gate dielectric layer; the polysilicon layer is a gate electrode layer; the second dielectric layer is an interlayer dielectrics (ILD); and the conductive layer is a metal wire layer.

6. A method for manufacturing an anti-fuse structure, comprising: providing a substrate; forming a shallow trench isolation region in the substrate that extends downward through the substrate surface into the substrate; etching the shallow trench isolation region to form a recess extending downward from the top surface of the shallow trench isolation structure; forming a first dielectric layer above the shallow trench isolation region to cover the top surface and the corner formed by the vertical wall of the recess and the top surface; forming a polysilicon layer above the dielectric layer to cover the corner; forming a second dielectric layer above the polysilicon layer to cover the corner; and forming a conductive layer above the second dielectric layer to cover the corner.

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