Clock burr-free output circuit and chip

Abstract

The invention relates to a clock burr-free output circuit and a chip. The clock burr-free output circuit comprises an oscillation stop detection circuit which is used for carrying out frequency division on a monitoring clock signal to generate a frequency division monitoring clock heartbeat signal and converting the frequency division monitoring clock heartbeat signal to a reference clock frequency domain in a cross-clock domain mode, determining whether the monitoring clock stops oscillation or not according to the frequency division monitoring clock heartbeat signal in the reference clock frequency domain, and outputting a detection result; and the burr-free clock output circuit is used for receiving a clock output selection signal and the detection result, and outputting a burr-free reference clock signal or a burr-free monitoring clock signal according to the clock output selection signal and the detection result. By adopting the circuit, the clock signal can be output without burrs.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a clock glitch-free output circuit and a chip. Background Art

[0002] Clock is a very important concept in chips. For a chip, the following scenarios of clock switching or frequency change are often involved:

[0003] 1) Initialization. During the chip initialization process, it is often necessary to configure the PLL to generate a reliable high-frequency clock. Before the PLL (Phase Locked Loop, which is used to uniformly integrate clock signals to enable high-frequency devices to work properly, such as accessing data in memory, etc.) outputs a stable clock, the chip operates based on a low-frequency reference clock (the reference clock generally directly comes from a crystal oscillator). After the PLL outputs a stable clock, the clock switches from the reference clock to the stable high-frequency clock output by the PLL;

[0004] 2) Low power consumption. In the low-power consumption scenario, the performance requirement is not high, and it is sensitive to power consumption. Generally, the clock frequency will be reduced (adjust the PLL configuration, or directly switch to work with a low-frequency clock);

[0005] 3) Adapt to peripherals. When there are multiple chip design specifications, a margin is left for the selection of peripherals. When different models of peripherals are selected, or when it is desired to adjust the interaction rate with the peripherals, it may be necessary to switch the clock frequency;

[0006] 4) Adaptive adjustment. Due to the influence of the chip's working environment voltage and temperature, when the chip detects that it is necessary to reduce the clock frequency to reduce the timing risk and ensure normal operation, it will actively adjust the PLL to reduce the clock frequency;

[0007] 5) Abnormal scenarios. There are two types, ① the clock quality suddenly deteriorates; ② the clock suddenly stops oscillating. For example:

[0008] a) The PLL is abnormal, resulting in the deterioration or even stoppage of the clock quality of the PLL output;

[0009] b) The clock source comes from the outside. When the external device powers off abnormally or fails to comply with the protocol specification when powering off, the clock stops oscillating.

[0010] One of the means to solve this problem is to switch the clock. During the clock switching process, if clock glitches are introduced, it may cause abnormal operation of the chip. Summary of the Invention

[0011] Based on this, in view of the above technical problems, it is necessary to provide a clock glitch-free output circuit and a chip that can output a clock signal without glitches.

[0012] The present application provides a clock glitch-free output circuit, including:

[0013] An oscillation stop detection circuit, configured to divide the monitored clock signal to generate a divided monitored clock heartbeat signal, convert the divided monitored clock heartbeat signal across clock domains to the reference clock frequency domain, determine whether the monitored clock stops oscillating according to the divided monitored clock heartbeat signal in the reference clock frequency domain, and output a detection result;

[0014] A glitch-free clock output circuit, configured to receive a clock output selection signal and the detection result, and output a glitch-free reference clock signal or monitored clock signal according to the clock output selection signal and the detection result.

[0015] In one embodiment, the oscillation stop detection circuit includes:

[0016] A frequency division module, configured to receive the monitored clock signal and divide the monitored clock signal to generate a divided monitored clock heartbeat signal;

[0017] A frequency domain conversion module, configured to convert the divided monitored clock heartbeat signal from the monitored clock frequency domain to the reference clock frequency domain;

[0018] An oscillation stop detection module, configured to monitor the number of flips of the divided monitored clock heartbeat signal, and determine that the monitored clock stops oscillating when the number of flips of the divided monitored clock heartbeat meets a set condition, otherwise, the monitored clock does not stop oscillating.

[0019] In one embodiment, the frequency division module includes a first counter and a first comparator;

[0020] The first counter is configured to count the monitored clock signal, and reset the count value of the first counter to 0 when the count value of the first counter reaches a first set value;

[0021] The first comparator is configured to compare the count value of the first counter with the first set value, and output the divided monitored clock heartbeat signal based on the comparison result.

[0022] In one embodiment, the oscillation stop monitoring module includes a transition edge detection module, a second counter, and an oscillation stop determination module;

[0023] The transition edge detection module is configured to detect the rising edge or falling edge of the divided monitored clock heartbeat signal;

[0024] The second counter is configured to reset the count value of the second counter to a second set value when the edge detection module detects a rising edge or a falling edge of the frequency-divided monitoring clock heartbeat signal, and subtract 1 from the second counter in each reference clock cycle when the edge monitoring module does not detect a rising edge and a falling edge of the frequency-divided monitoring clock heartbeat signal until the count value of the second counter becomes 0;

[0025] An oscillation stop determination module, configured to determine that the monitoring clock has stopped oscillating when the count value of the second counter is 0.

[0026] In one embodiment, if the frequency of the monitoring clock is f det , and the frequency of the reference clock is f ref , the first set value is T 1 , and the second set value is T 2 ,

[0027] In the case where f det is greater than or equal to f ref , if T 1 satisfies the following condition:

[0028]

[0029] then the second set value T 2 = 3;

[0030] In the case where f det is less than f ref , if T 1 satisfies the following condition:

[0031] T 1 = 1;

[0032] then T 2 is an integer greater than .

[0033] In one embodiment, the glitch-free clock output circuit includes:

[0034] An interlock module, configured to receive a clock output selection signal and a detection result signal of the oscillation stop detection circuit, output a selection clock control signal for selecting a reference clock output when the detection result is that the monitoring clock has stopped oscillating, and further configured to, when the detection result is that the monitoring clock has not stopped oscillating, output a selection clock control signal for selecting a reference clock output when the clock output selection signal is a reference clock selection signal, and output a selection clock control signal for selecting a monitoring clock output when the clock output selection signal is a monitoring clock selection signal;

[0035] A clock control output module for outputting a glitch-free monitoring clock signal or a glitch-free reference clock signal based on the selected clock control signal.

[0036] In one embodiment, the interlock module includes:

[0037] A reference clock output control signal synchronization unit for outputting a second selected clock control signal indicating whether to select the reference clock based on the detection result of the oscillation stop detection circuit, the clock output selection signal, and the first selected clock control signal;

[0038] A monitoring clock output control signal synchronization unit for outputting a first selected clock control signal indicating whether to select the monitoring clock based on the clock output selection signal and the second selected clock control signal;

[0039] A clock oscillation stop signal asynchronous reset synchronization unit for asynchronously resetting and synchronizing the clock oscillation stop signal and controlling the operation of the monitoring clock output control signal synchronization unit based on the signal obtained from the asynchronous reset synchronization.

[0040] In one embodiment, the reference clock output control signal synchronization unit includes:

[0041] A first NOT gate with the clock output selection signal input to its input terminal;

[0042] A first OR gate with the clock oscillation stop signal input to its first input terminal and the output terminal of the first NOT gate connected to its second input terminal;

[0043] A first AND gate with the output terminal of the first OR gate connected to its first input terminal and the opposite value of the first selected clock control signal input to its second input terminal;

[0044] A first synchronization sub-unit with its input terminal connected to the output terminal of the first AND gate and its output terminal outputting the second selected clock control signal to control the clock as the reference clock;

[0045] The monitoring clock output control signal synchronization unit includes:

[0046] A second AND gate with the clock output selection signal input to its first input terminal and the opposite value of the second selected clock control signal input to its second input terminal;

[0047] A second synchronization sub-unit with its input terminal connected to the output terminal of the second AND gate and its output terminal outputting the first selected clock control signal to control the clock as the monitoring clock;

[0048] The control terminal of the clock stop oscillation signal asynchronous reset synchronization unit inputs the clock stop oscillation signal, the input terminal inputs 1, the control clock is the monitoring clock, and the output terminal outputs the signal obtained by asynchronous reset synchronization.

[0049] In one embodiment, the clock control output module includes:

[0050] A third AND gate, the first input terminal inputs the second selection clock control signal, and the second input terminal inputs the reference clock signal;

[0051] A fourth AND gate, the first input terminal inputs the first selection clock control signal, and the second input terminal inputs the monitoring clock signal;

[0052] A second OR gate, the first input terminal is connected to the output terminal of the third AND gate, the second input terminal is connected to the output terminal of the fourth AND gate, and the output terminal outputs the monitoring clock or the reference clock.

[0053] In a second aspect, the present application further provides a chip, including the clock glitch-free output circuit described in any one of the above embodiments.

[0054] The above clock glitch-free output circuit and chip include a stop oscillation detection circuit and a glitch-free clock output circuit. The stop oscillation detection circuit is used to divide the frequency of the monitoring clock signal to generate a divided-frequency monitoring clock heartbeat signal, and convert the divided-frequency monitoring clock heartbeat signal across the clock domain to the reference clock frequency domain. In the reference clock frequency domain, it is determined whether the monitoring clock stops oscillating according to the divided-frequency monitoring clock heartbeat signal, and the detection result is output; the glitch-free clock output circuit is used to receive the clock output selection signal and the detection result, and output a glitch-free reference signal or monitoring clock signal according to the clock output selection signal and the detection result. In this way, the divided-frequency monitoring clock heartbeat signal is converted across the clock domain to the reference clock frequency domain, and in the reference clock frequency domain, it is determined whether the monitoring clock stops oscillating according to the divided-frequency monitoring clock heartbeat signal. Finally, based on the clock output selection signal and the detection result of whether it stops oscillating, a glitch-free reference clock signal or monitoring clock signal can be output. Description of the Drawings

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0056] Figure 1 Schematic diagram of clock glitches;

[0057] Figure 2 is the circuit diagram of the switching circuit in the traditional technology;

[0058] Figure 3 is the circuit diagram of the switching circuit in another traditional technology;

[0059] Figure 4 is the module schematic diagram of the clock glitch-free output circuit in one embodiment;

[0060] Figure 5 is the module schematic diagram of the oscillation stop detection circuit in one embodiment;

[0061] Figure 6 is the circuit diagram of the glitch-free clock output circuit in one embodiment. Detailed implementation manners

[0062] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0063] Combined with Figure 1 as shown, during the clock switching process, if clock glitches are introduced, it may cause abnormal operation of the chip.

[0064] For example, Figure 1 in [reference], sel_clk is the output clock after the selection of clk1 and clk2. Clock switching occurs at the red line. Before the red line (left), clk1 is selected, and after the red line (right), clk2 is selected. A clock glitch is generated at the arrow. If the circuit is sensitive to the clock duty cycle, the circuit will malfunction. The reason why clock glitches cause problems is that clock glitches are used as clocks, and their quality is uncontrollable. It is impossible to predict how clock glitches will occur and what their characteristics are.

[0065] To address this problem, usually the output clock is turned off before switching the clock.

[0066] 1) The software control method is to add Figure 1 an input clock gating (ICG) to sel_clk in [reference]. Before switching the clock, configure the ICG so that it does not output the clock, and then turn it on after the switching is completed. Its circuit structure is simple, with one-level SMUX for clock selection and one-level ICG for clock gating.

[0067] 2) The hardware control method uses a clock glitch-free switching circuit. The core idea is to add ICGs to the two input clocks respectively for clock gating. When a clock switch occurs, first turn off the currently selected clock, and then turn on the newly selected clock. The output clock is the OR of the two controlled clocks. Since the two input clocks are often asynchronous, the control path in this circuit needs to be synchronized from one clock to the other. When either of these two clocks stops oscillating, the circuit cannot work properly.

[0068] In summary, when in an abnormal scenario, neither the software control method nor the glitch-free switching circuit can handle it perfectly. When the output clock is used for the CPU or the configuration path, since the configuration command cannot be issued normally, the circuit cannot switch to the backup clock. Therefore, in the face of an expected abnormal scenario, a circuit that supports automatic glitch-free clock switching is needed.

[0069] For the abnormal scenario where the clock quality deteriorates, it is very likely that the circuit is already abnormal, and in this case, it should be restarted directly. For the abnormal scenario where the clock stops oscillating, the circuit state is still normal, but the clock temporarily stops, and the circuit can still work normally after the clock is restored. The clock that may stop oscillating is called the monitoring clock, and the alternative clock that will not stop oscillating is called the reference clock. The clock selected from the two is called the output clock. Normally, the circuit selects the monitoring clock as the output clock. Considering the abnormal scenario of clock stoppage, the circuit that supports automatic glitch-free clock switching needs to meet the following requirements:

[0070] 1) Detect whether the monitoring clock has stopped oscillating;

[0071] 2) After the monitoring clock stops oscillating, the output clock switches to the reference clock without glitches;

[0072] 3) After the monitoring clock resumes, the output clock switches back to the monitoring clock without glitches.

[0073] The common method for detecting whether the monitoring clock has stopped oscillating is to use the monitoring clock to generate a certain logic and then use the reference clock to make a judgment. The specific methods are as follows:

[0074] 1) The monitoring clock is a high-frequency clock, and unconditional counting is performed. After the count value crosses the clock domain to the reference clock, sampling is performed using the reference clock. Since the count value is generated at a high frequency, under normal circumstances, when the count value is sampled at a low frequency, the count value will be different in each cycle. When the monitoring clock stops oscillating, on the one hand, the count value no longer counts, and on the other hand, the circuit across the clock domain may also fail to work, and the count value seen by the reference clock will remain unchanged. At this time, it can be determined that the monitoring clock has stopped oscillating.

[0075] 2) Use a reference clock to generate a clear signal at a certain period, and synchronize this signal under the monitoring clock. Maintain an unconditional counter under the monitoring clock. Whenever the clear signal is detected, it is cleared to 0; otherwise, it increments by 1. Under normal circumstances, when the clear signal arrives, the count value under the monitoring clock should be a fixed value (due to cross-clock domain reasons, there may be a slight error value). When the clear signal arrives, determine whether the count value is normal under the monitoring clock, and generate a flag indicating whether the clock has stopped oscillating. Under the reference clock, if the flag signal indicating that the clock has not stopped oscillating is not detected, it means that the clock has stopped oscillating.

[0076] For the case where the output clock switches to the reference clock without glitches after the monitoring clock stops oscillating, the main method is to transform the glitch-free switching circuit. Specifically, it can be combined with Figure 2 as shown Figure 2 is a schematic diagram of a glitch-free switching circuit in the traditional technology. In this embodiment, an additional selection path for wdt_rst_n is added. When hclk stops oscillating, wdt_rst_n changes from 1 to 0. In the lclk clock path, the input of q1 becomes 1. Since lclk has not stopped oscillating, after synchronization, both ends of AND gate A see q3 output 1 and lclk, and A outputs the clock lclk; in the hclk clock path, although the input of q2 becomes 0, since hclk has stopped oscillating, the new value cannot be synchronized to the output of q4. Therefore, at the B end of the AND gate, the output value of q4 is 1 and the stopped hclk are seen. If hclk is low when it stops oscillating, then B outputs 0, and out_clk outputs the output value of A, that is, lclk; if hclk is high when it stops oscillating, then B outputs 1, and the output value of out_clk is 1. That is, this modified circuit can only complete the glitch-free switching of the output clock to the reference clock when hclk is low when it stops oscillating; if hclk is high when it stops oscillating, the output clock remains high, and the above function cannot be completed.

[0077] After the monitoring clock resumes, the common practice for the output clock to switch back to the monitoring clock without glitches is to modify the glitch-free switching circuit. Still combined with Figure 2 , when hclk resumes oscillation, wdt_rst_n changes from 0 to 1. In the lclk clock path, the new value input at the q1 end needs two clock cycles to be synchronized to A, and A will see the old value 1 for two clock cycles before it can see the new value. In the hclk clock path, the new value input at the q2 end needs two clock cycles to be synchronized to B, and B will see the old value 1 for two clock cycles (when hclk stops oscillating, the input value of q2 cannot be synchronized, and q4 always outputs the state before hclk stops oscillating, that is, 1). Therefore, when hclk resumes oscillation, A and B will briefly output the clock simultaneously, and out_clk is the OR of these two clocks, and there is likely to be a clock glitch.

[0078] In addition, it can also be combined with Figure 3 as shown, by Figure 2Cascade the circuit shown in with a glitch-free switching circuit to avoid this problem. When it is detected that the monitoring clock stops oscillating, the clock stop glitch-free switching circuit selects the reference clock output, and a reference clock arrives at point A of the glitch-free switching circuit. At this time, modify the clock selection of the glitch-free switching circuit to use the reference clock at point B instead. In this way, when the monitoring clock resumes oscillation, even if the clock stop glitch-free switching circuit causes clock glitches at point A, they will not be transmitted to the output clock. After the clock at point A stabilizes (after waiting for a period of time for the monitoring clock to resume), select the clock at point A again.

[0079] However, it should be noted that if the monitoring clock is at a high level when it stops oscillating, the value at point A is 1, and the glitch-free switching circuit cannot work. At this time, the output clock is 1 (high level), and the above functions cannot be achieved.

[0080] And Figure 3 The circuit shown in requires two levels of clock selection. On the one hand, it has a relatively large resource overhead. On the other hand, the more devices the clock path passes through, the worse the clock quality. In addition, a certain process needs to be coordinated in control. Most importantly, when the monitoring clock stops oscillating, its value is unpredictable. If it is at a high level, the traditional technology cannot work properly.

[0081] To solve the above technical problems, on the one hand, this application improves the clock stop detection circuit, so that fewer cross-clock domain signals can be used, and there are no requirements for the frequencies of the monitoring clock and the reference clock; on the other hand, it improves the clock switching circuit, so that after the monitoring clock stops oscillating, the output clock switches to the reference clock without glitches; after the monitoring clock resumes, the output clock switches back to the monitoring clock without glitches. Moreover, the clock switching circuit of this application only requires one level of clock selection, rather than two or more levels of clock selection in the traditional technology, reducing the resource overhead and shortening the clock path; in addition, it uses a hardware circuit for processing, with a rapid response and no need for software intervention; it also solves the problem that the traditional technology cannot work properly when the monitoring clock stops oscillating and is at a high level.

[0082] Combined with Figure 4 shown in Figure 4It is a schematic diagram of the module of the clock glitch-free output circuit in an embodiment. In this embodiment, the clock glitch-free output circuit includes a stop oscillation detection circuit and a glitch-free clock output circuit. The output terminal of the stop oscillation detection circuit is connected to the clock stop oscillation signal input terminal of the glitch-free clock output circuit. The input terminals of the stop oscillation detection circuit include a monitoring clock signal input terminal and a reference clock signal input terminal, which are respectively used for inputting a monitoring clock signal and a reference clock signal. The input terminals of the glitch-free clock output circuit include a clock stop oscillation signal input terminal, a clock output selection signal input terminal, a monitoring clock signal input terminal, and a reference clock signal input terminal, which are respectively used for inputting a clock stop oscillation signal, a clock output selection signal, a monitoring clock signal, and a reference clock signal. The output terminal of the glitch-free clock output circuit is used for outputting a glitch-free reference clock signal or monitoring clock signal.

[0083] Among them, the stop oscillation detection circuit is used to divide the frequency of the monitoring clock signal to generate a divided-frequency monitoring clock heartbeat signal, and convert the divided-frequency monitoring clock heartbeat signal across clock domains to the reference clock frequency domain. In the reference clock frequency domain, it determines whether the monitoring clock stops oscillating according to the divided-frequency monitoring clock heartbeat signal and outputs the detection result; the glitch-free clock output circuit is used to receive the clock output selection signal and the detection result, and output a glitch-free reference clock signal or monitoring clock signal according to the clock output selection signal and the detection result.

[0084] Among them, the divided-frequency monitoring clock heartbeat signal is generated by dividing the frequency of the monitoring clock signal. When the monitoring clock does not stop oscillating, the divided-frequency monitoring clock heartbeat signal can flip normally. When the monitoring clock stops oscillating, the divided-frequency monitoring clock heartbeat signal cannot flip for a long time.

[0085] In some alternative embodiments, the size of the divided-frequency monitoring clock heartbeat signal is a target size, and the target size is 1 bit. In this way, when the 1-bit divided-frequency monitoring clock heartbeat signal crosses the clock domain to the reference clock, only two or three beats of synchronization are required, which can simplify the processing of the signal across the clock domain.

[0086] In the reference clock frequency domain, determining whether the monitoring clock stops oscillating based on the divided-frequency monitoring clock heartbeat signal may include monitoring whether the divided-frequency monitoring clock heartbeat signal flips normally. If the divided-frequency monitoring clock heartbeat signal flips normally, the monitoring clock does not stop oscillating. If the divided-frequency monitoring clock heartbeat signal does not flip for a long time, the monitoring clock signal stops oscillating. Thus, it can be determined whether the monitoring clock stops oscillating by identifying the divided-frequency monitoring clock heartbeat signal.

[0087] The burr-free clock output circuit can output a burr-free reference clock signal or a monitoring clock signal based on a clock output selection signal and a detection result of monitoring whether the clock stops oscillating. For example, after the oscillation stop monitoring circuit detects that the monitoring clock stops oscillating, it outputs a burr-free reference clock signal. When the oscillation stop detection circuit detects that the monitoring clock does not stop oscillating, it outputs a burr-free reference clock signal or a monitoring clock signal based on the clock output selection signal.

[0088] In the above embodiment, the divided-frequency monitoring clock heartbeat signal is converted across clock domains to the reference clock frequency domain, and whether the monitoring clock stops oscillating is determined according to the divided-frequency monitoring clock heartbeat signal in the reference clock frequency domain. Finally, based on the clock output selection signal and the detection result of whether it stops oscillating, a burr-free reference clock signal or a monitoring clock signal can be output.

[0089] In some alternative embodiments, the oscillation stop detection circuit includes: a frequency division module, a frequency domain conversion module, and an oscillation stop detection module; wherein the input end of the frequency division module inputs a monitoring clock signal, the output end of the frequency division module is connected to the input end of the frequency domain conversion module, the output end of the frequency domain conversion module is connected to the input end of the divided-frequency monitoring clock heartbeat signal of the oscillation stop detection module, and the oscillation stop detection module further includes a reference clock signal input end for inputting a reference clock signal, and the output end of the oscillation stop detection module is used to output an oscillation stop detection signal, and this oscillation stop detection signal is used to indicate whether the monitoring clock stops oscillating. Among them:

[0090] The frequency division module is used to receive the monitoring clock signal and perform frequency division on the monitoring clock signal to generate a divided-frequency monitoring clock heartbeat signal.

[0091] The frequency domain conversion module is used to convert the divided-frequency monitoring clock heartbeat signal from the monitoring clock frequency domain to the reference clock frequency domain.

[0092] The oscillation stop detection module is used to monitor the number of flips of the divided-frequency monitoring clock heartbeat signal. When the number of flips of the divided-frequency monitoring clock heartbeat meets the set condition, it is determined that the monitoring clock stops oscillating; otherwise, the monitoring clock does not stop oscillating.

[0093] Specifically, as shown in Figure 5 shown, Figure 5 is a module schematic diagram of the oscillation stop detection circuit in an embodiment. In this embodiment, the oscillation stop detection circuit includes three parts, namely a frequency division module, a frequency domain conversion module, and an oscillation stop detection module. Among them, the frequency division module is used to perform frequency division on the monitoring clock signal to generate a divided-frequency monitoring clock heartbeat signal. When the monitoring clock signal stops oscillating, the divided-frequency monitoring clock heartbeat signal output by the frequency division module through frequency division of the stopped monitoring clock signal cannot flip normally. When the monitoring clock signal does not stop oscillating, the divided-frequency monitoring clock heartbeat signal output by the frequency division module through frequency division of the stopped monitoring clock signal flips normally.

[0094] In some alternative embodiments, the frequency division module includes a first counter and a first comparator; a monitoring clock signal is input to the input end of the first counter, the output end of which is connected to the first input end of the first comparator, a first set value is input to the second input end of the first comparator, and a frequency division monitoring clock heartbeat signal is output from the output end of the first comparator, and the output end of the first comparator serves as the output end of the frequency division module. Wherein:

[0095] The first counter is configured to count the monitoring clock signal, and when the count value of the first counter reaches the first set value, reset the count value of the first counter to 0; the first comparator is configured to compare the count value of the first counter with the first set value and output a frequency division monitoring clock heartbeat signal based on the comparison result.

[0096] Please continue to refer to Figure 5 As shown, the frequency division module can be regarded as a logic circuit, which includes a first counter. The first counter is configured to count under the monitoring clock signal and reset the count value of the first counter to 0 when the count value of the first counter reaches the first set value, where the first set value is adjusted according to the frequency of the monitoring clock and the frequency of the reference clock. The first comparator is configured to compare the count value of the first counter with the first set value to obtain a comparison result, and when the comparison result is that the count value of the first counter is equal to the first set value, flip the frequency division monitoring clock heartbeat signal, and when the comparison result is that the count value of the first counter is less than the first set value, do not flip the frequency division monitoring clock heartbeat signal.

[0097] In summary, the frequency division module can flip the frequency division monitoring clock heartbeat signal under the monitoring clock signal. Therefore, when the monitoring clock signal stops oscillating, the frequency division monitoring clock heartbeat signal cannot be flipped normally, so it is possible to determine whether the monitoring clock stops oscillating by detecting the flipping situation of the frequency division monitoring clock heartbeat signal.

[0098] The input end of the frequency domain conversion module is connected to the output end of the frequency division module, and the output end is connected to the input end of the oscillation stop detection module. The frequency domain conversion module is configured to synchronize the frequency division monitoring clock heartbeat signal from the monitoring clock signal frequency domain to the reference clock signal frequency domain, and since the frequency division monitoring clock heartbeat signal is a 1-bit signal, only two or three beats of synchronization are required.

[0099] The oscillation stop detection module is used to detect the inversion of the divided-frequency monitoring clock heartbeat signal. For example, it can detect whether the number of inversions of the divided-frequency monitoring clock heartbeat signal within a period of time meets the set conditions. If so, it is determined that the monitoring clock has stopped oscillating. The set conditions may include that the number of inversions of the divided-frequency monitoring clock heartbeat signal is 0. In other embodiments, the set conditions may also include that the number of inversions of the divided-frequency monitoring clock heartbeat signal is less than a number threshold, and the number threshold is the number of inversions of the divided-frequency monitoring clock heartbeat signal within a period of time when the monitoring clock signal has not stopped oscillating.

[0100] To obtain the number of inversions of the divided-frequency monitoring clock heartbeat signal, a counter is introduced in this application, and the counter is used to count the number of inversions of the divided-frequency monitoring clock heartbeat signal.

[0101] Continue to refer to Figure 5 As shown, in some alternative embodiments, the oscillation stop monitoring module includes a transition edge detection module, a second counter, and an oscillation stop determination module. The input end of the transition edge detection module is connected to the output end of the frequency domain conversion module, the output end of the transition edge detection module is connected to the input end of the second counter, the output end of the second counter is connected to the first input end of the oscillation stop determination module, a second set value is input to the second input end of the oscillation stop determination module, and the output end of the oscillation stop determination module is the detection result of whether the monitoring clock has stopped oscillating.

[0102] The transition edge detection module is used to detect the rising edge or falling edge of the divided-frequency monitoring clock heartbeat signal.

[0103] The second counter is used to reset the count value of the second counter to the second set value when the transition edge detection module detects the rising edge or falling edge of the divided-frequency monitoring clock heartbeat signal, and subtract 1 from the second counter in each reference clock cycle when the transition edge monitoring module does not detect the rising edge and falling edge of the divided-frequency monitoring clock heartbeat signal until the count value of the second counter is 0.

[0104] The oscillation stop determination module is used to determine that the monitoring clock has stopped oscillating when the count value of the second counter is 0.

[0105] Optionally, the edge detection module may include an exclusive-OR unit and a delay unit. The first input terminal of the exclusive-OR unit and the input terminal of the delay unit are connected to the output terminal of the frequency-domain conversion module. The output terminal of the delay unit is connected to the second input terminal of the exclusive-OR unit. The output terminal of the exclusive-OR unit is the output terminal of the edge detection module. The delay unit is configured to delay the input divided-frequency monitoring clock heartbeat signal by one clock cycle. The exclusive-OR unit is configured to perform an exclusive-OR calculation on the input divided-frequency monitoring clock heartbeat signal and the divided-frequency monitoring clock heartbeat signal delayed by one clock cycle to obtain an exclusive-OR result, and determine the rising edge or falling edge of the divided-frequency monitoring clock heartbeat signal based on the exclusive-OR result.

[0106] The second counter is maintained under the reference clock signal. The second counter is used to count the number of flips (a flip refers to the rising edge and falling edge of the divided-frequency monitoring clock heartbeat signal). Optionally, in this application, the edge monitoring module is used to detect whether there is a flip in the divided-frequency monitoring clock heartbeat signal. If there is a flip, the count value of the second counter is reset to the second set value. That is, when there is a flip in the divided-frequency monitoring clock heartbeat signal, it is determined that the monitoring clock does not stop oscillating; otherwise, the count value of the second counter is decremented by 1 in each reference clock cycle until the count value of the second counter becomes 0. That is, if there is no flip signal in the divided-frequency monitoring clock heartbeat signal for a certain period of time, it indicates that the monitoring clock has stopped oscillating.

[0107] Optionally, the oscillation stop determination module may include a second comparator. The first terminal of the second comparator is connected to the output terminal of the second counter, and the second terminal of the second comparator is connected to 0. When the second comparator determines that the count value of the second counter is 0, it is determined that the monitoring clock has stopped oscillating.

[0108] In some alternative embodiments, when at least one of the frequency of the monitoring clock and the frequency of the reference clock changes, adaptation can be performed by adjusting the first set value and the second set value.

[0109] In some alternative embodiments, if the frequency of the monitoring clock is f det , the frequency of the reference clock is f ref , the first set value is T 1 , and the second set value is T 2 ,

[0110] When f det is greater than or equal to f ref , if T 1 satisfies the following conditions:

[0111]

[0112] then the second set value T 2 = 3;

[0113] When f det is less than f ref and T 1 satisfies the following conditions:

[0114] T 1 = 1;

[0115] then T 2 is an integer greater than .

[0116] Wherein, when f det is greater than or equal to f ref , in order to ensure that the reference clock can definitely sample the flip of the divided - frequency monitoring clock heartbeat signal, the flip period of the divided - frequency monitoring clock heartbeat signal is made to be in the range of 1 to 2 times (excluding 1) of the reference clock period, that is, if T 1 satisfies the following conditions:

[0117]

[0118] Wherein, since f det ≥f ref , that is, f ref / f det ≤1, there must be a positive - integer solution for T1 in the above formula. At this time, the divided - frequency monitoring clock heartbeat signal can be sampled at most 3 consecutive times with unchanged values under the monitoring clock, so T2 is set to 3.

[0119] When f det is less than f ref , since the reference clock frequency is greater than the monitoring clock frequency, no matter what value T1 is set to, the flip period of the divided - frequency monitoring clock heartbeat signal will necessarily be greater than 1 times the reference clock period, and T1 is set to 1. The divided - frequency monitoring clock heartbeat signal can be sampled at most times with unchanged values, and T2 is set to the ceiling value of.

[0120] For easy understanding, taking the monitoring clock of 250M and the reference clock of 100M as an example, T1 can take any value of 3, 4, 5, and T2 is set to 3.

[0121] For easy understanding, as shown in Figure 6 shown, Figure 6 is the circuit diagram of a glitch - free clock output circuit in an embodiment. The main function of the glitch - free clock output circuit is to output a glitch - free clock to switch to the reference clock after the monitoring clock stops oscillating; and to output a glitch - free clock to switch back to the monitoring clock after the monitoring clock resumes.

[0122] As shown in Figure 6 shown, the glitch - free clock output circuit includes a mutual - lock module and a clock control output module.

[0123] Wherein:

[0124] The interlock module is used to receive the clock output selection signal and the detection result signal of the oscillation stop detection circuit. When the detection result is that the monitored clock stops oscillating, it outputs a selection clock control signal for selecting the reference clock output. It is also used when the detection result is that the monitored clock does not stop oscillating. When the clock output selection signal is the reference clock selection signal, it outputs a selection clock control signal for selecting the reference clock output. When the clock output selection signal is the monitored clock selection signal, it outputs a selection clock control signal for selecting the monitored clock output.

[0125] The clock control output module is used to output a glitch-free monitored clock signal or a glitch-free reference clock signal based on the selection clock control signal.

[0126] Wherein the interlock module realizes the output interlock of the reference clock and the monitored clock, that is, under the clock output selection signal and the oscillation stop detection signal, if the reference clock signal is output, the monitored clock signal is not output. If the monitored clock signal is output, the reference clock signal is not output.

[0127] Wherein when the detection result of the interlock module is that the monitored clock stops oscillating, the output selection clock output control signal is to select the reference clock signal output. When the detection result is that the monitored clock does not stop oscillating, it selects and outputs the reference clock signal or the monitored clock signal based on the clock output selection signal.

[0128] The clock control output module is then used to output the selection clock control signal and output a glitch-free monitored clock signal or reference clock signal.

[0129] In some alternative embodiments, continuing in conjunction with Figure 6 as shown, wherein the interlock module includes a reference clock output control signal synchronization unit, a monitored clock output control signal synchronization unit, and a clock stop signal asynchronous reset synchronization unit. Wherein:

[0130] The reference clock output control signal synchronization unit is used to output a second selection clock control signal for whether to select the reference clock based on the detection result of the oscillation stop detection circuit, the clock output selection signal, and the first selection clock control signal.

[0131] The monitored clock output control signal synchronization unit is used to output a first selection clock control signal for whether to select the monitored clock output based on the clock output selection signal and the second reference clock interlock signal.

[0132] The clock stop signal asynchronous reset synchronization unit is used to perform asynchronous reset synchronization on the clock stop signal and control the operation of the monitored clock output control signal synchronization unit based on the signal obtained by the asynchronous reset synchronization.

[0133] For the convenience of understanding, in combination with Figure 6 as shown in Figure 6 FIG. 1 is a circuit diagram of a burr-free clock output circuit in an embodiment, wherein the reference clock output control signal synchronization unit includes a first NOT gate, a first OR gate, a first AND gate, and a first synchronization sub-unit including a first logic device A1 and a second logic device A2; the monitoring clock output control signal synchronization unit includes a second AND gate and a second synchronization sub-unit including a third logic device B1 and a fourth logic device B2; the clock stop signal asynchronous reset synchronization unit includes a fifth logic device C1 and a sixth logic device C2.

[0134] The input terminal of the first NOT gate inputs a clock output selection signal; the first input terminal of the first OR gate inputs a clock stop signal, and the second input terminal of the first OR gate is connected to the output terminal of the first NOT gate; the first input terminal of the first AND gate is connected to the output terminal of the first OR gate, and the second input terminal of the first AND gate inputs the opposite value of the first selection clock control signal.

[0135] The input terminal of the first synchronization sub-unit is connected to the output terminal of the first AND gate, and the output terminal of the first synchronization sub-unit outputs a second selection clock control signal. The control clock of the first synchronization sub-unit is a reference clock. Under the control of the reference clock, the first synchronization sub-unit synchronously outputs the signal S2 output by the first AND gate to obtain a signal S3, that is, the second selection clock control signal in the above text.

[0136] The first input terminal of the second AND gate inputs a clock output selection signal, and the second input terminal of the second AND gate inputs the opposite value of the second selection clock control signal; the input terminal of the second synchronization sub-unit is connected to the output terminal of the second AND gate, and the output terminal of the second synchronization sub-unit outputs a first selection clock control signal. The control clock of the second synchronization sub-unit is a monitoring clock. Under the control of the monitoring clock, the second synchronization sub-unit synchronously outputs the signal S4 output by the second AND gate to obtain a signal S5, that is, the first selection clock control signal in the above text.

[0137] The control terminal of the clock stop signal asynchronous reset synchronization unit inputs the clock stop signal, the input terminal inputs 1, the control clock is the monitoring clock, and the output terminal outputs the signal obtained by asynchronous reset synchronization.

[0138] Specifically, when the clock stop signal changes from 0 to 1, the fifth logic device C1 and the sixth logic device C2 are immediately reset, and the signal S6 becomes 0. Since the control terminal of the third logic device B1 calculates the opposite value of the control signal for the control signal, when the signal S6 is 0, the reset monitoring clock output control signal synchronization unit can be released, that is, the fifth logic device C1 and the sixth logic device C2 determine the signal S5 based on the clock output selection signal and the second selection clock control signal. When the clock stop signal changes from 1 to 0, the fifth logic device C1 and the sixth logic device C2 are released from reset. After two monitoring clocks, the 1 at the D terminal of the fifth logic device C1 is synchronized to the signal S6. When the signal S6 is 1, the reset monitoring clock output control signal synchronization unit can be reset, that is, the signal S5 output from the output terminal of the sixth logic device C2 is 0.

[0139] In some alternative embodiments, the clock control output module includes a third AND gate, a fourth AND gate, and a second OR gate; wherein

[0140] The first input terminal of the third AND gate inputs the second selection clock control signal, and the second input terminal of the third AND gate inputs the reference clock signal.

[0141] The first input terminal of the fourth AND gate inputs the first selection clock control signal, and the second input terminal of the fourth AND gate inputs the monitoring clock signal.

[0142] The first input terminal of the second OR gate is connected to the output terminal of the third AND gate, the second input terminal of the second OR gate is connected to the output terminal of the fourth AND gate, and the output terminal outputs the monitoring clock or the reference clock.

[0143] The third AND gate is used to output the reference clock signal when the second selection clock control signal is for selecting the reference clock output, and output 0 when the second selection clock control signal is for not selecting the reference clock output; the fourth AND gate is used to output the monitoring clock signal when the first selection clock control signal is for selecting the monitoring clock output, and output 0 when the first selection clock control signal is for not selecting the monitoring clock output; the second OR gate is used to output a glitch-free reference signal or monitoring clock signal based on the output of the third AND gate and the output of the fourth AND gate.

[0144] Among them, for the convenience of understanding, continue to combine Figure 6As shown, in this embodiment: ① A1 and A2 complete the synchronization of signal S2; ② B1 and B2 complete the synchronization of signal S4; ③ C1 and C2 complete the asynchronous reset synchronization release of the clock stop signal det_clk_stop. When the clock stop signal det_clk_stop changes from 0 to 1, C1 and C2 are immediately reset, and S6 becomes 0. When det_clk_stop changes from 1 to 0, C1 and C2 are de - reset. After two monitoring clocks det_clk, the 1 at the D - end of C1 is synchronized to S6.

[0145] Specifically, the applicable scenarios of the above - mentioned glitch - free clock output circuit include:

[0146] Scenario 1: The reference clock ref_clk and the monitoring clock det_clk both flip normally. The selected clock is switched to the output clock out_clk without glitches through the clock selection signal sel.

[0147] Among them, the monitoring clock det_clk flips normally, the value of the clock stop signal det_clk_stop is 0, C1 and C2 are de - reset, S6 is 1, and B1 and B2 are de - reset. At this time, the circuit working state is a glitch - free clock output circuit, and the selected clock is switched to the output clock out_clk without glitches through the interlock based on the clock selection signal sel.

[0148] Scenario 2: The reference clock ref_clk flips normally, the monitoring clock det_clk stops flipping, and when it stops, it is at a low level. The clock stop signal det_clk_stop changes from 0 to 1 after the monitoring clock det_clk stops.

[0149] 1) When the clock selection signal sel is 0, the output clock out_clk is the reference clock ref_clk. At this time, the monitoring clock det_clk becomes 0, S8 is 0, the clock stop signal det_clk_stop changes from 0 to 1, which does not affect the output clock out_clk, and the reference clock ref_clk is still output.

[0150] 2) When the clock selection signal sel is 1, the output clock out_clk is the monitoring clock det_clk. At this time, the monitoring clock det_clk becomes 0, S8 is 0, and the output clock out_clk stops oscillating. The clock stop signal det_clk_stop changes from 0 to 1, C1 and C2 are immediately reset, S6 becomes 0, B1 and B2 are immediately reset, and S5 is set to 0. At the same time, since the clock stop signal det_clk_stop changes from 0 to 1, S1 becomes 1, and S5 is 0, then S2 is 1, and after synchronization with A1 and A2, S3 becomes 1, and S7 outputs the reference clock ref_clk. Since S8 is 0, the output clock out_clk is the reference clock ref_clk. The output clock out_clk has gone through the process of the monitoring clock det_clk first stopping oscillation and becoming 0, and then turning on the reference clock ref_clk, and there is no burr in the output clock out_clk.

[0151] Scenario 3: The reference clock ref_clk flips normally, and the monitoring clock det_clk stops flipping. It is at a high level when it stops. The clock stop signal det_clk_stop changes from 0 to 1 after the monitoring clock det_clk stops.

[0152] 1) When the clock selection signal sel is 0, the output realization out_clk is the reference clock ref_clk. At this time, the monitoring clock det_clk becomes 1, but because S5 is 0 and S8 is 0, the clock stop signal det_clk_stop changes from 0 to 1, which does not affect the output clock out_clk, and the reference clock ref_clk is still output.

[0153] 2) When the clock selection signal sel is 1, the output clock out_clk is the monitoring clock det_clk. At this time, the monitoring clock det_clk becomes 1, S8 is 1, and the output clock out_clk is 1. After that, the clock stop signal det_clk_stop changes from 0 to 1, C1 and C2 are immediately reset, S6 becomes 0, B1 and B2 are immediately reset, S5 is set to 0, S8 then becomes 0, and the output clock out_clk is 0. At the same time, since the clock stop signal det_clk_stop changes from 0 to 1, S1 becomes 1, and S5 is 0, then S2 is 1, and after synchronization with A1 and A2, S3 becomes 1, and S7 outputs the reference clock ref_clk. Since S8 is 0, the output clock out_clk is the reference clock ref_clk. The output clock out_clk goes through the process where the monitoring clock det_clk stops oscillating and changes to 1, and then the clock stop signal det_clk_stop changes from 0 to 1, the output clock out_clk changes to 0, and then the reference clock ref_clk is turned on. There is no glitch in the output clock out_clk.

[0154] Scenario 4: The reference clock ref_clk flips normally, the clock stop signal det_clk_stop is 1, the clock selection signal sel is 0, the monitoring clock det_clk resumes, and the clock stop signal det_clk_stop changes from 1 to 0 after the monitoring clock det_clk resumes.

[0155] When the clock stop signal det_clk_stop is 1 and the clock selection signal sel is 0, the monitoring clock det_clk resumes and the clock stop signal det_clk_stop changes from 1 to 0. On the one hand, C1 and C2 are de-reset, S6 becomes 1, and B1 and B2 are de-reset. However, since the clock selection signal sel is 0, S4 is 0 and S5 is 0. On the other hand, since the clock selection signal sel is 0, S1 is 1 and S5 is 0, so S2 is 1. At this time, the output clock out_clk maintains the selected reference as the ref_clk output unchanged.

[0156] Scenario 5: The reference clock ref_clk flips normally, the clock stop signal det_clk_stop is 1, the clock selection signal sel is 1, the monitoring clock det_clk resumes, and the clock stop signal det_clk_stop changes from 1 to 0 after the monitoring clock det_clk resumes.

[0157] When the clock stop signal det_clk_stop is 1 and the clock selection signal sel is 1, the monitoring clock det_clk resumes and the clock stop signal det_clk_stop changes from 1 to 0. On the one hand, C1 and C2 are de-reset, S6 becomes 1, and B1 and B2 are de-reset. On the other hand, as the clock stop signal det_clk_stop changes from 1 to 0 and the clock selection signal sel is 1, S1 changes from 1 to 0, S2 becomes 0, and after synchronization through A1 and A2, S3 changes from 1 to 0. When S3 changes from 1 to 0, the reference clock ref_clk output by the output out_clk is turned off, and at the same time S4 changes from 0 to 1. After B1 and B2 are de-reset and through synchronization, S5 also changes from 0 to 1, and S8 outputs the monitoring clock det_clk, and the output clock out_clk starts to output the monitoring clock det_clk. The output clock out_clk goes through the process of first turning off the reference clock ref_clk and then turning on the monitoring clock det_clk without glitches.

[0158] The above specific scenarios can be seen in Table 1:

[0159] Table 1

[0160]

[0161]

[0162] In the above embodiments, the circuit for monitoring whether the clock stops oscillating: converts the signal that needs to cross asynchrony into 1 bit, simplifying the cross-asynchrony processing; can support monitoring clocks and reference clocks of any frequency through modifying the configuration of the count value, with no limitation on the frequency. The glitch-free clock output circuit: simplifies the clock selection structure, only requiring one-level clock selection instead of two-level or multi-level clock selection in the prior art, reducing resource overhead and shortening the clock path; hardware circuit processing, with rapid response and no need for software intervention; solves the problem that in the prior art, when the monitored clock stops oscillating and is at a high level, it cannot work properly.

[0163] This application also provides a chip, including the glitch-free clock output circuit described in any one of the above embodiments.

[0164] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown in the direction of the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0165] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0166] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0167] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A clock glitch-free output circuit, characterized in that: include: A oscillation stop detection circuit is used to divide the monitoring clock signal to generate a divided monitoring clock heartbeat signal, and convert the divided monitoring clock heartbeat signal across the clock domain to the reference clock frequency domain, determine whether the monitoring clock stops oscillating according to the divided monitoring clock heartbeat signal in the reference clock frequency domain, and output a detection result; The glitch-free clock output circuit is used to receive a clock output selection signal and the detection result, and output a glitch-free reference clock signal or a monitoring clock signal according to the clock output selection signal and the detection result.

2. The clock glitch-free output circuit according to claim 1, characterized in that: The vibration stop detection circuit comprises: A frequency division module, used for receiving the monitoring clock signal, and dividing the frequency of the monitoring clock signal to generate a divided monitoring clock heartbeat signal; A frequency domain conversion module, used for converting the divided frequency monitoring clock heartbeat signal from the monitoring clock frequency domain to the reference clock frequency domain; The oscillation stop detection module is used to monitor the number of flips of the heartbeat signal of the frequency-divided monitoring clock. When the number of flips of the heartbeat signal of the frequency-divided monitoring clock meets the set conditions, it is determined that the monitoring clock has stopped oscillating, otherwise, the monitoring clock has not stopped oscillating.

3. The clock glitch-free output circuit according to claim 2, characterized in that: The frequency division module includes a first counter and a first comparator; The first counter is used to count the monitoring clock signal, and when the count value of the first counter is a first set value, the count value of the first counter is reset to 0; The first comparator is used to compare the count value of the first counter with the first set value, and output the divided monitoring clock heartbeat signal based on the comparison result.

4. The clock glitch-free output circuit according to claim 3, characterized in that: The vibration stop monitoring module includes a transition edge detection module, a second counter and a vibration stop determination module; The transition edge detection module is used to detect the rising edge or falling edge of the frequency-divided monitoring clock heartbeat signal; The second counter is used to reset the count value of the second counter to a second set value when the transition edge detection module detects a rising edge or a falling edge of the frequency-divided monitoring clock heartbeat signal, and to reduce the count value of the second counter by 1 in each reference clock cycle when the transition edge monitoring module does not detect a rising edge or a falling edge of the frequency-divided monitoring clock heartbeat signal until the count value of the second counter is 0; The oscillation stop determination module is used to determine that the monitoring clock has stopped oscillating when the count value of the second counter is 0.

5. The clock glitch-free output circuit according to claim 4, characterized in that: If the frequency of the monitoring clock is f det , the frequency of the reference clock is f ref , the first setting value is T1, the second setting value is T2, In f det Greater than or equal to f ref In the case of , if T1 satisfies the following conditions: Then the second setting value T2=3; In f det Less than f ref In the case of , if T1 satisfies the following conditions: T1＝1； Then T2 is greater than An integer.

6. The clock glitch-free output circuit according to claim 1, characterized in that: The glitch-free clock output circuit comprises: An interlocking module, for receiving a clock output selection signal and a detection result signal of the oscillation stop detection circuit, and outputting a selection clock control signal for selecting a reference clock output when the detection result is that the monitoring clock has stopped oscillating, and for outputting a selection clock control signal for selecting a reference clock output when the clock output selection signal is a reference clock selection signal when the detection result is that the monitoring clock has not stopped oscillating, and outputting a selection clock control signal for selecting a monitoring clock output when the clock output selection signal is a monitoring clock selection signal; A clock control output module is used to output a glitch-free monitoring clock signal or a glitch-free reference clock signal based on the selected clock control signal.

7. The clock glitch-free output circuit according to claim 6, characterized in that: The interlocking module comprises: A reference clock output control signal synchronization unit, configured to output a second selection clock control signal indicating whether to select a reference clock based on a detection result of the oscillation stop detection circuit, the clock output selection signal and the first selection clock control signal; A monitoring clock output control signal synchronization unit, configured to output a first selection clock control signal indicating whether to select a monitoring clock based on the clock output selection signal and the second selection clock control signal; The clock stop signal asynchronous reset synchronization unit is used to perform asynchronous reset synchronization on the clock stop signal, and control the operation of the monitoring clock output control signal synchronization unit based on the signal obtained by the asynchronous reset synchronization.

8. The clock glitch-free output circuit according to claim 7, characterized in that: The reference clock output control signal synchronization unit comprises: A first NOT gate, an input terminal of which inputs the clock output selection signal; A first OR gate, a first input terminal of which is input with the clock stop signal, and a second input terminal of which is connected with the output terminal of the first NOT gate; A first AND gate, a first input terminal connected to the output terminal of the first OR gate, and a second input terminal inputting an opposite value of the first selection clock control signal; A first synchronization subunit, whose input end is connected to the output end of the first AND gate, whose output end outputs the second selection clock control signal, and the control clock is the reference clock; The monitoring clock output control signal synchronization unit comprises: A second AND gate, wherein the clock output selection signal is input to a first input terminal and the opposite value of the second selection clock control signal is input to a second input terminal; A second synchronization subunit, whose input end is connected to the output end of the second AND gate, whose output end outputs the first selection clock control signal, and the control clock is the monitoring clock; The control end of the clock stop signal asynchronous reset synchronization unit inputs the clock stop signal, the input end inputs 1, the control clock is the monitoring clock, and the output end outputs the signal obtained by asynchronous reset synchronization.

9. The clock glitch-free output circuit according to claim 7, characterized in that: The clock control output module comprises: a third AND gate, a first input terminal of which is input with the second selection clock control signal, and a second input terminal of which is input with the reference clock signal; A fourth AND gate, a first input terminal of which is input with the first selection clock control signal, and a second input terminal of which is input with the monitoring clock signal; The second OR gate has a first input terminal connected to the output terminal of the third AND gate, a second input terminal connected to the output terminal of the fourth AND gate, and an output terminal outputting the monitoring clock or the reference clock.

10. A chip, characterized in that: A clock glitch-free output circuit comprising any one of claims 1 to 9.

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