A level shifter with ultra-low power consumption and single event transient immunity

Abstract

The present application relates to an ultra-low-power, single-particle transient-resistant level converter. The level converter comprises a main output stage and an auxiliary circuit. The main output stage utilizes a DICE structure, which is configured to rapidly release charge after a set charge impact via two pull-down paths at each node in the DICE structure. The auxiliary circuit comprises two improved LEDC structures. The improved LEDC structures are configured to completely cut off the static current in the improved LEDC structures by introducing an additional control signal to the DICE structures. The level converter rapidly releases charge after a set charge impact, maintaining a stable output. Compared to conventional LEDC structures, the improved LEDC structure can completely resolve the static current problem in the circuit, achieving ultra-low static power consumption for the entire circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to an ultra-low power consumption single-event transient resistant level converter. Background Art

[0002] With the advancement of aerospace technology and MOS tube technology, the demand for circuit performance indicators is no longer limited to traditional indicators such as delay and area. Single-particle transient effects (SET) and static power consumption have gradually become key indicators that need to be focused on in the design. The SET effect is one of the most common circuit soft errors. It originates from the influence of high-energy particles on the semiconductor region of the MOS tube, which in turn introduces current pulses in the semiconductor, changes the voltage and current of the corresponding node, and causes abnormal working conditions of the MOS tube. In the timing circuit, this abnormal signal will be transmitted step by step, and eventually affect multiple modules in the entire system. As an important component of the timing circuit, the level converter (LS) module is widely used in the connection between analog and digital circuits and between modules with different working voltages. However, research on the resistance of level converter circuits to the SET effect is relatively lacking. Because the structural design of the level converter circuit is relatively simple and fragile, when affected by the SET effect, its output waveform is easily disturbed, thereby affecting the signal transmission between modules. Three traditional level converter circuits such as Figure 1 As shown, Figure 1 (a) is a cross-type (ccls) level converter circuit, Figure 1 (b) is a mirror type (cmls) level converter circuit, Figure 1 (c) is a Wilson current mirror type level converter circuit. In terms of static power consumption, since the output signal is pulled up and pulled down by PMOS and NMOS tubes respectively, the pull-up PMOS tube cannot be completely turned off when the output is low. This has always been a difficult problem to solve in level converter circuits. This will cause a large static current in the circuit and thus generate high static power consumption. Therefore, in many circuits, the following circuits are used: Figure 2 The LEDC structure shown in the figure is used to reduce the static current of the circuit, but the LEDC structure itself will also generate a certain amount of static current, so this method cannot fundamentally solve the problem. Summary of the Invention

[0003] Based on this, it is necessary to provide an ultra-low power consumption single event transient resistant level converter to address the above technical problems.

[0004] An ultra-low power consumption single-particle transient resistant level converter comprises a main output stage and an auxiliary circuit.

[0005] The main output stage adopts a DICE structure, which is used to quickly release the charge after being impacted by the SET charge through two pull-down paths equipped at each node in the DICE structure.

[0006] The auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used for introducing an additional control signal for the DICE structure, and the static current in the improved LEDC structure is completely cut off through the additional control signal.

[0007] In one embodiment, the first improved LEDC structure includes five PMOS transistors and three NMOS transistors.

[0008] The sources of the first PMOS tube, the second PMOS tube, and the third PMOS tube are all connected to the VDDH terminal, and the drain of the first PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the fifth PMOS tube, and the drain of the first NMOS tube are all connected to the Q point.

[0009] The drain of the second PMOS tube is connected to the source of the fifth PMOS tube. The drain of the fifth PMOS tube, the drain of the third NMOS tube, and the drain of the fourth PMOS tube are all connected to point X. The source of the fourth PMOS tube is connected to the drain of the third PMOS tube. The gates of the third PMOS tube and the second NMOS tube are both connected to point B. The gates of the fourth PMOS tube and the third NMOS tube are both connected to the inverting input signal terminal. The source of the first NMOS tube is connected to the drain of the second NMOS tube. The gate of the first NMOS tube is connected to the input signal terminal. The sources of the second NMOS tube and the third NMOS tube are both grounded. Point X is the first additional control signal introduction point.

[0010] In one embodiment, the second improved LEDC structure includes: a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor.

[0011] The sources of the fourteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube are all connected to the VDDH terminal, and the drain of the fifteenth PMOS tube, the gate of the fifteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the eighteenth PMOS tube and the drain of the fourteenth NMOS tube are all connected to point K.

[0012] The drain of the fourteenth PMOS tube is connected to the source of the eighteenth PMOS tube, the drain of the eighteenth PMOS tube, the drain of the fifteenth NMOS tube and the drain of the seventeenth PMOS tube are all connected to point Y, the source of the seventeenth PMOS tube is connected to the drain of the sixteenth PMOS tube, the gates of the sixteenth PMOS tube and the sixteenth NMOS tube are both connected to the OUT terminal, and the gates of the seventeenth PMOS tube and the fifteenth NMOS tube are both connected to the input signal terminal; the source of the fourteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, the gate of the fourteenth NMOS tube is connected to the inverting input signal terminal, and the sources of the fifteenth NMOS tube and the sixteenth NMOS tube are both grounded.

[0013] In one embodiment, the main output stage includes: sixth to thirteenth PMOS transistors and fourth to thirteenth NMOS transistors.

[0014] The sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the VDDH terminal. The drain of the sixth PMOS transistor is connected to the source of the tenth PMOS transistor. The drain of the tenth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the tenth NMOS transistor, and the gate of the eighth NMOS transistor are all connected to node A. The gates of the tenth PMOS transistor and the twelfth PMOS transistor are all connected to point X. The gates of the eleventh PMOS transistor, the thirteenth PMOS transistor, the gate of the fourth NMOS transistor, and the gate of the thirteenth NMOS transistor are all connected to point Y. The drain of the seventh PMOS transistor is connected to the source of the eleventh PMOS transistor. The drain of the eighth PMOS transistor is connected to the source of the twelfth PMOS transistor. The drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor and the drain of the eighth NMOS transistor. The source of the ninth NMOS transistor is connected to the drain of the thirteenth NMOS transistor.

[0015] The gate of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the eleventh PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eleventh NMOS transistor are all connected to the node B.

[0016] The gate of the sixth NMOS transistor, the drain of the seventh NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the ninth PMOS transistor, and the drain of the twelfth NMOS transistor are all connected to the node C.

[0017] The gate of the sixth PMOS tube, the drain of the thirteenth PMOS tube, the drain of the fourth NMOS tube, and the drain of the ninth NMOS tube are all connected to the OUT terminal.

[0018] The gate of the seventh NMOS tube is connected to the source of the fourth NMOS tube and the drain of the eighth NMOS tube; the sources of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube are all grounded.

[0019] The gates of the tenth NMOS tube and the twelfth NMOS tube are connected to the input signal terminal, and the gates of the eleventh NMOS tube and the ninth NMOS tube are connected to the inverting signal input terminal.

[0020] The ultra-low-power, single-event transient (SET)-resistant level converter includes a main output stage and auxiliary circuitry. The main output stage utilizes a DICE structure, which rapidly releases charge after a SET charge event through two pull-down paths at each node in the DICE structure. The auxiliary circuitry includes two improved LEDC structures. The improved LEDC structures are designed to completely shut off the quiescent current by introducing an additional control signal to the DICE structure. This level converter rapidly releases charge after a SET charge event, maintaining output stability. Compared to traditional LEDC structures, the improved LEDC structure completely eliminates the quiescent current issue in the circuit, achieving ultra-low quiescent power consumption for the entire circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 There are three traditional level converter circuit diagrams, Figure 1 (a) is the circuit diagram of the cross-type level converter. Figure 1 (b) is the circuit diagram of the mirror type level converter. Figure 1 (c) is a circuit diagram of a Wilson current mirror type level converter;

[0022] Figure 2 This is a structural diagram of a flat converter using an LEDC structure as an auxiliary circuit in the prior art;

[0023] Figure 3 A circuit diagram of an ultra-low power single event transient resistant level converter in one embodiment;

[0024] Figure 4 FIG. 1 is a diagram of a commonly used LEDC structure in a level converter and an improved LEDC structure in another embodiment, wherein Figure 4 (a) is the LEDC structure diagram commonly used in level converters. Figure 4 (b) is the improved LEDC structure diagram;

[0025] Figure 5 FIG. 2 is a circuit timing waveform diagram in another embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0027] In one embodiment, Figure 3 As shown, an ultra-low power consumption single event transient resistant level converter is provided, and the level converter includes: a main output stage and an auxiliary circuit.

[0028] The main output stage adopts a DICE structure, which is used to quickly release the charge after being impacted by the SET charge through two pull-down paths equipped at each node in the DICE structure.

[0029] Specifically, the main output stage is improved based on the traditional DICE structure; a PMOS tube is added between the drain of the PMOS tube and the drain of the pull-down NMOS tube in the first pull-down path of each node, an NMOS tube is added between the drain of the added PMOS tube in the first pull-down path of the fourth node and the drain of the pull-down NMOS tube, and an NMOS tube is added in the second pull-down path of the fourth node.

[0030] The gates of the PMOS transistors added in the first pull-down paths of the first and third nodes are connected to point X, the gates of the PMOS transistors added in the first pull-down paths of the second and fourth nodes are connected to point Y, the gate of the NMOS transistor added in the first pull-down path of the fourth node is connected to point Y, the gate of the NMOS transistor added in the second pull-down path of the fourth node is connected to the inverting signal input terminal, and the gate of the pull-down NMOS transistor in the second pull-down path of the fourth node is connected to point Y.

[0031] The auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used for introducing an additional control signal for the DICE structure, and the static current in the improved LEDC structure is completely cut off through the additional control signal.

[0032] Specifically, the traditional LEDC structure is improved and added to the circuit as an auxiliary circuit. Compared with the traditional LEDC structure, the improved LEDC structure can completely solve the static current problem in the circuit and achieve ultra-low static power consumption of the entire circuit.

[0033] The main output stage of the level converter is used to quickly release charge after being impacted by SET charge. The improved LEDC structure on both sides further improves the output's resistance to the SET effect by introducing two additional control signals for the middle DICE structure, and also makes the circuit's delay and power consumption at a relatively good level.

[0034] When the level converter operates in steady state, the circuit has extremely low static power consumption, and all PMOS and NMOS can be completely turned off. When the circuit is affected by the external SET effect, the charge can be quickly released to maintain output stability.

[0035] The ultra-low-power, single-event transient (SET)-resistant level converter described above includes a main output stage and auxiliary circuitry. The main output stage utilizes a DICE structure, which rapidly releases charge after a SET charge event through two pull-down paths at each node in the DICE structure. The auxiliary circuitry includes two improved LEDC structures. The improved LEDC structures are configured to completely shut off the quiescent current by introducing an additional control signal to the DICE structure. This level converter rapidly releases charge after a SET charge event, maintaining output stability. Compared to conventional LEDC structures, the improved LEDC structure completely eliminates the quiescent current issue in the circuit, achieving ultra-low quiescent power consumption for the entire circuit.

[0036] In one embodiment, Figure 3 As shown, the first improved LEDC structure includes: 5 PMOS tubes and 3 NMOS tubes.

[0037] The sources of the first PMOS tube, the second PMOS tube, and the third PMOS tube are all connected to the VDDH terminal, and the drain of the first PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the fifth PMOS tube, and the drain of the first NMOS tube are all connected to the Q point.

[0038] The drain of the second PMOS tube is connected to the source of the fifth PMOS tube. The drain of the fifth PMOS tube, the drain of the third NMOS tube, and the drain of the fourth PMOS tube are all connected to point X. The source of the fourth PMOS tube is connected to the drain of the third PMOS tube. The gates of the third PMOS tube and the second NMOS tube are both connected to point B. The gates of the fourth PMOS tube and the third NMOS tube are both connected to the inverting input signal terminal. The source of the first NMOS tube is connected to the drain of the second NMOS tube. The gate of the first NMOS tube is connected to the input signal terminal. The sources of the second NMOS tube and the third NMOS tube are both grounded. Point X is the first additional control signal introduction point.

[0039] Specifically, Figure 4 (a) is the LEDC structure commonly used in level converter structures. P5 cannot be completely turned off, and the voltage at point Y will also be lost. Figure 4 (b) shows the improved LEDC structure. K point is used to control P5 to ensure that the transistor is completely turned off. The OUT voltage and IN voltage are used to control the P3 and P4 paths to maintain the Y point voltage at VDDH. This not only solves the voltage loss problem of the LEDC structure but also completely solves the static leakage current problem of the LS structure.

[0040] In one embodiment, Figure 3 As shown, the second improved LEDC structure includes: a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube.

[0041] The sources of the fourteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube are all connected to the VDDH terminal, and the drain of the fifteenth PMOS tube, the gate of the fifteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the eighteenth PMOS tube and the drain of the fourteenth NMOS tube are all connected to point K.

[0042] The drain of the fourteenth PMOS tube is connected to the source of the eighteenth PMOS tube, the drain of the eighteenth PMOS tube, the drain of the fifteenth NMOS tube and the drain of the seventeenth PMOS tube are all connected to point Y, the source of the seventeenth PMOS tube is connected to the drain of the sixteenth PMOS tube, the gates of the sixteenth PMOS tube and the sixteenth NMOS tube are all connected to the OUT terminal, and the gates of the seventeenth PMOS tube and the fifteenth NMOS tube are all connected to the input signal terminal; the source of the fourteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, the gate of the fourteenth NMOS tube is connected to the inverting input signal terminal, and the sources of the fifteenth NMOS tube and the sixteenth NMOS tube are both grounded; point Y is the first additional control signal introduction point.

[0043] In one embodiment, Figure 3 As shown, the main output stage includes: the sixth to the thirteenth PMOS transistors and the fourth to the thirteenth NMOS transistors.

[0044] The sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the VDDH terminal. The drain of the sixth PMOS transistor is connected to the source of the tenth PMOS transistor. The drain of the tenth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the tenth NMOS transistor, and the gate of the eighth NMOS transistor are all connected to node A. The gates of the tenth PMOS transistor and the twelfth PMOS transistor are all connected to point X. The gates of the eleventh PMOS transistor, the thirteenth PMOS transistor, the gate of the fourth NMOS transistor, and the gate of the thirteenth NMOS transistor are all connected to point Y. The drain of the seventh PMOS transistor is connected to the source of the eleventh PMOS transistor. The drain of the eighth PMOS transistor is connected to the source of the twelfth PMOS transistor. The drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor and the drain of the eighth NMOS transistor. The source of the ninth NMOS transistor is connected to the drain of the thirteenth NMOS transistor.

[0045] The gate of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the eleventh PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eleventh NMOS transistor are all connected to the node B.

[0046] The gate of the sixth NMOS transistor, the drain of the seventh NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the ninth PMOS transistor, and the drain of the twelfth NMOS transistor are all connected to the node C.

[0047] The gate of the sixth PMOS tube, the drain of the thirteenth PMOS tube, the drain of the fourth NMOS tube, and the drain of the ninth NMOS tube are all connected to the OUT terminal.

[0048] The gate of the seventh NMOS tube is connected to the source of the fourth NMOS tube and the drain of the eighth NMOS tube; the sources of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube are all grounded.

[0049] The gates of the tenth NMOS tube and the twelfth NMOS tube are connected to the input signal terminal, and the gates of the eleventh NMOS tube and the ninth NMOS tube are connected to the inverting signal input terminal.

[0050] Specifically, such as Figure 3 In the level converter shown, since the voltage changes of the LEDC structures on both sides of the circuit are in opposite directions, only the voltage change of the LEDC structure on the right is taken as a reference.

[0051] Low to high level: such as Figure 3As shown, when the input signal IN transitions from low to high, for the improved LEDC structure on the right, the fourteenth NMOS transistor N14 turns on, the fifteenth PMOS transistor P15 and the eighteenth PMOS transistor P18 turn off, and the potential at point Y is pulled down to 0. In the DICE structure, the fourth NMOS transistor N4 and the thirteenth NMOS transistor N13 turn off, while the thirteenth PMOS transistor P13 turns on. The twelfth NMOS transistor N12 turns on, causing the potential at point C to reach 0, and the ninth PMOS transistor P9 turns on, pulling the output up to VDDH. At this point, the two pull-down paths of the output—the fourth NMOS transistor N4 and the eighth NMOS transistor N8, as well as the ninth NMOS transistor N9 and the thirteenth NMOS transistor N13—are all in a closed state. If any of these MOS transistors is abnormally conductive due to the SET effect, the pull-down path remains closed, preventing the OUT terminal from being directly connected to a low potential and preventing significant output fluctuations. At this point, the fourteenth PMOS transistor P14 and the fifteenth NMOS transistor N15 in the right LEDC structure are turned off, and the potential at point K rises to VDDH-Vds (the seventeenth PMOS transistor P17), completely turning off the eighteenth PMOS transistor P18. The quiescent current in the improved LEDC is completely cut off.

[0052] High to low level: such as Figure 3As shown, when the input transitions from high to low, the inverting input signal INB of the right LEDC structure goes high. Due to delay, the OUT terminal remains high. The fifteenth and sixteenth NMOS transistors N15 and N16 turn on simultaneously, causing the voltage at point K to drop and turning on the sixteenth and eighteenth PMOS transistors P16 and P18, pulling the voltage at point Y to VDDH. Meanwhile, the thirteenth PMOS transistor P13 of the DICE structure turns off, blocking the output from the pull-up circuit. At this time, the ninth and thirteenth NMOS transistors N9 and N13 turn on simultaneously, pulling the output down to zero. At this time, the third NMOS transistor N3 of the left LEDC structure turns on, causing X to become 0. In the DICE structure, the sixth and tenth PMOS transistors P6 and P10, controlled by X, turn on, pulling point A up to VDDH. At this point, the second pull-down path for OUT, formed by the fourth and eighth NMOS transistors N4 and N8, opens, enhancing output stability. Similarly, the potential at point C rises to VDDH, shutting down the ninth PMOS transistor P9. In the pull-up path formed by the ninth and thirteenth PMOS transistors P9 and P13, one of the MOS transistors is affected by SET, while the other still blocks the output from the pull-up path, ensuring stable output. Simultaneously, the pull-up path formed by the fourteenth and fifteenth PMOS transistors P14 and P15 opens, maintaining the voltage at point Y at VDDH. The quiescent current in the DICE structure is completely shut off. The potential at point K continues to rise to VDDH-Vds (the seventeenth PMOS transistor P17), completely shutting down the eighteenth PMOS transistor P18. At this point, the OUT terminal reaches 0, and the sixteenth NMOS transistor N16 is completely shut off, completely cutting off the quiescent current in the improved LEDC.

[0053] In summary, the circuit can achieve strong SET resistance and ultra-low static power consumption during both the pull-up and pull-down processes. Figure 5 It shows the timing working waveform of the circuit and the waveform changes of different circuits after being impacted.

[0054] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. An ultra-low power single event transient resistant level converter, characterized in that: The level converter includes: a main output stage and an auxiliary circuit; The main output stage adopts a DICE structure; The auxiliary circuit includes: a first structure and a second structure, both of which adopt an improved LEDC structure; the improved LEDC structure is used to introduce an additional control signal to the DICE structure, and the quiescent current in the improved LEDC structure is completely cut off by the additional control signal; The improved LEDC structure includes: 5 PMOS transistors P1 to P5, 3 NMOS transistors N1 to N3; The sources of P1, P2, and P3 are all connected to the VDDH terminal, and the drain of P1, the gate of P1, the gate of P2, the gate of P5, and the drain of N1 are all connected to the Q point of the first structure or the K point of the second structure; The drain of P2 is connected to the source of P5. The drain of P5, the drain of N3, and the drain of P4 are all connected to point X of the first structure or point Y of the second structure. The source of P4 is connected to the drain of P3. The gates of P3 and N2 are both connected to node B of the first result or point OUT of the second structure. The gates of P4 and N3 are both connected to the inverting input signal terminal of the first structure or the input signal terminal of the second structure. The source of N1 is connected to the drain of N2. The gate of N1 is connected to the input signal terminal of the first structure or the inverting input signal terminal of the second structure. The sources of N2 and N3 are both grounded. Points X and Y are additional control signal introduction points. The main output stage includes: 8 PMOS tubes P6 to P13, and 10 NMOS tubes N4 to N13; The sources of P6, P7, P8, and P9 are all connected to the VDDH terminal, the drain of P6 is connected to the source of P10, the drain of P10, the gate of P7, the drain of N5, the drain of N10, and the gate of N8 are all connected to node A, the gates of P10 and P12 are all connected to point X, the gates of P11, P13, the gate of N4, and the gate of N13 are all connected to point Y, the drain of P7 is connected to the source of P11, the drain of P8 is connected to the source of P12, the drain of P9 is connected to the source of P13 and the drain of N8, and the source of N9 is connected to the drain of N13; The gate of N5, the drain of N6, the drain of P11, the gate of P8, and the drain of N11 are all connected to node B; The gate of N6, the drain of N7, the drain of P12, the gate of P9, and the drain of N12 are all connected to node C; The gate of P6, the drain of P13, the drain of N4 and the drain of N9 are all connected to the OUT terminal; The gate of N7 is connected to the source of N4 and the drain of N8; the sources of N5, N6, N7, N8, N10, N11, N12 and N13 are all grounded; The gates of N10 and N12 are connected to the input signal terminal, and the gates of N11 and N9 are connected to the inverting input signal terminal.

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