High speed transmitter circuitry for optical communications

Abstract

The embodiment of the invention relates to a high-speed transmitter circuit device for optical communication. An optical transmitter includes a DAC, a timing circuit, and a circuit arrangement. The DAC includes a switch configured to convert digital data into analog data that is modulated as an optical signal for transmission over an optical fiber. The timing circuit is configured to generate a timing signal to control switching of the DAC. The circuitry is configured to control an output data rate of the DAC by biasing the switch based on a logical combination of the digital data and the timing signal. The optical transmitter includes a DAC and a driver. The DAC is configured to receive digital data at a first data rate and output current at a second data rate greater than the first data rate. The driver is configured to receive a combined current comprising a current output by the DAC and to generate an output signal proportional to the combined current.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 609,338, filed Dec. 12, 2023. The entire disclosure of the above-referenced application is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to optical communication systems, and more particularly to high-speed transmitter circuitry for optical communication systems. Background Art

[0004] The background art description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently named inventors, to the extent it is described in this background art section, and aspects of the description that may not otherwise be attributable to prior art at the time of filing, are not, either expressly or impliedly, admitted to be prior art against the disclosure.

[0005] Optical communication systems include an optical transmitter and an optical receiver connected by an optical fiber. The optical transmitter modulates an optical signal (e.g., a laser) serving as a carrier with data to be transmitted and transmits the modulated optical signal via the optical fiber. The optical receiver receives the modulated optical signal via the optical fiber and extracts the data from the modulated optical signal. Summary of the Invention

[0006] An optical transmitter includes a digital-to-analog converter (DAC), a timing circuit, and circuitry. The DAC includes switches configured to convert digital data to analog data, which is modulated into an optical signal for transmission over an optical fiber. The timing circuit is configured to generate a timing signal to control the switches of the DAC. The circuitry is configured to control the output data rate of the DAC by biasing the switches based on a logical combination of the digital data and the timing signal.

[0007] In other features, by biasing the switches of the DAC based on a logical combination of the digital data and the timing signal, the DAC outputs analog data at an output data rate greater than the data rate of the digital data.

[0008] In other features, by biasing the switches of the DAC based on a logical combination of the digital data and the timing signal, the DAC outputs a linear current signal regardless of the output data rate of the DAC.

[0009] In other features, the timing circuit is configured to generate timing signals having a phase difference and adjust the phase difference to control the output data rate of the DAC.

[0010] Among other features, by adjusting a phase difference of a timing signal, a DAC outputs analog data at an output data rate greater than a data rate of digital data, independent of a pulse width of the digital data and a pulse width of the timing signal.

[0011] Among other features, the switch includes a first switch connected in series with a second switch. The circuit arrangement includes combinational logic circuitry configured to receive digital data and a timing signal, output a logical combination of the digital data and the timing signal to control the first switch, and control the second switch by a first timing signal among the timing signals.

[0012] Among other features, digital data powers the combinational logic circuitry.

[0013] Among other features, the switch further includes a third switch and a fourth switch. The third switch is connected to the first switch at a node and is biased to output a current signal including analog data. The fourth switch is connected to the node and, when the first switch and the second switch are off, the fourth switch is biased by a second timing signal among the timing signals to pull up the voltage at the node.

[0014] Among other features, the optical transmitter further includes a bias control circuit configured to control the bias of the third switch to control an output swing of the DAC.

[0015] Among other features, the optical transmitter includes a plurality of digital-to-analog converters (DACs) and a driver. The DAC is configured to receive digital data at a first data rate and output a current at a second data rate greater than the first data rate. The driver is configured to receive a combined current including the current output by the DAC and generate an output signal proportional to the combined current.

[0016] Among other features, the optical transmitter further includes a timing circuit and a circuit arrangement. The timing circuit is configured to generate a timing signal to control the DAC. The circuit arrangement is configured to bias the DAC based on a logical combination of the digital data and the timing signal to control the second data rate.

[0017] Among other features, the timing circuit is configured to generate a timing signal having a phase difference and adjust the phase difference to control the second data rate.

[0018] Among other features, the optical transmitter further includes a bias control circuit configured to control the bias of the DAC. An output swing of the driver linearly varies with the bias of the DAC.

[0019] Among other features, the driver includes a current-voltage converter, a preamplifier, an amplifier, and a balancing circuit. The current-voltage converter is configured to convert a combined current into a voltage signal and compensate for the capacitive load from the DAC. The preamplifier is configured to amplify the voltage signal and reduce the output impedance of the preamplifier. The amplifier is configured to amplify the output of the preamplifier. The balancing circuit is configured to balance the voltages at multiple nodes in the amplifier using a combination of a feedback voltage and a reference voltage to maintain the linear characteristics of the output of the amplifier and reduce the power consumption of the driver.

[0020] Among other features, the current-voltage converter includes a T-coil having a center tap, which is configured to receive the combined current and compensate for the capacitive load from the DAC.

[0021] Among other features, the preamplifier includes a source follower configured to amplify the voltage signal and includes an LC circuit that forms a negative feedback loop configured to reduce the output impedance of the preamplifier.

[0022] Among other features, the amplifier includes a cascode switch configured to reduce the capacitive load on the preamplifier.

[0023] Among other features, the amplifier is configured to generate a differential output via respective termination resistors. The amplifier includes a cascode switch configured to maintain the output impedance of the amplifier defined by the termination resistors to reduce signal reflections in the differential output of the amplifier.

[0024] Among other features, the amplifier is configured to generate a differential output through a first set of switches in a first branch and a second set of switches in a second branch. The amplifier includes a first node (N2) defined by the top and bottom switches in the first and second branches and configured to receive the output of the preamplifier. The amplifier includes a second node (N3) defined by the bottom switches in the first and second branches and configured to bias the bottom switches. The amplifier includes two termination resistors connected to each other at a third node (N4) and connected to the differential output. The amplifier includes a cascode switch connected between the top and bottom switches in the first and second branches, and the cascode switch is biased to reduce the capacitive load on the preamplifier and maintain the output impedance of the amplifier defined by the termination resistors.

[0025] Among other features, to maintain the linearity of the amplifier output and reduce the power consumption of the driver, the balancing circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to generate a power supply voltage provided to the DAC and the current-voltage converter, and to regulate the power supply voltage at a first node (N2) to keep the bottom switches of the first and second branches in the linear operating region. The second circuit is configured to sense the common-mode output voltage of the amplifier and generate a feedback signal input to a second node (N3). The feedback signal is configured to control the bias of the bottom switches in the first and second branches such that the bias current of the bottom switches is equal to the bias current of the cascode switches. The third circuit is coupled to a third node (N4) and is configured to control the low-frequency common-mode return loss of the driver to mitigate common-mode reflections from the differential output and generate a controllable voltage difference across the termination resistor, which provides a bias current to be added to or subtracted from the current flowing through the cascode switches of the bottom switches.

[0026] Among other features, the amplifier is configured to generate a differential output via a respective T-coil, which is configured to isolate the differential output from an external electrostatic discharge (ESD) protection device and reduce the capacitive load on the differential output from the ESD device.

[0027] Based on the detailed description, the claims, and the drawings, other application areas of the present disclosure will become apparent. The detailed description and specific examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Description of the Drawings

[0028] Figure 1 is a block diagram of an optical communication system.

[0029] Figure 2 is Figure 1 a functional block diagram of an optical transmitter of the optical communication system.

[0030] Figure 3A and Figure 3B is in Figure 2 a functional block diagram of a digital-to-analog converter (DAC) used in the optical transmitter.

[0031] Figure 4A is in Figure 2 a circuit diagram of the DAC used in the optical transmitter.

[0032] Figure 4B shows an example of a current mirror for generating Figure 4A a bias voltage for the DAC.

[0033] Figure 5A is Figure 4ATiming diagram of the DAC.

[0034] Figure 5B is Figure 4A truth table of the DAC.

[0035] Figure 5C is a graph showing Figure 2 linear characteristics of the output swing of the optical transmitter.

[0036] Figure 6 is Figure 2 functional block diagram of the driver used in the optical transmitter.

[0037] Figures 7 - 10 shows Figure 6 various circuits of the driver.

[0038] In the drawings, reference numerals may be reused to identify similar and / or identical elements. Detailed Description

[0039] Due to the recent proliferation of artificial intelligence (AI) and machine learning (ML) applications as well as cloud computing, the demand for high-speed and high-bandwidth optical communication systems in data centers is increasing. These applications continue to drive higher throughput in network components such as transmitter and receiver front-end circuitry used in optical communication systems in data centers. In addition, the high density of optical modules in the hardware racks used in data centers requires innovative low-power design techniques for high-power transceiver chips used in optical communication systems in data centers. To address the demand for these applications without significantly increasing the number of optical ports and implementation costs, a data rate of 200 Gbps or higher is required, which is twice the data rate of current-generation transceivers. Achieving such bandwidth without additional hardware is difficult, which increases power consumption and cost. In the present disclosure, the problems of achieving high bandwidth and high swing / low power consumption in the design of transmitters for optical communication applications are addressed.

[0040] In various commercially available optical communication systems compliant with one or more IEEE standards (e.g., IEEE P802.3dj), an optical transmitter uses up to eight channels, each channel outputting data at approximately 100 Gbps. The optical transmitter combines the outputs of the eight channels to transmit data at 800 Gbps. Each channel uses a digital-to-analog converter (DAC) including a single device to convert digital data bits into an analog signal. Specifically, each DAC includes a single switching device (e.g., a single transistor) operating in voltage mode. In voltage mode, the input data signal and the output data signal of the DAC are voltage signals of the same phase.

[0041] The above transmitter architectures have various drawbacks. The data rate for each channel is limited to 100 Gbps, and it is difficult to scale the data rate with such architectures. This is because the pulse width of the input signal to the DAC needs to be halved to double the data rate. However, for many reasons, halving the pulse width of the input signal is challenging. For example, additional circuitry is required to halve the pulse width of the input signal and maintain the halved pulse width of the input signal, which increases the power consumption of the optical transmitter. Additionally, the amplitude (voltage level or swing) of the output signal of the DAC does not change linearly with the amplitude of the input signal. Furthermore, the relationship between the input and output signals of the DAC changes significantly with temperature, process, and chip-to-chip variations. Thus, for practicality, to double the data rate of the transmitter, another set of 8 channels along with associated hardware needs to be added to the optical transmitter, which not only consumes more power but also increases the equipment cost.

[0042] The teachings of the present disclosure enable the data rate for each channel to be doubled and even scaled higher without sacrificing linear characteristics and without any significant increase in the power consumption of the optical transmitter. Specifically, by using a DAC that operates in current mode rather than voltage mode, the data rate for each channel is doubled, which thus obviates the need to double the number of channels (i.e., the amount of hardware) to double the data rate of the optical transmitter.

[0043] As described in detail below, the DAC uses two switches connected in series instead of one switch, and employs a circuit (e.g., a NAND gate) that uses a logical combination of two clock signals and digital data to drive the two switches. The pulse width of the output current of the DAC can be scaled by scaling the phase difference between the two clock signals. Operating the DAC in current mode allows for lower power usage, and the design based on phase difference rather than pulse width relaxes the timing constraints on the input signal. Specifically, the input signals (e.g., digital data and clock signals) can have a wider pulse width (i.e., lower frequency), and by controlling the phase offset between the clocks used to drive the DAC, the output current pulses of the DAC can be made narrower, resulting in a higher output data rate.

[0044] The DAC design of the present disclosure can be scaled to provide data rates even more than twice as high by controlling only the phase offset (phase difference) between the clocks used to drive the DAC. Additionally, the output current of the DAC can be linearly controlled by using a current mirror similar to the DAC. Due to the inherent matching between the current mirror and the DAC, temperature and process variations are managed.

[0045] In addition, the present disclosure also discloses a driver that converts the high-frequency current signal output by the DAC into a proportional voltage that can drive an external load (e.g., an optical device). As described in detail below, the driver employs four stages: a current-voltage (I-V or simply IV) converter stage, a buffer (pre-amplifier) stage, a differential amplifier stage, and a balancing stage. These stages provide a number of innovative features, which will be described in detail below.

[0046] Briefly, in the IV stage, the current outputs of the DAC are combined and input to the center tap of a coil. The coil compensates for the capacitive load from the DAC. The buffer stage uses a source follower. In a typical source follower, the bottom switch does not participate in signal modification and only operates as a current source. In contrast, the buffer stage employs an LC circuit that generates a negative feedback loop by reusing the current flowing through the bottom switch. Due to the negative feedback, the buffering effect of the source follower is enhanced, which allows the source follower to drive a higher capacitive load than a typical source follower.

[0047] The differential amplifier amplifies the output of the buffer stage while using a low supply voltage to reduce power consumption. The differential output of the amplifier is provided to a subsequent circuit (e.g., an optical modulator, etc.). The differential amplifier includes a termination resistor and a cascode transistor. The cascode transistor protects the input of the amplifier and the buffer stage from signal swings caused by the capacitive Miller effect within the amplifier. The cascode transistor in series with the input transistor also helps to maintain an effective termination resistor.

[0048] The balancing stage employs multiple operational amplifiers. The first operational amplifier is used to minimize the DC voltage variation at the output of the buffer stage and generate the required DC voltage at the gate of the NMOS device of the amplification stage. The second operational amplifier is used to minimize the DC voltage variation at the output of the amplifier stage and generate the required DC voltage at the drain nodes of the NMOS and PMOS devices of the amplifier stage. The third operational amplifier is used to improve the common-mode return loss and create a current offset between the bottom NMOS and top PMOS branches of the amplifier stage. These and other features of the present disclosure are described in more detail below.

[0049] Figure 1 A block diagram of an optical communication system 10 is shown. The optical communication system 10 includes an optical transmitter 12 and an optical receiver 14 connected by an optical fiber 16. Figure 2 The optical transmitter 12 is shown in more detail in

[0050] Figure 2 More particularly, the optical transmitter 12 is shown. The optical transmitter 12 includes a digital signal processor (DSP) 20; a plurality of serializers 22-1, 22-2... 22-N (collectively referred to as serializers 22), where N is a positive integer (e.g., N = 8); a plurality of DACs 24-1, 24-2... 24-N (collectively referred to as DAC 24); a driver 26; a laser source 28; and an optical modulator 30. In addition, although not shown, the optical transmitter 12 includes a power supply that generates all the power supply voltages (e.g., the power supply voltage, bias voltage, and reference voltage described below) required for the components of the optical transmitter 12.

[0051] The DSP 20 receives digital data (bits) to be transmitted. The DSP 20 divides the data into a plurality of bit data streams. Each serializer 22 serializes the bits in the corresponding data stream and outputs serial data. Each DAC 24 converts the serial data received from the corresponding serializer and outputs a current signal. The current signals from the DAC 24 are combined and input to the driver 26.

[0052] The driver 26 converts the combined current signal output by the DAC 24 into a proportional voltage that can drive an external load (e.g., the optical fiber 16). The driver 26 generates a modulation signal based on the combined current signal output by the DAC 24. The driver 26 outputs the modulation signal to the optical modulator 30.

[0053] The laser source 28 generates an optical signal (e.g., a laser), which is used by the transmitter 12 as a carrier to transmit data. The optical modulator 30 modulates the optical signal with the modulation signal received from the driver 26 and generates a modulated optical signal. The transmitter 12 transmits the modulated optical signal through the optical fiber 16.

[0054] Figure 3A and Figure 3B shows the design of the DAC 24. Figure 2 Each of the illustrated DACs 24 includes Figure 3A and Figure 3B the components shown. In the following description, Figure 2 each individual DAC 24 shown is referred to as DAC 24. The following description applies to Figure 2 each of the (multiple) DACs 24 shown. In Figure 3A , the DAC 24 includes a timing circuit 50, circuitry 52, and a DAC switch 54. In Figure 3BIn this case, the timing circuit 50 includes a clock generator 60 and a phase control circuit 62. The circuit arrangement 52 includes a logic circuit 64 and a bias control circuit 66. In some embodiments, the clock generator 60, the phase control circuit 62, and the bias control circuit 66 may be Figure 2 shared by all the DACs 24 shown. That is, in some embodiments, only one clock generator 60, only one phase control circuit 62, and only one bias control circuit 66 may be used to drive Figure 2 all the DACs 24 shown.

[0055] The DAC 24 is configured to convert digital data into analog data, and the analog data is modulated by an optical modulator 30 ( Figure 2 shown) into an optical modulation signal for transmission on an optical fiber 16 ( Figure 1 shown). The timing circuit 50 is configured to generate a timing signal to control the DAC switch 54. In the timing circuit 50, the clock generator 60 generates a timing signal (e.g., a clock signal) to control the DAC switch 54. As described in detail below with reference to Figure 4A and Figures 5A - 5B , the phase control circuit 62 controls the phase difference between clock signals (shown by reference numeral 70 in Figure 5A ) to control the output data rate of the DAC 24. Thus, the timing circuit 50 generates a timing signal including clock signals having a phase difference, and adjusts the phase difference to control the output data rate of the DAC 24, as described in further detail below.

[0056] In the circuit arrangement 52, the logic circuit 64 (e.g., the NAND gate-based circuit shown in Figure 4A ) receives the clock signal output by the timing circuit 50, and the clock signal has a phase difference tuned (selected) by the phase control circuit 62 to achieve the desired output data rate of the DAC 24. The logic circuit 64 also receives the digital data D output by the corresponding serializer 22 ( Figure 2 shown). The circuit arrangement 52 is configured to bias the DAC switch 54 based on a logical combination of the digital data and the timing signal to control the output data rate of the DAC 24, as described in further detail below with reference to Figure 4A and Figures 5A - 5B .

[0057] The DAC switch 54 is biased by a logical combination of digital data and a timing signal, and the DAC 24 outputs analog data having a data rate greater than the data rate of the digital data. For example, by selecting an appropriate phase difference between the clock signals used to drive the DAC switch 54, which is selected based on the desired output data rate of the DAC 24, the output data rate of the DAC 24 can be greater than (e.g., twice or even higher) the data rate of the digital data.

[0058] By using the phase control circuit 62 to adjust the phase difference of the timing signal, the DAC 24 outputs data at a data rate greater than the data rate of the digital data, regardless of the pulse width of the timing signal and the pulse width of the digital data. The phase difference between the clock signals can be tuned to scale the output data rate of the DAC 24. Controlling the output data rate of the DAC 24 by adjusting the phase difference of the timing signal relaxes the timing constraints on the digital data and the timing signal. Thus, the output data rate of the DAC 24 can be scaled without imposing constraints on the timing of the digital data and the timing signal (e.g., without narrowing the pulse width).

[0059] In addition, by biasing the DAC switch 54 based on a logical combination of digital data and a timing signal, the DAC 24 outputs a linear current signal, regardless of the output data rate of the DAC 24. Specifically, the DAC 24 does not operate in a voltage mode, in which the input and output of the DAC are synchronous voltage signals, and in the voltage mode, as explained below, it is challenging to achieve the linear characteristics of the DAC output at a higher data rate. Instead, the DAC 24 operates in a current mode using two switches connected in series ( Figure 4A as shown), in which the inputs (digital data and timing signal) to the DAC 24 are voltage signals, but the output parameter of interest for the DAC 24 is a current signal having a smaller pulse width compared to the input voltage signal. The current signal output by the DAC 24 varies linearly, regardless of the output data rate of the DAC 24 and regardless of the pulse widths of the digital data and the timing signal, as described below.

[0060] More specifically, in order to save power and increase the output data rate of the DAC, smaller voltage pulses are usually required to control the DAC. In voltage mode, the pulse width of the input signal of the DAC needs to be at least two times smaller than that in current mode. The narrower voltage pulses required to increase the output data rate of the DAC in voltage mode are difficult to generate and maintain (for example, additional circuit devices are required, which increases power consumption). In addition, voltage mode is not conducive to swing control because the output signal amplitude (voltage swing) of the DAC does not change linearly with the input signal amplitude. Many applications require the ability to linearly control the swing of the DAC output, which is difficult to achieve in voltage mode, especially when changing the pulse height of the input signal to change the swing also changes the bandwidth. Therefore, in voltage mode, the ability to increase bandwidth is coupled to the change of the output voltage swing of the DAC.

[0061] In contrast, the current mode does not have these limitations. This is because the logical combination of the output current signal of the DAC switch 54 drives the DAC switch 54 to control the output current of the DAC switch 54. By changing the phase difference of the timing signal, the logical combination of the digital data and the timing signal can linearly change the output current of the DAC 24, regardless of the pulse width of the digital data and the pulse width of the timing signal. Therefore, unlike the voltage mode, in the current mode, the output current of the DAC 24 is independent of the pulse height of the digital data and the pulse height of the timing signal (up to a certain limit). By adjusting the phase difference between the clock signals, the pulse width of the output data of the DAC 24 can be linearly changed without considering the pulse width of the digital data and the timing signal, and without increasing the power supply voltage, which reduces power consumption. Therefore, by operating the DAC 24 in the current mode, driving the DAC 24 by the logical combination of the digital data and the timing signal, and controlling the phase difference between the clock signals, the output data rate of the DAC 24 can be linearly increased without increasing power consumption, while relaxing the timing constraints on the input of the DAC 24.

[0062] Figures 4A - 4B and Figures 5A - 5B Shows Figure 3A and Figure 3B DAC 24 includes switches T1, T2, T3 and T4 ( Figure 3A and Figure 3B DAC switch 54 shown in FIG); and a NAND gate ( Figure 3A and Figure 3B The circuit arrangement 52 shown in FIG. Figure 3A and Figure 3B The timing circuit 50 shown generates Figure 5A The clock signals CK1 and CK2 are shown. For example,Figure 3B The clock generator 60 shown generates clock signals CK1 and CK2, and Figure 3B the phase control circuit 62 shown controls the phase difference 70 between the clock signals CK1 and CK2 based on the desired output data rate of the DAC 24.

[0063] The DAC 24 includes switches T1 and T2 connected in series with each other. As Figure 4A shown, switches T3 and T4 are connected to switch T1 at node N. Node N is referred to as the source node because node N is located at the source terminal of switch T1. Switch T3 is referred to as the bias switch, and switch T4 is referred to as the pull-up switch. The operations of switches T3 and T4 are described below.

[0064] The NAND gate receives two inputs and receives an input as the power supply of the NAND gate. The two inputs of the NAND gate are two clock signals CK1 and CK2 generated by the timing circuit 50 shown in Figure 3A and Figure 3B shown. The digital data D output by the serializer 22 (shown in Figure 2 ) is applied to the NAND gate as the power supply of the NAND gate. The NAND gate generates an output DI based on the two inputs CK1 and CK2 of the NAND gate and the digital data D as the power supply of the NAND gate.

[0065] Since the digital input D is applied to the NAND gate as the power supply of the NAND gate, when the digital data D that powers the NAND gate is 0, the output DI of the NAND gate is 0 because when the power supply to the NAND gate is 0, there can be no output. When the digital data D that powers the NAND gate is 1 as shown in the truth table shown in Figure 5B , the NAND gate switches the output DI according to the input clock signals CK1 and CK1. The output DI of the NAND gate drives switch T1. The clock signal CK1 drives switch T2. Switches T1 and T2 generate an output current Iout, which is the analog output of the DAC 24 representing the digital data D. Since the DAC 24 outputs a current signal representing the digital data D, the DAC 24 is referred to as operating in current mode.

[0066] Figure 5A shows Figure 4A the timing diagram of the signals shown in Figure 5B shows the truth table of the DAC 24. The truth table shows the on / off states of switches T1 to T4 when operating switches T1 to T4 using the signals shown in the timing diagram of Figure 5A .

[0067] In Figure 5AIn it, the phase difference between two clock signals CK1 and CK2 is shown by reference numeral 70. The pulse width of the output current Iout of the DAC 24 is proportional to the phase difference 70 between the two clock signals CK1 and CK2. Therefore, the output data rate of the DAC 24 can be controlled by controlling the phase difference 70 between the two clock signals CK1 and CK2.

[0068] The clock signals CK1 and CK2 have the same frequency, which is also the same as the frequency of the digital data D. However, the clock signals CK1 and CK2 are phase-shifted from each other by the phase difference 70. The clock signals CK1 and CK2 each have a 50% duty cycle. In other words, in the clock signals CK1 and CK2, the pulse width of the high pulse and the pulse width of the low pulse in one clock cycle are the same. The clock signal CK2b is the inverted clock signal CK2.

[0069] To adjust the output data rate of the DAC 24, the phase difference 70 between the clock signals CK1 and CK2 can be adjusted to any value less than the pulse width of the clock signals CK1 and CK2. To provide more room for scaling the output data rate of the DAC 24 (which is proportional to the phase difference 70), the pulse width of the clock signals CK1 and CK2 can be increased (i.e., the frequency of the clock signals CK1 and CK2 can be decreased). The increased pulse width of the clock signals CK1 and CK2 in turn can provide more room within which to vary the phase difference 70 to vary the output data rate of the DAC 24. The phase control circuit 62 can be programmable to select the pulse width of the clock signals CK1 and CK2. For example, a code word can be input to the phase control circuit 62 to set the pulse width of the clock signals CK1 and CK2.

[0070] The bias switch T3 is biased by a bias voltage VB. Figure 3B The illustrated bias control circuit 66 controls the bias voltage VB supplied to the bias switch T3. The bias voltage VB determines the output swing of the DAC 24, which in turn determines Figure 2 the output swing of the illustrated driver 26. The driver 26 maintains the linear characteristic of the current output by the DAC 24, as described below with reference to Figures 6 - 10 the following. The output swing of the driver 26 can be linearly controlled by controlling the bias voltage VB, as Figure 5C illustrated, which is useful in optical applications as described below.

[0071] In optical applications, among different optical transmitters, downstream circuits from a driver 26 (e.g., an additional external driver, a modulator 30, etc.) may exhibit optimal performance at different swing levels of the driver 26. The optical transmitter should be able to select the amplitude (swing level) of the driver 26 suitable for the downstream circuit without degrading the performance (e.g., linear characteristics and low power consumption) provided by the DAC 24 and the driver 26. When the DAC operates in voltage mode, this is difficult to achieve due to the non-linear characteristics of the voltage output of the DAC.

[0072] In contrast, when the DAC 24 operates in current mode, the bias control circuit 66 can control the bias voltage VB based on the swing requirements of the circuit following the driver 26 without degrading the performance provided by the DAC 24 and the driver 26. As Figure 5C shown, the output swing of the driver 26 varies linearly with the bias voltage VB of the DAC 24 within the operating range. The performance of the driver 26 (e.g., including the signal-ripple ratio) is insensitive to the swing amplitude (peak-to-peak output) of the driver 26.

[0073] The bias control circuit 66 can be programmable to select the bias voltage VB of the DAC 24 suitable for different optical applications. For example, a codeword can be input to the bias control circuit 66 to set the bias voltage VB of the DAC 24. For example, the bias control circuit 66 can include a low-speed bias DAC that generates the bias voltage VB based on the codeword. Alternatively, the bias control circuit 66 can include a voltage divider (e.g., a resistive ladder) having taps connected to switches, and different bias voltages VB can be output to the DAC 24 through the switches. A codeword can be used to control the switches to select the bias voltage VB of the DAC 24.

[0074] Figure 4B A current mirror circuit 80 is shown as another example of a bias control circuit 66 that can be used to generate the bias voltage VB of the DAC 24. The current mirror circuit 80 includes switches T5 and T6 connected in series, which are copies of switches T1 and T2 of the DAC 24, respectively. A switch T7 is connected in series to the source of the switch T2 and is a copy of the switch T3 of the DAC 24. The drain and gate of the switch T7 are connected to each other in a current mirror configuration. A switch similar to the switch T4 of the DAC 24 is not required in the current mirror circuit 80 because the switch T4 turns off when the current Iout of the DAC 24 flows. Using the switches T5, T6, and T7 in the current mirror circuit 80 as copies of the corresponding switches T1, T2, and T3 of the DAC 24 reduces the temperature and process variations in the DAC 24 due to the inherent matching between the current mirror circuit 80 and the DAC 24.

[0075] The output DI of the NAND gate of the DAC 24 that drives the switch T2 of the DAC 24 varies between 0V and the supply voltage DI-Supply. The constant voltage DI-Supply drives the switch T6 of the current mirror circuit 80. The clock CK1 that drives the switch T1 of the DAC 24 varies between 0V and the voltage CK1-Supply. The constant voltage CK1-Supply drives the switch T5 of the current mirror circuit. The bias DAC 82 (e.g., similar to the low-speed bias DAC described above with reference to the bias control circuit 66) provides a bias current Ibias through the switch T7 of the current mirror circuit 80. The switch T7 acts as a diode, with its drain and gate connected to each other. A voltage VB that maintains the bias current is generated across the switch T7. When the voltage VB generated across the switch T7 is applied to the gate of the switch T3 of the DAC 24, which matches the switch T7 of the current mirror circuit 80, the same current flowing through the switch T7 is generated through the switch T3 of the DAC 24. Thus, the bias current is mirrored in the DAC 24.

[0076] Specifically, there is a proportional relationship between the bias current Ibias flowing through the current mirror circuit 80 and the current Iout flowing through the DAC 24. For a given digital data input to the DAC 24, increasing the Ibias by N times increases the Iout by N times, which increases the swing of the DAC 24 by N times. Thus, the value of Ibias is linearly proportional to the codeword input to the low-speed bias DAC 82, and the bias voltage VB of the DAC 24 is programmed by programming the Ibias (by controlling the control of the codeword input to the bias DAC 82 that generates the Ibias). Thus, by controlling the codeword input to the bias DAC 82 that generates the Ibias, the current Iout of the DAC 24 can be linearly controlled. In addition, by controlling the codeword input to the bias DAC 82 that generates the Ibias, the bias voltage VB of the DAC 24 is also linearly controlled, which in turn linearly controls the swing of the outputs of the DAC 24 and the driver 26.

[0077] The pull-up switch T4 is driven by the clock signal CK2b. When the DAC switches T1 and T2 are off (when all inputs of the NAND gate D, CK1, and CK2 are high), the pull-up switch T4 pulls up the voltage at the source node N to Vdmp. Pulling up the source node N high when the DAC switches T1 and T2 are off causes the fall time of the output current Iout of the DAC 24 to rise sharply and increases the operating speed of the DAC 24.

[0078] Switch T2 is controlled by the clock signal CK1, rather than by switch T2 itself. This is because the voltage level of the clock signal CK1 can be less than the voltage level of the output DI of the NAND gate to reduce power consumption. By using a lower voltage signal such as the clock signal CK1, the switch T2, which is an NMOS device with its source grounded, can be easily and quickly turned on and off. By driving the switches T1 to T4 of the DAC 24 as described above, the 1 unit interval (1UI) pulse of the digital data D is converted into a high-speed current pulse I out,DAC , as Figure 5A shown.

[0079] Using N DACs 24 as shown in Figure 2 , the output of the serializer 22 operating at 1 / N of the desired data rate is converted into current by the N DACs 24. The currents output by the DACs 24 are Figure 2 combined and amplified by the driver 26 as shown to generate an output at the desired data rate. The desired data rate at the output of the DAC 24 can be set by selecting the phase difference 70 between the clock signals CK1 and CK2. Using the phase difference 70 to scale the output data rate of the DAC 24 does not require narrowing the pulse width of any of the inputs (digital data D and the two clocks CK1 and CK2) of the NAND gate, which does not require additional hardware, and which in turn reduces power consumption. Further, since the output current Iout of the DAC 24 varies linearly when the phase difference 70 between the two clocks CK1 and CK2 is adjusted based on the desired output data rate of the DAC 24, the output data rate of the DAC 24 can be linearly scaled.

[0080] Figure 6 shows a functional block diagram of the driver 26. The driver 26 receives the combined current of the DAC 24, which is the sum of the currents output by the DAC 24, converts the combined current into a voltage signal, and amplifies the voltage signal used by the optical modulator 30 ( Figure 2 shown) to generate an optical modulation signal. As explained below with reference to Figures 7 - 10 , the driver 26 operates as a transimpedance amplifier (TIA) and performs the conversion and amplification without losing the linear characteristics of the current output by the DAC 24 while maintaining low power consumption.

[0081] Driver 26 includes four stages. As described in detail below, the first stage includes two complementary IV converters 100-1, 100-2. The second stage includes two complementary preamplifiers (buffers) 102-1, 102-2. The third stage includes a differential amplifier 104. The fourth stage includes a balun circuit 106. Driver 26 uses a differential (instead of single-ended) design, which uses differential inputs (N, P) to generate differential outputs (N, P). Due to the differential design of driver 26, each stage of driver 26 includes two sets of circuits, where one set receives the N inputs from the previous stage and generates the N outputs for the next stage, and the other set receives the P inputs from the previous stage and generates the P outputs for the next stage.

[0082] The first stage of driver 26 is a current-voltage (I-V or IV) converter stage that includes IV converters 100-1, 100-2 (collectively referred to as IV converter 100). The second stage of driver 26 is a preamplifier (buffer) stage that includes preamplifiers (buffers) 102-1, 102-2 (collectively referred to as preamplifier 102). The third stage of driver 26 is an amplifier stage that includes differential amplifier 104. The fourth stage of driver 26 is balun stage 106. The four stages of driver 26 are described in detail below with reference to Figures 7 - 10 driver 26.

[0083] Briefly, IV converter 100 receives the combined current output by DAC 24 and converts the combined current into a corresponding voltage signal. The voltage signal output by IV converter 100 is input to preamplifier 102 for pre-amplification. The output of preamplifier 102 is fed to the input of differential amplifier 106 for further amplification. Balun stage 108 balances the voltages at the respective nodes of driver 26, as described in detail below. In the following description, only one IV converter 100 and one preamplifier 102 are described. The following description of IV converter 100 applies to both IV converters 102-1, 102-2. The following description of preamplifier 102 applies to both preamplifiers 102-1, 102-2.

[0084] Figure 7 An IV converter (referred to as IV converter) 100 is shown. IV converter 100 includes a T coil, which includes two series inductors L1 and L2 having a center tap. The node where inductors L1 and L2 are connected in series with each other there is called N1. The center tap of the T coil is located at node N1, also called center tap N1. Inductor L1 is connected to the power supply V that powers DAC 24 DACS .. Balun circuit 106 generates the V Figure 10 described below with reference to DACS .. Inductor L2 is connected to preamplifier 102.

[0085] The combined current output by the DAC 24 is input to the center tap N1 of the T coil. The T coil compensates for the capacitive load from the DAC 24, which helps maintain the linear characteristics of the current output by the DAC 24. The IV converter 100 converts the combined current output by the DAC 24 into a voltage signal input to the source follower of the preamplifier 102. The resistive load R of the T coil DAC defines the conversion gain of the IV converter 100. Due to the differential design of the driver 26, the voltage signals output by the IV converters 100-1 and 100-2 are respectively referred to as V SF，IP and V SF，IN .

[0086] Figure 8 The preamplifier 102 is shown. The preamplifier 102 includes a source follower, which includes two switches M1 and M2 (e.g., NMOS switches) connected in series. The node where the switches M1 and M2 are connected in series with each other is called N2. The switch M1 is called the top switch, and the switch M2 is called the bottom switch. The output of the preamplifier 102 at the node N2 is connected to the input of the amplifier 104. The bottom switch M2 is biased by the source follower bias voltage called V Bsf .

[0087] The preamplifier 102 also includes an LC circuit, which includes an inductor L and a capacitor C. The inductor L is connected between the top switch M1 and the power supply Vs. The capacitor C is connected between the control terminal (gate) of the bottom switch M2 and one end of the inductor L connected to the top switch M1. The LC circuit creates a negative feedback loop by reusing the current flowing through the bottom switch M2. The negative feedback loop including the LC circuit is designed such that the preamplifier 102 does not oscillate. Due to the negative feedback, the buffering effect of the source follower is enhanced, whereby the source follower can drive a higher capacitive load than a typical source follower without using negative feedback. The negative feedback helps maintain the linear characteristics of the current output by the DAC 24.

[0088] Specifically, the capacitor C is a high-speed capacitor, and the inductor L is a shunt peaking inductor L. For example, the high-speed capacitor C is a metal-to-metal capacitor with low parasitic (undesired) capacitance to the substrate. The high-speed capacitor C also has a high self-resonant frequency (SRF) and a low equivalent series resistance (ESR). When the current attempts to change due to any parasitic capacitor connected to this node, the shunt peaking inductor L initially shunts the current. Therefore, the influence of the parasitic capacitance is reduced, and the circuit becomes faster. Generally, the shunt peaking inductor is used in series with a load resistor (e.g., R SF ).

[0089] The feedback path is AC-coupled using a high-speed capacitor C to ensure that the loop bandwidth is high enough to maintain the linear characteristics of the driver 26. The shunt peaking inductor L is serially connected to the drain of the top switch M1 with a resistor RSF to increase the loop gain at high frequencies, such that the output impedance of the preamplifier 102 at the source of the top switch M1 (at node N2) remains low in the presence of parasitic capacitances at different nodes in the driver 26. The low-frequency loop gain of the preamplifier 102 is g m2 R SF , where g m2 is the transconductance (voltage-to-current gain) of the bottom switch M2.

[0090] Figure 9 The differential amplifier 104 is shown. The differential amplifier 104 includes four switches SW1, SW2, SW3, and SW4, which include NMOS and PMOS switches. Additionally, the differential amplifier 104 includes two cascode switches SW5 and SW6 (e.g., PMOS switches). Switches SW1 and SW3 are PMOS switches, while switches SW2 and SW4 are NMOS switches. For convenience, switches SW1 and SW2 are referred to as the upper left switch and the lower left switch, while switches SW3 and SW4 are referred to as the upper right switch and the lower right switch. The two upper switches SW1 and SW3 are connected to the power supply Vs. The two lower switches SW2 and SW4 are connected to node N3, and node N3 is coupled to a reference potential via a bias circuit (e.g., an NMOS switch) 110 for biasing switches SW2 and SW4.

[0091] The bias circuit 112 biases the cascode switches SW5 and SW6. The first cascode amplifier switch SW5 is connected in series with and between the upper left switch SW1 and the lower left switch SW2. The second cascode amplifier switch SW6 is connected in series with and between the upper right switch SW3 and the lower right switch SW4. The differential amplifier 104 outputs a first differential output at the first contact of the first cascode amplifier switch SW5 and the lower left switch SW2. The differential amplifier 104 outputs a second differential output at the second connection of the second cascode amplifier switch SW6 and the lower right switch SW4.

[0092] The differential amplifier 104 also includes two terminating resistors Rt connected in series with each other. The nodes where the terminating resistors Rt are connected in series with each other there are called node N4. One end of the first terminating resistor Rt opposite to node N4 is coupled to the first junction (the first output of the differential amplifier 104) via a T coil 109-1. One end of the second terminating resistor Rt opposite to node N4 is coupled to the second junction (the second output of the differential amplifier 104) via a T coil 109-2. The differential outputs V OUTN and V OUTPThey are transmitted through the terminal resistor Rt and the T coils 109-1 and 109-2 (collectively referred to as the T coil 109), respectively. The T coil 109 isolates the differential amplifier 104 from the electrostatic discharge (ESD) protection device 111, and the electrostatic discharge protection device 111 may be located at the differential outputs V OUTN and V OUTP of the differential amplifier 104. For example, the differential outputs V OUTN and V OUTP of the differential amplifier 104 are connected to the pads of the chip including the driver 26, and the ESD protection device 111 is connected to the pads inside the chip. The T coil 109 also compensates for the slow response caused by the capacitive load on the differential amplifier 104 from the contact pads and the ESD protection device.

[0093] Due to the differential design of the differential amplifier 104, the control terminals (gates) of the upper left switch SW1 and the lower left switch SW2 are coupled to the node N2 in the first branch of the differential amplifier 104. The control terminals (gates) of the upper right switch SW3 and the lower right switch SW4 are coupled to the analog of the node N2 on the opposite side of the node N2 in the second branch of the differential amplifier 104. One output terminal of the preamplifier 102 is directly connected to the control terminals (gates) of the lower left switch SW2 and the lower right switch SW4 in the first branch of the differential amplifier 104. The other output of the preamplifier 102 is connected to the control terminals (gates) of the upper left switch SW1 and the upper right switch SW3 in the second branch of the differential amplifier 104 through a high-speed AC coupling capacitor (not shown).

[0094] The cascode amplifier switches SW5 and SW6 in the respective branches of the differential amplifier 104 provide the following advantages. In the following description, only one cascode amplifier switch SW5 in the first branch of the differential amplifier 104 is referred to. This description also applies to the other cascode switch SW6 in the second branch of the differential amplifier 104. The cascode amplifier switch SW5 reduces the influence of the Miller capacitance load caused by the gate-drain capacitance (Cgd1) of the switch SW1 on the pre-preamplifier 102. Since the cascode node (the drain of SW1) is isolated from the first output node V OUTN of the differential amplifier 104 and experiences a smaller swing, Cgd1 does not experience a large swing and is not amplified. Similar cascode (e.g., by inserting an NMOS cascode switch between the first output node V OUTN and the drain of SW2) can be constructed on the NMOS side (SW2). However, to do so, the supply voltage V s needs to be increased, which will increase the power consumption and can therefore be avoided.

[0095] The cascode amplifier switch SW5 also ensures that the output impedances of the PMOS devices SW1 and SW5 do not affect the total output impedance of the differential amplifier 104, which must be kept as close as possible to a fixed value (e.g., 50 Ω) defined by the termination resistor Rt to reduce signal reflections and improve signal integrity. Typically, due to process / voltage / temperature (PVT) variations, the output impedance of CMOS devices varies significantly. The cascode amplifier design ensures that the output impedance of the differential amplifier 104 defined by the termination resistor Rt remains as unaffected as possible by these variations. Additionally, if a higher supply voltage Vs is used, similar benefits can be obtained on the NMOS side (SW2) (e.g., by inserting an NMOS cascode switch between the drain of SW2 and V OUTN ), which is avoided to keep the power consumption low.

[0096] Thus, the cascode amplifier switches SW5 and SW6 protect the inputs of the preamplifier 102 and the differential amplifier 104 from signal swings caused by capacitive effects within the differential amplifier 104. The cascode amplifier switches SW5 and SW6, which are serially connected to the upper left switch SW1 and the upper right switch SW3, respectively, also keep the effective output impedance of the differential amplifier 104 defined by the termination resistor Rt almost constant. Due to the above design, the differential amplifier 104 amplifies the output of the preamplifier 102 while maintaining the linear characteristics of the output and using a low supply voltage to reduce power consumption. The output of the differential amplifier 104 is provided to a subsequent circuit (e.g., Figure 2 the optical modulator 30 shown).

[0097] Figure 10 The balanced stage (also referred to as a balanced circuit) 106 of the driver 26 is shown. The balanced circuit 106 balances the voltages at the respective nodes of the driver 26 as follows. The balanced circuit 106 includes three operational amplifier-based circuits. The first operational amplifier circuit (referred to as the DAC operational amplifier) 150 is connected to the node N2. The second operational amplifier circuit 152 is connected to the node N3. The third operational amplifier circuit (referred to as the output common mode or output CM operational amplifier) 154 is connected to the node N4. In addition to the above high-speed circuit configuration, the three operational amplifier circuits 150, 152, 154 provide a low-speed circuit configuration to ensure the linear operation of the driver 26 as follows.

[0098] In the first operational amplifier circuit 150, a power supply voltage V DACS is generated from the power supply Vs using a feedback loop including the DAC operational amplifier 150 and provided to the DAC 24 and the IV converter 100. The reference voltage V ref，DACS from the node N2 and the voltage V SFout-cm(The common-mode output voltage of the source follower of the preamplifier 102) is input to the DAC operational amplifier 150. The output of the DAC operational amplifier 150 is coupled to the power supply Vs (e.g., via a switch (not shown)). The DAC operational amplifier 150 generates a power supply voltage V DACS , which is supplied to the DAC 24 and the IV converter 100 (as Figure 7 shown). The output-to-input feedback loop of the DAC operational amplifier 150 ensures that the voltage V SFout-cm from node N2 does not vary significantly due to PVT variations and does not bias the switches SW2 and SW4 of the differential amplifier 104 outside the linear operating region. Thus, the DAC operational amplifier 150 regulates the power supply voltage V DACS at node N2.

[0099] The second operational amplifier circuit 152 includes an operational amplifier called the common-mode feedback (CMFB) operational amplifier 160 and a sensing circuit 162, which forms a CMFB feedback loop at the output of the differential amplifier 104. The sensing circuit 162 senses the outputs V OUTN and V OUTP of the differential amplifier 104. The sensing circuit 162 generates a common-mode (CM) output signal V out-cm-sense , which is fed to one input of the CMFB operational amplifier 160. The reference voltage V ref，cmfb for the common-mode feedback is fed to the other input of the CMFB operational amplifier 160. Based on the inputs, the CMFB operational amplifier 160 generates a feedback signal input to node N3.

[0100] The CMFB loop at the output of the differential amplifier 104 ensures that the DC bias current of the NMOS switch (SW2) is equal to the DC bias current of the PMOS device (SW1) set by the bias circuit 112 of the PMOS switches SW1 and SW3 and any DC current flowing through the termination resistor Rt. The CMFB loop (i.e., the feedback signal input to node N3) controls the bias circuit 110 for biasing the NMOS switches SW2 and SW4 in the deep triode region, with a minimum voltage drop across the NMOS switches, which allows for low-voltage operation for low power consumption.

[0101] In the third operational amplifier circuit 154, the so-called output common-mode reference voltage V ref，out-cmThe reference voltage is input to one input of the output CM operational amplifier 154. The other input of the output CM operational amplifier 154 is connected to the output of the output CM operational amplifier 154, and the output of the output CM operational amplifier 154 is connected to node N4. The output CM operational amplifier 154 controls the low-frequency common-mode return loss of the driver 26 to mitigate the common-mode reflections from the output of the differential amplifier 104. The output CM operational amplifier 154 also generates a controllable voltage difference across the termination resistor Rt, which is converted into a known DC bias current that can be added to or subtracted from the current flowing through the PMOS switches of the NMOS switches SW2 and SW4. The added or subtracted current balances the current ratio between the top PMOS switches and the bottom NMOS switches.

[0102] Thus, in the balancing circuit 106, the first operational amplifier circuit 150 is used to minimize the DC voltage variations at the output of the preamplifier 102 (node N2) and generate the conductive DC voltages required for the NMOS devices (SW2, SW4) of the differential amplifier 104. By adjusting the voltage at node N2, the first operational amplifier circuit 150 improves the linear characteristics of the driver 26. The second operational amplifier circuit 152 is used to minimize the DC voltage variations at node N3 and at the output of the differential amplifier 104 and generate the conductive DC voltages required for the NMOS and PMOS devices (SW1 to SW6) of the differential amplifier 104. By adjusting the voltage at node N3, the second operational amplifier circuit 152 allows the use of a low supply voltage Vs, which reduces the power dissipation. The third operational amplifier circuit 154 is connected to node N4 in the differential amplifier 104 and is used to improve the common-mode return loss and generate a current offset between the bottom NMOS and top PMOS branches of the differential amplifier 104. The voltage regulation at node N4 performed by the third operational amplifier circuit 154 indirectly improves the linear characteristics of the driver 26 by balancing the current ratio between the top PMOS switches and the bottom NMOS switches as described above.

[0103] Due to the above functions provided by the three operational amplifier circuits 150, 152, 154, the driver 26 operates linearly at the output data rate of the DAC (i.e., without degrading the linear characteristics provided by the DAC 24), while operating at a low supply voltage Vs, which maintains low power consumption. As described above, the output swing of the driver 26 is controlled by controlling the bias voltage VB of the DAC 24. As Figure 5CAs shown and described above, the output swing of driver 26 varies linearly with the bias voltage VB of DAC 24. Thus, the optical transmitter 12 can transmit data at a higher data rate without replicating the hardware (without replicating serializer 22 and DAC 24), which saves cost and reduces the power consumption of the optical transmitter 12.

[0104] The foregoing description is merely illustrative in nature and is not intended to limit the present disclosure, its application, or uses. The broad teachings of the present disclosure can be implemented in a variety of forms. Thus, while the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited since other modifications will become apparent upon study of the drawings, the specification, and the appended claims. Some or all of the blocks shown in the figures include circuitry such as digital circuits, analog circuits, one or more processor circuits, and, where applicable, memory circuits that store code (instructions) executable by one or more processor circuits to provide the recited functionality.

Claims

1. An optical transmitter, comprising: A digital-to-analog converter DAC, comprising a switch configured to convert digital data into analog data, which is modulated into an optical signal for transmission over an optical fiber; a timing circuit configured to generate a timing signal to control the switch of the DAC; as well as A circuit arrangement is configured to control an output data rate of the DAC by biasing the switch based on a logical combination of the digital data and the timing signal.

2. The optical transmitter of claim 1 , wherein the DAC outputs the analog data at the output data rate that is greater than a data rate of the digital data by biasing the switches of the DAC based on the logical combination of the digital data and the timing signal.

3. The optical transmitter of claim 1, wherein by biasing the switches of the DAC based on a logical combination of the digital data and the timing signal, the DAC outputs a linear current signal regardless of the output data rate of the DAC. 4 . The optical transmitter of claim 1 , wherein the timing circuit is configured to generate a timing signal having a phase difference, and adjust the phase difference to control the output data rate of the DAC.

5. The optical transmitter of claim 4, wherein the DAC outputs the analog data at an output data rate greater than a data rate of the digital data by adjusting the phase difference of the timing signal regardless of a pulse width of the digital data and a pulse width of the timing signal.

6. The optical transmitter of claim 1, wherein: The switch includes a first switch connected in series with a second switch; and The circuit device includes a combinational logic circuit configured to receive the digital data and the timing signals, output a logical combination of the digital data and the timing signals to control the first switch, and control the second switch by a first timing signal among the timing signals.

7. The optical transmitter of claim 6, wherein the digital data powers the combinatorial logic circuit.

8. The optical transmitter of claim 6, wherein the switch further comprises a third switch and a fourth switch, and wherein: The third switch is connected to the first switch at a node and is biased to output a current signal including the analog data; and The fourth switch is connected to the node, and when the first switch and the second switch are turned off, the fourth switch is biased using a second timing signal of the timing signals to pull up a voltage at the node. 9 . The optical transmitter of claim 8 , further comprising a bias control circuit configured to control a bias of the third switch to control an output swing of the DAC.

10. An optical transmitter, comprising: a plurality of digital-to-analog converters DAC configured to receive digital data at a first data rate and output current at a second data rate greater than the first data rate; as well as A driver is configured to receive a combined current including the currents output by the DACs and generate an output signal proportional to the combined current.

11. The optical transmitter according to claim 10, further comprising: a timing circuit configured to generate a timing signal to control the DAC; as well as A circuit arrangement is configured to control the second data rate by biasing the DAC based on a logical combination of the digital data and the timing signal. 12 . The optical transmitter of claim 11 , wherein the timing circuit is configured to generate the timing signals with a phase difference, and adjust the phase difference to control the second data rate.

13. The optical transmitter of claim 10, further comprising a bias control circuit configured to control a bias of the DAC, wherein an output swing of the driver varies linearly with the bias of the DAC.

14. The optical transmitter of claim 10, wherein: The driver includes a current-to-voltage converter configured to convert the combined current into a voltage signal and compensate for a capacitive load from the DAC; a preamplifier configured to amplify the voltage signal and reduce an output impedance of the preamplifier; an amplifier configured to amplify an output of the preamplifier; as well as A balancing circuit is configured to balance voltages at a plurality of nodes in the amplifier using a combination of a feedback voltage and a reference voltage to maintain linearity of the output of the amplifier and reduce power consumption of the driver. 15 . The optical transmitter of claim 14 , wherein the current-to-voltage converter comprises a T-coil having a center tap, the T-coil configured to receive the combined current and compensate for the capacitive load from the DAC.

16. The optical transmitter of claim 14, wherein the preamplifier comprises a source follower configured to amplify the voltage signal, and comprises an LC circuit forming a negative feedback loop configured to reduce the output impedance of the preamplifier.

17. The optical transmitter of claim 14, wherein the amplifier comprises a cascode switch configured to reduce capacitive loading on the preamplifier.

18. An optical transmitter according to claim 14, wherein the amplifier is configured to generate differential outputs via corresponding terminal resistors, and the amplifier includes a cascode switch, which is configured to maintain the output impedance of the amplifier defined by the terminal resistor to reduce signal reflections in the differential outputs of the amplifier.

19. The optical transmitter of claim 14, wherein the amplifier is configured to generate a differential output through a first set of switches arranged in a first branch and a second set of switches arranged in a second branch, and comprises: a first node N2 defined by the top switch and the bottom switch in the first branch and the second branch and configured to receive the output of the preamplifier; a second node N3 defined by the bottom switches in the first branch and the second branch and configured to bias the bottom switches; two terminal resistors, connected to each other at a third node N4 and to the differential output, respectively; as well as A cascode switch is connected between the top and bottom switches in the first and second branches and is biased to reduce capacitive loading on the preamplifier and maintain the output impedance of the amplifier defined by the terminating resistor.

20. The optical transmitter of claim 19, wherein in order to maintain linearity of the output of the amplifier and reduce power consumption of the driver, the balancing circuit comprises: a first circuit configured to generate a supply voltage provided to the DAC and the current-to-voltage converter, and to adjust the supply voltage at the first node N2 to keep the bottom switches of the first branch and the second branch in a linear operating region; a second circuit configured to sense the common-mode output voltage of the amplifier and generate a feedback signal input to the second node N3, the feedback signal configured to control the bias of the bottom switches in the first branch and the second branch so that the bias current of the bottom switches is equal to the bias current of the cascode switch; as well as A third circuit is coupled to the third node N4 and is configured to control a low frequency common mode return loss of the driver to mitigate common mode reflections from the differential output and generate a controllable voltage difference across the terminal resistor, the controllable voltage difference providing a bias current to add to or subtract from a current of the cascode switch flowing through the bottom switch.

21. The optical transmitter of claim 14, wherein the amplifier is configured to generate differential outputs via corresponding T-coils, the T-coils configured to isolate the differential outputs from an external electrostatic discharge (ESD) protection device and reduce capacitive loading on the differential outputs from the ESD device.

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