A high-sensitivity pixel circuit and an image sensor

Abstract

The present application discloses a high-sensitivity pixel circuit and an image sensor, relating to the technical field of electronic circuits, and being used for reducing the duration required for the pixel circuit to complete the exposure of a frame of image. The high-sensitivity pixel circuit includes: a bipolar transistor, a reset circuit, a voltage boosting circuit, a feedback circuit, a photosensitive circuit, and a shutter circuit; wherein, the collector of the bipolar transistor is coupled to the ground terminal; the reset circuit is coupled to the emitter of the bipolar transistor and is configured to raise the base voltage of the bipolar transistor to a first voltage value by adjusting the voltage of the emitter; the voltage boosting circuit is coupled to the base and is configured to output a first base current to the base to raise the base voltage from the first voltage value to a second voltage value; the first end of the feedback circuit is coupled to the base, and the second end of the feedback circuit is coupled to the emitter; the first end of the photosensitive circuit is coupled to the base, and the second end of the photosensitive circuit is coupled to the ground terminal; the shutter circuit is coupled to the fourth end of the feedback circuit.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to a high-sensitivity pixel circuit and an image sensor. Background Art

[0002] An image sensor is composed of multiple pixel circuits. Each pixel circuit converts an incident optical signal into an electrical signal through photoelectric conversion to generate image information.

[0003] However, the pixel circuits in related technologies require a long time to complete photoelectric conversion, resulting in difficulty in achieving high-speed image acquisition and limiting the improvement of the frame rate of the image sensor. Summary of the Invention

[0004] This application provides a high-sensitivity pixel circuit and an image sensor, which are used to reduce the duration required for the pixel circuit to complete the exposure of one frame of an image and improve the frame rate of the image sensor.

[0005] To achieve the above object, this application adopts the following technical solutions:

[0006] In a first aspect, a high-sensitivity pixel circuit is provided. The high-sensitivity pixel circuit includes: a bipolar transistor, a reset circuit, a voltage boosting circuit, a feedback circuit, a photosensitive circuit, and a shutter circuit. Among them, the collector of the bipolar transistor is coupled to the ground terminal. The reset circuit is coupled to the emitter of the bipolar transistor and is configured to, according to the received first reset control signal, adjust the voltage of the emitter to raise the base voltage of the bipolar transistor to a first voltage value. The voltage boosting circuit is coupled to the base and is configured to, after the base voltage is raised to the first voltage value, output a first base current to the base according to the received first voltage boosting control signal, and raise the base voltage from the first voltage value to a second voltage value, where the second voltage value is greater than the first voltage value. The first end of the feedback circuit is coupled to the base, and the second end of the feedback circuit is coupled to the emitter and is configured to: adjust the voltage of the emitter according to the base voltage so that the voltage difference between the base and the emitter remains within a preset voltage range; the reset circuit is coupled to the emitter through the third end of the feedback circuit. The first end of the photosensitive circuit is coupled to the base, and the second end of the photosensitive circuit is coupled to the ground terminal and is configured to: after the base voltage is raised to the second voltage value, generate a second base current according to the intensity of the received light, and stabilize the base voltage from the second voltage value to a third voltage value through the feedback circuit. The shutter circuit is coupled to the fourth end of the feedback circuit and is configured to: control the on / off of the path between the second end and the third end of the feedback circuit according to the received shutter control signal.

[0007] In this embodiment, on the one hand, the pixel circuit significantly improves the exposure performance by adopting a bipolar transistor combined with a two-stage voltage regulation mechanism. Among them, the reset circuit first resets the base voltage to the first voltage value to complete the initial setting, and then the voltage boosting circuit injects a base current to further boost the voltage to a higher second voltage value. This phased regulation design effectively shortens the exposure time by optimizing the voltage establishment process. On the other hand, the pixel circuit realizes precise control of the photoelectric conversion process through the collaborative design of the feedback mechanism and the photosensitive circuit, significantly improving the imaging performance. The feedback circuit ensures that the base-emitter voltage difference is always stable within the preset range by continuously monitoring the base voltage and dynamically adjusting the voltage of the emitter in real time. The stable maintenance of the voltage difference enables the bipolar transistor to always operate in the optimal amplification region, significantly improving the linearity and consistency of signal transmission. In addition, the photosensitive circuit generates a second base current through the photoelectric effect based on the second voltage value, and cooperates with the dynamic adjustment of the feedback circuit to accurately stabilize the base voltage to the third voltage value. This closed-loop control mechanism effectively suppresses the signal disturbance caused by environmental light fluctuations and greatly improves the signal-to-noise ratio of the image. At the same time, the pixel circuit realizes seamless connection between the reset operation and the feedback regulation by coupling the reset circuit to the third terminal of the feedback circuit, ensuring both rapid establishment in the initial stage of exposure and voltage stability during the exposure process, making the entire system have both fast response ability and excellent anti-interference performance. On the other hand, the coordinated operation of the shutter circuit and the feedback system ensures that the photoelectric conversion signal is locked at the optimal moment, avoiding both signal overshoot and insufficient adjustment, and significantly improving the accuracy of the image signal.

[0008] In a possible implementation, the high-sensitivity pixel circuit further includes: a clearing circuit, coupled between the base and the ground terminal, and configured to: before the reset circuit raises the base voltage to the first voltage value, control the conduction between the base and the ground terminal according to the received clearing control signal, and control the open circuit between the base and the ground terminal before the voltage boosting circuit receives the first voltage boosting control signal.

[0009] In this embodiment, before the reset stage, the clearing circuit first conducts the path between the base and the ground terminal according to the clearing control signal, ensuring that the base voltage is completely discharged to the initial state, providing a unified starting state for subsequent operations, providing a definite initial condition for the reset circuit, ensuring the accuracy of the establishment of the first voltage value, and improving the accuracy of exposure control.

[0010] In a possible implementation, the clearing circuit includes: a first N-type metal-oxide-semiconductor transistor, the drain of the first N-type metal-oxide-semiconductor transistor is coupled to the base, the source of the first N-type metal-oxide-semiconductor transistor is coupled to the ground terminal, and the gate of the first N-type metal-oxide-semiconductor transistor is used to receive the clearing control signal.

[0011] In a possible implementation, the high-sensitivity pixel circuit further includes: a load capacitor, where a first end of the load capacitor is coupled to a third end of the feedback circuit, and a second end of the load capacitor is coupled to a ground terminal.

[0012] In a possible implementation, the reset circuit is further configured to: reset the load capacitor according to a received first reset control signal.

[0013] In this embodiment, through the active reset of the load capacitor by the reset circuit, it is ensured that the capacitor voltage is in an accurate initial state at the start of each exposure cycle, completely eliminating the residual influence of the previous frame signal and significantly reducing the image smear phenomenon; in addition, by using a single reset control signal to manage both the base voltage reset and the load capacitor reset simultaneously, the circuit structure is kept simple while improving the performance.

[0014] In a possible implementation, when the base voltage stabilizes at a third voltage value, the reset circuit receives a second reset control signal, and the second reset control signal is used to control the reset circuit to stop resetting the load capacitor. The collector discharges to the load capacitor until the shutter circuit disconnects the second end of the feedback circuit from the third end of the feedback circuit.

[0015] In this embodiment, after the base voltage stabilizes at the third voltage value, the second reset control signal is used to terminate the reset of the load capacitor by the reset circuit. The precise timing control ensures that the photoelectric conversion signal is locked in the best stable state, avoiding signal distortion caused by over-regulation; in addition, when the path between the second end and the third end of the feedback circuit is open, the system automatically enters a high-impedance state, effectively isolating the interference of the subsequent readout circuit to the sensitive photoelectric conversion node.

[0016] In a possible implementation, the shutter circuit includes: a second N-type metal-oxide semiconductor transistor, where a drain of the second N-type metal-oxide semiconductor transistor is coupled to a ground terminal, a source of the second N-type metal-oxide semiconductor transistor is coupled to a fourth end of the feedback circuit, and a gate of the second N-type metal-oxide semiconductor transistor is used to receive a shutter control signal.

[0017] In a possible implementation, light is generated by a light source after the base voltage is raised to a second voltage value, and the light stops after the second end of the feedback circuit is disconnected from the third end of the feedback circuit.

[0018] In this embodiment, by strictly controlling the effective light exposure time within the active interval of the feedback loop, the power consumption waste caused by invalid exposure is avoided.

[0019] In a possible implementation, after disconnecting the second end and the third end of the feedback circuit, the voltage boosting circuit receives a second voltage boosting control signal, which is used to control the voltage boosting circuit to stop generating the first base current.

[0020] In this embodiment, the pixel circuit realizes multi-level precise regulation of the optoelectronic conversion process by introducing a two-stage voltage boosting control mechanism. After the feedback loop is disconnected, the voltage boosting circuit is intelligently terminated through the second voltage boosting control signal. This timing control, firstly, effectively avoids signal distortion caused by overvoltage boosting by dynamically turning off the base current injection, ensuring that the base voltage is stable at the optimal operating point; secondly, this design forms a collaborative control with the feedback loop and exits in time after completing the voltage boosting mission, significantly reducing the static power consumption of the system.

[0021] In a possible implementation, the feedback circuit includes: a first P-type metal oxide semiconductor transistor, a third N-type metal oxide semiconductor transistor, and a fourth N-type metal oxide semiconductor transistor. The source of the first P-type metal oxide semiconductor transistor is coupled to the power supply terminal, the drain of the first P-type metal oxide semiconductor transistor serves as the fourth end of the feedback circuit, and the gate of the first P-type metal oxide semiconductor transistor is used to receive a bias voltage signal. The drain of the third N-type metal oxide semiconductor transistor is coupled to the drain of the first P-type metal oxide semiconductor transistor, the source of the third N-type metal oxide semiconductor transistor is coupled to the ground terminal, and the gate of the third N-type metal oxide semiconductor transistor serves as the first end of the feedback circuit. The drain of the fourth N-type metal oxide semiconductor transistor serves as the second end of the feedback circuit, the source of the fourth N-type metal oxide semiconductor transistor serves as the third end of the feedback circuit, and the gate of the fourth N-type metal oxide semiconductor transistor is coupled to the drain of the first P-type metal oxide semiconductor transistor.

[0022] In a possible implementation, the reset circuit includes: a second P-type metal oxide semiconductor transistor. The source of the second P-type metal oxide semiconductor transistor is coupled to the power supply terminal, the drain of the second P-type metal oxide semiconductor transistor is coupled to the third end of the feedback circuit, and the gate of the second P-type metal oxide semiconductor transistor is used to receive a reset control signal. Among them, the reset control signal includes a first reset control signal and a second reset control signal. The first reset control signal is used to control the reset circuit to adjust the voltage of the emitter, and the second reset control signal is used to control the reset circuit to stop resetting the load capacitor.

[0023] In a possible implementation, the boost circuit includes: a coupling capacitor, the first end of the coupling capacitor is coupled to the base, and the second end of the coupling capacitor is used to receive a boost control signal. Among them, the boost control signal includes a first boost control signal and a second boost control signal. The first boost control signal is used to control the boost circuit to output a first base current to the base, and the second boost control signal is used to control the boost circuit to stop generating the first base current.

[0024] In a second aspect, an image sensor is provided, and the image sensor includes: a light source;

[0025] a pixel array including a plurality of high-sensitivity pixel circuits as in the first aspect.

[0026] The beneficial effect of this application is that this application provides a high-sensitivity pixel circuit. The reset circuit is coupled to the emitter of the bipolar transistor. By adjusting the voltage of the emitter of the bipolar transistor, the base voltage of the bipolar transistor can be boosted to a first voltage value. And, by coupling the boost circuit to the base of the bipolar transistor, after the base voltage is boosted to the first voltage value, a first base current can be further output from the boost circuit to the base. In this way, combining the first base current output by the boost circuit and the reset circuit adjusting the voltage of the emitter of the bipolar transistor, the base voltage can be rapidly boosted from the first voltage value to a second voltage value. Thus, based on the combination of the reset circuit and the boost circuit, the steady state of the bipolar transistor can be established quickly in a relatively short time, so as to reduce the time required for the pixel circuit to complete the exposure of one frame of image and improve the frame rate of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of a pixel circuit provided by an embodiment of this application Figure 1 ;

[0028] Figure 2 Schematic diagram of a pixel circuit provided by an embodiment of this application Figure 2 ;

[0029] Figure 3 Schematic diagram of the working timing of a pixel circuit provided by an embodiment of this application;

[0030] Figure 4 Schematic diagram of a high-sensitivity pixel circuit provided by an embodiment of this application;

[0031] Figure 5 Schematic diagram of the working timing of a high-sensitivity pixel circuit provided by an embodiment of this application.

[0032] Reference numerals:

[0033] In the figure, PD1 is the first photosensitive diode, C1 is the parasitic capacitance, PD2 is the second photosensitive diode, 201 is the triode, C2 is the load capacitance, MN1 is the first N-type metal-oxide-semiconductor transistor, MN2 is the second N-type metal-oxide-semiconductor transistor, MN3 is the third N-type metal-oxide-semiconductor transistor, MN4 is the fourth N-type metal-oxide-semiconductor transistor, MN5 is the fifth N-type metal-oxide-semiconductor transistor, MN6 is the sixth N-type metal-oxide-semiconductor transistor, MN7 is the seventh N-type metal-oxide-semiconductor transistor, MN8 is the eighth N-type metal-oxide-semiconductor transistor, MN9 is the ninth N-type metal-oxide-semiconductor transistor, MN10 is the tenth N-type metal-oxide-semiconductor transistor, MP1 is the first P-type metal-oxide-semiconductor transistor, MP2 is the second P-type metal-oxide-semiconductor transistor, MP3 is the third P-type metal-oxide-semiconductor transistor, MP4 is the fourth P-type metal-oxide-semiconductor transistor, MP5 is the fifth P-type metal-oxide-semiconductor transistor, MP6 is the sixth P-type metal-oxide-semiconductor transistor, 401 is the bipolar transistor, 402 is the reset circuit, 403 is the voltage boosting circuit, 404 is the clearing circuit, 405 is the feedback circuit, 406 is the photosensitive circuit, 407 is the shutter circuit. Detailed implementation manners

[0034] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0035] In the description of the present application, unless otherwise specified, " / " means "or". For example, A / B may represent A or B. Herein, "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, "at least one" and "multiple" refer to two or more. The terms such as "first" and "second" do not limit the quantity and execution order, and the terms such as "first" and "second" do not necessarily limit to be different.

[0036] Image sensors are widely used in fields such as photography, video surveillance, medical imaging, industrial inspection, etc. Image sensors are composed of multiple pixel circuits, such as including but not limited to 3T pixel circuits and 4T pixel circuits, etc.

[0037] Such as Figure 1As shown, in a 3T pixel circuit, the positive electrode of the first photodiode (PD) PD1 is coupled to the ground terminal, the negative electrode of the first photodiode PD1 is coupled to the first terminal of the parasitic capacitor C1, and the second terminal of the parasitic capacitor C1 is coupled to the ground terminal. The base of the first photodiode PD1 is also coupled to the drain of the fifth N-type metal oxide semiconductor transistor MN5, and the base of the first photodiode PD1 is also coupled to the gate of the sixth N-type metal oxide semiconductor transistor MN6. Moreover, the first terminal of the parasitic capacitor C1 is also coupled to the drain of the fifth N-type metal oxide semiconductor transistor MN5, and the first terminal of the parasitic capacitor C1 is also coupled to the gate of the sixth N-type metal oxide semiconductor transistor MN6. The gate of the fifth N-type metal oxide semiconductor transistor MN5 is used to receive a reset signal, and the source of the fifth N-type metal oxide semiconductor transistor MN5 is coupled to the power supply terminal. The source of the sixth N-type metal oxide semiconductor transistor MN6 is coupled to the power supply terminal, and the drain of the sixth N-type metal oxide semiconductor transistor MN6 is coupled to the source of the seventh N-type metal oxide semiconductor transistor MN7. The gate of the seventh N-type metal oxide semiconductor transistor MN7 is used to receive a row selection signal, and the drain of the seventh N-type metal oxide semiconductor transistor MN7 is the output terminal.

[0038] In the 3T pixel circuit, due to the pixel photosensitive current output by the first photodiode PD1, it is necessary to discharge the parasitic capacitor C1 in the pixel photosensitive area to obtain an exposure signal. However, the capacitance value of the parasitic capacitor C1 is affected by the size of the pixel photosensitive area. When the capacitance value of the parasitic capacitor C1 is large, it will cause the 3T pixel circuit to require a long exposure time. Therefore, the current pixel circuit takes a long time to complete the exposure of one frame of the image, resulting in a low frame rate of the image sensor.

[0039] To solve the problem of too long exposure time in the 3T pixel circuit, the present disclosure provides an implementation manner. A PNP (Positive-Negative-Positive) type triode can be added to the center of the photodiode to obtain a PNP pixel circuit. The photosensitive current is amplified through the current amplification ability of the triode, thereby shortening the required exposure time.

[0040] As Figure 2As shown, the positive electrode of the second photosensitive diode PD2 is coupled to the ground terminal, the negative electrode of the second photosensitive diode PD2 is coupled to the base of the triode 201, the collector of the triode 201 is coupled to the ground terminal, the emitter of the triode 201 is coupled to the drain of the fifth P-type metal-oxide semiconductor transistor MP5, and the emitter of the triode 201 is coupled to the drain of the eighth N-type metal-oxide semiconductor transistor MN8. The gate of the fifth P-type metal-oxide semiconductor transistor MP5 is coupled to the gate of the eighth N-type metal-oxide semiconductor transistor MN8 to form a shutter, and the source of the eighth N-type metal-oxide semiconductor transistor MN8 is coupled to the power supply terminal. The source of the fifth P-type metal-oxide semiconductor transistor MP5 is coupled to the drain of the sixth P-type metal-oxide semiconductor transistor MP6. The gate of the sixth P-type metal-oxide semiconductor transistor MP6 is used to receive a reset signal, and the source of the sixth P-type metal-oxide semiconductor transistor MP6 is coupled to the power supply terminal. The first terminal of the load capacitor C2 is coupled to the source of the fifth P-type metal-oxide semiconductor transistor MP5 and the drain of the sixth P-type metal-oxide semiconductor transistor MP6, and the second terminal of the load capacitor C2 is coupled to the ground terminal. The first terminal of the load capacitor C2 is also coupled to the gate of the ninth N-type metal-oxide semiconductor transistor MN9. The source of the ninth N-type metal-oxide semiconductor transistor MN9 is coupled to the power supply terminal, and the drain of the ninth N-type metal-oxide semiconductor transistor MN9 is coupled to the source of the tenth N-type metal-oxide semiconductor transistor MN10. The gate of the tenth N-type metal-oxide semiconductor transistor MN10 is used to receive a row selection signal, and the drain of the tenth N-type metal-oxide semiconductor transistor MN10 is the output terminal.

[0041] Compared with the 3T pixel circuit, this PNP pixel circuit needs to add N-type metal-oxide semiconductor transistors, P-type metal-oxide semiconductor transistors and load capacitors. A shutter switch is jointly formed by the N-type metal-oxide semiconductor transistor and the P-type metal-oxide semiconductor transistor. When the shutter is not opened, a current is provided to the collector of the triode through the N-type metal-oxide semiconductor transistor to ensure that the triode establishes a steady state under the photosensitive current. After the shutter is opened, the N-type metal-oxide semiconductor transistor is controlled to turn off and the P-type metal-oxide semiconductor transistor is controlled to turn on, so that the collector of the triode discharges the load capacitor through the P-type metal-oxide semiconductor transistor. In this way, the PNP pixel circuit can adjust the discharge of the parasitic capacitor by the photosensitive current in the original 3T pixel circuit to the discharge of the load capacitor after the photosensitive current is amplified by the triode.

[0042] Combined with Figure 2 the PNP pixel circuit shown, as Figure 3As shown, at the first moment t1 before the second photosensitive diode PD2 is exposed (t1 is the moment when the reset circuit starts to conduct), by controlling the reset circuit (the sixth P-type metal oxide semiconductor transistor MP6) to conduct for a period of time through the reset signal, the reset of the load capacitor C2 can be completed. Then at the second moment t2 (t2 is the moment when the second photosensitive diode PD2 starts to light up), the second photosensitive diode PD2 is lit to make the triode 201 start to work, and the collector current of the triode 201 is established to the current state after the photosensitive current is amplified. Then at the third moment t3 (t3 is the moment when the conduction between the collector of the triode 201 and the load capacitor C2 starts), after the collector current of the triode 201 is stable, by pulling down the shutter signal, the conduction between the collector of the triode 201 and the load capacitor C2 is controlled to start discharging the load capacitor C2, so that the voltage of the load capacitor C2 drops from the reset voltage. When the exposure reaches an appropriate value at the fourth moment t4 (t4 is the moment when the conduction between the collector of the triode 201 and the load capacitor C2 starts to be disconnected), by pulling up the shutter signal, the conduction between the collector of the triode 201 and the load capacitor C2 is controlled to be disconnected, and the discharge of the load capacitor C2 ends.

[0043] However, since the photosensitive current is generally in the order of 1 pA to 10 nA, it takes a relatively long time to complete the steady-state establishment of the triode only relying on the photosensitive current. Therefore, although the PNP pixel circuit can achieve a very short shutter time, due to the long time for establishing the steady state, it still takes a long time to complete the exposure of one frame of the image.

[0044] Thus, although the PNP pixel circuit can achieve a shorter exposure time based on the current amplification ability of the triode. However, due to the low order of magnitude of the photosensitive current (generally 1 pA to 10 nA), it takes a long time to complete the steady-state establishment of the triode only relying on the photosensitive current. Thus, although the PNP pixel circuit can achieve a shorter exposure time, due to the long time for the triode to establish the steady state, the exposure of one frame of the image still takes a long time.

[0045] Based on this, an embodiment of the present application provides a high-sensitivity pixel circuit. By coupling a reset circuit to the emitter of a bipolar transistor, the base voltage of the bipolar transistor can be raised to a first voltage value by adjusting the voltage of the emitter of the bipolar transistor. Moreover, by coupling a voltage boosting circuit to the base of the bipolar transistor, after the base voltage is raised to the first voltage value, a first base current can be further output to the base through the voltage boosting circuit. In this way, by combining the first base current output by the voltage boosting circuit and the reset circuit adjusting the voltage of the emitter of the bipolar transistor, the base voltage can be rapidly raised from the first voltage value to a second voltage value. Thus, based on the combination of the reset circuit and the voltage boosting circuit, the steady state of the bipolar transistor can be established rapidly within a short time, so as to reduce the duration required for the pixel circuit to complete the exposure of one frame of an image and improve the frame rate of the image sensor.

[0046] The high-sensitivity pixel circuit provided by an embodiment of the present application is introduced below with reference to the accompanying drawings. The high-sensitivity pixel circuit provided by an embodiment of the present application is applicable to a pixel array in an image sensor and can be used to extract image data. In an embodiment of the present application, the image sensor can be applicable to a photographic device, a video surveillance device, a medical imaging device, an industrial inspection device, an optical mouse, etc., and the present application does not make specific limitations thereto.

[0047] As Figure 4 shown, it is a schematic diagram of a high-sensitivity pixel circuit provided by an embodiment of the present application. The high-sensitivity pixel circuit includes: a bipolar transistor 401, a reset circuit 402, a voltage boosting circuit 403, a clearing circuit 404, a feedback circuit 405, a photosensitive circuit 406, a load capacitor C2, and a shutter circuit 407. The bipolar transistor 401 is a PNP bipolar transistor.

[0048] Optionally, the high-sensitivity pixel circuit may further include: a third P-type metal oxide semiconductor transistor (MP3) and a fourth P-type metal oxide semiconductor transistor (MP4). The source of the third P-type metal oxide semiconductor transistor is coupled to a power supply terminal, the gate of the third P-type metal oxide semiconductor transistor is coupled to the first end of the load capacitor C2, the drain of the third P-type metal oxide semiconductor transistor is coupled to the source of the fourth P-type metal oxide semiconductor transistor, the drain of the fourth P-type metal oxide semiconductor transistor is an output terminal, and the gate of the fourth P-type metal oxide semiconductor transistor is used to receive a row selection signal.

[0049] In an embodiment of the present application, the collector of the bipolar transistor 401 is coupled to a ground terminal.

[0050] In an embodiment of the present application, the feedback circuit 405 includes: a first P-type metal-oxide-semiconductor transistor MP1, a third N-type metal-oxide-semiconductor transistor MN3, and a fourth N-type metal-oxide-semiconductor transistor MN4. The feedback circuit 405 and the bipolar transistor 401 can form a feedback loop.

[0051] It should be noted that the feedback loop is used to stabilize the operating state of the bipolar transistor 401 and ensure that the current gain of the bipolar transistor 401 is consistent during exposure.

[0052] In an embodiment of the present application, the source of the first P-type metal-oxide-semiconductor transistor MP1 is coupled to the power supply terminal, the drain of the first P-type metal-oxide-semiconductor transistor MP1 serves as the fourth terminal of the feedback circuit 405, and the gate of the first P-type metal-oxide-semiconductor transistor MP1 is used to receive a bias voltage signal.

[0053] It should be noted that the circuit formed by the first P-type metal-oxide-semiconductor transistor MP1 can be referred to as a bias circuit.

[0054] In an embodiment of the present application, the drain of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the drain of the first P-type metal-oxide-semiconductor transistor MP1, the source of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the ground terminal, and the gate of the third N-type metal-oxide-semiconductor transistor MN3 serves as the first terminal of the feedback circuit 405.

[0055] In an embodiment of the present application, the drain of the fourth N-type metal-oxide-semiconductor transistor MN4 serves as the second terminal of the feedback circuit 405, the source of the fourth N-type metal-oxide-semiconductor transistor MN4 serves as the third terminal of the feedback circuit 405, and the gate of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the drain of the first P-type metal-oxide-semiconductor transistor MP1 (and the drain of the third N-type metal-oxide-semiconductor transistor MN3).

[0056] In an embodiment of the present application, the first terminal of the feedback circuit 405 (i.e., the gate of the third N-type metal-oxide-semiconductor transistor MN3) is coupled to the base of the bipolar transistor 401, and the second terminal of the feedback circuit 405 (i.e., the drain of the fourth N-type metal-oxide-semiconductor transistor MN4) is coupled to the emitter of the bipolar transistor 401.

[0057] In an embodiment of the present application, the feedback circuit 405 is configured to: adjust the voltage of the emitter of the bipolar transistor 401 according to the base voltage of the bipolar transistor 401, so that the voltage difference between the base and the emitter of the bipolar transistor 401 remains within a preset voltage range.

[0058] In an embodiment of the present application, the reset circuit 402 is coupled to the emitter of the bipolar transistor 401.

[0059] In an embodiment of the present application, the reset circuit 402 is configured to: according to the received first reset control signal, by adjusting the voltage of the emitter of the bipolar transistor 401, raise the base voltage of the bipolar transistor 401 to a first voltage value.

[0060] In an embodiment of the present application, the reset circuit 402 is coupled to the emitter of the bipolar transistor 401 through the third terminal of the coupled feedback circuit 405.

[0061] In an embodiment of the present application, the reset circuit 402 includes: a second P-type metal-oxide-semiconductor transistor MP2, the source of the second P-type metal-oxide-semiconductor transistor MP2 is coupled to the power supply terminal, the drain of the second P-type metal-oxide-semiconductor transistor MP2 is coupled to the third terminal of the feedback circuit 405, and the gate of the second P-type metal-oxide-semiconductor transistor MP2 is used to receive the reset control signal.

[0062] Wherein, the reset control signal includes: a first reset control signal and a second reset control signal, the first reset control signal is used to control the reset circuit 402 to adjust the voltage of the emitter, and the second reset control signal is used to control the reset circuit 402 to stop resetting the load capacitor C2.

[0063] It can be understood that a fourth N-type metal-oxide-semiconductor transistor MN4 is coupled between the reset circuit 402 and the emitter of the bipolar transistor 401. That is, the drain of the second P-type metal-oxide-semiconductor transistor MP2 is coupled to the source of the fourth N-type metal-oxide-semiconductor transistor MN4.

[0064] In an embodiment of the present application, the first end of the load capacitor C2 is coupled to the third terminal of the feedback circuit 405, and the second end of the load capacitor C2 is coupled to the ground terminal.

[0065] That is, the first end of the load capacitor C2 is coupled to the drain of the second P-type metal-oxide-semiconductor transistor MP2, and the first end of the load capacitor C2 is coupled to the source of the fourth N-type metal-oxide-semiconductor transistor MN4.

[0066] In an embodiment of the present application, the reset circuit 402 is further configured to: according to the received first reset control signal, reset the load capacitor C2.

[0067] In this embodiment, through the active reset of the load capacitance by the reset circuit, it is ensured that the capacitance voltage is in an accurate initial state at the beginning of each exposure period, completely eliminating the residual influence of the previous frame signal and significantly reducing the image smear phenomenon. In addition, by using a single reset control signal to manage both the base voltage reset and the load capacitance reset simultaneously, the circuit structure is kept simple while improving the performance.

[0068] In the embodiment of the present application, when the base voltage of the bipolar transistor 401 is stabilized at the third voltage value, the reset circuit 402 receives the second reset control signal, and the second reset control signal is used to control the reset circuit 402 to stop resetting the load capacitance C2.

[0069] In the embodiment of the present application, the collector of the bipolar transistor 401 is also used to discharge the load capacitance C2 until the shutter circuit 407 disconnects the second end of the feedback circuit 405 from the third end of the feedback circuit 405.

[0070] In this embodiment, after the base voltage is stabilized at the third voltage value, the reset of the load capacitance by the reset circuit is terminated by the second reset control signal, and the precise timing control ensures that the optoelectronic conversion signal is locked in the best stable state, avoiding signal distortion caused by over-regulation. In addition, when the path between the second end and the third end of the feedback circuit is open, the system automatically enters a high-impedance state, effectively isolating the interference of the subsequent readout circuit to the sensitive optoelectronic conversion node.

[0071] In the embodiment of the present application, the light is generated by the light source after the base voltage is raised to the second voltage value, and the light is stopped after disconnecting the second end of the feedback circuit 405 from the third end of the feedback circuit 405 (i.e., the fourth N-type metal oxide semiconductor transistor MN4 is in an open state).

[0072] In this embodiment, by strictly controlling the effective light exposure time within the active interval of the feedback loop, the power consumption waste caused by ineffective exposure is avoided.

[0073] In the embodiment of the present application, the photosensitive circuit 406 can be the second photosensitive diode PD2. In practical applications, the photosensitive circuit 406 can be any circuit or component that can convert the light intensity into an electrical signal correspondingly, and no limitation is made here.

[0074] In the embodiment of the present application, the first end of the photosensitive circuit 406 is coupled to the base of the bipolar transistor 401, and the second end of the photosensitive circuit 406 is coupled to the ground terminal.

[0075] In the embodiment of the present application, the photosensitive circuit 406 is configured to: after the base voltage of the bipolar transistor 401 is raised to the second voltage value, generate a second base current according to the intensity of the received light, and stabilize the base voltage from the second voltage value to the third voltage value through the feedback circuit 405.

[0076] In this embodiment, through the collaborative design of the feedback mechanism and the photosensitive circuit in the pixel circuit, precise control of the photoelectric conversion process is achieved, significantly improving the imaging performance. The feedback circuit ensures that the base-emitter voltage difference is always stable within a preset range by continuously monitoring the base voltage and dynamically adjusting the emitter voltage in real time. The stable maintenance of the voltage difference enables the bipolar transistor to always operate in the optimal amplification region, significantly improving the linearity and consistency of signal transmission. In addition, the photosensitive circuit generates a second base current through the photoelectric effect based on the second voltage value, and cooperates with the dynamic regulation of the feedback circuit to precisely stabilize the base voltage to the third voltage value. This closed-loop control mechanism effectively suppresses the signal disturbance caused by environmental light fluctuations and greatly improves the signal-to-noise ratio of the image. At the same time, the pixel circuit realizes the seamless connection between the reset operation and the feedback regulation by coupling the reset circuit to the third terminal of the feedback circuit, ensuring both the rapid establishment in the initial stage of exposure and the voltage stability during the exposure process, making the entire system have both fast response ability and excellent anti-interference performance.

[0077] In the embodiment of the present application, the voltage boosting circuit 403 is coupled to the base of the bipolar transistor 401.

[0078] In the embodiment of the present application, the voltage boosting circuit 403 is configured to: after the base voltage is raised to the first voltage value, output a first base current to the base according to the received first voltage boosting control signal, and raise the base voltage from the first voltage value to the second voltage value, where the second voltage value is greater than the first voltage value.

[0079] In this embodiment, the pixel circuit significantly improves the exposure performance by adopting a bipolar transistor combined with a two-stage voltage regulation mechanism. Among them, the reset circuit first resets the base voltage to the first voltage value to complete the initial setting, and then the voltage boosting circuit injects a base current to further raise the voltage to a higher second voltage value. This phased regulation design effectively shortens the exposure time by optimizing the voltage establishment process.

[0080] In the embodiment of the present application, the voltage boosting circuit 403 includes: a coupling capacitor, the first end of the coupling capacitor is coupled to the base of the bipolar transistor 401, and the second end of the coupling capacitor is used to receive the voltage boosting control signal.

[0081] Among them, the lift-press control signal includes a first lift-press control signal and a second lift-press control signal. The first lift-press control signal is used to control the lift-press circuit 403 to output a first base current to the base of the bipolar transistor 401, and the second lift-press control signal is used to control the lift-press circuit 403 to stop generating the first base current.

[0082] In the embodiment of the present application, after disconnecting the second end and the third end of the feedback circuit 405, the lift-press circuit 403 receives the second lift-press control signal, and the second lift-press control signal is used to control the lift-press circuit 403 to stop generating the first base current.

[0083] In this embodiment, the pixel circuit realizes multi-level precise control of the optoelectronic conversion process by introducing a two-level lift-press control mechanism. After the feedback loop is disconnected, the second lift-press control signal is used to intelligently terminate the operation of the lift-press circuit. This timing control, firstly, effectively avoids signal distortion caused by over-lift by dynamically turning off the base current injection, ensuring that the base voltage is stabilized at the optimal operating point; secondly, this design forms a cooperative control with the feedback loop and exits in time after completing the voltage lift mission, significantly reducing the static power consumption of the system.

[0084] In the embodiment of the present application, the first end of the coupling capacitor is also coupled to the gate of the third N-type metal oxide semiconductor transistor MN3 (i.e., the first end of the feedback circuit 405).

[0085] In the embodiment of the present application, the clearing circuit 404 is coupled between the base of the bipolar transistor 401 and the ground terminal.

[0086] In the embodiment of the present application, the clearing circuit 404 is configured to: before the reset circuit 402 raises the base voltage to the first voltage value, control the conduction between the base and the ground terminal according to the received clearing control signal, and control the open circuit between the base and the ground terminal before the lift-press circuit 403 receives the first lift-press control signal.

[0087] In this embodiment, before the reset stage, the clearing circuit first conducts the path between the base and the ground terminal according to the clearing control signal, ensuring that the base voltage is fully discharged to the initial state, providing a unified starting state for subsequent operations, providing a definite initial condition for the reset circuit, ensuring the accuracy of the establishment of the first voltage value, and improving the accuracy of exposure control.

[0088] In the embodiment of the present application, the clearing circuit 404 includes: a first N-type metal oxide semiconductor transistor MN1. The drain of the first N-type metal oxide semiconductor transistor MN1 is coupled to the base of the bipolar transistor 401, the source of the first N-type metal oxide semiconductor transistor MN1 is coupled to the ground terminal, and the gate of the first N-type metal oxide semiconductor transistor MN1 is used to receive the clearing control signal.

[0089] In an embodiment of the present application, the drain of the first N-type metal oxide semiconductor transistor MN1 is further coupled to the first end of the coupling capacitor, and the drain of the first N-type metal oxide semiconductor transistor MN1 is further coupled to the gate of the third N-type metal oxide semiconductor transistor MN3 (i.e., the first end of the feedback circuit 405).

[0090] In an embodiment of the present application, the shutter circuit 407 is coupled to the fourth end of the feedback circuit 405.

[0091] In an embodiment of the present application, the shutter circuit 407 is configured to: control the on / off of the path between the second end and the third end of the feedback circuit 405 according to the received shutter control signal.

[0092] In this embodiment, the cooperative work of the shutter circuit and the feedback system ensures that the photoelectric conversion signal is locked at the optimal moment, avoiding both signal overshoot and insufficient adjustment, and significantly improving the accuracy of the image signal.

[0093] In an embodiment of the present application, the shutter circuit 407 includes: a second N-type metal oxide semiconductor transistor MN2. The drain of the second N-type metal oxide semiconductor transistor MN2 is coupled to the ground terminal, the source of the second N-type metal oxide semiconductor transistor MN2 is coupled to the fourth end of the feedback circuit 405, and the gate of the second N-type metal oxide semiconductor transistor MN2 is for receiving the shutter control signal.

[0094] That is, the source of the second N-type metal oxide semiconductor transistor MN2 is coupled to the drain of the first P-type metal oxide semiconductor transistor MP1, the source of the second N-type metal oxide semiconductor transistor MN2 is coupled to the drain of the third N-type metal oxide semiconductor transistor MN3, and the source of the second N-type metal oxide semiconductor transistor MN2 is coupled to the gate of the fourth N-type metal oxide semiconductor transistor MN4.

[0095] In an embodiment of the present application, during the establishment of the steady state of the bipolar transistor 401, the second P-type metal oxide semiconductor transistor MP2 remains turned on to provide the collector current of the bipolar transistor 401, ensuring the establishment of the steady state of the bipolar transistor 401 and resetting the load capacitor C2 at the same time.

[0096] Further, after the collector current of the bipolar transistor 401 stabilizes, the second P-type metal oxide semiconductor transistor MP2 is turned off, causing the collector current of the bipolar transistor 401 to start discharging the load capacitor C2. After exposure is completed, the second N-type metal oxide semiconductor transistor MN2 is turned on, thereby turning off the fourth N-type metal oxide semiconductor transistor MN4 and blocking the path between the collector current of the bipolar transistor 401 and the load capacitor C2, ending the shutter operation.

[0097] In the embodiment of the present application, the first N-type metal oxide semiconductor transistor MN1 and the coupling capacitor are used to improve the establishment speed of the steady state of the bipolar transistor 401. After the first N-type metal oxide semiconductor transistor MN1 is turned on, the base voltage of the bipolar transistor 401 in all pixels is pulled down to ground, and after release, the voltage of the bipolar transistor 401 in all pixels starts to establish a steady state from a unified state.

[0098] It should be noted that when establishing the steady state of the bipolar transistor 401 in the early stage, the establishment speed of the steady state is relatively fast. In the later stage of steady state establishment, the first base current is output to the base of the bipolar transistor 401 through the first voltage boosting control signal controlling the voltage boosting circuit 403 (that is, injecting charge into the base of the bipolar transistor 401 through the coupling capacitor), and the base voltage of the bipolar transistor 401 is quickly boosted to near the steady state. Then, turning on the LED allows the bipolar transistor 401 to complete the establishment of the steady state in a short time, so as to quickly start the shutter operation.

[0099] The operation mode of the high-sensitivity pixel circuit is described in more detail below. Based on Figure 4 , as Figure 5 shown, it is a schematic diagram of the working timing of the high-sensitivity pixel circuit provided by the embodiment of the present application.

[0100] As Figure 5 shown, at the first time point T1 before the start of an exposure, the reset circuit 402 is controlled by the first reset control signal (that is, the second P-type metal oxide semiconductor transistor MP2 is controlled to turn on) to reset the load capacitor C2. T1 is the moment when the reset circuit 402 starts to be controlled to reset the load capacitor C2.

[0101] At the same time, at the first time point T1, according to the received shutter control signal, the shutter circuit 407 turns off the second N-type metal oxide semiconductor transistor MN2, so that the first P-type metal oxide semiconductor transistor MP1, the third N-type metal oxide semiconductor transistor MN3, the fourth N-type metal oxide semiconductor transistor MN4, and the bipolar transistor 401 form a feedback loop.

[0102] At this time, while turning off the second N-type metal oxide semiconductor transistor MN2, the fourth N-type metal oxide semiconductor transistor MN4 is turned on, so that while resetting the load capacitor C2, the voltage of the emitter of the bipolar transistor 401 is adjusted through the reset circuit 402.

[0103] After resetting the load capacitor C2, at the second time point T2, the clearing circuit 404 controls the conduction between the base of the bipolar transistor 401 and the ground terminal according to the received clearing control signal (which controls the first N-type metal oxide semiconductor transistor MN1 to turn on), so as to pull down the base voltage of the bipolar transistor 401 to the ground through the first N-type metal oxide semiconductor transistor MN1. T2 is the moment when the conduction between the base of the bipolar transistor 401 and the ground terminal starts to be controlled.

[0104] It should be noted that the clearing control signal will control the conduction between the base of the bipolar transistor 401 and the ground terminal for a short period of time, that is, after the second time point T2, the clearing control signal will control the first N-type metal oxide semiconductor transistor MN1 to turn off to control the disconnection between the base of the bipolar transistor 401 and the ground terminal.

[0105] At the third time point T3, the first N-type metal oxide semiconductor transistor MN1 is controlled to turn off through the clearing control signal, so as to raise the base voltage of the bipolar transistor 401 to the first voltage value through the second P-type metal oxide semiconductor transistor MP2 and the fourth N-type metal oxide semiconductor transistor MN4 in the reset circuit 402. T3 is the moment when the first N-type metal oxide semiconductor transistor MN1 is controlled to turn off.

[0106] It should be noted that when the base voltage of the bipolar transistor 401 rises, the gate voltage of the third N-type metal oxide semiconductor transistor MN3 also rises accordingly, causing the impedance value of the third N-type metal oxide semiconductor transistor MN3 to decrease, the voltage division of the third N-type metal oxide semiconductor transistor MN3 to decrease, and the potential of the drain terminal of the third N-type metal oxide semiconductor transistor MN3 to decrease. Therefore, the gate voltage of the fourth N-type metal oxide semiconductor transistor MN4 will be reduced. When the gate voltage of the fourth N-type metal oxide semiconductor transistor MN4 is reduced, the voltage of the emitter of the bipolar transistor 401 will also be reduced, thereby enabling the base voltage of the bipolar transistor 401 to be reduced. When the base voltage of the bipolar transistor 401 is reduced, the gate voltage of the third N-type metal oxide semiconductor transistor MN3 will also be reduced accordingly, causing the impedance value of the third N-type metal oxide semiconductor transistor MN3 to increase, the voltage division of the third N-type metal oxide semiconductor transistor MN3 to increase, and the potential of the drain terminal of the third N-type metal oxide semiconductor transistor MN3 to increase. Therefore, the gate voltage of the fourth N-type metal oxide semiconductor transistor MN4 will be increased. When the gate voltage of the fourth N-type metal oxide semiconductor transistor MN4 is increased, the voltage of the emitter of the bipolar transistor 401 will also be increased, thereby enabling the base voltage of the bipolar transistor 401 to be increased. Such feedback adjustment is carried out until the cross-voltage between the base and emitter of the bipolar transistor 401 stabilizes at a preset voltage value.

[0107] After the third time point T3, the cross-voltage between the base and emitter of the bipolar transistor 401 will continue to rise until the bipolar transistor 401 operates at a stable current gain value, that is, the fourth time point T4.

[0108] At the fourth time point T4, when the base voltage of the bipolar transistor 401 rises to the first voltage value, the voltage boosting circuit 403 controls the voltage boosting circuit 403 to output a first base current to the base of the bipolar transistor 401 through the coupling capacitor according to the first voltage boosting control signal, so as to boost the base voltage of the bipolar transistor 401 to the second voltage value, so that the bipolar transistor 401 approaches a steady state. T4 is the moment when the voltage boosting circuit 403 starts to output the first base current to the base of the bipolar transistor 401 through the coupling capacitor.

[0109] Subsequently, when the bipolar transistor 401 approaches a steady state, exposure is generated by lighting the LED, causing the photosensitive circuit 406 to start outputting a photosensitive current to the base of the bipolar transistor 401, so that the bipolar transistor 401 establishes a steady state based on the photosensitive current.

[0110] At the fifth time point T5, after the bipolar transistor 401 completes the establishment of the steady state based on the photosensitive current, the reset circuit 402 is controlled by the second reset control signal (i.e., the second P-type metal oxide semiconductor transistor MP2 is controlled to turn off) to stop adjusting the voltage of the emitter of the bipolar transistor 401. So that the collector current of the bipolar transistor 401 starts to discharge the load capacitor C2, reducing the capacitance voltage of the load capacitor C2. T5 is the moment when the second P-type metal oxide semiconductor transistor MP2 is controlled to turn off.

[0111] At the sixth time point T6, the shutter circuit 407 turns on the second N-type metal oxide semiconductor transistor MN2 according to the received shutter control signal to turn off the fourth N-type metal oxide semiconductor transistor MN4, blocking the path between the collector of the bipolar transistor 401 and the load capacitor C2. T6 is the moment when the second N-type metal oxide semiconductor transistor MN2 is turned on.

[0112] Subsequently, the boost circuit 403 is controlled by the second boost control signal to stop generating the first base current, and the LED is turned off to complete one exposure.

[0113] This application also provides an image sensor, including a light source and a pixel array. The pixel array includes a plurality of high-sensitivity pixel circuits as Figure 4 shown. Among them, the light source is used to provide light for the high-sensitivity pixel circuits in the pixel array. Since the image sensor in the embodiments of this application includes the above-mentioned high-sensitivity pixel circuits, the technical effects that can be obtained can also refer to the embodiments of the above-mentioned high-sensitivity pixel circuits, which will not be elaborated here in the embodiments of this application.

[0114] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered by the protection scope of this application.

Claims

1. A high-sensitivity pixel circuit, characterized in that, Comprising: A bipolar transistor, the collector of the bipolar transistor being coupled to a ground terminal; A reset circuit, coupled to the emitter of the bipolar transistor, configured to: according to a received first reset control signal, by adjusting the voltage of the emitter, raise the base voltage of the bipolar transistor to a first voltage value; A voltage boosting circuit, coupled to the base, configured to: after the base voltage is raised to the first voltage value, according to a received first voltage boosting control signal, output a first base current to the base, and raise the base voltage from the first voltage value to a second voltage value, the second voltage value being greater than the first voltage value; A feedback circuit, a first end of the feedback circuit being coupled to the base, a second end of the feedback circuit being coupled to the emitter, configured to: according to the base voltage, adjust the voltage of the emitter such that the voltage difference between the base and the emitter remains within a preset voltage range; the reset circuit is coupled to the emitter through a third end of the feedback circuit; A photosensitive circuit, a first end of the photosensitive circuit being coupled to the base, a second end of the photosensitive circuit being coupled to the ground terminal, configured to: after the base voltage is raised to the second voltage value, according to the intensity of the received light, generate a second base current, and stabilize the base voltage from the second voltage value to a third voltage value through the feedback circuit; A shutter circuit, the shutter circuit being coupled to a fourth end of the feedback circuit, configured to: according to a received shutter control signal, control the on / off of the path between the second end and the third end of the feedback circuit.

2. The high-sensitivity pixel circuit according to claim 1, wherein The high-sensitivity pixel circuit further comprises: A clearing circuit, coupled between the base and the ground terminal, configured to: before the reset circuit raises the base voltage to the first voltage value, according to a received clearing control signal, control the conduction between the base and the ground terminal, and before the voltage boosting circuit receives the first voltage boosting control signal, control the open circuit between the base and the ground terminal.

3. The high-sensitivity pixel circuit according to claim 2, characterized in that, The clearing circuit comprises: A first N-type metal oxide semiconductor transistor, the drain of the first N-type metal oxide semiconductor transistor being coupled to the base, the source of the first N-type metal oxide semiconductor transistor being coupled to the ground terminal, and the gate of the first N-type metal oxide semiconductor transistor being used to receive a clearing control signal.

4. The high-sensitivity pixel circuit according to claim 1, characterized in that, The high-sensitivity pixel circuit further comprises: A load capacitor, a first end of the load capacitor being coupled to a third end of the feedback circuit, and a second end of the load capacitor being coupled to the ground terminal.

5. The high-sensitivity pixel circuit according to claim 4, wherein, The reset circuit is further configured to: according to a received first reset control signal, reset the load capacitor.

6. The high-sensitivity pixel circuit according to claim 4, characterized in that When the base voltage is stabilized at the third voltage value, the reset circuit receives a second reset control signal, and the second reset control signal is used to control the reset circuit to stop resetting the load capacitor; The collector discharges to the load capacitor until the shutter circuit disconnects the second end and the third end of the feedback circuit.

7. The high-sensitivity pixel circuit according to claim 1, wherein The shutter circuit comprises: A second N-type metal oxide semiconductor transistor, wherein a drain of the second N-type metal oxide semiconductor transistor is coupled to the ground terminal, a source of the second N-type metal oxide semiconductor transistor is coupled to a fourth terminal of the feedback circuit, and a gate of the second N-type metal oxide semiconductor transistor is configured to receive a shutter control signal.

8. The high-sensitivity pixel circuit according to claim 1, wherein The light illumination is generated by a light source after the base voltage is raised to a second voltage value, and the light illumination stops after disconnecting a second terminal of the feedback circuit from a third terminal of the feedback circuit.

9. The high-sensitivity pixel circuit according to claim 1, characterized in that, After disconnecting the second terminal of the feedback circuit from the third terminal of the feedback circuit, the voltage boosting circuit receives a second voltage boosting control signal, and the second voltage boosting control signal is used to control the voltage boosting circuit to stop generating the first base current.

10. The high-sensitivity pixel circuit according to claim 1, wherein The feedback circuit includes: A first P-type metal oxide semiconductor transistor, wherein a source of the first P-type metal oxide semiconductor transistor is coupled to a power supply terminal, a drain of the first P-type metal oxide semiconductor transistor serves as the fourth terminal of the feedback circuit, and a gate of the first P-type metal oxide semiconductor transistor is configured to receive a bias voltage signal; A third N-type metal oxide semiconductor transistor, wherein a drain of the third N-type metal oxide semiconductor transistor is coupled to the drain of the first P-type metal oxide semiconductor transistor, a source of the third N-type metal oxide semiconductor transistor is coupled to the ground terminal, and a gate of the third N-type metal oxide semiconductor transistor serves as the first terminal of the feedback circuit; A fourth N-type metal oxide semiconductor transistor, wherein a drain of the fourth N-type metal oxide semiconductor transistor serves as the second terminal of the feedback circuit, a source of the fourth N-type metal oxide semiconductor transistor serves as the third terminal of the feedback circuit, and a gate of the fourth N-type metal oxide semiconductor transistor is coupled to the drain of the first P-type metal oxide semiconductor transistor.

11. The high-sensitivity pixel circuit according to claim 1, wherein The reset circuit includes: A second P-type metal oxide semiconductor transistor, wherein a source of the second P-type metal oxide semiconductor transistor is coupled to a power supply terminal, a drain of the second P-type metal oxide semiconductor transistor is coupled to the third terminal of the feedback circuit, and a gate of the second P-type metal oxide semiconductor transistor is configured to receive a reset control signal; Wherein, the reset control signal includes a first reset control signal and a second reset control signal, the first reset control signal is used to control the reset circuit to adjust the voltage of the emitter, and the second reset control signal is used to control the reset circuit to stop resetting the load capacitor.

12. The high-sensitivity pixel circuit according to claim 1, wherein The voltage boosting circuit includes: A coupling capacitor, wherein a first terminal of the coupling capacitor is coupled to the base, and a second terminal of the coupling capacitor is configured to receive a voltage boosting control signal; Wherein, the voltage boosting control signal includes a first voltage boosting control signal and a second voltage boosting control signal, the first voltage boosting control signal is used to control the voltage boosting circuit to output a first base current to the base, and the second voltage boosting control signal is used to control the voltage boosting circuit to stop generating the first base current.

13. An image sensor, characterized in that, Includes: A light source; A pixel array, comprising a plurality of high-sensitivity pixel circuits as described in any one of claims 1-12.

Images