Embedded circuit board and preparation method thereof

Abstract

The invention discloses an embedded circuit board and a preparation method thereof, the embedded circuit board comprises an electronic device and at least two sub-layers, at least one of the sub-layers is provided with a groove body, the electronic device is embedded in the groove body, the surface of the electronic device is coated with a polymer coating, and the polymer coating is coated on the surface of the electronic device. And the polymer coating is used as a buffer dielectric layer arranged between the electronic device and the adjacent dielectric layer and is used for absorbing and releasing thermal stress of the circuit board in a reflow soldering process. Layering between an embedded device and a circuit board in the reflow soldering process and cracking of an embedded frame can be reduced, impact of high temperature and thermal stress generated in the reflow soldering process on the embedded circuit board is relieved, the reliability of a product is improved, the service life of the product is prolonged, and cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and particularly to an embedded circuit board and a preparation method thereof. Background Art

[0002] With the rapid development of electronic technology, electronic products tend to be miniaturized, high-performance, and highly integrated. Traditional packaging technologies are difficult to meet the requirements, and embedded packaging has emerged. The embedded packaging technology is to bury passive components such as resistors, capacitors, inductors, and even active devices such as ICs into the printed circuit board. Its characteristics and advantages are significant. First, it is miniaturized. By burying electronic components inside the substrate, the overall volume is reduced, and more components can be accommodated in the same space. Second, it improves performance. The signal transmission path is shortened, the delay and loss are reduced, the electromagnetic interference is reduced, and the signal integrity and stability are improved. Third, it has high integration. Multiple components can be three-dimensionally integrated, saving space, reducing costs, and improving efficiency. Fourth, it has good heat dissipation performance. The contact area between the components and the substrate is large, which is conducive to heat dissipation, improving reliability and service life. Fifth, it has high reliability. It can better protect electronic components, reduce the influence of the external environment, provide moisture-proof, dust-proof, and earthquake-proof performance, and enable electronic products to operate stably in harsh environments. Embedded packaging occupies an important position in the field of modern electronic packaging and has a very broad application prospect.

[0003] However, for an embedded circuit board, during the reflow soldering process of the embedded device, it is easy to be affected by stress (such as caused by lamination asymmetry, curing of semi-cured resin, etc.) due to the mismatch between the coefficient of thermal expansion (CTE) of the device and the CTE of the organic resin layer, resulting in delamination between the embedded device and the PCB. In severe cases, abnormal situations such as cracking of the embedded frame or device cracking may even occur, affecting the use reliability of the product. Summary of the Invention

[0004] Embodiments of the present invention provide an embedded circuit board and a preparation method thereof to solve the problems of delamination between the embedded device and the circuit board, cracking of the embedded frame, and low use reliability of the product during the reflow soldering process of the embedded circuit board.

[0005] Based on the above purpose, in one embodiment, an embedded circuit board is provided, including: an electronic device and at least two sub-layers, wherein, At least one of the sub-layers is provided with a groove, the electronic device is buried inside the groove, the surface of the electronic device is coated with a polymer coating, there is at least one layer of the polymer coating, and a filler layer is further provided in the polymer coating, which is used as a buffer dielectric layer provided between the electronic device and the adjacent dielectric layer to absorb and release the thermal stress of the circuit board during the reflow soldering process.

[0006] In one embodiment, when the polymer coating is a multi-layer coating, it includes: A first coating, a second coating,..., up to an Nth coating, which are arranged in sequence from the inside to the outside, where N≥2, The coefficient of thermal expansion of the Nth coating is greater than that of the (N - 1)th coating, and so on, and the coefficient of thermal expansion of the second coating is greater than that of the first coating.

[0007] In one embodiment, the filler layer is located between the electronic device and the first coating. The filler layer has a sheet structure, and the filler in the filler layer contains one or a mixture of two or more of talc, mica, and kaolin.

[0008] In one embodiment, the coefficients of thermal expansion of M coatings arranged in sequence from the inside to the outside in the polymer coating are between the coefficient of thermal expansion of the electronic device and the coefficient of thermal expansion of the adjacent dielectric layer, where 0<M<N.

[0009] In one embodiment, the polymer coating has transparency. The thickness range of the polymer coating is 1 - 200 um. The material of the polymer coating is epoxy resin, silicone resin, polyimide resin, phenolic resin, polyurethane, acrylic resin, or polyester resin. The material of each layer of the polymer coating is selected according to the requirement of the coefficient of thermal expansion of the polymer coating.

[0010] In one embodiment, the embedded circuit board specifically includes: A first metal layer, a first bonding dielectric layer, a first sub-layer, a first insulating dielectric layer, a second sub-layer, a second insulating dielectric layer, a third sub-layer, a second bonding dielectric layer, and a second metal layer, which are arranged in sequence from top to bottom, where A slot is provided in the second sub-layer, and the electronic device placed in the slot includes a magnetic core or a silicon carbide power chip module. Interconnecting vias are provided on the first bonding dielectric layer, the first sub-layer, the first insulating dielectric layer, the second sub-layer, the second insulating dielectric layer, the third sub-layer, and the second bonding dielectric layer.

[0011] In one embodiment, the embedded circuit board may further specifically include: A first metal layer, a first insulating dielectric layer, a first sub-layer, a first bonding dielectric layer, a second sub-layer, a second bonding dielectric layer, a third sub-layer, a second insulating dielectric layer, and a second metal layer, which are arranged in sequence from top to bottom, where Slots are provided in the first sub-layer, the first bonding dielectric layer, the second sub-layer, the second bonding dielectric layer, and the third sub-layer. The electronic device placed in the slot includes an inductor, a capacitor, or a resistor. One end of the electronic device is connected to the first metal layer through a first blind via, and the other end of the electronic device is connected to the second metal layer through a second blind via.

[0012] In one embodiment, a method for preparing an embedded circuit board is provided, including: Providing an electronic device, forming a polymer coating on the surface of the electronic device to obtain an electronic device with a polymer coating; Providing at least two sub-layers, and providing a groove in at least one of the sub-layers; Stacking the sub-layers in sequence, providing a dielectric layer between two adjacent sub-layers, and placing the electronic device into the groove to obtain a circuit board with the electronic device placed therein; Performing a lamination process on the circuit board with the electronic device placed therein to obtain the embedded circuit board; Wherein, the polymer coating is used as a buffer dielectric layer disposed between the electronic device and the adjacent dielectric layer to absorb and release the thermal stress of the circuit board during the reflow soldering process.

[0013] In one embodiment, performing a lamination process on the circuit board with the electronic device placed therein to obtain the embedded circuit board includes: Laying a first insulating dielectric layer on the circuit board with the electronic device placed therein, making the first insulating dielectric layer located above the electronic device, and performing a first lamination process to obtain a circuit board after the first lamination process, wherein the temperature range of the first lamination process is within a preset low temperature range; Laying a second insulating dielectric layer on the circuit board after the first lamination process, making the first insulating dielectric layer located below the electronic device, and performing a second lamination process to obtain a circuit board after the second lamination process, wherein the temperature range of the second lamination process is within a preset high temperature range.

[0014] In one embodiment, after forming the polymer coating on the surface of the electronic device, performing plasma treatment on the polymer coating to activate the surface of the polymer coating, so that the polymer coating is tightly adhered to the surface of the electronic device.

[0015] For the above-mentioned embedded circuit board and its preparation method, by coating the surface of the embedded electronic device with a polymer coating, using the polymer coating as a buffer dielectric layer between the electronic device and the dielectric layer, absorbing and releasing the thermal stress generated during the reflow soldering process, reducing the delamination of the embedded device from the circuit board and the cracking of the embedded frame during the reflow soldering process, alleviating the impact of the high temperature and thermal stress generated during the reflow soldering process on the embedded circuit board, improving the reliability of the product, extending the service life of the product, and reducing the cost. Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 is an exemplary diagram of coating a polymer coating on the surface of an electronic device in an embodiment of the present invention; Figure 2 is another exemplary diagram of coating a polymer coating on the surface of an electronic device in an embodiment of the present invention; Figure 3 is an exemplary diagram of an embedded circuit board in an embodiment of the present invention; Figure 4 is another exemplary diagram of an embedded circuit board in an embodiment of the present invention; Figure 5 is a flowchart for preparing an embedded circuit board in an embodiment of the present invention.

[0018] Exemplary drawings: 1. Embedded circuit board, 101. First metal layer, 102. First adhesive medium layer, 103. First sub-layer, 104. First insulating medium layer, 105. Second sub-layer, 106. Second insulating medium layer, 107. Third sub-layer, 108. Second adhesive medium layer, 109. Second metal layer, 110. Electronic device, 112. Interconnecting via, 113. First blind via, 114. Second blind via, 115. Electronic device terminal, 3. Polymer coating, 301. Filler layer, 303. First coating, 305. Second coating. Detailed implementation manners

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0020] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0022] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0024] To fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

[0025] In one embodiment, a method for grading the capacity of a lithium-ion battery is provided, including: A buried circuit board is provided, including: electronic devices and at least two sub-layers, wherein, A groove is provided in at least one of the sub-layers. The electronic device is buried inside the groove. The surface of the electronic device is coated with a polymer coating. There is at least one layer of the polymer coating, and a filler layer is further provided in the polymer coating for serving as a buffer dielectric layer disposed between the electronic device and an adjacent dielectric layer to absorb and release the thermal stress of the circuit board during the reflow soldering process.

[0026] Wherein, when the polymer coating is one layer, as Figure 1 shown, a polymer coating 3 is coated outside the electronic device 110. The polymer coating 3 serves as a buffer dielectric layer to absorb and release the thermal stress of the buried circuit board during the reflow soldering process. In the sub-layers of the circuit board, at least one sub-layer is provided with a groove, and the electronic device coated with the polymer coating is buried inside the groove.

[0027] In this embodiment, by coating the polymer coating outside the electronic device and using the polymer coating as a buffer dielectric layer between the electronic device and an adjacent dielectric layer to absorb and release the thermal stress of the circuit board during the reflow soldering process, the delamination of the buried device from the circuit board and the cracking of the buried frame during the reflow soldering process are reduced, the impact of the high temperature and thermal stress generated during the reflow soldering process on the buried circuit board is alleviated, the reliability of the product is improved, the service life of the product is prolonged, and the cost can also be reduced.

[0028] In one embodiment, when the polymer coating is multiple layers, it includes: A first coating, a second coating,..., up to an Nth coating arranged in sequence from the inside to the outside, wherein N≥2, The thermal expansion coefficient of the Nth coating is greater than that of the (N - 1)th coating, and so on, and the thermal expansion coefficient of the second coating is greater than that of the first coating.

[0029] Wherein, when the polymer coating is multiple coatings, the thermal expansion coefficients of each coating are different. The thermal expansion coefficient of the first coating is the smallest, the thermal expansion coefficients of the coatings from the inside to the outside gradually increase, and the thermal expansion coefficient of the outermost Nth coating is the largest, but the thermal expansion coefficient of the Nth coating does not exceed 200 ppm / k.

[0030] Example: As Figure 2 shown, there are two layers of the polymer coating 3 provided on the surface of the electronic device. Assuming that the thermal expansion coefficient of the first coating 303 is 50 ppm / k, then the thermal expansion coefficient of the second coating 305 is between 50 - 200 ppm / k.

[0031] In this embodiment, there are multiple polymer coatings provided on the surface of the electronic device. During the reflow soldering process, the temperature of the circuit board increases. Due to the gradually increasing coefficient of thermal expansion of each coating arranged from the inside to the outside, the thermal stress generated by the reflow soldering is gradually released among the multiple coatings, avoiding the concentration of thermal stress, preventing the device from cracking, reducing the dimensional change caused by the temperature change, preventing the cracking of the embedded frame, maintaining the stability of the embedded circuit board, and increasing the reliability of the embedded circuit board.

[0032] In one embodiment, the filler layer 301 is located between the electronic device and the first coating. The filler layer 301 has a sheet-like structure, and the filler in the filler layer 301 contains one or a mixture of two or more of talc, mica, and kaolin.

[0033] Among them, as Figure 1 shown, when the polymer coating is one layer, a filler layer 301 is provided between the electronic device 110 and the polymer coating 3. When the polymer coating is multiple layers, as Figure 2 shown, a filler layer 301 is provided between the electronic device 110 and the first coating 303. Among them, the filler in the filler layer 301 can be one or a mixture of two or more of talc, mica, and kaolin. The filler has good thermal stability. Among them, talc has a unique flaky structure and can withstand a certain temperature during the processing. Therefore, when mixed with other components under high-temperature conditions, no chemical change will occur; mica can remain stable in a high-temperature environment and is not prone to decomposition or deformation; kaolin also has relatively good thermal stability.

[0034] In this embodiment, a filler layer is provided between the electronic device and the first coating, and one or a mixture of two or more of talc, mica, and kaolin is provided in the filler layer, which can exert a synergistic effect, more effectively reduce the coefficient of thermal expansion of the filler layer, and at the same time improve the heat resistance of the filler layer. This reduces the influence of the thermal stress generated by the reflow soldering, prevents the device from cracking, reduces the dimensional change of the polymer coating caused by the temperature change, prevents the cracking of the embedded frame, maintains the stability of the embedded circuit board, and increases the reliability of the embedded circuit board.

[0035] In one embodiment, the coefficient of thermal expansion of the M coatings arranged from the inside to the outside in the polymer coating is between the coefficient of thermal expansion of the electronic device and the coefficient of thermal expansion of the adjacent dielectric layer, where 0 < M < N.

[0036] Among them, in the polymer coating, there are M coatings whose coefficient of thermal expansion is between that of the electronic device and that of the adjacent dielectric layer. The electronic device is usually an inorganic material with a coefficient of thermal expansion within 10 ppm / k, while the adjacent dielectric layer is usually an organic resin layer with a coefficient of thermal expansion usually being 50 ppm / k; that is to say, there are M coatings whose coefficient of thermal expansion is between 10 - 50 ppm / k.

[0037] Example: There are a total of three coatings in the polymer coating. Among them, there are two coatings whose coefficient of thermal expansion is between that of the electronic device and that of the adjacent dielectric layer. The coefficient of thermal expansion of the first coating is set between 10 - 30 ppm, the coefficient of thermal expansion of the second coating is set between 30 - 50 ppm, and the coefficient of thermal expansion of the third coating is set between 50 - 200 ppm.

[0038] In this embodiment, the coefficient of thermal expansion of the M coatings arranged in sequence from the inside to the outside in the polymer coating is between that of the electronic device and that of the adjacent dielectric layer, so that the influence caused by the thermal stress generated during reflow soldering is absorbed and released by the polymer coating, preventing delamination of the electronic device and improving the reliability of the embedded circuit board.

[0039] In one embodiment, the polymer coating has transparency, the thickness range of the polymer coating is 1 - 200 um, and the material of the polymer coating is epoxy resin, silicone resin, polyimide resin, phenolic resin, polyurethane, acrylic resin or polyester resin. The material of each layer of the polymer coating is selected according to the requirement of the coefficient of thermal expansion, and the material of each layer of the polymer coating is selected according to the requirement of the coefficient of thermal expansion of the polymer coating.

[0040] Among them, the thickness range of the polymer coating is 1 - 200 um and it has transparency, which is convenient for the device to automatically sample and place materials through the identification terminal.

[0041] The materials of the polymer coating are epoxy resin, silicone resin, polyimide resin, phenolic resin, polyurethane, acrylic resin or polyester resin. If the polymer coating is a single layer, one of them is selected as the material of the polymer coating according to the coefficient of thermal expansion of the polymer coating. If the polymer coating is multiple layers, the materials of each layer of polymer are selected according to the requirements of the coefficient of thermal expansion of each layer of polymer coating, and the materials of each layer of polymer coating are different. Among them, epoxy resin has good heat resistance, low coefficient of thermal expansion, and low shrinkage rate after curing, and has good dimensional stability; silicone resin has excellent heat resistance, its coefficient of thermal expansion is relatively high, but it can adapt to the thermal stress brought by the reflow soldering process to a certain extent; polyimide resin has extremely high heat resistance, its coefficient of thermal expansion is low, and it has excellent dimensional stability; phenolic resin has good heat resistance and low coefficient of thermal expansion; polyurethane has general heat resistance, but low coefficient of thermal expansion, has good flexibility, and can also adapt to the thermal stress brought by the reflow soldering process to a certain extent; acrylic resin has good heat resistance, low coefficient of thermal expansion, and also has good dimensional stability; polyester resin has good heat resistance, low coefficient of thermal expansion, and also has good dimensional stability.

[0042] When selecting the material of the coating, it should be strongly combined with the electronic device and pass the 0-level of the cross-cut test ISO. The cross-cut test is an experimental method used to evaluate the adhesion of coatings, platings or paint films. During the test, use a cross-cut knife or blade to draw squares of 1mm×1mm or 2mm×2mm on the sprayed surface until the substrate is exposed, then stick a specific type of tape (such as 3M600 or 610) on the scribed area, press it firmly with your finger to ensure that the tape is in close contact with the coating, and finally quickly tear off the tape in the vertical direction to observe the coating peeling situation; The ISO grades range from 0 to 5. Grade 0 means that the cut edges are completely smooth and there is no peeling; Grade 5 means that the peeling area exceeds 65%.

[0043] In this embodiment, the polymer coating should have transparency to facilitate the device to automatically sample through its identification segments, and place the electronic device coated with the polymer coating in the set slot; select a material with a suitable coefficient of thermal expansion as the coating and pass the 0-level of the cross-cut test ISO. The strong combination of the coating material and the electronic device enables the polymer coating covering the surface of the electronic device not to detach from the surface of the electronic device when absorbing and releasing the thermal stress generated during the reflow soldering process, thereby reducing the delamination of the embedded electronic device from the circuit board during the reflow soldering process and improving the reliability of the product.

[0044] In one embodiment, as Figure 3 shown, the embedded circuit board 1 specifically includes: A first metal layer 101, a first adhesive medium layer 102, a first sub-layer 103, a first insulating medium layer 104, a second sub-layer 105, a second insulating medium layer 106, a third sub-layer 107, a second adhesive medium layer 108, and a second metal layer 109 are sequentially arranged from top to bottom, wherein, a groove is provided in the second sub-layer 105, and the electronic device 110 placed in the groove includes a magnetic core or a silicon carbide power chip module, and through-holes 112 are provided on the first adhesive medium layer 102, the first sub-layer 103, the first insulating medium layer 104, the second sub-layer 105, the second insulating medium layer 106, the third sub-layer 107, and the second adhesive medium layer 108.

[0045] Wherein, as Figure 3 shown, a groove is provided in the second sub-layer 105 of the embedded circuit board 1 for placing the electronic device 110, and signals are transmitted through the through-holes 112 to realize the function of the embedded circuit board 1. The embedded circuit board 1 in this embodiment is applicable to small electronic devices such as magnetic cores or silicon carbide power chip modules. Only by providing a groove on one sub-layer, small electronic devices such as magnetic cores or silicon carbide power chip modules can be placed in the groove and completely buried. The embedded electronic devices include but are not limited to the components mentioned in this embodiment, and are all within the protection scope of this application.

[0046] In this embodiment, the electronic components with a polymer coating are placed into the circuit board to form a complete embedded circuit board, realizing a shorter signal transmission path, reducing signal delay and distortion, improving signal transmission efficiency, enabling more circuits and components to be arranged within the effective area of the circuit board, and improving the integration and functionality of the circuit board. At the same time, the surface of the embedded electronic device is coated with a polymer coating, reducing delamination between the embedded device and the circuit board and cracking of the embedded frame during the reflow soldering process, alleviating the impact of high temperature and thermal stress generated during the reflow soldering process on the embedded circuit board, improving the reliability of the embedded circuit board, extending the service life, and reducing costs.

[0047] In one embodiment, as Figure 4 shown, the embedded circuit board 1 may further specifically include: a first metal layer 101, a first insulating medium layer 104, a first sub-layer 103, a first adhesive medium layer 102, a second sub-layer 105, a second adhesive medium layer 108, a third sub-layer 107, a second insulating medium layer 106, and a second metal layer 109 are sequentially arranged from top to bottom, wherein, The groove is provided in the first sub-layer 103, the first adhesive medium layer 102, the second sub-layer 105, the second adhesive medium layer 108, and the third sub-layer 107. The electronic device 110 placed in the groove includes an inductor, a capacitor, or a resistor. One end of the electronic device 110 is connected to the first metal layer 101 through the first blind hole 113, and the other end of the electronic device 110 is connected to the second metal layer 109 through the second blind hole 114.

[0048] Among them, as Figure 4 shown, the groove is provided in the first sub-layer 103, the first adhesive medium layer 102, the second sub-layer 105, the second adhesive medium layer 108, and the third sub-layer 107 of the embedded circuit board 1 for placing the electronic device 110. The electronic device terminals 115 are respectively connected to the corresponding two metal layers through two blind holes. The embedded circuit board 1 in this embodiment is applicable to electronic devices such as inductors, capacitors, or resistors. Grooves need to be provided on three sub-layers, and electronic devices such as inductors are placed in the grooves and completely buried. The buried electronic devices include but are not limited to the components mentioned in this embodiment, and all are within the protection scope of this application.

[0049] In this embodiment, the electronic component with the polymer coating is placed into the circuit board to form a complete embedded circuit board, avoiding problems such as poor soldering caused by surface mounting. Moreover, the buried electronic component is protected by the PCB material, avoiding the influence of the external environment. At the same time, the surface of the buried electronic device is coated with a polymer coating, reducing the delamination between the buried device and the circuit board and the cracking of the buried frame during the reflow soldering process, alleviating the impact of the high temperature and thermal stress generated during the reflow soldering process on the embedded circuit board, improving the reliability of the embedded circuit board, extending the service life, and reducing the cost.

[0050] In one embodiment, as Figure 5 described, a method for preparing an embedded circuit board is provided, including: S801, providing an electronic device, and forming a polymer coating on the surface of the electronic device to obtain an electronic device with a polymer coating; Among them, the electronic device is first processed to set a polymer coating on its surface.

[0051] S802, providing at least two sub-layers, and providing a groove in at least one of the sub-layers; Among them, at least two sub-layers are required to prepare the embedded circuit board. In the sub-layers, at least one sub-layer is provided with a groove for placing the electronic device with a polymer coating in S801.

[0052] S803. Stack the sub-layers in sequence, with a dielectric layer provided between two adjacent sub-layers. Place the electronic device into the slot to obtain a circuit board with the electronic device placed therein. Among them, a dielectric layer is provided between two adjacent sub-layers, and the sub-layers are stacked in sequence. Stick a single-sided tape inside the slot, and then place the electronic device into the slot set in S802. The single-sided tape fixes the electronic device to ensure that it does not shift during subsequent processing and is located at a preset position.

[0053] S804. Perform a lamination process on the circuit board with the electronic device placed therein to obtain the embedded circuit board. Among them, the polymer coating is used as a buffer dielectric layer provided between the electronic device and the adjacent dielectric layer to absorb and release the thermal stress of the circuit board during the reflow soldering process.

[0054] The preparation method of an embedded circuit board provided in this embodiment can prepare two types of embedded circuit boards through the above preparation steps, such as Figure 3 and Figure 4 as shown. Figure 3 The electronic component in Figure 4 is a magnetic core or a silicon carbide power chip module, or it can also be other electronic components that can be placed into a slot provided in one sub-layer;

[0055] In this embodiment, by coating the surface of the embedded electronic device with a polymer coating and using the polymer coating as a buffer dielectric layer between the electronic device and the dielectric layer, the thermal stress generated during the reflow soldering process is absorbed and released, reducing the delamination of the embedded device from the circuit board and the cracking of the embedded frame during the reflow soldering process, alleviating the impact of the high temperature and thermal stress generated during the reflow soldering process on the embedded circuit board, improving the reliability of the product, extending the service life of the product, and reducing the cost.

[0056] In one embodiment, performing a lamination process on the circuit board with the electronic device placed therein to obtain the embedded circuit board includes: S901. Lay a first insulating dielectric layer on the circuit board with the electronic device placed therein, making the first insulating dielectric layer located above the electronic device, and perform a first lamination process to obtain a circuit board after the first lamination process. The temperature range of the first lamination process is within a preset low temperature range. Among them, after placing the electronic device, a first insulating dielectric layer is laid above the electronic device. The first insulating dielectric layer is a material with high flowable adhesive properties, such as prepreg, build-up film, etc. After laying, the first lamination process is carried out. When laminating, the preset low-temperature range refers to less than 150 °C, so that the first insulating dielectric layer fills the groove body and embeds the electronic device.

[0057] S902, a second insulating dielectric layer is laid on the circuit board after the first lamination process, so that the first insulating dielectric layer is located below the electronic device, and the second lamination process is carried out to obtain the circuit board after the second lamination process. The temperature range of the second lamination process is within the preset high-temperature range.

[0058] Among them, after the first lamination process, the single-sided adhesive tape attached to the bottom of the groove body is peeled off, and the second insulating dielectric layer is laid on the side where the single-sided adhesive tape is removed. The second insulating dielectric layer is a material with high flowable adhesive properties, such as prepreg, build-up film, etc. After laying, the second lamination process is carried out. When laminating, the preset high-temperature range refers to greater than 150 °C, and the electronic device is completely embedded in the circuit board.

[0059] In this embodiment, when laying the first insulating dielectric layer and carrying out the lamination process, low-temperature lamination is adopted to prevent excessive curing of the material of the first insulating dielectric layer, reduce its thermal stress, and can also avoid deformation of the material of the first insulating dielectric layer, reduce the cracking of the circuit board embedded in the frame during the reflow soldering process, and improve the reliability of the embedded circuit board.

[0060] In one embodiment, after forming a polymer coating on the surface of the electronic device, the polymer coating is subjected to plasma treatment to activate the surface of the polymer coating, so that the polymer coating is tightly adhered to the surface of the electronic device.

[0061] Among them, the plasma treatment of the polymer coating specifically includes: Clean and dry the surface of the polymer coating to ensure no impurities and water, and check the plasma treatment equipment to ensure its normal operation; According to the characteristics of the polymer coating, set parameters such as the power, treatment time, and gas flow rate of the plasma source; Put the polymer coating into the plasma treatment chamber, start the plasma source, introduce a mixed gas of oxygen and carbon tetrafluoride, monitor the change of the polymer coating, and activate the surface of the polymer coating; Take it out in time after the treatment is completed, so as to improve the bonding force between the polymer coating and the frame of the embedded circuit board.

[0062] In this embodiment, by performing plasma treatment on the polymer coating covering the electronic device, the surface of the polymer coating is activated, so that the polymer coating is tightly adhered to the surface of the electronic device, enhancing the bonding force between the polymer coating and the frame of the embedded circuit board, reducing the delamination of the embedded device from the circuit board during the reflow soldering process, improving the reliability of the product, and extending the service life of the embedded circuit board.

[0063] The above-described embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention and should all be included within the protection scope of the present invention.

Claims

1. An embedded circuit board, characterized in that: include: An electronic device and at least two sublayers, wherein At least one of the sublayers is provided with a slot body, the electronic device is buried inside the slot body, the surface of the electronic device is covered with a polymer coating, the polymer coating has at least one layer, and a filler layer is also provided in the polymer coating, which is used as a buffer dielectric layer provided between the electronic device and the adjacent dielectric layer to absorb and release the thermal stress of the circuit board during the reflow soldering process.

2. The embedded circuit board according to claim 1, characterized in that: When the polymer coating is multi-layer, it includes: The first coating layer, the second coating layer, ..., the Nth coating layer are arranged in sequence from the inside to the outside, wherein N ≥ 2, The thermal expansion coefficient of the Nth coating layer is greater than the thermal expansion coefficient of the N-1th coating layer, and so on, the thermal expansion coefficient of the second coating layer is greater than the thermal expansion coefficient of the first coating layer.

3. The embedded circuit board according to claim 2, characterized in that: The filler layer is located between the electronic device and the first coating layer. The filler layer is a sheet structure. The filler in the filler layer contains one or a mixture of two or more of talc, mica and kaolin.

4. The embedded circuit board according to claim 2, characterized in that: The thermal expansion coefficients of the M coatings arranged sequentially from the inside to the outside of the polymer coating are between the thermal expansion coefficient of the electronic device and the thermal expansion coefficient of the adjacent dielectric layer, wherein 0<M<N.

5. The embedded circuit board according to claim 4, characterized in that: The polymer coating is transparent, the thickness of the polymer coating ranges from 1 to 200 um, and the material of the polymer coating is epoxy resin, silicone resin, polyimide resin, phenolic resin, polyurethane, acrylic resin or polyester resin. The material of each layer of the polymer coating is selected according to the requirements of the thermal expansion coefficient of the polymer coating.

6. The embedded circuit board according to claim 1, characterized in that: The embedded circuit board specifically comprises: The first metal layer, the first adhesive medium layer, the first sublayer, the first insulating medium layer, the second sublayer, the second insulating medium layer, the third sublayer, the second adhesive medium layer and the second metal layer are arranged in sequence from top to bottom, wherein: The slot body is arranged in the second sub-layer, and the electronic device placed in the slot body includes a magnetic core or a silicon carbide power chip module. Interconnection through holes are arranged on the first adhesive medium layer, the first sub-layer, the first insulating medium layer, the second sub-layer, the second insulating medium layer, the third sub-layer and the second adhesive medium layer.

7. The embedded circuit board according to claim 1, characterized in that: The embedded circuit board specifically comprises: The first metal layer, the first insulating medium layer, the first sublayer, the first adhesive medium layer, the second sublayer, the second adhesive medium layer, the third sublayer, the second insulating medium layer and the second metal layer are sequentially arranged from top to bottom, wherein: The slot body is arranged in the first sublayer, the first adhesive medium layer, the second sublayer, the second adhesive medium layer and the third sublayer. The electronic device placed in the slot body includes an inductor, a capacitor or a resistor. One end of the electronic device is connected to the first metal layer through a first blind hole, and the other end of the electronic device is connected to the second metal layer through a second blind hole.

8. A method for preparing an embedded circuit board, characterized in that: include: Providing an electronic device, forming a polymer coating on the surface of the electronic device to obtain an electronic device having the polymer coating; Providing at least two sub-layers, wherein at least one of the sub-layers has a groove body disposed therein; The sub-layers are stacked in sequence, a dielectric layer is provided between two adjacent sub-layers, and the electronic device is placed in the slot to obtain a circuit board with the electronic device placed therein; Performing a pressing process on the circuit board with embedded electronic devices to obtain the embedded circuit board; The polymer coating is used as a buffer dielectric layer disposed between the electronic device and an adjacent dielectric layer to absorb and release back the thermal stress of the circuit board during the flow soldering process.

9. The preparation method according to claim 8, characterized in that: The circuit board with embedded electronic devices is pressed to obtain the embedded circuit board, comprising: Laying a first insulating medium layer on the circuit board with the electronic device embedded therein so that the first insulating medium layer is located above the electronic device, performing a first pressing process to obtain a circuit board after the first pressing process, wherein the temperature range of the first pressing process is within a preset low temperature range; A second insulating medium layer is laid on the circuit board after the first lamination process, so that the first insulating medium layer is located below the electronic device, and a second lamination process is performed to obtain the circuit board after the second lamination process. The temperature range of the second lamination process is within a preset high temperature range.

10. The preparation method according to claim 8, characterized in that: After the polymer coating is formed on the surface of the electronic device, the polymer coating is subjected to plasma treatment to activate the surface of the polymer coating so that the polymer coating is tightly bonded to the surface of the electronic device.

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