Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a substrate, a first conductive line on the substrate, extending along a first direction, and a plurality of the first conductive lines arranged along a second direction intersecting the first direction, a memory array on the first conductive line and connected with the first conductive line, a second conductive line connected with the memory array and extending along a third direction intersecting the first direction, a first interconnection structure on the first conductive line and electrically connected with the first conductive line, and a second interconnection structure on the second conductive line and connected with the second conductive line. By arranging the plurality of the first conductive lines on the substrate and arranging the memory array on the first conductive line, the first conductive line is arranged below the memory array, without occupying the space above the memory array, thereby leaving more manufacturing space for the second conductive line, and reducing the difficulty of manufacturing the first conductive line and the second conductive line.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] In the prior art, a memory often has structures such as word lines, bit lines and transistors. The transistors are connected with logic circuits through structures such as word lines and bit lines. With the miniaturization of the memory, the interconnection space of the word lines and the bit lines with the logic circuits is limited.

[0003] Nowadays, how to improve the integration of the memory has become a problem to be solved. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof for solving the problem of how to improve the integration of the memory.

[0005] To achieve the above-mentioned purpose, in one aspect, the present disclosure provides a semiconductor structure, comprising:

[0006] a substrate;

[0007] a first conductive line located on the substrate, extending along a first direction, and a plurality of the first conductive lines arranged along a second direction intersecting the first direction;

[0008] a storage array located on the first conductive line and connected with the first conductive line;

[0009] a second conductive line connected with the storage array, extending along a third direction intersecting the first direction;

[0010] a first interconnection structure extending along a vertical direction and located on the first conductive line and electrically connected with the first conductive line;

[0011] a second interconnection structure extending along the vertical direction and located on the second conductive line and connected with the second conductive line.

[0012] In some embodiments, the substrate comprises a substrate and an isolation layer located between the substrate and the first conductive line; the first conductive line is located on the upper surface of the isolation layer, or the first conductive line is located in a groove of the isolation layer.

[0013] In some embodiments, the first interconnection structure is located at the end of the first conductive line, and the semiconductor structure further comprises:

[0014] a pad layer over the first interconnect structure and the second interconnect structure, the pad layer including a first pad electrically connected to the first interconnect structure and a second pad electrically connected to the second interconnect structure.

[0015] In some embodiments, the second conductive lines are arranged along the first direction and the vertical direction, the memory array includes memory cells located on opposite sides of each of the second conductive lines along the first direction, the memory cells located on opposite sides of the same second conductive line are staggered along the third direction, and the memory cells located on opposite sides of the same second conductive line are connected to the first conductive lines; the first conductive lines have a dimension along the first direction greater than a dimension of the memory array along the first direction, and the first interconnect structures connected to adjacent first conductive lines are located on opposite sides of the memory array along the first direction, respectively.

[0016] In some embodiments, the semiconductor structure further includes:

[0017] a first connection line, the first connection line being in contact with a top end of the first interconnect structure and extending in a direction from an outer periphery of the memory array to an inner portion of the memory array;

[0018] a third interconnect structure extending along the vertical direction and located between the first connection line and the first pad;

[0019] a second connection line, the second connection line being in contact with a top end of the second interconnect structure and extending in a direction from an outer periphery of the memory array to an inner portion of the memory array;

[0020] a fourth interconnect structure extending along the vertical direction and located between the second connection line and the second pad.

[0021] In some embodiments, the third interconnect structures located on different first connection lines are staggered.

[0022] The first connection lines extend along the first direction and a plurality of the first connection lines are arranged along the second direction, the lengths of the plurality of the first connection lines arranged along the second direction increase or decrease in turn.

[0023] The present disclosure also provides a method for manufacturing a semiconductor structure, including the following steps:

[0024] providing a substrate;

[0025] forming a plurality of first conductive lines extending along a first direction and arranged along a second direction on the substrate, the second direction intersecting the first direction;

[0026] forming a storage array on the plurality of first conductive lines, and forming a plurality of second conductive lines extending along a third direction and arranged along the first direction, the second conductive lines and the first conductive lines both connecting the storage array, the third direction intersecting the first direction;

[0027] forming a first interconnection structure on the first conductive lines, and forming a second interconnection structure on the second conductive lines, the first interconnection structure and the second interconnection structure both extending along a vertical direction.

[0028] In some embodiments, the substrate includes a substrate and an isolation layer.

[0029] The forming, on the substrate, the plurality of first conductive lines extending along a first direction and arranged along a second direction includes:

[0030] forming a trench in the isolation layer;

[0031] forming the first conductive lines filling the trench;

[0032] or,

[0033] The forming, on the substrate, the plurality of first conductive lines extending along a first direction and arranged along a second direction includes:

[0034] forming a first conductive line material layer on the isolation layer;

[0035] performing a patterning process on the first conductive line material layer to form the first conductive lines.

[0036] In some embodiments, the forming, on the first conductive lines, a first interconnection structure, and forming, on the second conductive lines, a second interconnection structure includes:

[0037] forming the first interconnection structure on end portions of the first conductive lines along the first direction;

[0038] after the forming, on the first conductive lines, a first interconnection structure, and forming, on the second conductive lines, a second interconnection structure, includes:

[0039] forming a pad layer above the first interconnection structure and the second interconnection structure, the pad layer including a first pad and a second pad, the first pad electrically connecting the first interconnection structure, and the second pad electrically connecting the second interconnection structure.

[0040] In some embodiments, before the forming, above the first interconnection structure and the second interconnection structure, a pad layer, further includes:

[0041] forming a first connection line extending along the first direction on the first interconnection structure, the first connection line extending from a first interconnection structure top end in a direction away from the memory array edge;

[0042] forming a second connection line extending along the first direction on the second interconnection structure, the second connection line extending from a second interconnection structure top end in a direction away from the memory array edge;

[0043] forming a third interconnection structure on the first connection line, the third interconnection structure being between the first connection line and the first pad;

[0044] forming a fourth interconnection structure on the second connection line, the fourth interconnection structure being between the second connection line and the second pad.

[0045] In the semiconductor structure and the preparation method thereof, the first conductive lines are arranged on the substrate, and the memory array is arranged on the first conductive lines, so that the first conductive lines are arranged below the memory array and do not occupy the space above the memory array, thereby leaving more space for the preparation of the second conductive lines, reducing the difficulty in the preparation of the first conductive lines and the second conductive lines, and improving the integration of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] Figure 1 It is a schematic diagram of a memory structure in the related art;

[0048] Figure 2 It is a flowchart of a preparation method of a semiconductor structure provided in an embodiment;

[0049] Figures 3 to 7 It is a schematic diagram of an intermediate structure obtained in the preparation process of a semiconductor structure provided in an embodiment;

[0050] Figure 8 It is a schematic diagram of a semiconductor structure provided in an embodiment;

[0051] Figure 9 It is a schematic diagram of a pad layer provided in an embodiment.

[0052] Reference numerals: semiconductor structure - 100; base - 110; substrate - 111; isolation layer - 112; first conductive line - 120; memory array - 130; transistor - 131; gate structure - 1311; channel region - 1312; source - 1313; drain - 1314; capacitor - 132; second conductive line - 140; first interconnect structure - 150; second interconnect structure - 160; pad layer - 170; first pad - 171; second pad - 172; first connection line - 181; second connection line - 182; third interconnect structure - 191; fourth interconnect structure - 192. DETAILED DESCRIPTION

[0053] For the purposes of this disclosure, reference will be made to the accompanying drawings which form a part of the disclosure. The drawings are schematic and for purposes of illustration only. Embodiments of the present disclosure will be described with the understanding that the present disclosure is not limited to the embodiments described and illustrated, but is capable of being practiced in various ways, including variations of the embodiments described herein. The terminology used herein is for the purpose of describing only the particular embodiments and is not intended to be limiting of the present disclosure.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0055] It should be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected to" another element or layer, it can be directly on or adjacent to the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0056] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0057] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", and the like are used synonymously with the term "includes" and / or "including" and / or "containing", and / or "containing", and will be understood to allow for elements, integers, steps, or groups thereof, to be present or added, but not to the exclusion of one or more other elements, integers, steps, or groups thereof.

[0058] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0059] As indicated in the background section, in the related art, as memory size is scaled down, the interconnection space for word lines and bit lines and logic circuits is limited.

[0060] As an example, in a wafer on wafer (WOW) technology, a memory array and a logic circuit can be formed on two wafers respectively, and the two wafers are interconnected by hybrid bonding or the like to form a memory. See Figure 1After the formation of the memory array 10, a word line lead-out structure 21 for leading out the word lines 11 in the memory array 10 and a bit line lead-out structure 22 for leading out the bit lines 12 in the memory array 10 can be formed, and the memory array 10 needs to be interconnected with a logic circuit on another wafer through the bit line lead-out structure 22 and the word line lead-out structure 21. Since at least one of the bit lines 12 and the word lines 11 is a horizontally extending structure, at least one of the bit line lead-out structure 22 and the word line lead-out structure 21 needs to connect the horizontally extending structures of the memory array 10 located at different layers through a step structure. Figure 1 As shown in FIG. 1, the word lines 11 are horizontally extending structures, and the word line lead-out structure 21 is connected to the word lines 11 through a word line step structure 13. However, as the number of layers of the memory array 10 increases, the step structure 13 needs to occupy a large area, which will be detrimental to the improvement of integration.

[0061] Based on this, in some embodiments, referring to Figure 2 The present disclosure provides a preparation method of a semiconductor structure 100, comprising the following steps:

[0062] Step S100: providing a substrate 110.

[0063] Step S200: forming a plurality of first conductive lines 120 extending along a first direction and arranged along a second direction on the substrate 110, the second direction intersecting the first direction.

[0064] Step S300: forming a memory array 130 on the plurality of first conductive lines 120, and forming a plurality of second conductive lines 140 extending along a third direction and arranged along the first direction, the second conductive lines 140 and the first conductive lines 120 both connecting the memory array 130, the third direction intersecting the first direction.

[0065] Step S400: forming a first interconnection structure 150 on the first conductive lines 120, and forming a second interconnection structure 160 on the second conductive lines 140, the first interconnection structure 150 and the second interconnection structure 160 both extending along a vertical direction.

[0066] In step S100, referring to Figure 3 The substrate 110 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof.

[0067] In step 200, referring to Figure 3 The plurality of first conductive lines 120 formed on the substrate 110 can be arranged in parallel.

[0068] Any first conductive line 120 extends along a first direction. And the plurality of first conductive lines 120 are arranged along a second direction, the second direction intersecting the first direction. As an example, the first direction and the second direction can be perpendicular. As an example, referring toFigure 3 The X direction can be a first direction, and the Y direction can be a second direction.

[0069] The material of the first conductive line 120 can be a conductive material. For example, the material of the first conductive line 120 can be a conductive material, such as one or more of the following: a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al)); an alloy (e.g., a Co-based alloy, a Mo-based alloy, a Ti-based alloy); a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal oxide); and a conductive doped semiconductor material (e.g., a conductive doped polysilicon, a conductive doped silicon germanium (SiGe)).

[0070] In step S300, referring to Figure 4 The memory array 130 is located above the first conductive line 120 and is connected with the first conductive line 120.

[0071] The second conductive line 140 can be formed after or during the formation of the memory array 130. The second conductive line 140 is connected with the memory array 130.

[0072] The second conductive line 140 extends along a third direction and is arranged along a first direction. The third direction intersects the first direction. The first direction, the second direction and the third direction are all directions parallel to the plane on which the substrate lies. As an example, the third direction can be perpendicular to the first direction. In this case, the third direction is in the same direction as the second direction. Of course, the third direction can be at other angles to the first direction. For example, the third direction can be at an angle of 30 degrees, 45 degrees or 60 degrees to the first direction.

[0073] There can be a plurality of second conductive lines 140, and the plurality of second conductive lines 140 can be arranged in parallel along a vertical direction. The vertical direction is a direction perpendicular to the plane on which the substrate lies.

[0074] Similarly, the material of the second conductive line 140 can be a conductive material such as a metal or a metal oxide. For example, the material of the second conductive line 140 can be copper, aluminum or silver. The material of the second conductive line 140 can be the same as the material of the first conductive line 120. Of course, the material of the second conductive line 140 can also be different from the material of the first conductive line 120.

[0075] As an example, when the memory array includes word lines extending along the vertical direction, the first conductive line 120 can be arranged to be connected with the word lines, and the second conductive line 140 can be a bit line. As another example, when the memory array includes bit lines extending along the vertical direction, the first conductive line 120 can be arranged to be connected with the bit lines, and the second conductive line 140 can be a word line. Referring to Figure 8 The Z direction can be a vertical direction.

[0076] The following exemplary describes a memory structure in which the first conductive lines 120 are connected to word lines extending in a vertical direction, and the second conductive lines 140 are bit lines.

[0077] Referring to Figure 4 , Figure 7 and Figure 8 , the first conductive lines 120 extend in a first direction and are arranged in a second direction, and the memory array 130 is located above the first conductive lines 120. The second conductive lines 140 extend in a third direction and are arranged in the first direction and the vertical direction. At this time, the third direction is in the same direction as the second direction, and the third direction (or the second direction) is perpendicular to the first direction.

[0078] The memory array 130 includes a plurality of memory cells. The plurality of memory cells are connected to both sides of the second conductive lines 140.

[0079] The memory cell includes a transistor 131 and a capacitor 132. The transistor 131 includes a gate structure 1311, a channel region 1312, a source 1313, and a drain 1314. The gate structure 1311 extends in the vertical direction and is connected to the first conductive line 120. The gate structure 1311 includes a gate and a gate dielectric layer, and the gates of the plurality of transistors 131 arranged in the vertical direction are connected to each other as a word line extending in the vertical direction. In some embodiments, referring to Figure 8 , the transistor 131 is a vertical Cylindrical Array of Annular (CAA) structure, the gate dielectric layer surrounds the gate, the channel region 1312 is disposed between the source 1313 and the drain 1314, and the channel region 1312 surrounds the gate dielectric layer between the source 1313 and the drain 1314. In other embodiments, the transistor 131 can also be a Gate-All-Around (GAA) structure, and the gate structure covers at least one side of the channel region. The present disclosure does not limit the type of transistor 131.

[0080] The capacitor 132 can include a lower plate, a capacitor dielectric layer, and an upper plate. Either the source 1313 or the drain 1314 of the transistor 131 is connected to the second conductive line 140, and the other is connected to the lower plate of the capacitor 132. As Figure 8 indicated, the source 1313 of the transistor 131 is connected to the second conductive line 140, and the drain 1314 is connected to the lower plate of the capacitor 132.

[0081] The memory cells located on opposite sides of the same second conductive line 140 are arranged in the third direction (or the second direction) with a shift, and adjacent memory cells located on opposite sides of the same second conductive line 140 are connected to adjacent first conductive lines 120.

[0082] It can be understood that, in the vertical direction (for example, Figure 8The storage units stacked in the Z direction form a storage unit group. The first conductive lines 120 are connected to the storage unit groups on opposite sides of the second conductive lines 140, respectively. In this case, the first conductive lines 120 are electrically connected to word lines, the second conductive lines 140 are bit lines, the bit lines can be shared, and the word lines need to be connected separately to control the storage unit groups, so as to select the storage units.

[0083] The word lines of the plurality of storage unit groups arranged in the first direction can be connected by the same first conductive line 120.

[0084] The size of the first conductive line 120 in the first direction is greater than the size of the storage array 130 in the first direction, and the first interconnection structure 150 connected on the adjacent first conductive line 120 is located on opposite sides of the storage array 130 in the first direction. At this time, it is convenient to arrange the first interconnection structure 150 at both ends of the first conductive line 120.

[0085] In step S400, please refer to Figure 6 The material of the first interconnection structure 150 is a conductive material, and is connected with the first conductive line 120. The first conductive line 120 is connected with other structures through the first interconnection structure 150, so that the arrangement of the first conductive line 120 is more flexible.

[0086] At the same time, the material of the second interconnection structure 160 is also a conductive material, and is connected with the second conductive line 140. The second conductive line 140 is connected with other structures through the second interconnection structure 160, so that the arrangement of the second conductive line 140 is more flexible. In the third direction in which the second conductive line 140 extends, a plurality of second interconnection structures 160 can be arranged. The projection of the plurality of second interconnection structures 160 on the substrate 111 at least partially overlaps the projection of the second conductive line 140 on the substrate 111. The projection of the second interconnection structure 160 on the substrate 111 can be located between the projections of the first conductive lines 120 on the substrate 111, and the projections of the second interconnection structures 160 on the substrate 111 are arranged at intervals with the projections of the first conductive lines 120 on the substrate 111. The lengths of the second interconnection structures 160 in the vertical direction can be different, and different second interconnection structures 160 are respectively electrically connected to second conductive lines 140 located at different layers. In this case, an electrically isolated layer can also be formed between the second interconnection structure 160 and the second conductive line 140 which is not electrically connected.

[0087] As an example, the first interconnection structure 150 and the second interconnection structure 160 can both extend in the thickness direction of the storage array 130, that is, in the vertical direction. It can be understood that the first interconnection structure 150 and the second interconnection structure 160 can extend in the same direction. Of course, the first interconnection structure 150 and the second interconnection structure 160 can also extend in different directions.

[0088] In the embodiment, the first conductive lines 120 are arranged under the memory array 130 without a step structure, so that the arrangement density of the conductive lines is improved, and the storage density is improved.

[0089] In some embodiments, the substrate 110 includes a substrate 111 and an isolation layer 112 above the substrate 111. In this case, the step S200 includes:

[0090] The step S210 includes forming a trench in the isolation layer 112.

[0091] The step S220 includes forming the first conductive lines 120 to fill the trench.

[0092] In the step S210, the material of the isolation layer 112 is an insulating material. As an example, the material of the isolation layer 112 is silicon oxide, silicon nitride or silicon oxynitride. The isolation layer 112 can better isolate the first conductive lines 120 formed later from the substrate 111.

[0093] In the step S210, the trench can be formed in the isolation layer 112 by using a dry etching method or a wet etching method. As an example, the dry etching method can include at least any one of a reactive ion etching, an inductively coupled plasma etching or a high-density plasma etching.

[0094] In the step S220, the trench is filled with a conductive material to form the first conductive lines 120. As an example, a conductive material layer can be formed by a deposition process. Then, the conductive material layer outside the trench is removed to retain the conductive material layer in the trench, so as to form the first conductive lines 120. For example, the deposition process can include but is not limited to one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process and a spin-on dielectric layer process.

[0095] In the embodiment, the trench is formed, and the first conductive lines 120 are formed by filling the trench, so that a flat upper surface can be obtained. The flat upper surface allows the memory array 130 to be formed on the flat surface, so that the performance of the memory array 130 is improved.

[0096] In another embodiment, the substrate 110 includes a substrate 111 and an isolation layer 112 above the substrate 111. The step S200 can further include:

[0097] The step S2100 includes forming a first conductive line material layer on the isolation layer 112.

[0098] The step S2200 includes performing a patterning process on the first conductive line material layer to form the first conductive lines 120.

[0099] In step S2100, a first conductive line material layer can be formed by depositing a whole surface on the isolation layer 112.

[0100] In step S2200, a mask can be formed on the first conductive line material layer, and the first conductive line material layer can be etched based on the mask to form the first conductive line 120.

[0101] In some embodiments, step S400 includes:

[0102] Step S410: forming a first interconnection structure 150 at an end of the first conductive line 120 along the first direction.

[0103] Step S400 includes:

[0104] Step S600: forming a pad layer 170 above the first interconnection structure 150 and the second interconnection structure 160, the pad layer 170 including a first pad 171 electrically connected to the first interconnection structure 150 and a second pad 172 electrically connected to the second interconnection structure 160.

[0105] In step S410, referring to Figure 6 , the size of the first conductive line 120 along the first direction is greater than the size of the storage array 130 along the first direction, facilitating the first interconnection structure 150 to be arranged at the end of the first conductive line 120 along the first direction, and the first interconnection structure 150 extends along the vertical direction.

[0106] At this time, the plurality of first interconnection structures 150 can be arranged in a staggered manner. As an example, adjacent first interconnection structures 150 corresponding to adjacent first conductive lines 120 can be located at different ends of the adjacent first conductive lines 120, respectively. The first conductive line 120 has opposite first and second ends. The first interconnection structure 150 and the first conductive line 120 are electrically connected one-to-one, and the plurality of first interconnection structures 150 are alternately located at one of the two ends of the first conductive line 120, for example, the first odd-numbered first interconnection structures 150 are located at the first ends of the corresponding first odd-numbered first conductive lines 120, and the second even-numbered first interconnection structures 150 are located at the second ends of the corresponding first odd-numbered first conductive lines 120, thereby reducing the parasitic capacitance between adjacent first interconnection structures 150. At the same time, the plurality of first interconnection structures 150 arranged in a staggered manner can make each first interconnection structure 150 have a larger preparation space, save the occupied area, and reduce the preparation difficulty. The first conductive line 120 is connected in series with a plurality of storage units arranged along the first direction, thereby being able to reduce the number of first interconnection structures 150 and the manufacturing difficulty of the first interconnection structure 150.

[0107] In other embodiments, the plurality of first interconnection structures 150 can also be located at the same end of the plurality of first conductive lines 120.

[0108] Meanwhile, the ends of the plurality of first conductive lines 120 can be aligned along the second direction, i.e., the projections of the ends of the plurality of first conductive lines 120 along the second direction coincide. Alternatively, the ends of the plurality of first conductive lines 120 can be at least partially aligned along the second direction. Exemplarily, the ends of the odd-numbered first conductive lines 120 are aligned with each other, the ends of the even-numbered first conductive lines 120 are aligned with each other, and the ends of the odd-numbered first conductive lines 120 and the ends of the even-numbered first conductive lines 120 can be staggered in the second direction to increase the space for the ends of the first conductive lines 120 to contact the first interconnection structure 150.

[0109] The height of the first interconnection structure 150 in the vertical direction is greater than the thickness of the memory array 130, thereby facilitating the formation of the first connection lines 181 connected with the first interconnection structure 150 above the memory array 130 in subsequent steps.

[0110] In step S600, referring to Figure 7 Exemplarily, the first interconnection structure 150 and the second interconnection structure 160 both extend along the vertical direction, and the top ends of the first interconnection structure 150 and the second interconnection structure 160 can be flush.

[0111] At this time, the first pads 171 can be formed at the ends of the first interconnection structure 150 or the ends of the first connection lines 181 connected with the first interconnection structure 150, and the second pads 172 can be formed at the ends of the second interconnection structure 160. The first pads 171 and the second pads 172 can be staggered in height or can be flush. The first pads 171 and the second pads 172 constitute the pad layer 170.

[0112] In the present embodiment, the pad layer 170 can be used to connect the logic circuit on the driving substrate. The first pads 171 and the second pads 172 can be used for welding or bonding with the driving substrate.

[0113] In some embodiments, before step S600, the following steps are included:

[0114] Step S500: forming first connection lines 181 extending along the first direction on the first interconnection structure 150, the first connection lines 181 extending from the outer periphery of the memory array 130 to the inner part of the memory array 130.

[0115] Step S510: forming second connection lines 182 extending along the first direction on the second interconnection structure 160, the second connection lines 182 extending from the outer periphery of the memory array 130 to the inner part of the memory array 130.

[0116] Step S520: Forming a third interconnection structure 191 on the first connection line 181, the third interconnection structure 191 is between the first connection line 181 and the first pad 171.

[0117] Step S530: Forming a fourth interconnection structure 192 on the second connection line 182, the fourth interconnection structure 192 is between the second connection line 182 and the second pad 172.

[0118] In step S500, referring to Figure 6 and Figure 7 , a first dielectric layer covering the second conductive line 140 and the memory array 130 can be formed first, and then the first dielectric layer is etched to form a plurality of first trenches extending from the outer periphery of the memory array 130 to the inner part of the memory array 130. The first trenches are filled with conductive material to form the first connection line 181.

[0119] When the plurality of first interconnection structures 150 are staggered, the plurality of corresponding first connection lines 181 extend from the opposite outer periphery of the memory array 130 to the inner part of the memory array 130.

[0120] Of course, when the plurality of first interconnection structures 150 are on the same side of the first conductive line 120, the plurality of corresponding first connection lines 181 extend from the same side of the outer periphery of the memory array 130 to the inner part of the memory array 130.

[0121] In step S510, similarly, the second connection line 182 extending in the first direction is formed at the end of the second interconnection structure 160. The second connection line 182 extends in the direction from the outer periphery of the memory array 130 to the inner part of the memory array 130.

[0122] The process of forming the second connection line 182 is similar to that of forming the first connection line 181, which will not be described in detail here.

[0123] In step S520, the third interconnection structure 191 is connected to the end of the first connection line 181, and the third interconnection structure 191 can be distributed in the vertical direction.

[0124] As an example, after forming the first connection line 181 and the second connection line 182, a second dielectric layer covering the first connection line 181 and the second connection line 182 can be formed. Etching the second dielectric layer forms a plurality of vias, the plurality of vias expose the first connection line 181. Filling the plurality of vias forms the third interconnection structure 191.

[0125] After forming the third interconnection structure 191, the first pad 171 is formed at the top end of the third interconnection structure 191.

[0126] In step S530, the fourth interconnection structure 192 is also connected with the end of the second connection line 182, and the fourth interconnection structure 192 can also extend in the vertical direction.

[0127] The forming process of the fourth interconnection structure 192 is similar to that of the third interconnection structure 191, and thus will not be described in detail here.

[0128] After the fourth interconnection structure 192 is formed, the second pad 172 is formed at the top end of the fourth interconnection structure 192.

[0129] In this embodiment, by forming the first connection line 181 and the second connection line 182, not only can the positions of the pads in the pad layer 170 be arranged more flexibly, so that the first interconnection structure 150 and the second interconnection structure 160 avoid other structures, but also the pad layer 170 can be conveniently arranged in a dispersed manner.

[0130] Of course, the first connection line 181 and the second connection line 182 can be formed at the same time. The third interconnection structure 191 and the fourth interconnection structure 192 can also be formed at the same time.

[0131] In some embodiments, the third interconnection structures 191 located on different first connection lines 181 are arranged in an interleaved manner.

[0132] The first connection line 181 extends in the first direction, and a plurality of first connection lines 181 are arranged in the second direction. At this time, as an example, the lengths of the plurality of first connection lines 181 arranged in the second direction increase in turn. Alternatively, the lengths of the plurality of first connection lines 181 arranged in the second direction decrease in turn. Alternatively, the lengths of the plurality of first connection lines 181 arranged in the second direction can also be arranged in an interval of long and short.

[0133] At this time, the first pads 171 connected with the third interconnection structures 191 are also arranged in an interleaved manner, so that the plurality of first pads 171 can be distributed more uniformly.

[0134] In another embodiment, the fourth interconnection structures 192 located on different second connection lines 182 can also be arranged in an interleaved manner. Similarly, the second pads 172 connected with the fourth interconnection structures 192 are also arranged in an interleaved manner.

[0135] In another embodiment, referring to Figure 9 , the first pads 171 and the second pads 172 can also be arranged in an aligned manner.

[0136] It should be understood that, although Figure 2 the steps in the flowchart are shown in order according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover,Figure 2 At least one of the steps in the method can include multiple steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times, and the order of the steps or stages is not necessarily sequential, but can be performed alternately or alternately with at least one of the other steps or steps or stages.

[0137] Please continue to see Figure 8 The present disclosure also provides a semiconductor structure 100, comprising: a substrate 110, a first conductive line 120, a memory array 130, a second conductive line 140, a first interconnection structure 150, a second interconnection structure 160.

[0138] The substrate 110 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof.

[0139] The first conductive line 120 is located on the substrate 110. The first conductive line 120 extends along a first direction, and a plurality of first conductive lines 120 are arranged along a second direction.

[0140] The first direction intersects the second direction. As an example, the first direction and the second direction can be perpendicular.

[0141] The material of the first conductive line 120 can be a conductive material, such as one or more of the following: metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al)); alloy (e.g., Co-based alloy, Mo-based alloy, Ti-based alloy); conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal oxide); and conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped silicon germanium (SiGe)).

[0142] The memory array 130 is located on the first conductive line 120, and the memory array 130 is connected to the first conductive line 120.

[0143] The second conductive line 140 connects the memory array 130 and extends along a third direction. The first direction intersects the third direction. As an example, the first direction and the third direction can be perpendicular. It can be understood that the third direction and the second direction can be in the same direction. Of course, the third direction can be at other angles to the first direction. For example, the third direction and the first direction are at an angle of 30 degrees, 45 degrees, or 60 degrees, etc.

[0144] Similarly, the material of the second conductive line 140 can be a conductive material such as metal or metal oxide. For example, the material of the second conductive line 140 is copper, aluminum, or silver. The material of the second conductive line 140 can be the same as the material of the first conductive line 120. Of course, the material of the second conductive line 140 can also be different from the material of the first conductive line 120.

[0145] When the semiconductor structure 100 is a memory, the first conductive lines 120 can be electrically connected to word lines, or can be electrically connected to bit lines. When the first conductive lines 120 are electrically connected to word lines, the second conductive lines 140 are bit lines; conversely, when the first conductive lines 120 are electrically connected to bit lines, the second conductive lines 140 are word lines.

[0146] The following exemplary describes a memory structure when the first conductive lines 120 are electrically connected to word lines, and the second conductive lines 140 are bit lines.

[0147] The first conductive lines 120 extend along a first direction and are arranged along a second direction, and the memory array 130 is located above the first conductive lines 120. The second conductive lines 140 extend along a third direction and are arranged along the first direction and a vertical direction. At this time, the third direction is in the same direction as the second direction, and the third direction (or the second direction) is perpendicular to the first direction.

[0148] The memory array 130 includes a plurality of memory cells. The memory array 130 includes a plurality of memory cells arranged in the first direction, the second direction, and the vertical direction. Each of the first conductive lines 120 is electrically connected to at least two memory cells arranged along the first direction, and two memory cells electrically connected by adjacent first conductive lines 120 can be connected to the same second conductive line 140. The plurality of memory cells arranged along the first direction and the vertical direction can be led out by one second conductive line 140 and connected to other structures, thereby improving interconnection efficiency.

[0149] The memory cell includes a transistor 131 and a capacitor 132. The gate structure 1311 of the transistor 131 extends along the vertical direction and is connected to the first conductive line 120. The gate structure 1311 includes a gate and a gate dielectric layer. The gate dielectric layer 1312 surrounds the gate. The channel region 1312 is provided between the source 1313 and the drain 1314, and the gate dielectric layer surrounds the source 1313 and the drain 1314 between the source 1313 and the drain 1314.

[0150] The capacitor 132 can include a lower plate, a capacitor dielectric layer, and an upper plate. Either the source 1313 or the drain 1314 of the transistor 131 is connected to the second conductive line 140, and the other is connected to the lower plate of the capacitor. As shown, the source 1313 of the transistor 131 is connected to the second conductive line 140, and the drain 1314 is connected to the lower plate of the capacitor 132. Figure 8

[0151] The memory cells located on opposite sides of the same second conductive line 140 are arranged in the third direction (or the second direction) with a staggered arrangement, and adjacent memory cells located on opposite sides of the same second conductive line 140 are connected to adjacent first conductive lines 120.

[0152] It can be understood that, in the vertical direction (for example,​Figure 8 The storage units stacked along the Z direction constitute a storage unit group, and the adjacent first conductive lines 120 are connected to the storage unit groups on opposite sides of the second conductive line 140. Exemplarily, at this time, the first conductive line 120 is electrically connected to a word line, and the second conductive line 140 is a bit line. The bit lines can be shared, and the word lines need to be connected separately to control the storage unit group, so as to select the storage unit.

[0153] The word lines of the plurality of storage unit groups arranged along the first direction can be connected by the same first conductive line 120.

[0154] The size of the first conductive line 120 along the first direction is greater than the size of the storage array 130 along the first direction, and the first interconnection structure 150 connected on the adjacent first conductive line 120 is located on opposite sides of the storage array 130 along the first direction.

[0155] The first interconnection structure 150 is located on the first conductive line 120 and is electrically connected to the first conductive line 120. The second interconnection structure 160 is located on the second conductive line 140 and is connected to the second conductive line 140. The first conductive line 120 is connected to other structures through the first interconnection structure 150, so that the arrangement of the first conductive line 120 is more flexible.

[0156] Meanwhile, the material of the second interconnection structure 160 is also a conductive material and is connected to the second conductive line 140. The second conductive line 140 is connected to other structures through the second interconnection structure 160, so that the arrangement of the second conductive line 140 is more flexible.

[0157] As an example, the first interconnection structure 150 and the second interconnection structure 160 can both extend along the vertical direction. At this time, the first interconnection structure 150 and the second interconnection structure 160 can both extend along the vertical direction. Please refer to Figure 8 , the Z direction can be a vertical direction. It can be understood that the first interconnection structure 150 and the second interconnection structure 160 can extend in the same direction. Of course, the first interconnection structure 150 and the second interconnection structure 160 can also extend in different directions.

[0158] In this embodiment, the first conductive line 120 is arranged below the storage array 130, and the second conductive line 140 is arranged above the storage array 130. Not only does this reduce the difficulty of manufacturing the first conductive line 120 and the second conductive line 140, but it also eliminates the need for a step structure, improves the arrangement density of the conductive lines, and improves the integration of the semiconductor structure.

[0159] In some embodiments, the substrate 110 includes a substrate 111 and an isolation layer 112 located above the substrate 111. The isolation layer 112 is located between the substrate 111 and the first conductive line 120. At this time, the first conductive line 120 is located on the upper surface of the isolation layer 112.

[0160] The material of the isolation layer 112 is an insulating material. As an example, the material of the isolation layer 112 is silicon oxide, silicon nitride or silicon oxynitride. The isolation layer 112 can better isolate the first conductive lines 120 formed later from the substrate 111.

[0161] In another embodiment, the isolation layer 112 is provided with a trench, and the first conductive lines 120 are located in the trench of the isolation layer 112.

[0162] In this embodiment, the first conductive lines 120 are formed by forming a trench and filling the trench, so that a flat upper surface can be obtained. The flat upper surface allows the storage array 130 to be formed on the flat surface, thereby improving the performance of the storage array 130.

[0163] In some embodiments, the first interconnection structure 150 is located at the end of the first conductive line 120. The semiconductor structure 100 further includes a pad layer 170.

[0164] The size of the first conductive line 120 along the first direction is greater than the size of the storage array 130 along the first direction, so as to facilitate the first interconnection structure 150 to be arranged at the end of the first conductive line 120 along the first direction, and the first interconnection structure 150 extends along the vertical direction.

[0165] At this time, the plurality of first interconnection structures 150 or the plurality of second interconnection structures 160 can be arranged in a staggered manner. As an example, the adjacent first interconnection structures 150 corresponding to the adjacent first conductive lines 120 can be located at different ends of the adjacent first conductive lines 120, respectively. The first conductive line 120 has opposite first and second ends. The plurality of first interconnection structures 150 are alternately located at one of the two ends of the first conductive line 120, and the odd-numbered first interconnection structures 150 are located at the first end of the first conductive line 120, and the even-numbered first interconnection structures 150 are located at the second end of the first conductive line 120, thereby reducing the parasitic capacitance between the adjacent first interconnection structures 150. At the same time, the plurality of first interconnection structures 150 arranged in a staggered manner can make each first interconnection structure 150 have a larger preparation space, save the occupied area, and reduce the preparation difficulty.

[0166] Of course, the plurality of first interconnection structures 150 can also be located at the same end of the plurality of first conductive lines 120.

[0167] Meanwhile, the ends of the plurality of first conductive lines 120 can be aligned in the second direction. Alternatively, the ends of the plurality of first conductive lines 120 can be at least partially aligned in the second direction. For example, the ends of the odd-numbered first conductive lines 120 can be aligned with each other, the ends of the even-numbered first conductive lines 120 can be aligned with each other, and the ends of the odd-numbered first conductive lines 120 and the ends of the even-numbered first conductive lines 120 can be staggered in the second direction to increase the space for the ends of the first conductive lines 120 to contact the first interconnection structure 150.

[0168] The first interconnection structure 150 and the second interconnection structure 160 extend in the vertical direction, and the top ends of the first interconnection structure 150 and the second interconnection structure 160 are flush. The height of the first interconnection structure 150 in the vertical direction is greater than the thickness of the memory array 130, so as to facilitate the formation of the first connection line 181 connected to the first interconnection structure 150 in a subsequent step.

[0169] The pad layer 170 is located above the first interconnection structure 150 and the second interconnection structure 160, and the pad layer 170 includes a first pad 171 electrically connected to the first interconnection structure 150 and a second pad 172 electrically connected to the second interconnection structure 160.

[0170] At this time, the first pad 171 is formed at the end of the first interconnection structure 150, and the second pad 172 is formed at the end of the second interconnection structure 160. The first pad 171 and the second pad 172 can be staggered in height or flush.

[0171] In the embodiment, the pad layer 170 is used to connect devices such as logic circuits. The flush first pad 171 and the second pad 172 can be used for welding or bonding with a driving substrate.

[0172] In some embodiments, the semiconductor structure 100 further includes a first connection line 181, a second connection line 182, a third interconnection structure 191, and a fourth interconnection structure 192.

[0173] The first connection line 181 contacts the top end of the first interconnection structure 150 and extends in a direction from the outer periphery of the memory array 130 to the inner part of the memory array 130.

[0174] The third interconnection structure 191 is located between the first connection line 181 and the first pad 171.

[0175] The second connection line 182 contacts the top end of the second interconnection structure 160 and extends in a direction from the outer periphery of the memory array 130 to the inner part of the memory array 130.

[0176] The fourth interconnection structure 192 is located between the second connection line 182 and the second pad 172.

[0177] In the embodiment, by forming the first connection lines 181 and the second connection lines 182, not only can the positions of the pads in the pad layer 170 be arranged more flexibly, so that the first interconnection structure 150 and the second interconnection structure 160 avoid other structures, but also the pad layer 170 can be arranged more evenly.

[0178] In some embodiments, the third interconnection structures 191 located on different first connection lines 181 are arranged in an interleaved manner.

[0179] The first connection lines 181 extend along a first direction, and a plurality of the first connection lines 181 are arranged along a second direction. At this time, as an example, the lengths of the plurality of the first connection lines 181 arranged along the second direction increase in turn. Alternatively, the lengths of the plurality of the first connection lines 181 arranged along the second direction decrease in turn. Alternatively, the lengths of the plurality of the first connection lines 181 arranged along the second direction can also be arranged in an alternating manner.

[0180] At this time, the first pads 171 connected with the third interconnection structures 191 are also arranged in an interleaved manner, so that the plurality of the first pads 171 can be arranged more evenly.

[0181] In another embodiment, the fourth interconnection structures 192 located on different second connection lines 182 can also be arranged in an interleaved manner. Similarly, the second pads 172 connected with the fourth interconnection structures 192 are also arranged in an interleaved manner.

[0182] In another embodiment, referring to Figure 9 , the first pads 171 and the second pads 172 can also be arranged in an aligned manner.

[0183] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features of the above embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as falling within the scope of the present disclosure.

[0184] The above-described embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope. It should be noted that, for those skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which all belong to the protection scope of the present disclosure. Therefore, the patent protection scope of the present disclosure should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a plurality of first conductive lines on the substrate, the first conductive lines extending along a first direction, and a plurality of the first conductive lines arranged along a second direction intersecting the first direction; a memory array on the first conductive lines and connected to the first conductive lines; a plurality of second conductive lines connected to the memory array, the second conductive lines extending along a third direction intersecting the first direction, and a plurality of the second conductive lines arranged along a vertical direction, the memory array comprising memory cells on opposite sides of each of the second conductive lines along the first direction, the memory cells on opposite sides of the same second conductive line being arranged staggered along the third direction; a first interconnection structure extending along the vertical direction and on the first conductive lines, and electrically connected to the first conductive lines; a second interconnection structure extending along the vertical direction and on the second conductive lines, and electrically connected to the second conductive lines.

2. The semiconductor structure of claim 1, wherein, The substrate comprises a substrate and an isolation layer between the substrate and the first conductive lines; the first conductive lines are on a top surface of the isolation layer, or the first conductive lines are in trenches of the isolation layer.

3. The semiconductor structure of claim 1, wherein, The first interconnection structure is on an end of the first conductive line, and the semiconductor structure further comprises: a pad layer above the first interconnection structure and the second interconnection structure, the pad layer comprising a first pad electrically connected to the first interconnection structure and a second pad electrically connected to the second interconnection structure.

4. The semiconductor structure of claim 1, wherein, A plurality of the second conductive lines are arranged along the first direction, and the memory cells on opposite sides of the same second conductive line are connected to adjacent first conductive lines; a dimension of the first conductive lines along the first direction is greater than a dimension of the memory array along the first direction, and the first interconnection structures connected on adjacent first conductive lines are respectively on opposite sides of the memory array along the first direction.

5. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises: a first connection line in contact with a top end of the first interconnection structure and extending from an outer periphery of the memory array to an inner part of the memory array; a third interconnection structure extending along the vertical direction and between the first connection line and the first pad; a second connection line in contact with a top end of the second interconnection structure and extending from an outer periphery of the memory array to an inner part of the memory array; a fourth interconnection structure extending along the vertical direction and between the second connection line and the second pad.

6. The semiconductor structure of claim 5, wherein, The third interconnection structures on different first connection lines are arranged staggered; The first connection lines extend along the first direction and a plurality of the first connection lines are arranged along the second direction, and lengths of the first connection lines arranged along the second direction increase or decrease in turn.

7. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; forming a plurality of first conductive lines on the substrate, the first conductive lines extending along a first direction and arranged along a second direction intersecting the first direction; forming a storage array on the plurality of first conductive lines, and forming a plurality of second conductive lines extending along a third direction and arranged along a first direction, the second conductive lines being connected to the storage array as the first conductive lines, the plurality of second conductive lines being arranged along a vertical direction, the storage array comprising storage units located on opposite sides of each of the second conductive lines along the first direction, the storage units located on opposite sides of the same second conductive line being arranged in a staggered manner along the third direction, the third direction intersecting the first direction; forming a first interconnection structure on the first conductive lines, and forming a second interconnection structure on the second conductive lines, the first interconnection structure and the second interconnection structure extending along the vertical direction.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The substrate comprises a substrate and an isolation layer. The forming of the plurality of first conductive lines extending along a first direction and arranged along a second direction on the substrate comprises: forming a trench in the isolation layer; forming the first conductive lines to fill the trench; Alternatively, The forming of the plurality of first conductive lines extending along a first direction and arranged along a second direction on the substrate comprises: forming a first conductive line material layer on the isolation layer; performing a patterning process on the first conductive line material layer to form the first conductive lines.

9. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The forming of the first interconnection structure on the first conductive lines, and the forming of the second interconnection structure on the second conductive lines comprises: forming the first interconnection structure on end portions of the first conductive lines along the first direction; after the forming of the first interconnection structure on the first conductive lines, and the forming of the second interconnection structure on the second conductive lines, the method further comprises: forming a pad layer above the first interconnection structure and the second interconnection structure, the pad layer comprising a first pad and a second pad, the first pad being electrically connected to the first interconnection structure, and the second pad being electrically connected to the second interconnection structure.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: Before the forming of the pad layer above the first interconnection structure and the second interconnection structure, the method further comprises: forming a first connection line extending along the first direction on the first interconnection structure, the first connection line extending in a direction from an outer periphery of the storage array to an inner portion of the storage array; forming a second connection line extending along the first direction on the second interconnection structure, the second connection line extending in a direction from an outer periphery of the storage array to an inner portion of the storage array; forming a third interconnection structure on the first connection line, the third interconnection structure being located between the first connection line and the first pad; forming a fourth interconnection structure on the second connection line, the fourth interconnection structure being located between the second connection line and the second pad.

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