Embedded storage structure, resistive random access memory and preparation method thereof

Abstract

The present invention discloses an embedded storage structure, a resistive random access memory and a method for preparing the same, belonging to the field of semiconductors. The present invention first prepares a first intermetallic dielectric layer on an interlayer dielectric layer of a first semiconductor structure; prepares a first metal circuit and a first electrode plate in the first intermetallic dielectric layer; continues to prepare a first barrier layer; uses an etching process to open the first intermetallic dielectric in an area on one side of the first electrode plate to form a first groove; deposits resistive random access material and conductive metal material in sequence; flattens and rests on the first barrier layer to obtain an embedded storage structure. The present invention prepares a resistive random access memory unit that changes the orientation of the electrode plate through a completely new process sequence, and prepares a resistive random access memory using this structure, making the resistive random access memory compact as a whole and compatible with the MOS process in the prior art. After simulation verification, the present invention has strong reliability and operability, and has a high production yield.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors and relates to a resistive random access memory technology, in particular to an embedded storage structure, a resistive random access memory and a preparation method thereof. Background Art

[0002] Resistive Random Access Memory (RRAM) is a type of non-volatile memory. The RRAM cell is the core of RRAM technology. It typically adopts a structure similar to a parallel plate capacitor, namely a sandwich structure formed by a top electrode (TE), a switch layer (SW), and a bottom electrode (BE) stacked across the thickness of the wafer. The top and bottom electrodes are conductive metals, and the BE is typically a transition metal oxide. An external electric field induces the formation of conductive filament channels based on oxygen vacancies in the oxide BE. Under the stimulation of the external electric field, the BE undergoes a reversible transition between high and low resistance states, and the high and low resistance states are maintained after the electric field is removed. In specific use, the forming process refers to the process by which the RRAM first transitions from its initial high-resistance state to a low-resistance state. Conversely, the RRAM in the low-resistance state can be converted to a high-resistance state after a certain voltage is applied. The transition from a low-resistance state to a high-resistance state is called a reset. After the reset process, the RRAM that enters the high-resistance state can also be converted to the low-resistance state by applying voltage stimulation. This process is different from the first high-resistance state jump to the low-resistance state and is called the Set (reset) process.

[0003] In terms of process implementation, this sandwich structure can usually be directly embedded in the back-end of Line (BEOL) between two metal layers. Although it is directly compatible with existing processes, the process development implementation requires the re-embedding of RRAM structure development, and the inter-metal dielectric (IMD) between the two metal layers will become thicker. The corresponding connecting vias (Via) in the interconnect structure cannot reuse the existing process and need to be redeveloped, which invisibly causes the process cycle and cost of secondary development.

[0004] Therefore, it is necessary to improve and develop the structure of the resistive memory unit to reduce costs, improve structural compactness and yield while being compatible with existing CMOS processes. Summary of the Invention

[0005] One of the objectives of the present invention is to provide an embedded memory structure that reduces design and manufacturing costs while retaining the advantages of RRAM.

[0006] Another object of the present invention is to provide a method for preparing an embedded storage structure, which can be used to manufacture the above-mentioned embedded storage structure with high quality in a low-cost manner, thereby shortening the product development cycle, reducing costs and improving competitiveness.

[0007] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0008] A method for preparing an embedded storage structure comprises the following steps:

[0009] Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer;

[0010] forming a first intermetallic dielectric layer on the interlayer dielectric layer;

[0011] preparing a first metal circuit and a first electrode plate in a first intermetallic dielectric layer;

[0012] forming a first barrier layer on the first metal interconnection layer;

[0013] Using an etching process to open the first intermetallic dielectric in a region on one side of the first electrode plate to form a first groove;

[0014] Filling the first groove with a resistive material;

[0015] Depositing a conductive metal material on the resistive material until the first groove is filled;

[0016] The first barrier layer is used as a stop layer, and a planarization process is used to planarize the resistive material and the conductive metal material and keep them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit.

[0017] Furthermore, preparing a first intermetallic dielectric layer on the interlayer dielectric layer includes the following steps:

[0018] forming a second barrier layer on the interlayer dielectric layer of the first semiconductor structure;

[0019] An intermetallic dielectric material is deposited on the second barrier layer to form a first intermetallic dielectric layer.

[0020] Furthermore, preparing a first metal circuit and a first electrode plate in the first intermetallic dielectric layer includes the following steps:

[0021] Using an etching process to prepare a metal line groove and a first electrode plate groove on the first intermetallic dielectric layer;

[0022] The metal line groove and the first electrode plate groove are filled with conductive material and planarized to obtain a first metal line and a first electrode plate.

[0023] Furthermore, the thickness of the first electrode plate is 5-100 nm.

[0024] Furthermore, the thickness of the resistive material deposited in the first groove is 3-30 nm.

[0025] Furthermore, the resistive material filled in the first groove is transition metal oxide, lanthanide metal oxide, or metal oxide of Group IV, V, or VI.

[0026] Furthermore, the first electrode plate and the second electrode plate are made of metal conductive material or metal nitride conductive material.

[0027] Furthermore, a second metal interconnection layer is prepared on the first metal interconnection layer on which the resistive switching unit is prepared, and the electrode plate is led out using the second metal interconnection layer.

[0028] Furthermore, the second metal interconnection layer includes at least a second metal circuit, a first electrode plate lead and a second electrode plate lead, the second metal circuit is used to conduct with the first metal circuit, and the first electrode plate lead and the second electrode plate lead lead out the first electrode plate and the second electrode plate respectively.

[0029] Furthermore, by selecting the relative orientation of the first groove and the first electrode plate, the first electrode plates or the second electrode plates of two adjacent resistive switching units are arranged adjacent to each other.

[0030] On the other hand, the present invention provides an embedded storage structure prepared by the above preparation method.

[0031] In another aspect, the present invention provides a method for preparing an embedded storage structure, comprising the following steps:

[0032] Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer;

[0033] sequentially preparing a plurality of metal interconnection layers on the interlayer dielectric layer;

[0034] forming an intermetallic dielectric layer on the topmost metal interconnect layer;

[0035] preparing a first metal circuit and a first electrode plate in the intermetallic dielectric layer;

[0036] forming a first barrier layer on the intermetallic dielectric layer;

[0037] An etching process is used to open the intermetallic dielectric in a region on one side of the first electrode plate to form a first groove;

[0038] Filling the first groove with a resistive material;

[0039] Depositing a conductive metal material on the resistive material until the first groove is filled;

[0040] The first barrier layer is used as a stop layer, and a planarization process is used to planarize the resistive material and the conductive metal material and keep them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] By changing the orientation of the electrode plates of the resistive memory cell, the present invention replaces the stacked electrode plates used in the prior art with vertically inserted plates (perpendicular to the direction of the semiconductor substrate). This creates a completely new resistive memory cell structure, which, together with the resistive logic unit used in the prior art, can form a complete resistive memory. This unexpected technical effect avoids the prior art situation in which the insertion of the resistive memory cell requires changes to the existing process between the two metal interconnect layers, requiring redevelopment. This solution is compatible with the prior art MOS process and makes the resistive memory more compact. Simulations have shown that the reliability and operability of the present invention are no different from those of the conventional prior art solution stacked along the wafer thickness, and the read and write speeds are faster than those of the prior art solution under the same conditions.

[0043] The present invention creatively changes the preparation order of the electrode plates, first inserting and manufacturing the first electrode plate, and then inserting and manufacturing the second electrode plate and the resistive material together, thereby solving the problem that when the resistive electrode plate is embedded in a parallel direction, it is difficult to control lateral damage to the electrode plate and the resistive layer when etching and cutting the electrode plate in the vertical direction during the separate deposition and etching of the resistive layer. In the manufacturing method of the present invention, although the resistive material completely wraps the bottom and all sides of the second electrode plate, the unexpected technical effect is: it has been verified that the present invention can still complete the preparation of the resistive unit with high quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of a common RRAM structure in the prior art.

[0045] Figure 2 Schematic diagram of a resistive memory unit embedded in a first metal interconnection layer in an embodiment of the present invention.

[0046] Figure 3 Schematic diagram of metal line wiring in a top view of the second metal interconnection layer 1 in an embodiment of the present invention.

[0047] Figure 4 Schematic diagram of preparing the third metal interconnect layer for the embedded storage structure in Example 1.

[0048] Figure 5 This is a flow chart of preparing an embedded storage structure in the first metal interconnection layer in Example 2 of the present invention.

[0049] Figure 6 This is a schematic diagram of the first semiconductor structure provided in Example 2 of the present invention.

[0050] Figure 7 This is a schematic diagram of preparing a second barrier layer on the first semiconductor structure in Example 2 of the present invention.

[0051] Figure 8 Schematic diagram of preparing a first intermetallic dielectric layer on the second barrier layer in Example 2 of the present invention.

[0052] Figure 9 Schematic diagram of cutting grooves on the first intermetallic dielectric in embodiment 2 of the present invention.

[0053] Figure 10 This is a schematic diagram of the preparation of the electrode plate in the first metal interconnection layer in Example 2 of the present invention.

[0054] Figure 11 Schematic diagram of preparing a first barrier layer on the first metal interconnection layer in Example 2 of the present invention.

[0055] Figure 12 This is a schematic diagram of coating a photoresist layer on the first barrier layer and completing patterning of the photoresist layer in Example 2 of the present invention.

[0056] Figure 13 This is a schematic diagram of opening a first groove on the first metal interconnection layer in Example 2 of the present invention.

[0057] Figure 14 This is a schematic diagram of filling the resistive material in the first groove in Example 2 of the present invention.

[0058] Figure 15 Schematic diagram of the preparation of the first metal interconnection layer after planarizing the resistive charging material in Example 2 of the present invention.

[0059] Figure 16 Schematic diagram of preparing a second intermetallic dielectric layer on the first metal interconnect layer in Example 2 of the present invention.

[0060] Figure 17 This is a flow chart of preparing an embedded storage structure in the second metal interconnection layer in Example 3 of the present invention.

[0061] Figure 18 This is a schematic diagram of embedding a resistive memory unit in the second metal interconnect layer in Example 3 of the present invention.

[0062] Figure 19 This is a schematic diagram of preparing a fourth metal interconnection layer on the third metal interconnection layer in Example 3 of the present invention.

[0063] 30-RRAM cell, 30a-bottom electrode, 30b-resistive layer, 30c-top electrode, 30d-interlayer dielectric layer;

[0064] 100 - first semiconductor structure; 110 - semiconductor substrate, 120 - STI structure, 130 - source, 140 - drain, 150 - gate, 160 - interlayer dielectric layer, 170 - contact hole;

[0065] 200 - first metal interconnect layer, 210 - second barrier layer, 220 - first intermetallic dielectric layer, 230 - first metal line, 231 - first source lead, 232 - first drain lead, 240 - first groove, 241 - first metal line groove, 242 - first plate groove;

[0066] 300 - resistive memory unit, 310 - first electrode plate, 320 - resistive layer, 321 - resistive material, 330 - second electrode plate; 340 - photoresist layer, 331 - conductive metal material;

[0067] 400 - second metal interconnect layer, 410 - first barrier layer, 420 - second intermetallic dielectric layer, 430 - second metal line, 431 - second source lead, 432 - second drain lead, 440 - first plate lead, 450 - second plate lead;

[0068] 500 - third metal interconnect layer; 510 - third metal line, 520 - first plate lead, 530 - second plate lead;

[0069] 600 - fourth metal interconnection layer, 610 - fourth metal line. DETAILED DESCRIPTION

[0070] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0071] In the description of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0072] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integral connection; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0073] like Figure 1 The above is a common structure of RRAM in the prior art. Figure 1 The first semiconductor structure 100 shown has a MOS cell. The MOS cell includes an active region isolated on a semiconductor substrate 110 by two STI structures 120 (shallow trench isolation structures). A source 130, a drain 140, and a gate 150 are provided in the active region. The gate 150 is protected by an interlayer dielectric layer 160. The source 130 and the drain 140 are led out through contact holes 170. A first metal interconnect layer 200 is provided on the interlayer dielectric layer 160. A first metal line 230 for leading out of the MOS cell is provided on the first metal interconnect layer 200. It should be noted that Figure 1 This is just a schematic diagram. Multiple MOS units can be provided as needed, and the lead connection method of the MOS unit is not limited to the structure in the figure. For example, Figure 1 Only the source and drain leads are shown in the figure, but there must be a gate lead in reality. A second metal interconnect layer 400 is provided above the first metal interconnect layer 200, and a second metal line 430 is provided in the second metal interconnect layer 400. The RRAM cell 30 is provided between the first metal interconnect layer 200 and the second metal interconnect layer 400, and is wrapped by an interlayer dielectric layer 30d (IMD). The RRAM cell 30 includes a bottom electrode 30a, a resistive switching layer 30b, and a top electrode 30c stacked on the barrier layer 20 in the thickness direction. The bottom electrode 30a is connected to the first metal line 230 through a via. The top electrode 30c is connected to the first metal line 230 through a via. The second metal line 430 is conductive. In this structure, due to the limitation that the growth of the semiconductor structure is all deposited in the thickness direction, the conventional art usually designs RRAM cells stacked in the thickness direction, that is, the bottom electrode 30a, the resistive layer 30b and the top electrode 30c are all flat structures and parallel to the semiconductor substrate 110. As a result, an RRAM cell needs to be designed between the first metal interconnect layer 200 and the second metal interconnect layer 400. The connecting through hole cannot reuse the existing process and a new process needs to be developed, which invisibly increases the process cycle and cost of secondary development.

[0074] In order to solve the above problems, the present invention redesigns the RRAM unit and provides an embedded storage structure prepared on a semiconductor structure, such as Figures 2 to 4As shown, Figure 2 A semiconductor structure is shown having a MOS cell. The MOS cell includes an active region isolated on a semiconductor substrate 110 by two STI structures 120 (shallow trench isolation structures). A source 130, a drain 140, and a gate 150 are provided in the active region. The gate 150 is protected by an interlayer dielectric layer 160. The source 130 and the drain 140 are led out through contact holes 170. A first metal interconnect layer 200 is provided on the interlayer dielectric layer 160. A first metal line 230 for leading out of the MOS cell is provided on the first metal interconnect layer 200. It should be noted that Figure 2 This is just a schematic diagram. Multiple MOS units can be provided as needed, and the lead connection method of the MOS unit is not limited to the structure in the figure. For example, Figure 2 Only the source and drain leads are shown; in practice there must also be a gate lead.

[0075] In this embodiment, the resistive memory unit 300 is embedded in one of the metal interconnection layers, for example, the first metal interconnection layer 200 is embedded in the resistive memory unit 300. Figures 2 to 3 As shown, the resistive memory unit 300 includes:

[0076] A first electrode plate 310 , vertically embedded in the first metal interconnect layer 200 ;

[0077] A second electrode plate 330 , parallel to and opposite to the first electrode plate 310 , is embedded in the first metal interconnection layer 200 ; and

[0078] The resistive layer 320 is embedded between the first electrode plate 310 and the second electrode plate 330 .

[0079] By changing the orientation of the electrode plates of the resistive memory cell, the present invention replaces the stacked electrode plates of the prior art with vertically inserted ones. Specifically, the electrode plates are positioned perpendicular to the panel direction of the semiconductor substrate 110 (or perpendicular to the layer direction of the metal interconnect layer). This results in a completely new resistive memory cell 300 structure, which, together with the resistive logic unit of the prior art, can form a complete resistive memory. This unexpected technical effect avoids the need to redevelop the existing process between the two metal interconnect layers after inserting the resistive memory cell, which is a problem in the prior art. This solution is compatible with the existing MOS process and makes the resistive memory more compact. Simulations have shown that the reliability and operability of the present invention are no significantly different from those of the conventional solution stacked along the wafer thickness, and the read and write speeds are faster than those of the prior art under the same conditions.

[0080] In order to demonstrate the functional integrity, the first metal interconnection layer 200 is further provided with a first metal line 230, such as Figure 2As shown, it at least includes a first source lead 231 and a first drain lead 232, which are respectively connected to the source 130 and the drain 140 of the MOS unit through the contact hole 170; in order to electrically connect and lead out the resistive memory unit 300, a second metal line 430, a first electrode lead 440 and a second electrode lead 450 are provided in the second metal interconnection layer 400, and the first electrode lead 440 and the second electrode lead 450 are respectively connected to the first electrode plate 310 and the second electrode plate 330 through through holes, and the second metal line 430 includes a second source lead 431 and a second drain lead 432, and the second source lead 431 and the second drain lead 432 are respectively connected to the first source lead 231 and the first drain lead 232 in the first metal interconnection layer 200 through through holes, for leading out the MOS unit.

[0081] In order to completely lead out the electrode plate of the resistive memory cell 300, a third metal interconnection layer 500 needs to be prepared, such as Figure 4 As shown, the third metal interconnection layer 500 includes a third metal line 510 , which leads out the first plate lead 440 and the second plate lead 450 respectively, thereby realizing circuit control of the resistive memory unit 300 .

[0082] The first electrode plate 310 and the second electrode plate 330 are made of a metal conductive material, a metal nitride conductive material, or a similar conductive material. The metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed from at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In one embodiment, the first electrode plate 310 and the second electrode plate 330 can be made of different materials or the same material, and preferably, both are made of TiN.

[0083] The material of the resistive layer 320 is a transition metal oxide or a lanthanide metal oxide or a metal oxide of Group IV, V, or VI. x , HfO x 、AlO x 、TaO x and ZrO x Any of the materials mentioned above can be well compatible with traditional CMOS process.

[0084] In some embodiments, the two electrode plates have the same area and size, and the resistive layer 320 is just embedded between the two electrode plates. Taking the electrode plates as rectangular plates as an example, the corresponding resistive layer 320 is also a rectangular plate sandwiched between the two rectangular plates.

[0085] In some embodiments, the thickness of the electrode plate is 5-100 nm, and the thickness of the resistive layer 320 is 3-30 nm. The thickness designs of the electrode plate and the resistive layer 320 need to meet the design rules of the current metal interconnection layer.

[0086] In some embodiments, the area of the electrode plate is 100-20000 nm 2 The area design of the electrode plate needs to meet the design rules of the current metal interconnect layer. Under the premise of meeting the storage function, the smaller the area of the electrode plate, the better, in order to improve the density of the resistive memory cell. Therefore, the preferred area range is 100-2000nm 2 .

[0087] In some embodiments, two adjacent resistive memory cells 300 can be arranged in a mirror-symmetrical manner, so that adjacent electrode plates can share a common lead wire. Figure 2 In two adjacent resistive memory cells 300 , two adjacent first electrode plates 310 share a first electrode plate lead 440 , which can save leads and simplify design and manufacturing costs.

[0088] In the preparation process of the above-mentioned embedded storage structure, the conventional process is to first prepare two electrode plates on the metal interconnect layer to be inserted, and then insert the resistive switching layer between the two electrode plates. However, the applicant discovered a problem during the verification and use process. The thickness of the resistive switching layer is relatively thin, generally around 3-30nm, and has a certain depth, which makes it difficult to deposit metal conductive materials. For certain conductive materials, it is easy to be deposited incompletely and have defects, thereby affecting the reliability of the resistive switching unit and the storage read rate; therefore, the applicant developed a new process to realize this structure.

[0089] Example 2: Figure 5 As shown, this embodiment provides a method for preparing an embedded storage structure, comprising the following steps:

[0090] S100, providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer;

[0091] S200, preparing a first intermetallic dielectric layer on the interlayer dielectric layer;

[0092] S300, preparing a first metal circuit and a first electrode plate in a first intermetallic dielectric layer;

[0093] S400, preparing a first barrier layer on the first intermetallic dielectric layer;

[0094] S500, using an etching process to open a first intermetallic dielectric in a region on one side of the first electrode plate to form a first groove;

[0095] S600, filling the first groove with a resistive switching material;

[0096] S700, depositing a conductive metal material on the resistive material until the first groove is filled;

[0097] S800 , using the first barrier layer as a stop layer, planarizing the resistive material and the conductive metal material using a planarization process and leaving them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit.

[0098] The present invention creatively changes the preparation order of the electrode plates, first inserting and manufacturing the first electrode plate 310, and then inserting and manufacturing the second electrode plate and the resistive material together, so as to solve the problem that when the resistive plate is embedded in a parallel direction, it is difficult to control lateral damage to the plate and the resistive layer when etching and cutting the plate in the vertical direction during the process of separate deposition and etching of the resistive layer. In the manufacturing method of the present invention, although the edge material completely wraps the bottom and four sides of the second electrode plate, the unexpected technical effect is: it has been verified that the present invention can still complete the preparation of the resistive unit with high quality.

[0099] In S100, a first semiconductor structure 100 is provided, such as Figure 6 As shown, a MOS unit is schematically illustrated on the first semiconductor structure 100. The MOS unit includes an active area isolated by two STI structures 120. The source, drain and gate are respectively prepared in the active area. The gate is encapsulated by an interlayer dielectric layer 160. The interlayer dielectric layer 160 is provided with a contact hole 170 for leading out the source 130 and the drain 140. It should be emphasized that the first semiconductor structure 100 is only a schematic diagram. Different designs are actually required according to the application scenario, which does not affect the technical problem solved by the present invention.

[0100] S200, preparing a first intermetallic dielectric layer 220 on the interlayer dielectric layer 160; the preparation method is as follows:

[0101] S210, forming a second barrier layer 210 on the interlayer dielectric layer 160 of the first semiconductor structure 100, such as Figure 7 As shown;

[0102] Specifically, the second barrier layer 210 may be formed by physical vapor deposition or chemical vapor deposition. The material of the second barrier layer 210 is silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN).

[0103] In step S220, a first intermetallic dielectric layer 220 is formed on the second barrier layer 210, such as Figure 8As shown; the material of the first intermetallic dielectric layer 220 includes an oxide formed of tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), organosilicate glass (OSG), SiOC) and / or any suitable low-k dielectric material (for example, a material having a dielectric constant lower than that of silicon dioxide), and can be deposited by spin coating, CVD, FCVD, PECVD, PVD or any suitable deposition technique.

[0104] In S300, the first metal line 230 and the first electrode plate 310 are prepared in the first intermetallic dielectric layer 220, including the following steps:

[0105] S310, coating photoresist on the first intermetallic dielectric layer 220;

[0106] S320, patterning the photoresist using exposure and development technology;

[0107] S330, using the second barrier layer 210 as an etch stop layer, performing etching by dry etching, wet etching, or a combination of the two, preferably dry etching, and then performing wet cleaning to remove residues; opening a first metal line trench 241 and a first electrode plate trench 242 in the first intermetallic dielectric layer 220;

[0108] S340, using a wet cleaning process to remove the photoresist, to obtain the first metal line groove 241 and the first electrode groove 242, as shown in FIG. Figure 9 shown.

[0109] S350, fill the first metal line groove 241 and the first electrode plate groove 242 with conductive material and flatten them, completing the preparation of the first metal line 230 and the first electrode plate 310, as shown in FIG. Figure 10 As shown; the conductive material is a metal conductive material or a metal nitride conductive material, and the metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge, such as TiN. The thickness of the electrode plate is 5-100nm and the area is 100-20000nm 2 For the electrode plate, there is generally no special requirement for thickness, as long as it meets the electrical performance and process requirements. The area of the electrode plate can be such that sufficient voltage can be applied to produce high and low resistance conversion.

[0110] S400, preparing a first barrier layer 410 on the first intermetallic dielectric layer 220, such as Figure 11 As shown; the function of the first barrier layer 410 is to isolate the first electrode plate 310, the second electrode plate 330 and the second metal interconnection layer 400. The preparation process can adopt physical vapor deposition or chemical vapor deposition. The material is silicon carbide (SiC) layer, silicon oxynitride (SiON) layer, silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN); the thickness of the first barrier layer 410 is thicker than that in the prior art to provide for subsequent grinding and polishing consumption when preparing the resistive layer 320, generally 100-200nm, so that the thickness after consumption is roughly the same as the barrier layer thickness in the prior art.

[0111] S500, using an etching process to open the area on one side of the first electrode plate 310 ( Figure 13 The first intermetallic dielectric layer 220 (on the left side of the first electrode plate 310 on the left and on the right side of the first electrode plate 310 on the right) forms a first groove 240, such as Figure 13 As shown; including the following steps:

[0112] S510, coating a photoresist layer 340 on the first barrier layer 410, and opening the photoresist layer 340 on the left side of the left first electrode plate 310 and the photoresist layer 340 on the right side of the right first electrode plate 310 by using exposure and development technology, as shown in FIG. Figure 12 As shown;

[0113] S620, using the second barrier layer 210 as a stop layer, etching to form a first groove 240; the etching process adopts dry etching, wet etching or atomic layer etching with a high selectivity; preferably, dry etching and wet etching are performed alternately, and a plasma dry etching (Dry Plasma Etching) process can also be used, in which active free radicals and ions are generated by plasma (such as Cl2, HBr, CF4 and other gases), and are directionally bombarded on the wafer surface under the action of an electric field to achieve anisotropic (vertical) etching to avoid damage to the first electrode plate 310 during the etching process.

[0114] S530, remove the photoresist material by wet cleaning to complete the opening of the first groove 240, such as Figure 13 As shown, wet cleaning can effectively remove particles or impurities remaining in the first groove 240 , preventing the impurities from generating voids or defects when the resistive material 321 is subsequently filled, thereby affecting the reliability of the resistive memory unit 300 .

[0115] In S600, the first groove 240 is filled with a resistive material 321 such as Figure 14As shown; the resistive material 321 is a transition metal oxide or a lanthanide metal oxide and a metal oxide of the main group IV, V, VI. Specifically, TiO x , HfO x 、AlO x 、TaO x and ZrO x After selecting the resistive material 321, a corresponding filling process can be selected; the present invention can be filled with a single resistive material or a composite resistive material, as long as the RRAM unit function can be completed.

[0116] The thickness of the resistive layer 320 is 3-30nm. There is generally no special requirement for the thickness. The standard is to be able to generate high and low resistance conversion when voltage is applied through the electrode plate, and this conversion can exist stably under voltage control. It should be noted that since the present invention changes the distribution direction of the electrode plate and the resistive layer 320, and the thickness of the resistive layer 320 is only 3-30nm, which is relatively narrow, the depth is relatively deep when filled. Therefore, it should be given priority to select a resistive material 321 with small particles and high filling efficiency to obtain a resistive layer 320 with good performance.

[0117] In S700, a conductive metal material is deposited on the resistive material until the first groove is filled. Figure 15 As shown; the conductive material is a metal conductive material or a metal nitride conductive material, the metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge, such as TiN.

[0118] In S800 , the planarization is performed by using a CMP process. After the planarization, the first electrode plate 310 and the adjacent resistive switching layer 320 and the second electrode plate 330 form a resistive switching unit.

[0119] The second metal interconnection layer 400 is continuously prepared on the planarized first metal interconnection layer 200, and the electrode plate of the resistive switching unit can be led out, such as Figure 2 As shown; a third metal interconnection layer 500 is prepared on the second metal interconnection layer 400, and the first electrode plate 310 and the second electrode plate 330 of the resistive switching unit can be led out respectively.

[0120] Example 3: In this example, a resistive switching unit is prepared on the second metal interconnect layer, such as Figure 17 As shown, the following steps are included:

[0121] S100, providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer;

[0122] S200, sequentially preparing a first metal interconnection layer on the interlayer dielectric layer;

[0123] S300, preparing a second intermetallic dielectric layer on the first metal interconnect layer;

[0124] S400, preparing a second metal circuit and a first electrode plate in the second intermetallic dielectric layer to obtain a second metal interconnect layer;

[0125] S500, preparing a first barrier layer on the second intermetallic dielectric layer;

[0126] S600, using an etching process to open the first intermetallic dielectric layer in a region on one side of the first electrode plate to form a first groove;

[0127] S700, filling the first groove with a resistive switching material;

[0128] S800, depositing a conductive metal material on the resistive material until the first groove is filled;

[0129] S900 , using the first barrier layer as a stop layer, planarizing the resistive material and the conductive metal material using a planarization process and leaving them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit.

[0130] The third metal interconnection layer 500 is continuously prepared on the planarized second metal interconnection layer 400, and the electrode plate of the resistive switching unit can be led out. The structure is as follows: Figure 18 As shown; in this embodiment, the third metal interconnection layer 500 includes a third metal line 510, a first electrode lead 520, and a second electrode lead 530. The third metal line 510 is used to interconnect the metal layers, and the first electrode plate 310 and the second electrode plate 330 are led out through the first electrode lead 520 and the second electrode lead 530; and at least a fourth metal interconnection layer 600 needs to be manufactured, and the fourth metal interconnection layer 600 has a fourth metal line 610 in order to form a complete circuit control of a single resistive memory cell 300, as shown in FIG. Figure 19 shown.

[0131] It should be noted that the resistive switching unit can be prepared on the third metal interconnection layer or the fourth metal interconnection layer, which will not be described in detail in the present invention.

[0132] The above embodiments are intended to illustrate the present invention only and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that various combinations, modifications, or equivalent substitutions of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention and should be encompassed by the scope of the claims of the present invention.

Claims

1. A method for preparing an embedded storage structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; forming a first intermetallic dielectric layer on the interlayer dielectric layer; preparing a first metal circuit and a first electrode plate in a first intermetallic dielectric layer; forming a first barrier layer on the first intermetallic dielectric layer; Using an etching process to open the first intermetallic dielectric in a region on one side of the first electrode plate to form a first groove; Filling the first groove with a resistive material; Depositing a conductive metal material on the resistive material until the first groove is filled; Using the first barrier layer as a stop layer, a planarization process is used to planarize the resistive material and the conductive metal material and leave them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit. By selecting the relative orientation of the first groove and the first electrode plate, the first electrode plates of two adjacent resistive switching units are arranged adjacent to each other, and the two adjacent first electrode plates share a common electrode lead; the first metal circuit includes a source lead and a drain lead.

2. The method for preparing the embedded storage structure according to claim 1, characterized in that: Preparing a first intermetallic dielectric layer on the interlayer dielectric layer comprises the following steps: forming a second barrier layer on the interlayer dielectric layer of the first semiconductor structure; An intermetallic dielectric material is deposited on the second barrier layer to form a first intermetallic dielectric layer.

3. The method for preparing the embedded storage structure according to claim 2, characterized in that: preparing a first metal circuit and a first electrode plate in the first intermetallic dielectric layer, The following steps are included: Using an etching process to prepare a metal line groove and a first electrode plate groove on the first intermetallic dielectric layer; The metal line groove and the first electrode plate groove are filled with conductive material and planarized to obtain a first metal line and a first electrode plate.

4. The method for preparing the embedded storage structure according to claim 2, wherein: The resistive material filled in the first groove is a transition metal oxide, a lanthanide metal oxide, or a metal oxide of the main groups IV, V, and VI.

5. The method for preparing the embedded storage structure according to claim 2, characterized in that: The first electrode plate and the second electrode plate are made of metal conductive material or metal nitride conductive material.

6. The method for preparing the embedded storage structure according to claim 2, characterized in that: A second metal interconnection layer is prepared on the first metal interconnection layer on which the resistive switching unit is prepared, and the electrode plate is led out using the second metal interconnection layer.

7. The method for preparing the embedded storage structure according to claim 6, characterized in that: The second metal interconnection layer includes at least a second metal circuit, a first electrode plate lead and a second electrode plate lead. The second metal circuit is used to conduct with the first metal circuit. The first electrode plate lead and the second electrode plate lead lead out the first electrode plate and the second electrode plate respectively.

8. An embedded storage structure, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 7.

9. A method for preparing an embedded storage structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; sequentially preparing a plurality of metal interconnection layers on the interlayer dielectric layer; forming an intermetallic dielectric layer on the topmost metal interconnect layer; preparing a first metal circuit and a first electrode plate in the intermetallic dielectric layer; forming a first barrier layer on the intermetallic dielectric layer; An etching process is used to open the intermetallic dielectric in a region on one side of the first electrode plate to form a first groove; Filling the first groove with a resistive material; Depositing a conductive metal material on the resistive material until the first groove is filled; Using the first barrier layer as a stop layer, a planarization process is used to planarize the resistive material and the conductive metal material and leave them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit. By selecting the relative orientation of the first groove and the first electrode plate, the first electrode plates of two adjacent resistive switching units are arranged adjacent to each other, and the two adjacent first electrode plates share a common electrode lead; the first metal circuit includes a source lead and a drain lead.

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