A p-type-si and n-type-ga2o3 heterojunction diode

Abstract

The application provides a P-type-Si and N-type-Ga2O3 heterojunction diode, which comprises a cathode ohmic electrode, a substrate and a drift layer arranged from bottom to top, and a P region located above the drift layer, an oxide dielectric layer located on both sides of the P region and an anode ohmic electrode located above the P region; two ends of the P region are step-shaped structures extending to both sides from bottom to top; the oxide dielectric layer is in step-shaped contact adaptation with the P region, and a lower surface thereof is located on the drift layer, and an upper surface thereof is consistent with the height of the P region; the anode ohmic electrode covers the upper surface of the P region, and extends outward to cover part of the oxide dielectric layer on both sides, forming a metal field plate layer; the substrate material is N-type heavily doped Ga2O3; the drift layer material is N-type lightly doped Ga2O3; and the P region material is P-type heavily doped Si. The P-type-Si and N-type-Ga2O3 heterojunction diode has excellent performances of high withstand voltage and low on-resistance, and can be used as a basic material of a p-n-p Ga2O3-based bipolar diode and applied to a gate drive circuit.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of heterojunction diodes, and particularly relates to a P-type-Si and N-type-Ga2O3 heterojunction diode. BACKGROUND

[0002] Gallium oxide (Ga2O3) has a bandgap of 4.9 eV and a predicted breakdown field of up to 8 MV / cm, making it one of the most promising materials in wide-bandgap semiconductors. Its electron mobility is 300 cm² / V·s, resulting in excellent performance in high-power electronic devices. The power figure of merit of gallium oxide is 3444, which is 10 times that of silicon carbide (SiC) and 4 times that of gallium nitride (GaN), showing great application prospects in high-temperature, high-pressure and high-frequency electronic devices.

[0003] Currently, the research on Ga2O3 power devices mainly focuses on the structural design and device preparation technology of Schottky barrier diodes (SBD), field effect transistors (FET) and heterojunction diodes. However, gallium oxide faces many challenges in practical applications. Due to the localized self-limiting phenomenon of holes in gallium oxide, the realization of p-type gallium oxide is difficult, which is the main bottleneck hindering its wide application. To solve this problem, researchers are exploring the introduction of appropriate hetero-p-type materials combined with heterojunction structures to realize high-efficiency gallium oxide-based power devices. This idea not only helps to overcome the limitations of p-type doping, but also improves the thermal performance and overall efficiency of the device.

[0004] Currently, among the methods of integrating Ga2O3 with other p-type materials, hetero-PN junction diodes based on nickel oxide (NiO) / gallium oxide (Ga2O3), cuprous oxide (Cu2O) / gallium oxide, P-GaN / N-Ga2O3 and stannous oxide (SnO) / gallium oxide have been widely reported and have shown excellent electrical properties. Among them, p-NiO / Ga2O3 and p-Cu2O / Ga2O3 diodes have achieved high breakdown voltage, showing great potential in high-voltage applications. However, using oxide semiconductor materials as the P region has significant technical limitations: first, the polycrystalline nature of oxide materials leads to a decrease in carrier mobility, and their high defect density limits device performance, making them unsuitable as core materials for n-p-n Ga2O3 bipolar transistors and difficult to integrate; second, using oxide semiconductor materials to form a heterojunction with gallium oxide makes it difficult to apply in gate drive circuits.

[0005] In contrast, the integration of Ga2O3 with P-type-Si has significant advantages. Silicon material has high-quality single crystal growth technology and low defect density, which can greatly improve the carrier mobility and stability of the device. At the same time, the mature processing technology of silicon and the extensive industrial foundation support its flexible integration in the gate drive circuit. By combining silicon and gallium oxide heterogeneously, not only can the device performance be further optimized, but also the seamless compatibility of silicon-based technology can be achieved. However, such devices face the problem of large on-resistance and low breakdown voltage, which limits their further application in high-voltage and high-frequency fields. In 2023, J. Gong et al. (arXiv:2305.19138 [physics.app-ph]) first used the grafting technology to prepare Si / β-Ga2O3 p-n junction heterojunction diodes, which had good diode characteristics compared to wafer bonding, glass, nanomembrane transfer technology, etc. The breakdown voltage is in the range of 20-25V. Currently, the highest quality factor of the experimental device comes from the heterojunction device of the University of Wisconsin-Madison in March 2024 (IEEE Electron Device Letters (Volume: 45, Issue: 3, March 2024), the quality factor is about 96.7 MW·cm -2 , the breakdown voltage is 0.86KV. SUMMARY

[0006] Therefore, in order to solve the above technical problems, the present application provides a P-type-Si and N-type-Ga2O3 heterojunction diode, which fully utilizes the high-quality single crystal growth technology and low defect density of silicon material, greatly improves the carrier mobility and stability of the device, and provides a basis for the subsequent development of gallium oxide-based triodes and the integration of gallium oxide devices. At the same time, through reasonable structural design, the problem of large on-resistance and low breakdown voltage faced by such devices is overcome.

[0007] To achieve the above purpose, the technical scheme of the present application is as follows:

[0008] The application discloses a P-type-Si and N-type-Ga2O3 heterojunction diode, which comprises a cathode ohmic electrode, a substrate and a drift layer arranged from bottom to top in sequence; further comprises a P region located above the drift layer, an oxide dielectric layer located on both sides of the P region and an anode ohmic electrode located above the P region; both ends of the P region are in a stepped structure extending from bottom to top to both sides; the oxide dielectric layer is in a stepped contact adaptation on both sides of the P region, the lower surface of the oxide dielectric layer is located on the drift layer, and the upper surface is consistent with the height of the P region; the anode ohmic electrode covers the upper surface of the P region and extends outward on both sides to cover part of the oxide dielectric layer, forming a metal field plate layer; the material of the substrate is N-type heavily doped Ga2O3; the material of the drift layer is N-type lightly doped Ga2O3; and the material of the P region is P-type heavily doped Si.

[0009] Both ends of the P region are in a stepped structure extending from bottom to top to both sides, and the structure of the oxide dielectric layer is adapted, so that the oxide dielectric layer is in a stepped contact adaptation on both sides of the P region, and the anode ohmic electrode covering the upper surface of the P region is extended outward on both sides to cover part of the oxide dielectric layer, forming a metal field plate layer. The structure design reduces the electric field intensity below the P region, relieves the electric field concentration and improves the reverse breakdown voltage of the heterojunction diode.

[0010] Silicon is used as the P-type semiconductor material of the Ga2O3 heterojunction diode, combined with N-type gallium oxide, and through heavy doping, low on-voltage is realized, so that the power loss of the device is significantly reduced. Meanwhile, the P-type silicon and the Ga2O3 interface have good stability and low contact resistance, the high barrier problem of the oxide material is avoided, and the electrical performance of the device can be significantly improved.

[0011] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diode, the material of the cathode ohmic electrode is one of Ni, Pt, Ti and Au mixed material, Au, Ag, Cu and W; the material of the oxide dielectric layer is one of SiO2, Al2O3, HfO2, Cu2O, ZnO, TiO2 and Si3N4; and the material of the anode ohmic electrode is one of Ni, Pt, Ti and Au mixed material, Au, Ag, Cu and W.

[0012] The materials of the cathode ohmic electrode and the anode ohmic electrode are preferably Ni, and the material of the oxide dielectric layer is preferably SiO2; nickel can form ohmic contact with the P region, significantly reduce the contact resistance, optimize the forward conduction characteristics and improve the device efficiency. Meanwhile, nickel has excellent thermal stability and mechanical properties, can keep the interface characteristics stable in a high-temperature environment and is suitable for high-power devices. In addition, nickel can form low-resistance nickel silicide (NiSi) with silicon in a high-temperature annealing process, further improving the interface electrical performance.

[0013] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention, the thickness of the cathode ohmic electrode is 0.2 to 0.8 μm; and the thickness of the anode ohmic electrode is 0.4 to 1.0 μm.

[0014] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention, the doping concentration N of the heavily N-type doped Ga2O3 in the substrate material is... d 1.8×10 19 cm -3 The doping concentration N of the lightly doped Ga2O3 in the drift layer material is... d 3.0×10 15 cm -3 Up to 7.4×10 15 cm -3 The doping concentration N of the heavily p-type doped Si in the p-region material is... a 2.0×10 20 cm -3 .

[0015] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention, the doping concentration N of the lightly doped N-type Ga2O3 in the drift layer material is... d It is 6.6 × 10 15 cm -3 .

[0016] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention, the thickness T of the substrate is... s The thickness of the drift layer is 2–6 μm; T d It is 8–12 μm.

[0017] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention, the number N of the steps at both ends of the P region is 2 to 8, and the height of each step is 0.5 to 1.0 μm and the width is 0.2 to 0.8 μm.

[0018] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention, the number N of the steps at both ends of the P region is 6 to 8.

[0019] By optimizing the number of steps, as well as their height and width, the superimposed field strength at the corners of the steps is reduced, further alleviating electric field concentration and significantly improving the reverse breakdown voltage of the heterojunction diode.

[0020] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diode of the present application, the length L of the metal field plate layer is 2-5 μm.

[0021] In some preferred embodiments of the P-type-Si and N-type-Ga2O3 heterojunction diode of the present application, the length L of the metal field plate layer is 4 μm.

[0022] The metal field plate layer on the oxide dielectric layer is designed to make the electric field distribution under the step more uniform by optimizing the length of the metal field plate layer, thereby avoiding premature breakdown of the dielectric layer.

[0023] Compared with the prior art, the P-type-Si and N-type-Ga2O3 heterojunction diode of the present application has the following advantages:

[0024] (1) The P-type-Si and N-type-Ga2O3 heterojunction diode of the present application uses silicon material as the P region to form a heterojunction diode with gallium oxide. Due to the single crystal characteristics of silicon material, silicon material has high-quality single crystal growth technology and low defect density, which can greatly improve the carrier mobility and stability of the device when forming a heterojunction with gallium oxide. At the same time, the mature processing technology of silicon and the extensive industrial foundation support its flexible integration in the gate drive circuit. Through the heterojunction of silicon and gallium oxide, not only the device performance can be further optimized, but also the seamless compatibility of silicon-based process can be realized.

[0025] (2) The P-type-Si and N-type-Ga2O3 heterojunction diode of the present application overcomes the problems of large on-resistance and low breakdown voltage of such devices through reasonable structural design, with a breakdown voltage of up to 1.72 KV and a quality factor of 468 MW· cm -2 , which is about five times the highest quality factor of the currently prepared devices, showing superior characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which form a part of the present application, are used to provide a further understanding of the present application, and the schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 is a structural schematic diagram of the P-type-Si and N-type-Ga2O3 heterojunction diode of the present application;

[0028] Figure 2 is a breakdown voltage of the P-type-Si and N-type-Ga2O3 heterojunction diode of the present application as a function of the doping concentration of the drift layer;

[0029] Figure 3The quality factor (P-FOM) of the P-type-Si and N-type-Ga2O3 heterojunction diodes described in this invention varies with the doping concentration of the drift layer;

[0030] Figure 4 The variation of the peak electric field intensity inside the dielectric layer of the P-type-Si and N-type-Ga2O3 heterojunction diodes of the present invention with the applied reverse voltage under different metal field plate lengths;

[0031] Figure 5 This is a partial enlarged view of the steps at different numbers of steps N in the P-type-Si and N-type-Ga2O3 heterojunction diodes described in this invention; wherein, Figure 5 When a is N=8 Figure 5 When b is N=6 Figure 5 When c is N=4 Figure 5 When d is N=2, Figure 5 When e is N=1;

[0032] Figure 6 The breakdown voltage of the P-type-Si and N-type-Ga2O3 heterojunction diodes described in this invention at different numbers of steps N;

[0033] Figure 7 The forward IV characteristic curves and forward conduction resistance (R) of the P-type-Si and N-type-Ga2O3 heterojunction diodes described in this invention are shown. on );

[0034] Figure 8 This is a schematic diagram illustrating the fabrication steps of the P-type-Si and N-type-Ga2O3 heterojunction diodes described in this invention.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1-Cathode ohmic electrode; 2-Substrate; 3-Drift layer; 4-P region; 5-Oxide dielectric layer; 6-Anode ohmic electrode; 7-Metal field plate layer. Detailed Implementation

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0038] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Rather, the embodiments of this application include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0039] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Example 1

[0041] like Figure 1 As shown, a P-type-Si and N-type-Ga2O3 heterojunction diode includes a cathode ohmic electrode 1, a substrate 2 and a drift layer 3 arranged sequentially from bottom to top, and also includes a P-region 4 above the drift layer 3, an oxide dielectric layer 5 on both sides of the P-region 4 and an anode ohmic electrode 6 above the P-region 4.

[0042] The cathode ohmic electrode 1 is made of Ni; the thickness of the cathode ohmic electrode 1 is 0.2 μm.

[0043] Substrate 2 is made of heavily N-type doped Ga2O3, with a doping concentration of N... d 1.8×10 19 cm -3 The thickness T of substrate 2 s It is 2μm;

[0044] The material of drift layer 3 is lightly doped N-type Ga2O3, with a doping concentration of N... d 3.0×10 15 cm -3 Up to 7.4×10 15 cm -3 The thickness T of drift layer 3 d It is 8μm;

[0045] The material in region P4 is heavily p-doped Si with a doping concentration of N. a 2.0×10 20 cm -3 The two ends of region P4 are stepped structures that extend from bottom to top to both sides. There are 8 steps N at both ends of region P4. The height of the first and second steps from bottom to top is 0.5μm, and the height of the other six steps is 1.0μm. The width of the first and second steps is 0.5μm, the width of the third step is 0.8μm, the width of the fourth step is 0.4μm, the width of the fifth step is 0.6μm, the width of the sixth step is 0.2μm, and the width of the seventh and eighth steps is 0.5μm.

[0046] The oxide dielectric layer 5 is made of SiO2; the oxide dielectric layer 5 is adapted to the stepped contact on both sides of the P region 4, the lower surface of the oxide dielectric layer 5 is located on the drift layer 3, and the upper surface is at the same height as the P region 4.

[0047] The anode ohmic electrode 6 is made of Ni; the anode ohmic electrode 6 covers the upper surface of the P region 4, and extends outward on both sides to cover part of the oxide dielectric layer 5, forming a metal field plate layer 7, the length L of the metal field plate layer 7 is 4μm; the thickness of the anode ohmic electrode 6 is 0.4μm.

[0048] For P-type-Si and N-type-Ga2O3 heterojunction diodes, the doping concentration N of drift layer 3 is... d This will affect the forward conduction resistance and reverse breakdown voltage of the heterojunction diode. In Example 1, the doping concentration N of drift layer 3 is... d The selection range is 3×10. 15 cm -3 Up to 7.4×10 15 cm -3 Comparative study of different N doping concentrations in drift layer 3 d The breakdown voltage and on-resistance of a Ga2O3 heterojunction diode. By comparison, such as... Figure 2 At doping concentration N d At lower voltages, the corresponding breakdown voltage is as high as 1.92 kV, but the corresponding on-resistance is also high at 13.62 mΩ·cm. 2 As the doping concentration N d As the dielectric strength increases, the breakdown voltage decreases, and the on-resistance also gradually decreases. Because drift layer 3 is lightly doped, the electric field intensity is concentrated at the interface between oxide dielectric layer 5 and drift layer 3; therefore, the N2 concentration in drift layer 3 is relatively low. d It has a significant impact on the breakdown voltage.

[0049] like Figure 3 To obtain the optimal doping concentration, the power quality factor (P-FOM), a parameter characterizing the performance of power devices, is introduced. The power quality factor of the device is calculated using formula (1), where R in formula (1) is... on BV is the on-resistance, and BM is the breakdown voltage. The doping concentration corresponding to the FOM inflection point is defined as the optimal doping concentration for the device structure, yielding an optimal doping concentration of 6.6 × 10⁻⁶ for drift layer 3. 15 cm -3 .

[0050] FOM=BV 2 / R on (1).

[0051] Example 2

[0052] Based on Example 1, the difference is that the doping concentration of drift layer 3 in the P-type-Si and N-type-Ga2O3 heterojunction diodes is determined to be 6.6 × 10⁻⁶. 15 cm -3 The doping concentration N in region P4 a2.0 x 10 20 cm -3 , oxide dielectric layer 5 thickness T 0x 0.8 μm; wherein the variables are the number of steps N and the length L of the metal field plate layer 7.

[0053] The TCAD tool is used to study the impact of different numbers of steps N and lengths L of the metal field plate layer 7 on the breakdown voltage and the forward characteristics of the P-type-Si and N-type-Ga2O3 heterojunction diode. The band gap and electron affinity of the Ga2O3 material are set to 4.8 eV and 4.0 eV, respectively, and the ionization calculation uses α(E) = 0.79 x 10 6 cm -1 exp[-(2.92 x 10 7 v / cm) / E]. In addition, considering the additional scattering caused by etching damage and SiO2 / Ga2O3 interface charges, the mobility of the drift layer 3 at the contact surface of the drift layer 3 and the oxide dielectric layer 5 is set to 50 cm 2 / V·s, and the mobility of the rest of the drift layer 3 is set to 118 cm 2 / V·s. The electrode work function is 5.01 eV. The relative dielectric constant of the oxide dielectric layer 5 material is 3.99, and the critical breakdown field strength is taken as 8.5 MV·cm -1 .

[0054] By changing the length L of the metal field plate layer 7 and the number of steps N, the electric field distribution and breakdown performance of the heterojunction diode device are calculated. L varies from 0 μm to 5 μm, N takes 1, 2, 4, 6, and 8. The electric field distribution of different lengths L of the metal field plate layer 7 is observed to find the optimal length L of the metal field plate layer 7. Then, the appropriate number of steps N is selected to optimize the steps.

[0055] First step: study the impact of the length L of the metal field plate layer 7 on the peak electric field strength of the lower P region 4. Set the number of steps N to a fixed value of 8, and the peak electric field of the lower P region 4 in the range of L = 0 μm to 5 μm of the length of the metal field plate layer 7. Figure 4 The electric field strength under different lengths L of the metal field plate layer 7 is shown, and we take the critical breakdown field strength of SiO2 to be 8.5 MV·cm -2 , and when it reaches the critical breakdown field strength, it is considered that the device has broken down. As can be seen from the figure, as the reverse voltage increases, the electric field strength of the lower P region 4 gradually increases, and in the absence of the metal field plate layer 7, the device breaks down prematurely, with a breakdown voltage of 1.50 KV. When the length of the metal field plate layer 7 is greater than 4 μm, the peak electric field tends to be stable, and the breakdown voltage of the device reaches 1.74 KV.

[0056] Second step: study the influence of the number of steps N on the breakdown voltage. The breakdown voltage is 1, 2, 4, 6, 8 steps respectively. Figure 5 The zoomed-in view of the different number of steps N is shown, Figure 6 The breakdown voltage of each step number under different metal field plate layer length is shown. As can be seen from the figure, with the increase of the number of steps, the breakdown voltage gradually increases. When the number of steps is greater than 6, the breakdown voltage is basically stable. With the increase of the length L of the metal field plate layer 7, the breakdown voltage of the device also increases. When N is 8, the breakdown voltages corresponding to the lengths of 0 μm, 1 μm, 2 μm, 3 μm, 4 μm and 5 μm of the metal field plate layer 7 are 1.50 KV, 1.62 KV, 1.65 KV, 1.68 KV, 1.72 KV and 1.74 KV respectively.

[0057] The length L of the metal field plate layer is 4 μm, and the number of steps is 8. The forward I-V characteristic curve and the forward conduction resistance (R on ) of the device are extracted. The data and results are shown in Figure 7 .

[0058] In summary, when the doping concentration N d of the drift layer 3 is in the range of 3×10 15 cm -3 to 7.4×10 15 cm -3 , the length L of the metal field plate layer 7 is in the range of 2-5 μm, and the number of steps N is in the range of 2-8, the related performance parameters of the P-type-Si and N-type-Ga2O3 heterojunction diode are better than the prior art (the heterojunction device of the University of Wisconsin-Madison in March 2024, the quality factor is about 96.7 MW·cm -2 , and the breakdown voltage is 0.86 KV). Among them, when the doping concentration N d of the drift layer 3 is 6.6×10 15 cm -3 , the length L of the metal field plate layer 7 is 4 μm, and the number of steps N is 8, it is the best parameter design. The reverse breakdown voltage V BR of the P-type-Si and N-type-Ga2O3 heterojunction diode under this parameter can reach 1.72 KV, the on-resistance R on is 6.308 mΩ·cm 2 , and the quality factor FOM is 468 MW·cm -2 .

[0059] In addition, as shown in Figure 8 , the P-type-Si and N-type-Ga2O3 heterojunction diodes in Example 1 and Example 2 are prepared by the following methods:

[0060] S1, epitaxially growing a lightly doped Ga2O3 drift layer 3 on a substrate 2 by metal organic chemical vapor deposition (MOCVD);

[0061] S2, depositing a SiO2 film on the surface of the drift layer 3 by plasma enhanced chemical vapor deposition (PECVD), and defining a step structure region by using a photolithography technology;

[0062] S3, etching the initial step structure layer by layer by a reactive ion etching (RIE) process, the etching depth and horizontal length being controlled by multi-level photolithography masks; further using a wet etching to optimize the transition region of each step edge, forming a smooth transition step profile; finally removing the photoresist, and performing a heat annealing treatment on the sample in a range of 400°C to 600°C; obtaining a constructed oxide dielectric layer 5;

[0063] S4, depositing a silicon film on the step structure by a chemical vapor deposition (CVD) method, and adjusting the growth parameters to make the silicon film form a relatively thin transition layer on both sides of the step structure and a relatively thick silicon layer in the center region, thereby constructing a heterojunction structure; after deposition, performing a high-temperature annealing treatment on the device, and the annealing temperature is preferably 800°C to 1000°C; after annealing, performing a cleaning treatment to remove by-products in the CVD process and surface impurities in the annealing process; obtaining a constructed P region 4;

[0064] S5, forming a Ni ohmic contact electrode on the back surface of the substrate 2 by an electron beam metal evaporation, i.e., obtaining a cathode ohmic electrode 1;

[0065] S6, depositing a Ni metal layer on the P region 4 and the surface of the SiO2 by a sputtering or electron beam evaporation method, defining an electrode pattern by using a photolithography technology, and then removing the metal in the unmasked region by a reactive ion etching (RIE) using BCl3 and Ar gas, finally performing an annealing treatment on the electrode, thereby constructing an anode ohmic electrode 6, and finally obtaining the P-type-Si and N-type-Ga2O3 heterojunction diode.

Claims

1. A P-type-Si and N-type-Ga203 heterojunction diode comprising, from bottom to top, a cathode ohmic electrode (1), a substrate (2) and a drift layer (3), characterized in that: Further comprising a P region (4) above the drift layer (3), an oxide dielectric layer (5) on both sides of the P region (4), and an anode ohmic electrode (6) above the P region (4); both ends of the P region (4) are a stepped structure extending to both sides from bottom to top; the oxide dielectric layer (5) is in stepped contact with both sides of the P region (4), the lower surface of the oxide dielectric layer (5) is on the drift layer (3), and the upper surface is consistent with the height of the P region (4); the anode ohmic electrode (6) covers the upper surface of the P region (4) and extends outward on both sides to cover part of the oxide dielectric layer (5), forming a metal field plate layer (7); the material of the substrate (2) is N-type heavily doped Ga2O3; the material of the drift layer (3) is N-type lightly doped Ga2O3; the material of the P region (4) is P-type heavily doped Si; the thickness of the cathode ohmic electrode (1) is 0.2-0.8 μm; the thickness of the anode ohmic electrode (6) is 0.4-1.0 μm; the thickness T s of the substrate (2) is 2-6 μm; the thickness T d of the drift layer (3) is 8-12 μm; the number of steps N at both ends of the P region (4) is 2-8, the height of each step is 0.5-1.0 μm, and the width is 0.2-0.8 μm; the length L of the metal field plate layer (7) is 2-5 μm.

2. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 1, characterized by: The material of the cathode ohmic electrode (1) is one of Ni, Pt, Ti and Au mixed material, Au, Ag, Cu and W; the material of the oxide medium layer (5) is one of SiO2, Al2O3, HfO2, Cu2O, ZnO, TiO2 and Si3N4; the material of the anode ohmic electrode (6) is one of Ni, Pt, Ti and Au mixed material, Au, Ag, Cu and W.

3. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 1, wherein: The doping concentration of N-type heavily doped Ga2O3 in the substrate (2) material is N d 1.8×10 19 cm -3 The doping concentration N of the lightly doped Ga2O3 in the drift layer (3) material is... d 3.0×10 15 cm -3 Up to 7.4×10 15 cm -3 The doping concentration N of the heavily doped Si in the P-region (4) material is... a 2.0×10 20 cm -3 .

4. The P-type-Si and N-type-Ga2O3 heterojunction diode according to claim 3, wherein: The doping concentration N of N-type lightly doped Ga2O3 in the material of the drift layer (3) is 6.6 x 1014cm-3 d 6.6 x 1014cm-3 15 cm-3 -3 .

5. The P-type-Si and N-type-Ga2O3 heterojunction diode of claim 1, wherein: The number of steps N at both ends of the P region (4) is 6-8.

6. The P-type-Si and N-type-Ga2O3 heterojunction diode of claim 1, wherein: The length L of the metal field plate layer (7) is 4 μm.

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