A semiconductor structure and its fabrication method

Abstract

This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region. A P-type semiconductor layer is located on the gate region. A first hydrogen-rich layer is located on the side of the P-type semiconductor layer near the drain region. The hydrogen concentration of the first hydrogen-rich layer is greater than that of the P-type semiconductor layer. Compared with the P-type semiconductor layer, the resistivity of the first hydrogen-rich layer is higher, which can reduce the leakage current on the side of the gate near the drain when the gate is off and reduce the electric field strength on the drain side when the gate is on, thereby improving the reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials, especially GaN (gallium nitride)-based materials, have advantages such as large bandgap, high breakdown field strength, high electron mobility, and strong radiation resistance. GaN-based HEMT (High Electron Mobility Transistor) devices have great development potential in high-frequency, high-power fields such as wireless communication base stations, radar, and automotive electronics.

[0003] Typically, GaN-based HEMT devices are depletion-mode field-effect transistors. In radio frequency and microwave applications, negative turn-on voltages are required, which complicates the circuit structure and affects the circuit's anti-false-start protection function, reducing circuit safety. Therefore, it is necessary to conduct research on enhancement-mode GaN-based HEMT devices.

[0004] Common methods for achieving enhancement-mode devices include trench gate technology, fluorine ion implantation technology, and P-type gate technology. P-type gate technology involves adding a P-type GaN-based epitaxial layer between the gate metal and the barrier layer, lowering the barrier height. Due to the conduction band difference between the P-type GaN-based epitaxial layer and the barrier layer, the conduction band of the entire heterojunction rises above the Fermi level, depleting the 2DEG (two-dimensional electron gas) in the channel below the gate, thus achieving enhancement mode. However, during device fabrication, the P-type GaN-based epitaxial layer between the gate source and gate drain needs to be etched away. Controlling the etching precision is difficult, introducing etching damage, ultimately leading to a decrease in output current density, an increase in gate leakage current, and a reduction in device stability. Summary of the Invention

[0005] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the same, to solve the technical problem of gate leakage current in power devices in the prior art.

[0006] According to one aspect of this application, an embodiment of this application provides a semiconductor structure. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer stacked sequentially, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region; a P-type semiconductor layer located on the gate region; a first hydrogen-rich layer located on the side of the P-type semiconductor layer near the drain region, wherein the hydrogen concentration of the first hydrogen-rich layer is greater than the hydrogen concentration of the P-type semiconductor layer; a gate, a source, and a drain, wherein the gate is located on the side of the P-type semiconductor layer away from the substrate, the source is located on the source region, and the drain is located on the drain region.

[0007] According to another aspect of this application, one embodiment of this application provides a method for fabricating a semiconductor structure. The method includes: epitaxially fabricating a channel layer and a barrier layer on a substrate, the channel layer and barrier layer including a gate region, and source regions and drain regions located on either side of the gate region; epitaxially fabricating a P-type semiconductor layer in the gate region; fabricating a first hydrogen-rich layer on the side of the P-type semiconductor layer near the drain region, the hydrogen concentration of the first hydrogen-rich layer being greater than the hydrogen concentration of the P-type semiconductor layer; and fabricating a gate, a source, and a drain, the gate being located on the side of the P-type semiconductor layer away from the substrate, the source being located on the source region, and the drain being located on the drain region.

[0008] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region. A P-type semiconductor layer is located on the gate region to form an enhancement-mode device. A first hydrogen-rich layer is located on the side of the P-type semiconductor layer near the drain region. The hydrogen concentration of the first hydrogen-rich layer is greater than that of the P-type semiconductor layer. Compared with the P-type semiconductor layer, the resistivity of the first hydrogen-rich layer is higher, which can reduce the leakage current on the side of the gate near the drain when the gate is off and reduce the electric field strength on the drain side when the gate is on, thereby improving the reliability of the device. Attached Figure Description

[0009] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application.

[0010] Figure 2 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0011] Figure 3 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0012] Figure 4 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0013] Figure 5 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0014] Figure 6 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0015] Figure 7 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0016] Figure 8The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0017] Figure 9 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0018] Figures 10 to 18 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] In enhancement-mode devices, leakage current is prone to occur at the gate when the device is in the off state, which reduces the reliability of the device.

[0021] To address the aforementioned problems, this application provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer stacked sequentially, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region; a P-type semiconductor layer located on the gate region; a first hydrogen-rich layer located on the side of the P-type semiconductor layer near the drain region, wherein the hydrogen concentration of the first hydrogen-rich layer is greater than the hydrogen concentration of the P-type semiconductor layer; and a gate, a source, and a drain, wherein the gate is located on the side of the P-type semiconductor layer away from the substrate, the source is located on the source region, and the drain is located on the drain region.

[0022] The following is combined with Figures 1 to 15 Further examples illustrate the semiconductor structures and fabrication methods mentioned in this application.

[0023] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially. The channel layer 20 and the barrier layer 30 include a gate region 40a, and a source region 40b and a drain region 40c located on both sides of the gate region 40a; a P-type semiconductor layer 50 located on the gate region 40a; a first hydrogen-rich layer 61 located on the side of the P-type semiconductor layer 50 near the drain region 40c, wherein the hydrogen concentration of the first hydrogen-rich layer 61 is greater than the hydrogen concentration of the P-type semiconductor layer 50; a gate 41, a source 42, and a drain 43, wherein the gate 41 is located on the side of the P-type semiconductor layer 50 away from the substrate 10, the source 42 is located on the source region 40b, and the drain 43 is located on the drain region 40c.

[0024] Specifically, the channel layer 20 and the barrier layer 30 form a heterojunction, and a 2DEG channel is formed on the surface of the channel layer 20 near the barrier layer 30. When the semiconductor device is in the off state, the P-type semiconductor layer 50 can deplete the 2DEG at the channel to realize an enhancement-mode device. The first hydrogen-rich layer 61 is located on the side of the P-type semiconductor layer 50 near the drain region 40c. The hydrogen concentration of the first hydrogen-rich layer 61 is greater than that of the P-type semiconductor layer. Therefore, the resistivity of the first hydrogen-rich layer 61 is higher than that of the P-type semiconductor layer 50, which can reduce the leakage current on the side of the gate near the drain when the device is off, and can also reduce the electric field strength on the drain side when the device is on, thereby improving the reliability of the device.

[0025] Optionally, after forming the P-type semiconductor layer, hydrogen ions are injected into the side of the P-type semiconductor layer near the drain, hydrogen plasma treatment is performed, or hydrogen in SiN undergoes reverse diffusion, so that the free Mg in it can bond with H again, reducing the P-type concentration and forming a first hydrogen-rich layer 61 with high resistivity.

[0026] It should be noted that hydrogen concentration refers to the number of H atoms per unit volume.

[0027] In one embodiment, Figure 2 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 2 As shown, the semiconductor structure also includes a second hydrogen-rich layer 62, located on the side of the P-type semiconductor layer 50 near the source region 40b, and the hydrogen concentration of the second hydrogen-rich layer 62 is greater than the hydrogen concentration of the P-type semiconductor layer 50.

[0028] Specifically, the hydrogen concentration of the second hydrogen-rich layer 62 is greater than that of the P-type semiconductor layer 50. Compared with the P-type semiconductor layer 50, the resistivity of the first hydrogen-rich layer 61 and the second hydrogen-rich layer 62 is higher, which can reduce the gate leakage current in the off state and reduce the electric field strength near the gate in the on state, thereby improving the reliability of the device.

[0029] Optionally, the first hydrogen-rich layer 61 and the second hydrogen-rich layer 62 are formed simultaneously, and the hydrogen concentration of the first hydrogen-rich layer 61 is equal to the hydrogen concentration of the second hydrogen-rich layer 62. Optionally, the hydrogen concentration of the first hydrogen-rich layer 61 is greater than the hydrogen concentration of the second hydrogen-rich layer 62. Since the electric field strength is greater on the side of the gate near the drain, the first hydrogen-rich layer 61 has a higher hydrogen concentration and higher resistivity, which can better improve the reliability of the device.

[0030] In one embodiment, Figure 3 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 3As shown, in the direction parallel to the plane of the substrate 10, the width L1 of the first hydrogen-rich layer 61 is greater than the width L2 of the second hydrogen-rich layer 62. Specifically, the width L1 of the first hydrogen-rich layer 61 is larger, that is, the high-resistivity region near the drain is larger, which can better reduce the gate leakage current in the off state.

[0031] In one embodiment, Figure 4 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the semiconductor structure also includes a first passivation layer 71, located between the first hydrogen-rich layer 61 and the drain 43, and in contact with the first hydrogen-rich layer 61. The first passivation layer 71 comprises a hydrogen-containing material. Specifically, during the fabrication of the first hydrogen-rich layer 61, H in the first passivation layer 71 diffuses backward into the P-type semiconductor layer 50, causing free Mg to bond with H on the surface of the P-type semiconductor layer 50 near the first passivation layer 71. Ultimately, a high-resistivity first hydrogen-rich layer 61 is formed between the P-type semiconductor layer 50 and the first passivation layer 71, which can reduce the gate leakage current in the off state and improve device reliability.

[0032] Optionally, the first passivation layer 71 comprises SiN with a hydrogen content of 5% to 20%. Specifically, H in SiN diffuses backward into the P-type semiconductor layer 50, and after H bonds with free Mg, a first hydrogen-rich layer 61 in a high-resistivity state is formed between the P-type semiconductor layer 50 and SiN.

[0033] Optionally, such as Figure 4 As shown, a second passivation layer 72 is disposed between the P-type semiconductor layer 50 and the source electrode 42. The second passivation layer 72 comprises SiN with a hydrogen content of 5% to 20%. The second hydrogen-rich layer 62 is formed between the P-type semiconductor layer 50 and the second passivation layer 72 simultaneously with the formation of the first hydrogen-rich layer 61. Optionally, the first passivation layer 71 and the second passivation layer 72 are formed simultaneously.

[0034] It should be noted that the hydrogen content in SiN is 5% to 20%, which means that the percentage of H atoms is between 5% and 20%.

[0035] In one embodiment, along the direction from the gate 41 to the drain 43, the thickness of the first hydrogen-rich layer 61 remains constant or decreases in the direction perpendicular to the plane of the substrate 10. Optionally, as Figure 1 As shown, the thickness of the first hydrogen-rich layer 61 remains consistent.

[0036] Optionally, Figure 5 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 5As shown, the thickness of the first hydrogen-rich layer 61 decreases along the direction from the gate 41 to the drain 43. It can be understood that the closer to the barrier layer 30, the larger the projected area of ​​the first hydrogen-rich layer 61 in the high-resistivity state on the substrate 10, reducing the leakage current that may occur near the barrier layer and lowering the electric field strength near the barrier layer in the on-state, thus improving device reliability. Optionally, the thickness of the first hydrogen-rich layer 61 can decrease linearly, curve-likely, or stepwise; for example... Figure 5 As shown, the thickness of the first hydrogen-rich layer 61 decreases linearly.

[0037] Optionally, in embodiments including a second hydrogen-rich layer 62, the thickness of the second hydrogen-rich layer 62 remains constant or decreases along the direction from the gate 41 to the source 42 in a direction perpendicular to the plane of the substrate 10.

[0038] In one embodiment, Figure 6 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 6 As shown, the P-type semiconductor layer 50 includes a protrusion structure 501 near the drain 43. Along the direction from the gate 41 to the drain 43, the thickness of the protrusion structure 501 decreases in the direction perpendicular to the plane of the substrate 10. The shape of the first hydrogen-rich layer 61 is consistent with the shape of the P-type semiconductor layer 50 near the drain 43.

[0039] Specifically, such as Figure 6 As shown, the protrusion structure 501 is of P-type conductivity. Because the thickness of the protrusion structure 501 decreases in the direction perpendicular to the plane of the substrate 10, the protrusion structure 501 can deplete part of the 2DEG in the channel, which can reduce the electric field strength of the gate 41 near the drain 43 and further improve the breakdown voltage of the device.

[0040] Specifically, such as Figure 6 As shown, the shape of the first hydrogen-rich layer 61 is consistent with the shape of the P-type semiconductor layer 50 near the drain 43. The sidewall of the protrusion structure 501 near the drain 43 is straight. The cross-sectional shape of the first hydrogen-rich layer 61 in the plane perpendicular to the substrate 10 is straight.

[0041] Optionally, Figure 7 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 7 As shown, the sidewall of the protrusion structure 501 near the drain electrode 43 is stepped, and the cross-sectional shape of the first hydrogen-rich layer 61 in the plane perpendicular to the substrate 10 is stepped.

[0042] Optionally, Figure 8 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 8As shown, the sidewall of the protrusion structure 501 near the drain electrode 43 is curved, and the cross-sectional shape of the first hydrogen-rich layer 61 in the plane perpendicular to the substrate 10 is curved.

[0043] Optionally, in embodiments including a second hydrogen-rich layer 62, the shape of the second hydrogen-rich layer 62 is consistent with the shape of the P-type semiconductor layer 50 near the source 42.

[0044] In one embodiment, Figure 9 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 9 As shown, the semiconductor structure also includes a third hydrogen-rich layer 63, which covers a portion of the surface of the P-type semiconductor layer 50 away from the substrate 10, and the third hydrogen-rich layer 63 is connected to the first hydrogen-rich layer 61. Specifically, the first hydrogen-rich layer 61 and the third hydrogen-rich layer 63 cover the side surface and a portion of the upper surface of the P-type semiconductor layer 50, increasing the area of ​​the high-resistivity region to reduce the gate leakage current in the off state.

[0045] Optionally, near the source electrode 42, a second hydrogen-rich layer 62 and a third hydrogen-rich layer 63 cover the side surface and part of the upper surface of the P-type semiconductor layer 50, and the second hydrogen-rich layer 62 and the third hydrogen-rich layer 63 near the source electrode 42 are connected. Optionally, hydrogen-containing SiN is coated on the side surface and part of the upper surface of the P-type semiconductor layer 50, and after annealing, a first hydrogen-rich layer 61, a second hydrogen-rich layer 62, and a third hydrogen-rich layer 63 are formed.

[0046] One embodiment of this application also provides a method for fabricating a semiconductor structure. Figures 10 to 15 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application. The fabrication method includes:

[0047] Step S1, as follows Figure 10 As shown, a channel layer 20 and a barrier layer 30 are epitaxially fabricated sequentially on a substrate 10. The channel layer 20 and the barrier layer 30 include a gate region 40a, and a source region 40b and a drain region 40c located on both sides of the gate region 40a. Specifically, before epitaxially fabricating the channel layer 20, a core layer and a buffer layer are first epitaxially fabricated on the substrate 10.

[0048] Step S2, as follows Figure 11As shown, a P-type semiconductor layer 50 is epitaxially fabricated in the gate region 40a. Specifically, a P-type doped semiconductor layer is epitaxially formed on the entire surface of the barrier layer 30, and then annealed and etched to form the P-type semiconductor layer 50; or, a P-type doped semiconductor layer is epitaxially formed on the entire surface of the barrier layer 30, and then etched and annealed to form the P-type semiconductor layer 50; or, a SiO2 layer with an opening is fabricated on the barrier layer 30, the opening exposing the gate region of the barrier layer, a P-type doped semiconductor layer is epitaxially formed in the opening, and then annealed to form the P-type semiconductor layer, and the SiO2 layer can be etched away.

[0049] Step S3: On the side of the P-type semiconductor layer 50 near the drain region 40c, a first hydrogen-rich layer 61 is formed, and the hydrogen concentration of the first hydrogen-rich layer 61 is greater than the hydrogen concentration of the P-type semiconductor layer 50.

[0050] Optionally, the first hydrogen-rich layer 61 is prepared, including steps S31 and S32, as follows:

[0051] Step S31, as follows Figure 12 As shown, a mask layer 51 is fabricated on the P-type semiconductor layer 50, exposing the side of the P-type semiconductor layer 50 near the drain region 40c. Optionally, the mask layer 51 can be formed by full-surface deposition and etching. Optionally, the material of the mask layer 51 is a metal, SiN, or AlN.

[0052] Step S32, as follows Figure 13 As shown, under the protection of the mask layer 51, hydrogen ions are implanted or hydrogen plasma treatment is performed on the region of the P-type semiconductor layer 50 exposed by the mask layer 51 to form a first hydrogen-rich layer 61, such that the first hydrogen-rich layer 61 is located on the side of the P-type semiconductor layer 50 near the drain region 40c. Specifically, by implanting hydrogen ions or performing hydrogen plasma treatment, the free Mg in the P-type semiconductor layer 50 can be rebonded with H, reducing the P-type concentration and forming a high-resistivity first hydrogen-rich layer 61 on the side of the P-type semiconductor layer 50 near the drain region 40c. Optionally, the mask layer 51 is etched away.

[0053] Optionally, the first hydrogen-rich layer 61 is prepared, including steps S33 and S34, as follows:

[0054] Step S33, as follows Figure 14 As shown, a first passivation layer 71 is formed between the P-type semiconductor layer 50 and the drain region 40c. The first passivation layer 71 comprises a hydrogen-containing material. Specifically, the first passivation layer 71 covers the sidewalls of the P-type semiconductor layer 50. Optionally, a second passivation layer 72 is formed between the P-type semiconductor layer 50 and the source region 40b, and the second passivation layer 72 covers the sidewalls of the P-type semiconductor layer 50.

[0055] Step S34, as Figure 15As shown, the first passivation layer 71 undergoes high-temperature annealing, allowing H atoms in the first passivation layer 71 to enter the P-type semiconductor layer 50, thus forming a first hydrogen-rich layer 61 on the side of the P-type semiconductor layer 50 near the drain region 40c. Optionally, the material of the first passivation layer 71 is SiN with a hydrogen content of 5% to 20%. H atoms in the SiN diffuse backward into the P-type semiconductor layer 50, causing the free Mg atoms in the P-type semiconductor layer 50 to bond with H atoms again, reducing the P-type concentration and forming a high-resistivity first hydrogen-rich layer 61 on the side of the P-type semiconductor layer 50 near the drain region 40c. Optionally, the second passivation layer 72 forms a second hydrogen-rich layer 62 on the side of the P-type semiconductor layer 50 near the source region 40b.

[0056] Optionally, the thickness of the first hydrogen-rich layer 61 is 1 to 50 nm, where the thickness refers to the distance from which H in the first passivation layer 71 enters the P-type semiconductor layer 50.

[0057] Step S4, as follows Figure 1 As shown, a gate 41, a source 42, and a drain 43 are fabricated. The gate 41 is located on the side of the P-type semiconductor layer 50 away from the substrate 10, the source 42 is located on the source region 40b, and the drain 43 is located on the drain region 40c.

[0058] Optionally, in the intermediate structure formed in step S32, the mask layer 51 is first etched away, and then the gate 41, source 42, and drain 43 are fabricated on the gate region 40a, source region 40b, and drain region 40c, respectively. Optionally, in the intermediate structure formed in step S34, the first passivation layer 71 of the drain region 40c and the second passivation layer 72 of the source region 40b are etched until the barrier layer 30 or the channel layer 20 is exposed, and then the gate 41, source 42, and drain 43 are fabricated on the gate region 40a, source region 40b, and drain region 40c, respectively.

[0059] Optionally, the first hydrogen-rich layer 61 is prepared, including steps S35 to S37, as follows:

[0060] Step S35, as Figure 16 As shown, a passivation material layer 70 is fabricated on the P-type semiconductor layer 50 and the barrier layer 30. The passivation material layer 70 includes a hydrogen-containing material. Optionally, a thicker passivation material layer 70 is fabricated, and then the passivation material layer 70 is chemically polished to form a flat upper surface. Optionally, the passivation material layer is conformally fabricated on the P-type semiconductor layer 50 (not shown).

[0061] Step S36, as follows Figure 17As shown, etching removes a portion of the passivation material layer 70 on the P-type semiconductor layer 50, forming an opening 701 exposing the P-type semiconductor layer 50. The remaining passivation material layer 70 forms a first passivation layer 71 between the gate region 40a and the drain region 40c, and a second passivation layer 72 between the gate region 40a and the source region 40b. Optionally, a patterned mask layer is fabricated on the passivation material layer 70 to etch away a portion of the passivation material layer 70.

[0062] Step S37, as Figure 18 As shown, the first passivation layer 71 and the second passivation layer 72 are subjected to high-temperature annealing. Hydrogen (H) from the first passivation layer 71 and the second passivation layer 72 enters the P-type semiconductor layer 50, forming a first hydrogen-rich layer 61 on the side of the P-type semiconductor layer 50 near the drain region 40c, and a second hydrogen-rich layer 62 on the side of the P-type semiconductor layer 50 near the source region 40b. Specifically, the H diffusion principle is described in the aforementioned embodiment and will not be repeated here.

[0063] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region. A P-type semiconductor layer is located on the gate region to form an enhancement-mode device. A first hydrogen-rich layer is located on the side of the P-type semiconductor layer near the drain region. The hydrogen concentration of the first hydrogen-rich layer is greater than that of the P-type semiconductor layer. Compared with the P-type semiconductor layer, the resistivity of the first hydrogen-rich layer is higher, which can reduce the leakage current on the side of the gate near the drain when the gate is off and reduce the electric field strength on the drain side when the gate is on, thereby improving the reliability of the device.

[0064] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, a channel layer, and a barrier layer are stacked sequentially, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region; A P-type semiconductor layer is located on the gate region; A first hydrogen-rich layer is located on the side of the P-type semiconductor layer near the drain region. The hydrogen concentration of the first hydrogen-rich layer is greater than that of the P-type semiconductor layer, and the first hydrogen-rich layer decreases in thickness along the direction from the gate to the drain along the direction perpendicular to the plane of the substrate. The device comprises a gate, a source, and a drain, wherein the gate is located on the side of the P-type semiconductor layer away from the substrate, the source is located on the source region, and the drain is located on the drain region.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: The second hydrogen-rich layer is located on the side of the P-type semiconductor layer near the source region, and the hydrogen concentration of the second hydrogen-rich layer is greater than the hydrogen concentration of the P-type semiconductor layer.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: A first passivation layer is located between the first hydrogen-rich layer and the drain electrode, and is in contact with the first hydrogen-rich layer. The first passivation layer comprises a hydrogen-containing material.

4. The semiconductor structure according to claim 3, characterized in that, The first passivation layer comprises SiN with a hydrogen content of 5% to 20%.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: A third hydrogen-rich layer covers a portion of the surface of the P-type semiconductor layer away from the substrate, and the third hydrogen-rich layer is connected to the first hydrogen-rich layer.

6. A method for fabricating a semiconductor structure, characterized in that, include: A channel layer and a barrier layer are sequentially epitaxially fabricated on a substrate. The channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region. A P-type semiconductor layer is epitaxially fabricated in the gate region; A first hydrogen-rich layer is formed on the side of the P-type semiconductor layer near the drain region. The hydrogen concentration of the first hydrogen-rich layer is greater than that of the P-type semiconductor layer, and the thickness of the first hydrogen-rich layer decreases in the direction perpendicular to the plane of the substrate along the direction from the gate to the drain. A gate, a source, and a drain are fabricated, wherein the gate is located on the side of the P-type semiconductor layer away from the substrate, the source is located on the source region, and the drain is located on the drain region.

7. The manufacturing method according to claim 6, characterized in that, The fabrication of the first hydrogen-rich layer includes: A mask layer is fabricated on the P-type semiconductor layer, the mask layer exposing the side of the P-type semiconductor layer near the drain region; Under the protection of the mask layer, hydrogen ions are injected or hydrogen plasma treatment is performed on the region of the mask layer that exposes the P-type semiconductor layer to form the first hydrogen-rich layer, such that the first hydrogen-rich layer is located on the side of the P-type semiconductor layer near the drain region.

8. The manufacturing method according to claim 6, characterized in that, The fabrication of the first hydrogen-rich layer includes: A first passivation layer is formed between the P-type semiconductor layer and the drain region, the first passivation layer comprising a hydrogen-containing material; The first passivation layer is subjected to high-temperature annealing, and H in the first passivation layer enters the P-type semiconductor layer, thereby forming the first hydrogen-rich layer on the side of the P-type semiconductor layer near the drain region.

9. The manufacturing method according to claim 6, characterized in that, The fabrication of the first hydrogen-rich layer includes: A passivation material layer is fabricated on the P-type semiconductor layer and the barrier layer, the passivation material layer comprising a hydrogen-containing material; Etching removes a portion of the passivation material layer on the P-type semiconductor layer to form an opening exposing the P-type semiconductor layer. The remaining passivation material layer forms a first passivation layer between the gate region and the drain region and a second passivation layer between the gate region and the source region. The first passivation layer and the second passivation layer are subjected to high-temperature annealing, and H in the first passivation layer and the second passivation layer enters the P-type semiconductor layer, so that the first hydrogen-rich layer is formed on the side of the P-type semiconductor layer near the drain region, and the second hydrogen-rich layer is formed on the side of the P-type semiconductor layer near the source region.

10. The manufacturing method according to claim 8, characterized in that, The thickness of the first hydrogen-rich layer is 1~50 nm.

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