Semiconductor device

Abstract

A semiconductor device may include: a substrate including an active region; a gate structure including first and second gate structures crossing the first and second active regions; a channel layer on the active region surrounded by the gate structure; a source / drain region connected to the channel layer, including a first source / drain region having a first conductivity type in which the first active region is recessed, and a second source / drain region having a second conductivity type in which the second active region is recessed; internal spacers between the first gate structure and the first source / drain region and between the second gate structure and the second source / drain region, each of the first internal spacers including a spacer insulating film between a spacer dielectric layer and the gate structure, and a thickness of the first internal spacer may be greater than a thickness of the second internal spacer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration degree of semiconductor devices is increasing. When manufacturing semiconductor devices with fine patterns in response to the trend of high integration of semiconductor devices, it is desirable to achieve patterns with fine widths or fine pitch distances. In addition, in order to overcome the limitations of operating characteristics due to the reduction in size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs), efforts are being made to develop semiconductor devices including FinFETs having three-dimensional channels. Summary of the Invention

[0003] Some aspects of the present disclosure are to provide semiconductor devices with improved integration and reliability.

[0004] According to some aspects of the present disclosure, a semiconductor device may include: a substrate including a plurality of active regions, the plurality of active regions extending in a first direction and including a first active region and a second active region spaced apart from each other in a second direction intersecting the first direction; a plurality of gate structures extending in the second direction on the substrate and including a first gate structure intersecting the first active region and a second gate structure intersecting the second active region; a plurality of channel layers on each of the plurality of active regions, the plurality of channel layers spaced apart from each other in a third direction perpendicular to the upper surface of the substrate and surrounded by the gate structures; a plurality of source / drain regions on one side of each of the plurality of gate structures, the plurality of source / drain regions including a first source / drain region in a first recessed region and a second source / drain region in a second recessed region, in the first recessed region the first active region is recessed, the first source / drain region is connected to the plurality of channel layers on the first active region and has a first conductivity type, in the second recessed region the second active region is recessed, the second source / drain region is connected to the plurality of channel layers on the second active region and has a second conductivity type different from the first conductivity type; a first inner spacer between the first gate structure and the first source / drain region, below each of the plurality of channel layers on the first active region; and a second inner spacer between the second gate structure and the second source / drain region, below each of the plurality of channel layers on the second active region, each of the first inner spacers may include a spacer dielectric layer and a spacer insulating film between the spacer dielectric layer and the gate structure, and the central thickness of each of the first inner spacers in the first direction may be greater than the central thickness of each of the second inner spacers in the first direction.

[0005] According to some aspects of the present invention, a semiconductor device may include: a substrate including an active region extending in a first direction; a gate structure extending on the substrate in a second direction intersecting the active region; a plurality of channel layers on the active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the upper surface of the substrate and surrounded by the gate structure; source / drain regions on at least one side of the gate structure and connected to the plurality of channel layers; and internal spacers between the plurality of channel layers and separating the gate structure from the source / drain regions, wherein each of the internal spacers may include a spacer insulating film in contact with the gate structure, a spacer stacked film in contact with the source / drain regions, and a spacer dielectric layer filling a space between the spacer insulating film and the spacer stacked film, and the spacer dielectric layer may include a material different from the spacer stacked film and the spacer insulating film.

[0006] According to some aspects of the present disclosure, a semiconductor device may include: a substrate including a first region and a second region; a first active region extending on the substrate in the first region in a first direction; a second active region extending on the substrate in the second region in the first direction; a first gate structure extending on the first active region in a second direction intersecting the first direction; a second gate structure extending on the second active region in the second direction; a plurality of channel layers on the first active region and the second active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the upper surface of the substrate and surrounded by the gate structures; a first source / drain region on both sides of the first gate structure in a first recess region where the first active region is recessed, the first source / drain region being connected to the plurality of channel layers on the first active region and having a first conductivity type; a second source / drain region on both sides of the second gate structure in a second recess region where the second active region is recessed, the second source / drain region being connected to the plurality of channel layers on the second active region and having a second conductivity type different from the first conductivity type; a first internal spacer separating the first gate structure and the first source / drain region below each of the plurality of channel layers on the first active region; and a second internal spacer provided to separate the second gate structure and the second source / drain region below each of the plurality of channel layers on the second active region, wherein a central thickness in the first direction of each of the first internal spacer and the second internal spacer may be less than a top thickness of each of the first internal spacer and the second internal spacer.

[0007] The structure or material of the internal spacer may be optimized or improved according to the source / drain conductivity type, thereby providing a semiconductor device with improved reliability.

[0008] The advantages and effects of the present application are not limited to the foregoing, and can be more easily understood during the process of describing specific exemplary embodiments of the present disclosure. Description of the Drawings

[0009] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic top view showing a semiconductor device according to an exemplary embodiment;

[0011] Figure 2 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment;

[0012] Figures 3A to 3I is a partial enlarged view showing a semiconductor device according to an exemplary embodiment;

[0013] Figure 4 is a schematic top view showing a semiconductor device according to an exemplary embodiment;

[0014] Figure 5 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment;

[0015] Figure 6A and Figure 6B is a partial enlarged view showing a semiconductor device according to an exemplary embodiment;

[0016] Figures 7A to 7E and Figure 9 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment in a process sequence; and

[0017] Figures 8A to 8E is a partial enlarged view showing a method of manufacturing a semiconductor device according to an exemplary embodiment in a process sequence. DETAILED DESCRIPTION

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, it can be understood that expressions such as "on", "above", "upper", "below", "beneath", "lower", and "side" are only indicated based on the drawings, except when they are indicated by the drawings and mentioned separately.

[0019] Figure 1 is a schematic top view showing a semiconductor device according to an exemplary embodiment. For ease of explanation, Figure 1 only some components of the semiconductor device are shown.

[0020] Figure 2 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment. Figure 2 Schematically shows the Figure 1Cross-section of a semiconductor device.

[0021] Figure 3A Is a partially enlarged view showing a semiconductor device according to an exemplary embodiment. Figure 3A Shows Figure 2 An enlarged view of region 'A' of the semiconductor device.

[0022] Reference Figures 1 to 3A , the semiconductor device 100A may include: a substrate 101 including an active region 105; a channel structure 140 including first to fourth channel layers 141, 142, 143, and 144 vertically spaced apart from each other on the active region 105; a gate structure 160 extending by crossing the active region 105 and each including a gate electrode 165; source / drain regions 130 in contact with the channel structure 140; internal spacers 150 disposed between the gate structure 160 and the source / drain regions 130 below each of the channel layers 141, 142, 143, and 144; and a contact structure 180 connected to the source / drain regions 130. The semiconductor device 100A may further include a device isolation layer 110 and an interlayer insulating layer 170.

[0023] In the semiconductor device 100A, the active region 105 may have a fin structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140, and on the channel structure 140. Accordingly, the semiconductor device 100A may include a transistor having an MBCFET TM (Multi-Bridge Channel FET) structure, which is a gate-all-around field effect transistor.

[0024] The substrate 101 may have an upper surface extending in the X and Y directions. The substrate 101 may include a semiconductor material, such as a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI compound semiconductor. For example, examples of Group-IV semiconductors may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0025] The substrate 101 may include an active region 105 disposed on its upper portion. The active region 105 may be defined in the substrate 101 by a device isolation layer 110 and may be arranged to extend in a first direction (e.g., the X direction). However, depending on the interpretation method, the active region 105 may be described as a configuration separate from the substrate 101. The active region 105 may partially protrude onto the device isolation layer 110, and the upper surface of the active region 105 may be disposed at a level higher than the upper surface of the device isolation layer 110. The active region 105 may be formed as part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. However, on both sides of the gate structure 160, the active region 105 may be partially recessed to form a recessed region, and the source / drain regions 130 may be disposed in the recessed region.

[0026] In an example embodiment, the active region 105 may or may not include a well region containing impurities. For example, in the case of a P-type transistor (pFET), the well region may include N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an N-type transistor (nFET), the well region may include P-type impurities such as boron (B), gallium (Ga), and / or indium (In). For example, the well region may be disposed at a predetermined (or alternatively, desired or selected) depth from the upper surface of the active region 105.

[0027] The device isolation layer 110 may define the active region 105 in the substrate 101. For example, the device isolation layer 110 may be formed in a shallow trench isolation (STI) process. The device isolation layer 110 may expose the upper surface of the active region 105 and may partially expose the upper portion. In some example embodiments, the device isolation layer 110 may have a curved upper surface such that the device isolation layer 110 has a higher level when it is adjacent to the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0028] The gate structure 160 may be arranged to extend in a second direction (e.g., the Y direction) by crossing the active region 105 and the channel structure 140 over the active region 105 and the channel structure 140. The functional channel region of the transistor may be formed in the active region 105 and / or the channel structure 140 that crosses the gate electrode 165 of the gate structure 160. Each of the gate structures 160 may include a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the first to fourth channel layers 141, 142, 143, and 144, and a gate spacer layer 164 on the side surfaces of the gate electrode 165.

[0029] The gate dielectric layer 162 can be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and can be configured to cover at least some of the surface of the gate electrode 165. For example, the gate dielectric layer 162 can be configured to surround all surfaces of the gate electrode 165 except for its uppermost surface. The gate dielectric layer 162 can be in contact with the inner spacer 150 under the plurality of channel layers 141, 142, 143, and 144, and can be spaced apart from the source / drain region 130 by the inner spacer 150. The gate dielectric layer 162 can extend between the gate electrode 165 and the gate spacer layer 164, but the present disclosure is not limited thereto. The gate dielectric layer 162 can include an oxide, a nitride, or a high-κ material. The high-κ material can refer to a dielectric material having a dielectric constant higher than that of a silicon oxide film (SiO 2 ). The high-κ material can be, for example, aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSixOy), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr 2 O 3 ) among others. According to an example embodiment, the gate dielectric layer 162 can be formed of a multilayer film.

[0030] The gate electrode 165 can be configured to fill the space between the first through fourth channel layers 141, 142, 143, and 144 over the active region 105 and extend over the channel structure 140. The gate electrode 165 can be spaced apart from the first through fourth channel layers 141, 142, 143, and 144 by the gate dielectric layer 162. The gate electrode 165 can include a conductive material or a semiconductor material (such as doped polysilicon), and the conductive material is, for example, a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)). According to an example embodiment, the gate electrode 165 can be formed of two or more multilayers.

[0031] The gate spacer layer 164 may be disposed on two side surfaces of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain regions 130 and the gate electrode 165. According to an exemplary embodiment, the gate spacer layer 164 may have a multi-layer structure. The gate spacer layer 164 may be formed of at least one of an oxide, a nitride, and / or a oxynitride, and may be formed of, for example, a low dielectric constant film.

[0032] The channel structure 140 may be disposed on the active region 105, in a region where the active region 105 intersects with the gate structure 160. Each of the channel structures 140 may include first to fourth channel layers 141, 142, 143, and 144, which are a plurality of channel layers spaced apart from each other in the Z direction. The first to fourth channel layers 141, 142, 143, and 144 may be sequentially disposed from the lower part, and the first channel layer 141 may be the bottommost channel layer. The channel structure 140 may be connected to the source / drain regions 130. The channel structure 140 may have a width equal to or similar to that of the gate structure 160 in the X direction, and may have a width equal to or less than the width of the active region 105 in the Y direction. In a cross-section taken along the Y direction, the channel layer disposed in the lower part of the first to fourth channel layers 141, 142, 143, and 144 may have a width equal to or greater than the width of the channel layer disposed in the upper part. In an exemplary embodiment, the number and shape of the channel layers forming one channel structure 140 may be variably changed. For example, one channel structure 140 may include three channel layers, may include two channel layers, or may include five or more channel layers.

[0033] The channel structure 140 may be formed of a semiconductor material, and may include at least one of, for example, silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the channel structure 140 may be formed of the same material as the active region 105. In some exemplary embodiments, the channel structure 140 may include an impurity region disposed adjacent to the source / drain regions 130.

[0034] The source / drain regions 130 may be disposed in the recessed regions on both sides of the gate structure 160, where an upper portion of the active region 105 is recessed in the recessed regions. The recessed regions may extend along side surfaces of the channel structure 140 and side surfaces of the gate dielectric layer 162. The source / drain regions 130 may be configured to cover side surfaces in the X direction of each of the first through fourth channel layers 141, 142, 143, and 144 of the channel structure 140. An upper surface of the source / drain regions 130 may be disposed at a level equal to or higher than a level of a lower surface of the gate electrode 165 on the channel structure 140, and in an exemplary embodiment, this level may be variably changed. Side surfaces of the source / drain regions 130 may be curved according to the first through fourth channel layers 141, 142, 143, and 144 and the inner spacers 150. Side surfaces of the source / drain regions 130 may protrude in a direction of the gate structure 160 between the plurality of channel layers 141, 142, 143, and 144. However, in an exemplary embodiment, a specific shape of the side surfaces of the source / drain regions 130 may be variably changed. The source / drain regions 130 may be epitaxial growth regions and may include a plurality of epitaxial layers. An epitaxial growth surface of the source / drain regions 130 may contact the channel structure 140, the inner spacers 150, and the interlayer insulating layer 170.

[0035] The source / drain regions 130 may include at least one of semiconductor materials such as silicon (Si) and germanium (Ge), and may further include dopants. For example, when the semiconductor device 100A is an nFET, the dopants may be at least one of phosphorus (P), arsenic (As), and / or antimony (Sb). For example, when the semiconductor device 100A is a pFET, the dopants may be at least one of boron (B), gallium (Ga), and / or indium (In). According to an exemplary embodiment, the source / drain regions 130 may be formed of a plurality of epitaxial layers.

[0036] The interlayer insulating layer 170 may be disposed on the device isolation layer 110 to cover an upper surface of the device isolation layer 110 and the source / drain regions 130. The interlayer insulating layer 170 may include at least one of an oxide, a nitride, and / or a oxynitride, and may include, for example, a low dielectric constant material. According to an exemplary embodiment, the interlayer insulating layer 170 may include a plurality of insulating layers.

[0037] The inner spacers 150 may be disposed between the gate structure 160 and the source / drain regions 130, under each of the first through fourth channel layers 141, 142, 143, and 144 on the active region 105. The inner spacers 150 may be disposed parallel to the gate electrode 165 in a third direction (here, the Z direction) between the first through fourth channel layers 141, 142, 143, and 144. The inner spacers 150 may cover side surfaces in the X direction of the gate structure 160 under the channel structure 140. ForFigure 3A , the region 'A' between the second channel layer 142 and the third channel layer 143 is shown enlarged, but this is exemplary, and the inner spacers 150 under the multiple other channel layers 141, 142, 143, and 144 may have the same or similar characteristics as the inner spacer 150 described in the reference Figure 3A . The gate electrode 165 can be stably spaced apart from the source / drain region 130 by the inner spacer 150 and can be electrically isolated. The inner spacers 150 under the second to fourth channel layers 142, 143, and 144 can be understood to be disposed between adjacent channel layers, and the inner spacer 150 under the first channel layer 141 can be understood to be disposed between the first channel layer 141 and the active region 105. The upper and lower ends of the side surface of the inner spacer 150 facing the gate electrode 165 can have a shape protruding toward the gate electrode 165. The inner spacer 150 can have a concave side surface facing the gate electrode 165. That is, the gate electrode 165 can have a convex shape toward the inner spacer 150. Since the side surface of the source / drain region 130 has a shape protruding in the direction of the gate electrode 165 between the multiple channel layers 141, 142, 143, and 144, the side surface of the inner spacer 150 in contact with the source / drain region 130 can have a recessed rounded shape toward the source / drain region 130. In the first direction (here, the X direction), the central thickness D1 of each of the inner spacers 150 can be less than the top thickness D2 of each of the inner spacers 150. The central thickness D1 of each of the inner spacers 150 can be the minimum thickness, and the top thickness can be the maximum thickness. In some example embodiments, the central thickness D1 of each of the inner spacers 150 can be about or exactly 1 nm to about or exactly 3 nm, and in some example embodiments, the central thickness D1 can be about or exactly 1.5 nm to about or exactly 2.5 nm. Depending on the shape of the source / drain region 130, the processing method and order of the inner spacer 150, etc., the shape of the inner spacer 150 can be modified in various ways.

[0038] Each inner spacer 150 can include a spacer dielectric layer 151, a spacer insulating film 153 in contact with the gate structure 160, and a spacer deposition film 155 in contact with the source / drain region 130.

[0039] The spacer dielectric layer 151 can be adjacent to the channel layer (e.g., in Figure 3AIn the case of, the second channel layer 142 and the third channel layer 143 are in contact. The spacer dielectric layer 151 can be spaced apart from the gate structure 160 by the spacer insulating film 153 and can be spaced apart from the source / drain region 130 by the spacer stacking film 155. The spacer dielectric layer 151 can include an insulating material and can include at least one of an oxide, a nitride, and / or a oxynitride.

[0040] The spacer insulating film 153 can be disposed on a side surface of the spacer dielectric layer 151 facing the gate structure 160 and can be in contact with the gate structure 160. The spacer insulating film 153 can include an insulating material and can include at least one of an oxide, a nitride, and / or a oxynitride. The spacer insulating film 153 can include a material different from that of the spacer dielectric layer 151. For example, the spacer dielectric layer 151 can include silicon oxide (SiO), and the spacer insulating film 153 can include at least one of silicon nitride (SiN) and silicon oxynitride (SiON).

[0041] The spacer stacking film 155 can be disposed on a side surface of the spacer dielectric layer 151 facing the source / drain region 130 and can be in contact with the source / drain region 130. The spacer stacking film 155 can extend along the surface of the source / drain region 130 between the plurality of channel layers 141, 142, 143, and 144. The spacer dielectric layer 151 can be spaced apart from the source / drain region 130 by the spacer stacking film 155. The spacer stacking film 155 can include an insulating material and can include at least one of an oxide, a nitride, and / or a oxynitride. The spacer stacking film 155 can include a material different from that of the spacer dielectric layer 151 and can include the same material as the spacer insulating film 153. For example, the spacer dielectric layer 151 includes silicon oxide (SiO), and the spacer insulating film 153 and the spacer stacking film 155 can include at least one of silicon nitride (SiN) and silicon oxynitride (SiON). For example, the spacer dielectric layer 151 includes silicon oxide (SiO), the spacer stacking film 155 includes silicon nitride (SiN), and the spacer insulating film 153 includes silicon nitride (SiN) or silicon oxynitride (SiON).

[0042] Since the internal spacer 150 that can allow the gate electrode 165 and the source / drain region 130 to be electrically separated includes the spacer dielectric layer 151, the spacer insulating film 153, and the spacer stacking film 155, the gate electrode 165 and the source / drain region 130 can be stably separated from each other, and the internal spacer 150 can have an appropriate thickness depending on the conductivity type of the source / drain region 130. Therefore, a semiconductor device with improved reliability can be provided.

[0043] The contact structure 180 may be disposed on the source / drain region 130. The contact structure 180 may be connected to the source / drain region 130 and may apply an electrical signal to the source / drain region 130. The contact structure 180 may recess the source / drain region 130 and may extend into the source / drain region 130. The contact structure 180 may have an inclined side surface such that its width decreases toward the substrate 101 due to the aspect ratio, but the present disclosure is not limited thereto. As in some example embodiments, the contact structure 180 may extend from a lower portion of the channel structure 140 that is below the lower surface of the fourth channel layer 144, and according to some example embodiments, the contact structure 180 may extend below the lower surface of the second channel layer 142 or the third channel layer 143. For example, the contact structure 180 may include a metallic material such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), or aluminum (Al).

[0044] In the description of the following embodiments, descriptions that are repetitive with those referred to above Figures 1 to 3A will be omitted.

[0045] Figures 3B to 3I is a partial enlarged view showing a semiconductor device according to an example embodiment. Figures 3B to 3I Shows a magnified region corresponding to the region shown by magnifying region ‘A’ of the semiconductor device in Figure 2 and shows a modified embodiment of Figure 3A . The specific form of the inner spacer 150 is not limited to Figures 3A to 3I the example embodiment of

[0046] With Figure 2 referred to together Figure 3B , the spacer insulating film 153 may cover a part of the side surface of the spacer dielectric layer 151 facing the gate electrode 165, and the spacer dielectric layer 151 may contact the gate dielectric layer 162 of the gate structure 160. The spacer insulating film 153 may cover the remaining portion of the spacer dielectric layer 151 except for the upper and lower portions of the side surface facing the gate electrode 165. The thickness of the spacer insulating film 153 may vary according to the level. In some example embodiments, the spacer insulating film 153 may become thinner as it approaches an adjacent channel layer in the third direction (here, the Z direction).

[0047] With Figure 2 referred to together Figure 3C , the side surface of the inner spacer 150 facing the gate electrode 165 may have a concave and rounded shape toward the gate electrode 165. That is, the gate electrode 165 may have a convex and rounded shape toward the inner spacer 150. The top thickness D2' of the inner spacer 150 may be greater than the center thickness D1' of the inner spacer 150, andFigure 3C In some example embodiments of Figure 3A the difference between the top thickness D2' and the center thickness D1' can be greater than

[0048] Reference Figure 3D , the upper portion of the spacer insulating film 153 can partially extend along the lower surface of an adjacent channel layer (e.g., the third channel layer 143). A part of the upper surface of the gate dielectric layer 162 can contact the lower surface of the channel layer (e.g., the third channel layer 143), and the remaining part can contact the spacer insulating film 153. The lower portion of the spacer insulating film 153 can partially extend along the upper surface of an adjacent channel layer (e.g., the second channel layer 142). A part of the lower surface of the gate dielectric layer 162 can contact the upper surface of the channel layer (e.g., the second channel layer 142), and the remaining part can contact the spacer insulating film 153. Referring together to Figure 2 , in the case where the inner spacer 150 is disposed below the first channel layer 141, the lower portion of the spacer insulating film 153 can partially extend along the upper surface of the active region 105.

[0049] Reference Figure 3E , the inner spacer 150 can be shaped to surround the gate electrode 165 at the same level. The spacer insulating film 153 can extend along the surface of the gate dielectric layer 162 below each of the channel layers 141, 142, 143, and 144, and can surround the gate electrode 165. The spacer insulating film 153 can surround the gate structure 160 between the plurality of channel layers 141, 142, 143, and 144. Due to the spacer insulating film 153, the gate dielectric layer 162 can be prevented from contacting the adjacent channel layers. Hereinafter, Figures 3F to 3G an example embodiment is shown in which the inner spacer 150 surrounds the gate electrode 165.

[0050] Reference Figure 3F , different from Figure 3E the example embodiments of

[0051] Reference Figure 3G , different from Figure 3FDifferent from the example embodiment, the spacer insulating film 153 and the spacer dielectric layer 151 of the internal spacer 150 may surround adjacent gate electrodes 165, and the spacer stacking film 155 may cover the side surface of the spacer dielectric layer 151 facing the source / drain region 130.

[0052] Reference Figure 3H , and Figures 3A to 3G different from the example embodiment, the internal spacer 150 may not include the spacer stacking film 155. Accordingly, the spacer dielectric layer 151 may be in direct contact with the source / drain region 130.

[0053] Reference Figure 3I , and Figures 3A to 3H different from the example embodiment, the side surface of the source / drain region 130 may not protrude toward the gate electrode 165 between each of the channel layers 141, 142, 143, and 144. Accordingly, the side surface of the internal spacer 150 in contact with the source / drain region 130 may be formed along the side surface of the source / drain region 130 and may have a flat shape.

[0054] The above Figures 3A to 3I example embodiment is exemplary, and the detailed configuration and arrangement relationship of the gate structure 160 including the gate electrode 165, the source / drain region 130, and the internal spacer 150, their contact relationship, the thickness of each component, or the presence or absence thereof, etc. are not limited thereto and may be modified in various ways. For example, the spacer stacking film 155 may only cover a part of the side surface of the source / drain region 130 in contact with the internal spacer 150. Additionally, for example, even between the internal spacers 150 at the same level, the presence or absence and the thickness of the spacer stacking film 155 may vary. According to some example embodiments, each of the internal spacers 150 below the plurality of channel layers 141, 142, 143, and 144 may have Figures 3A to 3I one of the forms of the embodiment and its modified examples. That is, the internal spacer 150 may exist in different forms.

[0055] Figure 4 is a schematic top view showing a semiconductor device according to an example embodiment. For ease of explanation, Figure 4 only some components of the semiconductor device are shown.

[0056] Figure 5 is a schematic cross-sectional view showing a semiconductor device according to an example embodiment. Figure 5 Schematically shows a cross-section of the Figure 4 semiconductor device taken along cutting lines III-III' and IV-IV'.

[0057] Figure 6AIt is a partial enlarged view showing a semiconductor device according to an exemplary embodiment. Figure 6A Shows Figure 5 An enlarged view of regions 'B' and 'C' of the semiconductor device of.

[0058] Referring to Figures 4 to 6A , the semiconductor device 100B may include a first region R1 and a second region R2 having different conduction types. According to some exemplary embodiments, the first region R1 and the second region R2 may be adjacent to each other or may be spaced apart from each other. According to some exemplary embodiments, the gate structure 160 in the first region R1 may extend into the second region R2. Depending on the description method, the gate structure 160 in the first region R1 may be referred to as the first gate structure 160, and the gate structure 160 in the second region R2 may be referred to as the second gate structure 160. According to some exemplary embodiments, the first gate structure 160 in the first region R1 and the second gate structure 160 in the second region R2 may be separate configurations and may be configured to extend and continue in a second direction (here, the Y direction). Each component in the first region R1 may have the same or similar characteristics as each component described with reference to Figures 1 to 3A . Its repeated description will be omitted.

[0059] The first source / drain region 130a in the first region R1 may have a first conduction type, and the second source / drain region 130b in the second region R2 may have a second conduction type different from the first conduction type. For example, the first source / drain region 130a having the first conduction type may be N-type, and the first source / drain region 130a may include at least one dopant selected from phosphorus (P), arsenic (As), and / or antimony (Sb). For example, the second source / drain region 130b having the second conduction type may be P-type, and the second source / drain region 130b may include at least one dopant selected from boron (B), gallium (Ga), and / or indium (In).

[0060] In the first region R1, a first internal spacer 150a may be disposed between the gate structure 160 and the first source / drain region 130a, below each of the plurality of channel layers 141, 142, 143, and 144 on the first active region 105a. The first internal spacer 150a may be parallel to the gate electrode 165 between the first through fourth channel layers 141, 142, 143, and 144 in a third direction (here, the Z direction). The first internal spacer 150a may cover a side surface in the X direction of the first gate structure 160 below the channel structure 140. The gate electrode 165 may be stably spaced apart from the first source / drain region 130a by the first internal spacer 150a and may be electrically separated therefrom. The first internal spacer 150a below the second through fourth channel layers 142, 143, and 144 may be understood to be disposed between adjacent channel layers, and the first internal spacer 150a below the first channel layer 141 may be understood to be disposed between the first channel layer 141 and the first active region 105a. The first internal spacer 150a may have the same or similar characteristics as the internal spacer 150 Figures 3A to 3I described. For example, in some example embodiments, a center thickness D1 of each of the first internal spacers 150a may be about or exactly 1 nm to about or exactly 3 nm, and in some example embodiments, a center thickness D1 of each of the first internal spacers 150a may be about or exactly 1.5 nm to about or exactly 2.5 nm.

[0061] In the second region R2, the second inner spacer 150b may be disposed between the second gate structure 160 and the second source / drain region 130b, below each of the plurality of channel layers 141, 142, 143, and 144 on the second active region 105b. The second inner spacer 150b may be parallel to the gate electrode 165 between the first through fourth channel layers 141, 142, 143, and 144 in a third direction (here, the Z direction). The second inner spacer 150b may cover the side surface in the X direction of the second gate structure 160 below the channel structure 140. Different from the first inner spacer 150a, the second inner spacer 150b may not include the spacer insulating film 153a and the spacer stacking film 155a included in the first inner spacer 150a. In some example embodiments, the second inner spacer 150b may include an insulating material such as silicon oxide. The center thickness of each of the first inner spacer 150a and the second inner spacer 150b may be less than the top thickness of each of the first inner spacer 150a and the second inner spacer 150b. The center thickness D1 of the first inner spacer 150a may be greater than the center thickness W1 of the second inner spacer 150b, and the top thickness D2 of the first inner spacer 150a may be greater than the top thickness W2 of the second inner spacer 150b. In some example embodiments, the center thickness W1 of each of the second inner spacers 150b may be about or exactly 0.5 nm to about or exactly 2 nm, and in some example embodiments, the center thickness W1 of each of the second inner spacers 150b may be about or exactly 0.7 nm to about or exactly 1.5 nm. Except for the characteristics different from the above-mentioned first inner spacer 150a, the second inner spacer 150b may have characteristics similar to those of the first inner spacer 150a.

[0062] In the case where the semiconductor device 100B includes a plurality of source / drain regions 130 having different conductivity types, the optimized (or alternatively, improved, desired, or selected) shapes of the inner spacers 150a and 150b disposed between the gate electrode 165 and the source / drain regions 130 may be different from each other. For example, in the case of the first inner spacer 150a in contact with the first source / drain region 130a having an N-type conductivity type, it may be desirable to more reliably isolate the gate electrode 165 and the first source / drain region 130a than the second inner spacer 150b in contact with the second source / drain region 130b having a P-type conductivity type. Therefore, unlike the second inner spacer 150b, the first inner spacer 150a may further include a plurality of insulating material layers, such as the first spacer insulating film 153a and the spacer stacking film 155a, or the central thickness D1 and the top thickness D2 of the first inner spacer 150a may be greater than the central thickness W1 and the top thickness W2 of the second inner spacer 150b, respectively. The first inner spacer 150a and the second inner spacer 150b optimized or improved for each conductivity type may be provided to improve the reliability of the semiconductor device.

[0063] In some example embodiments, the first source / drain region 130a in the first region R1 and the second source / drain region 130b in the second region R2 may have the same conductivity type. Even if the first source / drain region 130a in contact with the first inner spacer 150a and the second source / drain region 130b in contact with the second inner spacer 150b have the same conductivity type, the first inner spacer 150a and the second inner spacer 150b may have different configurations and shapes as needed.

[0064] Figure 6B is a partially enlarged view showing a semiconductor device according to an example embodiment. Figure 6B shows the corresponding enlarged regions corresponding to the regions shown by magnifying the regions 'B' and 'C' of the semiconductor device in Figure 5 and shows a modified embodiment of Figure 6A the semiconductor device.

[0065] Referring to Figure 6B , the second inner spacer 150b may include a spacer dielectric layer 151b, a spacer insulating film 153b, and a spacer stacking film 155b, and may have a shape substantially the same as or the same as that of the first inner spacer 150a. According to some example embodiments, the second inner spacer 150b may have a reference Figures 3A to 3IThe form of the described internal spacer 150. The second internal spacer 150b does not necessarily have a different shape from the first internal spacer 150a, and in some exemplary embodiments of the present disclosure, the second internal spacer 150b may have the same or similar characteristics as the first internal spacer 150a as needed (such as to simplify the process).

[0066] Figures 7A to 7E and Figure 9 are cross-sectional views shown in the process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. Figures 7A to 7E and Figure 9 show a cross-section corresponding to Figure 5 .

[0067] Figures 8A to 8E is a partially enlarged view shown in the process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. Figures 8A to 8E shows an enlarged view corresponding to Figure 6A .

[0068] Unless otherwise specified, the process can be understood to proceed in the order of the drawings.

[0069] Referring to Figure 7A , a plurality of sacrificial layers 120 and a plurality of channel layers 141, 142, 143, and 144 may be alternately stacked on a substrate 101.

[0070] The substrate 101 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0071] The plurality of channel layers 141, 142, 143, and 144 may include first to fourth channel layers 141, 142, 143, and 144. The sacrificial layer 120 may be a layer that is under the fourth channel layer 144 and is replaced by a gate dielectric layer 162 and a gate electrode 165 through a subsequent process, as Figure 5 shown. The sacrificial layer 120 may be formed of a material having an etching selectivity with respect to the first to fourth channel layers 141, 142, 143, and 144, respectively. The first to fourth channel layers 141, 142, 143, and 144 may include a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 include, for example, a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si).

[0072] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 can be formed by performing an epitaxial growth process on the stacked structure. In an exemplary embodiment, the number of sacrificial layers 120 and the number of channel layers stacked alternately can be changed differently.

[0073] Reference Figure 7B , an active structure including the active region 105 can be formed by partially removing the sacrificial layer 120, the first to fourth channel layers 141, 142, 143, and 144, and the substrate 101, the device isolation layer 110 can be formed (see Figure 2 ), and a sacrificial gate structure 200 and a gate spacer layer 164 can be formed on the active structure.

[0074] The active structure can include the active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144. The active structure can be formed in the form of a line extending in one direction (e.g., the X direction) and can be formed to be spaced apart from adjacent active structures in the Y direction. The side surfaces of the active structure in the Y direction can be coplanar with each other and can be arranged in a straight line.

[0075] In a region where a part of each of the active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144 is removed, the device isolation layer 110 can be formed by burying an insulating material and partially removing the insulating material so that the active region 105 protrudes. The upper surface of the device isolation layer 110 can be formed to be lower than the upper surface of the active region 105.

[0076] Each of the sacrificial gate structures 200 can be a sacrificial structure formed in a region where a gate dielectric layer 162 and a gate electrode 165 will be provided on the channel structure 140 through a subsequent process, as Figure 5 shown. The sacrificial gate structure 200 can have a line shape extending in one direction by crossing the active structure. The sacrificial gate structure 200 can extend, for example, in the Y direction. Each of the sacrificial gate structures 200 can include a first sacrificial gate layer 202, a second sacrificial gate layer 205, and a mask pattern layer 206 stacked in sequence. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 can be patterned using the mask pattern layer 206.

[0077] The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be an insulating layer and a conductive layer respectively, but the present disclosure is not limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 includes silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and / or silicon nitride.

[0078] The gate spacer layer 164 may be formed on two sidewalls of the sacrificial gate structure 200. The gate spacer layer 164 may be formed of a low-κ material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0079] Reference Figure 7C , the sacrificial gate structure 200 may be used as an etching mask to perform an etching process, and the etching process may penetrate the active structure to form a recessed region RC exposing the active region 105.

[0080] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 exposed from the sacrificial gate structure 200 may be partially removed to form the recessed region RC and remove some of the sacrificial layer 120. Accordingly, the first to fourth channel layers 141, 142, 143, and 144 may form a channel structure 140 having a limited length in the X direction.

[0081] Reference Figure 7D , a plurality of source / drain regions 130 may be formed in the recessed region RC.

[0082] The source / drain regions 130 may be formed in the recessed region RC and may be formed by, for example, selective epitaxial growth from the side surfaces of the channel structure 140 and the active region 105. The source / drain regions 130 may include a plurality of epitaxial layers, and these epitaxial layers may have different non-silicon concentrations. The source / drain regions 130 may include impurities by in-situ doping and may include a plurality of layers having different doping elements and / or doping concentrations. The first source / drain region 130a may have an N-type conductivity type and may be formed to include at least one dopant of phosphorus (P), arsenic (As), and / or antimony (Sb). The second source / drain region 130b may have a P-type conductivity type and may be formed to include at least one dopant of boron (B), gallium (Ga), and / or indium (In).

[0083] Reference Figure 7E , the interlayer insulating layer 170 may be partially formed, and the sacrificial gate structure 200 and the sacrificial layer 120 may be removed.

[0084] The interlayer insulating layer 170 can be formed by forming an insulating film covering the sacrificial gate structure 200 and the first and second source / drain regions 130a and 130b and performing a planarization process.

[0085] The sacrificial gate structure 200 and the sacrificial layer 120 can be selectively removed with respect to the gate spacer layer 164 and the channel structure 140. First, after removing the sacrificial gate structure 200 to form the upper gap region UR, the sacrificial layer 120 exposed through the upper gap region UR can be removed to form the lower gap region LR. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 can be selectively removed with respect to the channel structure 140 by performing a wet etching process.

[0086] In conjunction with Figure 7E reference Figure 8A , a spacer dielectric layer 151a can be formed under the plurality of channel layers 141, 142, 143, and 144 on the first active region 105a.

[0087] The spacer dielectric layer 151a can be formed along the surface of the first source / drain region 130a in the lower gap region LR on the first active region 105a. However, according to some example embodiments, as in region 'C' of Figure 8D , the spacer dielectric layer 151a can be formed along the surface of the source / drain region 130a and along the surfaces of the plurality of channel layers 141, 142, 143, and 144 and the first active region 105a. When a process is performed on the first active region 105a, the upper and lower gap regions UR and LR on the second active region 105b can be blocked so that the process is not performed on the second active region 105b.

[0088] In conjunction with Figure 7E reference Figure 8B , a spacer insulating film 153a can be formed on the spacer dielectric layer 151a.

[0089] The spacer insulating film 153a may be an oxide, nitride, and / or oxynitride formed on the spacer dielectric layer 151a and the plurality of channel layers 141, 142, 143, and 144 in the lower gap region LR. In some example embodiments, the spacer insulating film 153a may be configured such that silicon nitride (SiN) is formed on the spacer dielectric layer 151a and the plurality of channel layers 141, 142, 143, and 144 in the lower gap region LR, and may be oxidized to include silicon oxynitride (SiON). In some example embodiments, the spacer insulating film 153a may be configured to be provided with silicon oxide (SiO) formed by oxidizing the upper surfaces of the plurality of adjacent channel layers 141, 142, 143, and 144 or the first active region 105a. Depending on the material included in the spacer insulating film 153a, the spacer insulating film 153a may have an etching selectivity different from that of the spacer dielectric layer 151a.

[0090] With Figure 7E reference to Figure 8C , a portion of the spacer dielectric layer 151a and the spacer insulating film 153a may be removed through an etching process, and the first internal spacer 150a may be formed by forming a spacer stack film 155a.

[0091] A portion of the spacer insulating film 153a covering the plurality of channel layers 141, 142, 143, and 144 and the first active region 105a may be removed through an etching process. In this process, the thickness of the spacer insulating film 153a may be thinned. Accordingly, some surfaces of the plurality of channel layers 141, 142, 143, and 144 and some surfaces of the first active region 105a may be exposed as the lower gap region LR. In some example embodiments, due to the difference in etching selectivity between silicon oxide (SiO) and silicon nitride (SiN), the spacer insulating film 153a remains along the side surface of the spacer dielectric layer 151a, and the portion in contact with the plurality of adjacent channel layers 141, 142, 143, and 144 and the first active region 105a may be removed such that the plurality of channel layers 141, 142, 143, and 144 and the first active region 105a may be exposed on the lower gap region LR. In some example embodiments, the spacer insulating film 153a may remain along the side surface of the spacer dielectric layer 151a due to the thickness difference, and the portion in contact with the adjacent channel layers 141, 142, 143, and 144 and the first active region 105a may be removed.

[0092] The spacer stacking film 155a can be formed by diffusing the material included in the spacer insulating film 153a through the spacer dielectric layer 151a onto the surface of the first source / drain region 130a. The spacer stacking film 155a can be formed along the side surface of the first source / drain region 130a. The spacer stacking film 155a can include at least a portion of the material included in the spacer insulating film 153a and can include a material different from the spacer dielectric layer 151a.

[0093] Depending on the differences in the shape, thickness, etching degree, etc. of the spacer dielectric layer 151a, the spacer insulating film 153a, and the spacer stacking film 155a, several modified embodiments can be fabricated. Figures 3A to 3I The side surface of the first internal spacer 150a in contact with the first source / drain region 130a can be determined according to the surface shape of the side surface of the first source / drain region 130a. The side surface of the first internal spacer 150a facing the gate structure 160 can be determined by the type of insulating material, the amount of insulating material, the formation method, the etching method, the etching time, etc.

[0094] Together with Figure 7E reference Figures 8D to 8E it is possible to form a second internal spacer 150b under the multiple channel layers 141, 142, 143, and 144 on the second active region 105b.

[0095] After forming a dielectric layer along the upper surface of the second active region 105b and along the surfaces of the multiple channel layers 141, 142, 143, and 144 and the second source / drain region 130b in the lower gap region LR on the second active region 105b, a second internal spacer 150b can be formed for the etching process to expose the multiple channel layers 141, 142, 143, and 144. During the process of forming the second internal spacer 150b, the gap regions UR and LR on the first active region 105a can be blocked to prevent the process from advancing on the first active region 105a. Except for the process of forming the spacer insulating film 153a and the spacer stacking film 155a in the first internal spacer 150a, the process of forming the second internal spacer 150b can be performed in the same or similar process.

[0096] In this way, the first internal spacer 150a can be formed according to the process described with reference to Figures 8A to 8C and in a separate process, the second internal spacer 150b can be formed according to the process of Figures 8D to 8E thus forming different types of internal spacers 150a and 150b optimized or improved for each source / drain region 130. In the process of Figures 8A to 8C the second region R2 can be blocked to form the first internal spacer 150a only in the first region R1, and inFigures 8D to 8E In the process, the first region R1 can be blocked to form the second inner spacer 150b only in the second region R2. In the reference Figures 8A to 8E description, it is described that the first inner spacer 150a is formed first, and then the second inner spacer 150b is formed, and the process sequence is not limited to this. For example, after performing the process of region 'C' in Figures 8D to 8E to form the second inner spacer 150b, the first inner spacer 150a can be formed by performing the process in region 'B' of Figures 8A to 8C . When the first inner spacer 150a and the second inner spacer 150b are formed in the same shape as in the embodiment of Figure 6B , the processes of Figures 8A to 8C can be performed simultaneously in region 'B' and region 'C'.

[0097] Referring to Figure 9 , the gate structure 160 can be formed by forming a gate dielectric layer 162 and a gate electrode 165.

[0098] The gate structure 160 can be formed to fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 can be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. After forming the gate electrode 165 to completely fill the upper gap region UR and the lower gap region LR, the gate electrode 165, the gate dielectric layer 162, and the gate spacer layer 164 can be removed from the upper part of the upper gap region UR by a predetermined (or alternatively, desired or selected) depth. As a result, the gate structure 160 including the gate dielectric layer 162, the gate electrode 165, and the gate spacer layer 164 can be formed respectively.

[0099] The gate dielectric layer 162, the gate electrode 165, and the gate spacer layer 164 can be formed to continuously extend in the Y direction, and then can be removed in some regions by an etching process. Therefore, the gate structures 160 separated from each other in the Y direction can be formed. The gate structure 160 in the first region R1 can be referred to as the first gate structure 160, and the gate structure 160 in the second region R2 can be referred to as the second gate structure 160.

[0100] Then, referring to Figure 5 , an interlayer insulating layer 170 can be further formed on the gate structure 160, and a contact structure 180 can be formed on the plurality of source / drain regions 130.

[0101] The contact structure 180 can be formed by partially removing the interlayer insulating layer 170 and then depositing a conductive material. The first contact structure 180a can be formed to be connected to the first source / drain region 130a, and the second contact structure 180b can be formed to be connected to the second source / drain region 130b. According to some example embodiments, after forming the contact structure 180, the contact structure 180 and the interlayer insulating layer 170 can be partially etched from its upper surface by a planarization process.

[0102] When the term "about" or "substantially" is used in this specification in combination with a numerical value, it is intended that the associated numerical value include manufacturing or operating tolerances (e.g., ±10%) near the stated numerical value. In addition, when the words "substantially" and "about" are used in combination with a geometric shape, it is intended that no precision of the geometric shape is required, but rather a tolerance of the shape is within the scope of the present disclosure. Further, whether the numerical value or the shape is modified by "about" or "substantially", it should be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) near the stated numerical value or shape.

[0103] The present disclosure is not limited to the above embodiments and drawings, but is defined by the appended claims. Accordingly, various substitutions, modifications or changes can be made by those of ordinary skill in the art without departing from the scope of the present disclosure defined by the appended claims, and these substitutions, modifications or changes should be construed as being included within the scope of the present disclosure.

[0104] This application claims the priority of Korean Patent Application Nos. 10-2023-0178830 and 10-2024-0017767, filed with the Korean Intellectual Property Office on December 11, 2023 and February 5, 2024, respectively, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A semiconductor device, comprising: a substrate including a plurality of active regions extending in a first direction and including a first active region and a second active region spaced apart from each other in a second direction intersecting the first direction; a plurality of gate structures extending in the second direction on the substrate and including a first gate structure intersecting the first active region and a second gate structure intersecting the second active region; a plurality of channel layers, on each of the plurality of active regions, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the upper surface of the substrate and surrounded by the gate structure; a plurality of source / drain regions, on one side of each of the plurality of gate structures, the plurality of source / drain regions including a first source / drain region in a first recessed region in which the first active region is recessed, the first source / drain region being connected to the plurality of channel layers on the first active region and having a first conductivity type, and a second source / drain region in a second recessed region in which the second active region is recessed, the second source / drain region being connected to the plurality of channel layers on the second active region and having a second conductivity type different from the first conductivity type; a first inner spacer between the first gate structure and the first source / drain region and below each of the plurality of channel layers on the first active region; as well as a second inner spacer between the second gate structure and the second source / drain region and below each of the plurality of channel layers on the second active region, Each of the first inner spacers includes a spacer dielectric layer and a spacer insulating film between the spacer dielectric layer and the gate structure, and A central thickness of each of the first inner spacers in the first direction is greater than a central thickness of each of the second inner spacers in the first direction.

2. The semiconductor device according to claim 1, wherein At least some of the first inner spacers further include a spacer stacked film in contact with the first source / drain region, and The spacer accumulation film includes a material different from that of the spacer dielectric layer. 3 . The semiconductor device according to claim 2 , wherein the spacer accumulation film extends along a surface of the first source / drain region between the plurality of channel layers. 4 . The semiconductor device according to claim 2 , wherein the spacer dielectric layer is spaced apart from the first source / drain region by the spacer accumulation film.

5. The semiconductor device according to claim 2, wherein The spacer dielectric layer includes silicon oxide, and The spacer accumulation film includes silicon nitride. 6 . The semiconductor device according to claim 5 , wherein the spacer insulating film comprises silicon nitride or silicon oxynitride.

7. The semiconductor device according to claim 1, wherein The first conductivity type is N type, and The second conductivity type is P type. 8 . The semiconductor device of claim 1 , wherein in the first direction, at least some of the first inner spacers and the second inner spacers have a concave shape toward the gate structure. 9 . The semiconductor device according to claim 1 , wherein a center thickness of each of the second inner spacers in the first direction is smaller than a top thickness of each of the second inner spacers in the first direction. 10 . The semiconductor device of claim 1 , wherein in the first direction, a top thickness of each of the first inner spacers is greater than a top thickness of each of the second inner spacers. 11 . The semiconductor device according to claim 1 , wherein in at least a portion of each of the first inner spacers, the spacer dielectric layer is spaced apart from the gate structure by the spacer insulating film.

12. The semiconductor device according to claim 1, wherein The first inner spacer includes at least one of silicon oxynitride and silicon nitride, and The second inner spacer includes silicon oxide.

13. The semiconductor device according to claim 1, wherein The center thickness of each of the first inner spacers is 1 nm to 3 nm, and A central thickness of each of the second inner spacers is 0.5 nm to 2 nm. 14 . The semiconductor device according to claim 1 , wherein in at least some of the first inner spacers, the spacer insulating film surrounds the gate structure between the plurality of channel layers.

15. A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending on the substrate in a second direction intersecting the active region; a plurality of channel layers, on the active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the upper surface of the substrate and surrounded by the gate structure; a source / drain region on at least one side of the gate structure and connected to the plurality of channel layers; as well as an inner spacer between the plurality of channel layers and separating the gate structure from the source / drain region, Each of the internal spacers comprises: a spacer insulating film, contacting the gate structure, a spacer accumulation film in contact with the source / drain region, and a spacer dielectric layer filling a space between the spacer insulating film and the spacer deposited film, and The spacer dielectric layer includes a material different from that of the spacer accumulation film and the spacer insulating film.

16. The semiconductor device according to claim 15, wherein The spacer accumulation film and the spacer insulating film include silicon nitride or silicon oxynitride, and The spacer dielectric layer includes silicon oxide. 17 . The semiconductor device according to claim 15 , wherein in the first direction, each of the inner spacers has a concave shape toward the gate structure. 18 . The semiconductor device according to claim 17 , wherein a minimum thickness of each of the inner spacers in the first direction is 1 nm to 3 nm.

19. A semiconductor device comprising: a substrate including a first region and a second region; a first active region extending in a first direction in the first region on the substrate; a second active region extending in the first direction in the second region on the substrate; a first gate structure extending on the first active region in a second direction intersecting the first direction; a second gate structure extending in the second direction on the second active region; a plurality of channel layers, on the first active region and the second active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the upper surface of the substrate and surrounded by the first gate structure and the second gate structure; a first source / drain region in a first recessed region on both sides of the first gate structure, in which the first active region is recessed, the first source / drain region being connected to the plurality of channel layers on the first active region and having a first conductivity type; a second source / drain region on both sides of the second gate structure in a second recessed region in which the second active region is recessed, the second source / drain region being connected to the plurality of channel layers on the second active region and having a second conductivity type different from the first conductivity type; a first inner spacer separating the first gate structure and the first source / drain region below each of the plurality of channel layers on the first active region; as well as a second inner spacer separating the second gate structure and the second source / drain region below each of the plurality of channel layers on the second active region, A center thickness of each of the first inner spacer and the second inner spacer in the first direction is smaller than a thickness of an upper end of each of the first inner spacer and the second inner spacer.

20. The semiconductor device according to claim 19, wherein The first conductivity type is N type, and The second conductivity type is P type.

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