SiC JFET structure integrated with Schottky diode

Abstract

The SiC JFET structure comprises a drain electrode metallization layer, an N + substrate layer, an N-drift region, a P first gate region, an N current expansion region, a P second gate region, an N + source region, a gate electrode metallization layer, an insulating dielectric layer, a source electrode ohmic contact layer, a source electrode Schottky contact layer and a source electrode metallization layer. The P first gate regions are embedded in the upper surface of the N-drift region, the gap between the two P first gate regions forms a vertical conductive channel structure, and the source Schottky contact layer is located right above a channel to form a Schottky diode structure, so that the conduction loss during follow current of the device can be effectively reduced; meanwhile, the gate metallization layer is located at the bottom of the gate trench and directly connected with the P first gate region, the gate metallization layer is isolated from the source metallization layer through the insulating dielectric layer in the gate trench, and the device has the advantages of being small in reverse blocking leakage current, high in reliability and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and particularly relates to a SiC JFET structure integrated with a Schottky diode. Background Art

[0002] Silicon Carbide (SiC) Junction Field-Effect Transistor (JFET) has no gate oxide layer structure. The on and off of the device are realized by controlling the gate PN junction, without problems such as low channel mobility and unstable threshold voltage caused by the gate oxide layer structure of SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Therefore, SiC JFET has a small on-resistance, a high switching frequency, and high reliability, and is very suitable for working in extreme environments, having important application value in the field of power electronics.

[0003] In a power electronic system, diodes are required for freewheeling in half-bridge circuits and full-bridge circuits. If the body diode of the SiC field-effect transistor is directly used for freewheeling, a large forward voltage drop across the PN junction will generate a large conduction loss. Therefore, the industry usually adopts the method of anti-parallel connection of SiC Schottky diodes for freewheeling. However, anti-parallel connection of a SiC Schottky diode outside the SiC JFET will increase the volume and cost of the system, and at the same time introduce parasitic inductance and parasitic capacitance, which will limit the high-frequency working ability of the SiC JFET to a certain extent. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a SiC JFET structure integrated with a Schottky diode to solve the problems of limited high-frequency working ability of the device, increased system cost, and increased system volume caused by anti-parallel connection of a SiC Schottky diode outside the SiC JFET.

[0005] The above object of the present invention is mainly achieved by the following technical solutions:

[0006] A SiC JFET cell structure integrated with a Schottky diode, comprising a drain metallization layer, an N+ substrate layer, an N- drift region, a P first gate region, an N current spreading region, a P second gate region, an N+ source region, a source ohmic contact layer, a source Schottky contact layer, a source metallization layer, and a gate trench; wherein, from bottom to top, there are successively a drain metallization layer, an N+ substrate layer, an N- drift region, and an N current spreading region. The N- drift region is T-shaped, and the P first gate region is arranged on both sides of the vertical section of the N- drift region, and the upper surface of the P first gate region is flush with the upper surface of the N- drift region; the N current spreading region is T-shaped, the P second gate region is located on both sides of the horizontal crossbeam section of the N current spreading region, the lower surface of the P second gate region is in contact with the upper surface of the P first gate region, and the N+ source region is arranged on both sides of the vertical section of the N current spreading region, and the lower surface of the N+ source region is in contact with the N current spreading region and the P second gate region; a source ohmic contact layer is arranged on the upper surface of the N+ source region, and a source Schottky contact layer is arranged on the upper surface of the N current spreading region between the two parts of the source ohmic contact layer; the gate trench includes an insulating dielectric layer and a gate metallization layer, and the gate metallization layer is arranged on the upper surface of the P first gate region; the insulating dielectric layer isolates the gate metallization layer from the P second gate region and the N+ source region; the source metallization layer is located on the upper surfaces of the source ohmic contact layer, the source Schottky contact layer, and the insulating dielectric layer.

[0007] The N current spreading region is T-shaped, the N+ source region is arranged on both sides of the vertical section of the N current spreading region, the upper surface of the N+ source region is flush with the upper surface of the N current spreading region, and the lower surface of the source Schottky contact layer is aligned with the upper surface of the vertical section of the N current spreading region.

[0008] A vertical conductive channel structure is formed between the two parts of the P first gate region. Applying a voltage of -5V to -20V on the gate metallization layer can turn off the channel; applying a voltage of 0V on the gate metallization layer can turn on the channel.

[0009] The source Schottky contact layer is located directly above the vertical conductive channel structure, forming a Schottky diode structure.

[0010] The materials of the N+ substrate layer, the N- drift region, the N current spreading region, and the N+ source region are N-type silicon carbide, and the doping elements are nitrogen or phosphorus. The doping concentration of the N+ substrate layer is 1×10 19 ~1×10 20 cm -3 The doping concentration of the N- drift region is 1×10 15 ~1×10 16 cm -3 The doping concentration of the N current spreading region is 1×10 16 ~5×10 17 cm -3 The doping concentration of the N+ source region is 1×10 19 ~1×1020 cm -3 。

[0011] The materials of the first P gate region and the second P gate region are P-type silicon carbide, and the doping elements are aluminum or boron. The doping concentration of the first P gate region is 1×10 18 ~5×10 19 cm -3 , and the doping concentration of the second P gate region is 1×10 17 ~1×10 18 cm -3 。

[0012] The thickness of the first P gate region is 0.5 μm to 2 μm, and the thickness of the second P gate region is 0.2 μm to 1 μm.

[0013] The insulating dielectric layer includes SiN, HfO 2 or Al 2 O 3 。

[0014] The cell structures are sequentially connected to obtain the SiC JFET structure of the integrated Schottky diode.

[0015] A method for fabricating a SiC JFET structure of an integrated Schottky diode includes the following steps:

[0016] (1), epitaxially grow an N-epitaxial layer on the silicon carbide N+ substrate layer to form an N-drift region;

[0017] (2), perform P-type ion implantation on the upper surface of the N-drift region obtained in step (1), and perform high-temperature activation annealing to form the first P gate region;

[0018] (3), epitaxially grow another N-type epitaxial layer on the upper surface of the N-drift region obtained in step (2) to form an N current spreading region;

[0019] (4), perform P-type ion implantation on the upper surface of the N current spreading region obtained in step (3);

[0020] (5), perform N-type ion implantation on the upper surface of the N current spreading region obtained in step (4), and perform high-temperature activation annealing to form an N+ source region and the second P gate region;

[0021] (6), etch the N+ source region obtained in step (5) to form a gate trench, and fabricate a gate metallization layer at the bottom of the trench;

[0022] (7), deposit an insulating dielectric layer inside the gate trench obtained in step (6);

[0023] (8) Sputter an ohmic contact layer of metal on the upper surface of the N+ source region, and sputter a Schottky contact layer in the region between the N+ source regions;

[0024] (9) Form a source metallization layer on the upper surfaces of the Schottky contact layer, the ohmic contact layer, and the insulating dielectric layer; form a drain metallization layer on the lower surface of the N substrate, and finally obtain a SiC JFET cell structure integrated with a Schottky diode;

[0025] (10) Connect the SiC JFET cell structures integrated with Schottky diodes obtained in multiple steps (9) in sequence to obtain a SiC JFET structure integrated with a Schottky diode.

[0026] The present invention has at least the following beneficial effects compared with the prior art:

[0027] (1) In the present invention, the source Schottky contact layer is arranged directly above the vertical conductive channel structure to form a Schottky diode structure. When the device operates in the freewheeling state, the current flows through the Schottky diode, the on-state voltage drop decreases significantly, and the current path is smooth, suppressing current oscillation.

[0028] (2) In the present invention, the P first gate region and the P second gate region form an integral P-type doped region, which is connected to the gate metallization layer. There is no structure of a body diode PN junction inside the device. When there is a large current overshoot, the freewheeling current still all flows through the Schottky diode, ensuring that the voltage drop during freewheeling does not increase.

[0029] (3) In the present invention, the gate metallization layer is located at the bottom of the gate trench and is directly connected to the P first gate region, reducing the voltage drop in the P-type region, and can effectively shield the N+ source region and the source Schottky contact layer, ensuring that the breakdown ability does not decrease and the leakage current does not increase in the blocking state. Description of the Drawings

[0030] Figure 1 is a schematic diagram of a SiC JFET cell structure integrated with a Schottky diode according to the present invention;

[0031] Figure 2 is a schematic diagram of a SiC JFET structure integrated with a Schottky diode according to the present invention;

[0032] Figure 3 is a flowchart of a preparation method of a SiC JFET structure integrated with a Schottky diode according to the present invention;

[0033] Figure 4 is a schematic diagram of a preparation method of a SiC JFET structure integrated with a Schottky diode according to the present invention. Detailed Embodiments

[0034] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0035] As shown Figure 1 in the figure is the cell structure of a SiC JFET integrated with a Schottky diode, including a drain metallization layer 101, an N+ substrate layer 102, an N- drift region 103, a P first gate region 104, an N current spreading region 105, a P second gate region 106, an N+ source region 107, a source ohmic contact layer 108, a source Schottky contact layer 109, a source metallization layer 110, and a gate trench 113. Among them, from bottom to top are the drain metallization layer 101, the N+ substrate layer 102, the N- drift region 103, and the N current spreading region 105. The N- drift region 103 is T-shaped. The P first gate region 104 is arranged on both sides of the vertical section of the N- drift region 103, and the upper surface of the P first gate region 104 is flush with the upper surface of the N- drift region 103. The P second gate region 106 is located on both sides of the N current spreading region 105. The lower surface of the P second gate region 106 is in contact with the upper surface of the P first gate region 104, and the upper surface of the P second gate region 106 is in contact with the lower surface of the N+ source region 107. The source ohmic contact layer 108 is arranged on the upper surface of the N+ source region 107, and the source Schottky contact layer 109 is arranged on the upper surface of the N current spreading region 105, between the two parts of the source ohmic contact layer 108. The gate trench 113 includes an insulating dielectric layer 112 and a gate metallization layer 111. The gate metallization layer 111 is arranged on the upper surface of the P first gate region 104. The insulating dielectric layer 112 isolates the gate metallization layer 111 from the P second gate region 106 and the N+ source region 107. The source metallization layer 110 is located on the upper surfaces of the source ohmic contact layer 108, the source Schottky contact layer 109, and the insulating dielectric layer 112.

[0036] The N current spreading region 105 is T-shaped. The N+ source region 107 is arranged on both sides of the vertical section of the N current spreading region 105. The upper surface of the N+ source region 107 is flush with the upper surface of the N current spreading region 105, and the lower surface of the source Schottky contact layer 109 is aligned with the upper surface of the vertical section of the N current spreading region 105.

[0037] A vertical conductive channel structure is formed between the two parts of the P first gate region 104. Applying a voltage of -5V to -20V to the gate metallization layer 111 can turn off the channel. Applying a voltage of 0V to the gate metallization layer 111 can turn on the channel. The source Schottky contact layer 109 is located directly above the vertical conductive channel structure, forming a Schottky diode structure.

[0038] The materials of the N+ substrate layer 102, the N- drift region 103, the N current spreading region 105, and the N+ source region 107 are N-type silicon carbide, and the doping elements are nitrogen or phosphorus. The doping concentration of the N+ substrate layer 102 is 1×10 19 ~1×10 20 cm -3, the doping concentration of the N-drift region 103 is 1×10 15 ~1×10 16 cm -3 , the doping concentration of the N current extension region 105 is 1×10 16 ~5×10 17 cm -3 , the doping concentration of the N+ source region 107 is 1×10 19 ~1×10 20 cm -3 .

[0039] The material of the P first gate region 104 and the P second gate region 106 is P-type silicon carbide, and the doping element is aluminum or boron. The doping concentration of the P first gate region 104 is 1×10 18 ~5×10 19 cm -3 , the doping concentration of the second gate region 104 is 1×10 17 ~1×10 18 cm -3 .

[0040] The thickness of the P first gate region 104 is 0.5 μm to 2 μm, and the thickness of the P second gate region 106 is 0.2 μm to 1 μm.

[0041] The insulating dielectric layer 112 includes SiN, HfO 2 or Al 2 O 3 .

[0042] like Figure 2 As shown, the SiC JFET cell structures with integrated Schottky diodes are connected in sequence to obtain the SiC JFET structure with integrated Schottky diodes.

[0043] like Figure 3 and Figure 4 As shown, the present invention provides a method for preparing a SiC JFET structure with an integrated Schottky diode, comprising the following steps:

[0044] (1) epitaxially growing an N- epitaxial layer on the silicon carbide N+ substrate layer 102 to form an N- drift region 103;

[0045] (2) performing P-type ion implantation on the upper surface of the N-drift region 103 obtained in step (1), and performing high temperature activation annealing to form a P first gate region 104;

[0046] (3) epitaxially growing another N-type epitaxial layer on the upper surface of the N-drift region 103 obtained in step (2) to form an N current extension region 105;

[0047] (4), perform P-type ion implantation on the upper surface of the N current spreading region 105 obtained in step (3);

[0048] (5), perform N-type ion implantation on the upper surface of the N current spreading region 105 obtained in step (4), and perform high-temperature activation annealing to form an N+ source region 107 and a P second gate region 106;

[0049] (6), etch on the N+ source region (107) obtained in step (5) to form a gate trench 113, and fabricate a gate metallization layer 111 at the bottom of the trench;

[0050] (7), deposit an insulating dielectric layer 112 inside the gate trench 113 obtained in step (6);

[0051] (8), sputter an ohmic contact layer 108 on the upper surface of the N+ source region 107, and sputter a Schottky contact layer 109 in the region between the N+ source regions 107;

[0052] (9), fabricate and form a source metallization layer 110 on the upper surfaces of the Schottky contact layer 109, the ohmic contact layer 108, and the insulating dielectric layer 112; fabricate and form a drain metallization layer 111 on the lower surface of the N substrate, and finally obtain a SiC JFET cell structure integrated with a Schottky diode.

[0053] (10), connect the SiC JFET cell structures integrated with Schottky diodes obtained in multiple steps (9) in sequence to obtain a SiC JFET structure integrated with a Schottky diode.

[0054] As described above, it is only the best specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

[0055] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. A SiC JFET cell structure with an integrated Schottky diode, characterized in that: The invention comprises a drain metallization layer (101), an N+ substrate layer (102), an N-drift region (103), a P first gate region (104), an N current extension region (105), a P second gate region (106), an N+ source region (107), a source ohmic contact layer (108), a source Schottky contact layer (109), a source metallization layer (110) and a gate trench (113); wherein, from bottom to top, the drain metallization layer (101), the N+ substrate layer (102), the N-drift region (103), the P first gate region (104), the N current extension region (105), the P second gate region (106), the N+ source region (107), the source ohmic contact layer (108), the source Schottky contact layer (109), the source metallization layer (110) and the gate trench (113) are sequentially provided. -drift region (103) and N current expansion region (105), the N-drift region (103) is T-shaped, the P first gate region (104) is arranged on both sides of the vertical section of the N-drift region (103), and the upper surface of the P first gate region (104) is flush with the upper surface of the N-drift region (103); the N current expansion region (105) is T-shaped, the P second gate region (106) is located on both sides of the horizontal beam section of the N current expansion region (105), and the lower surface of the P second gate region (106) is flush with the P first gate region The upper surface of the N+ source region (104) is in contact with the N+ source region (107), the N+ source region (107) is arranged on both sides of the vertical section of the N current expansion region (105), and the lower surface of the N+ source region (107) is in contact with the N current expansion region (105) and the P second gate region (106); the source ohmic contact layer (108) is arranged on the upper surface of the N+ source region (107), and the source Schottky contact layer (109) is arranged on the upper surface of the N current expansion region (105), between the two parts of the source ohmic contact layer (108); the gate groove The groove (113) comprises an insulating dielectric layer (112) and a gate metallization layer (111), wherein the gate metallization layer (111) is arranged on the upper surface of the P first gate region (104); the insulating dielectric layer (112) isolates the gate metallization layer (111) from the P second gate region (106) and the N+ source region (107); and the source metallization layer (110) is located on the upper surfaces of the source ohmic contact layer (108), the source Schottky contact layer (109) and the insulating dielectric layer (112).

2. The SiC JFET cell structure with integrated Schottky diode according to claim 1, characterized in that: The N current extension region (105) is T-shaped, the N+ source region (107) is arranged on both sides of the vertical section of the N current extension region (105), the upper surface of the N+ source region (107) is flush with the upper surface of the N current extension region (105), and the lower surface of the source Schottky contact layer (109) is aligned with the upper surface of the vertical section of the N current extension region (105).

3. The SiC JFET cell structure with integrated Schottky diode according to claim 1, characterized in that: A vertical conductive channel structure is formed between the two P first gate regions (104). Applying a voltage of -5V to -20V on the gate metallization layer (111) can turn off the channel; applying a voltage of 0V on the gate metallization layer (111) can turn on the channel.

4. The SiC JFET cell structure with integrated Schottky diode according to claim 3, characterized in that: The source Schottky contact layer (109) is located directly above the vertical conductive channel structure to form a Schottky diode structure.

5. The SiC JFET cell structure with integrated Schottky diode according to claim 1, characterized in that: The materials of the N+ substrate layer (102), the N-drift region (103), the N current extension region (105), and the N+ source region (107) are N-type silicon carbide, and the doping elements are nitrogen or phosphorus. The doping concentration of the N+ substrate layer (102) is 1×10 19 ~1×10 20 cm -3 , the doping concentration of the N-drift region (103) is 1×10 15 ~1×10 16 cm -3 , the doping concentration of the N current extension region (105) is 1×10 16 ~5×10 17 cm -3 , the doping concentration of the N+ source region (107) is 1×10 19 ~1×10 20 cm -3 .

6. The SiC JFET cell structure with integrated Schottky diode according to claim 1, characterized in that: The material of the P first gate region (104) and the P second gate region (106) is P-type silicon carbide, the doping element is aluminum or boron, and the doping concentration of the P first gate region (104) is 1×10 18 ~5×10 19 cm -3 , the doping concentration of the second gate region (104) is 1×10 17 ~1×10 18 cm -3 .

7. The SiC JFET cell structure with integrated Schottky diode according to claim 1, characterized in that: The thickness of the P first gate region (104) is 0.5 μm to 2 μm, and the thickness of the P second gate region (106) is 0.2 μm to 1 μm.

8. The SiC JFET cell structure with integrated Schottky diode according to claim 1, characterized in that: The insulating dielectric layer (112) includes SiN, HfO2 or Al2O3.

9. A SiC JFET structure with an integrated Schottky diode, characterized in that: It is obtained by sequentially connecting the cellular structures described in any one of claims 1 to 8.

10. A method for preparing a SiC JFET structure with an integrated Schottky diode, characterized in that: The following steps are involved: (1) epitaxially growing an N-epitaxial layer on the silicon carbide N+ substrate layer (102) to form an N-drift region (103); (2) performing P-type ion implantation on the upper surface of the N-drift region (103) obtained in step (1), and performing high-temperature activation annealing to form a P first gate region (104); (3) epitaxially growing another N-type epitaxial layer on the upper surface of the N-drift region (103) obtained in step (2) to form an N current extension region (105); (4) performing P-type ion implantation on the upper surface of the N current extension region (105) obtained in step (3); (5) performing N-type ion implantation on the upper surface of the N current extension region (105) obtained in step (4), and performing high temperature activation annealing to form an N+ source region (107) and a P second gate region (106); (6) Etching is performed on the N+ source region (107) obtained in step (5) to form a gate trench (113), and a gate metallization layer (111) is formed at the bottom of the trench; (7) An insulating dielectric layer (112) is formed inside the gate trench (113) obtained in step (6); (8) sputtering an ohmic contact layer (108) on the upper surface of the N+ source region (107), and sputtering a Schottky contact layer (109) in the area between the N+ source regions (107); (9), forming a source metallization layer (110) on the upper surfaces of the Schottky contact layer (109), the ohmic contact layer (108) and the insulating dielectric layer (112); forming a drain metallization layer (111) on the lower surface of the N substrate, and finally obtaining a SiC JFET cell structure with an integrated Schottky diode; (10) Connecting multiple SiC JFET cell structures with integrated Schottky diodes obtained in step (9) in sequence to obtain a SiC JFET structure with integrated Schottky diodes.

Images