Semiconductor element and forming method thereof

Abstract

The invention relates to a semiconductor element and a forming method thereof. Techniques described herein include forming respective (different) types of gate metals for p-type metal oxide semiconductor (PMOS) nanostructure transistors and maintaining intrinsic n-type metal oxide semiconductor (NMOS) nanostructure transistors for semiconductor elements. A p-type gate metal may be formed around a nanostructure channel of a PMOS nanostructure transistor. A surface of the p-type gate metal may then be oxidized to form a metal oxide layer on the p-type gate metal. During formation of an n-type gate metal around a nanostructured channel of an NMOS nanostructured transistor, a metal oxide layer on a p-type gate metal prevents the n-type gate metal from being formed on the p-type gate metal. This results in little or no n-type gate metal deposition on the p-type gate metal, thereby minimizing the impact of the p-type threshold voltage (PVt) on the PMOS nanostructured transistor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of forming the same. Background Art

[0002] With the progress of semiconductor device manufacturing and the reduction of the size of the technology processing nodes, transistors may be affected by short-channel effects (SCEs), such as hot-carrier degradation, barrier lowering, and quantum confinement. In addition, as the gate length of the transistor is reduced to achieve a smaller technology node, the source / drain (S / D) electron tunneling effect increases, thereby increasing the off-current of the transistor (the current flowing through the transistor channel when the transistor is turned off). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, nanoribbons, nanotubes, multi-bridge channels, and gate-all-around (GAA) devices, are potential candidates for overcoming short-channel effects at smaller technology nodes. Nanostructure transistors are efficient structures that can reduce SCEs and enhance carrier mobility compared to other types of transistors. Summary of the Invention

[0003] The present disclosure provides a method of forming a semiconductor device, comprising: forming a first plurality of nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; forming a second plurality of nanostructure channel layers arranged in a direction substantially perpendicular to the semiconductor substrate; forming a first-type metal layer surrounding the first plurality of nanostructure channel layers; forming a metal oxide layer on the first-type metal layer; and forming a second-type metal layer on the metal oxide layer and on the second plurality of nanostructure channel layers. Wherein a first thickness of the second-type metal layer on the metal oxide layer is different from a second thickness of the second-type metal layer on the second plurality of nanostructure channel layers.

[0004] The present disclosure provides a semiconductor device, comprising a first plurality of nanostructure channel layers, a second plurality of nanostructure channel layers, a first gate structure, and a second gate structure. The first plurality of nanostructure channel layers are arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. The second plurality of nanostructure channel layers are adjacent to the first plurality of nanostructure channel layers and are arranged in a direction substantially perpendicular to the semiconductor substrate. The first gate structure surrounds the first plurality of nanostructure channel layers and comprises a p-type metal layer and a metal oxide layer. The metal oxide layer comprises a material. The material comprises an oxide of a p-type metal of the p-type metal layer. The second gate structure surrounds the second plurality of nanostructure channel layers and comprises an n-type metal layer. The n-type metal layer is disposed on the metal oxide layer of the first gate structure.

[0005] The present disclosure provides a method for forming a semiconductor device, comprising: forming a first plurality of nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; forming a second plurality of nanostructure channel layers arranged in a direction substantially perpendicular to the semiconductor substrate; forming a p-type metal layer such that the p-type metal layer surrounds the first plurality of nanostructure channel layers and the second plurality of nanostructure channel layers; forming a mask layer over the first plurality of nanostructure channel layers; when the mask layer is located over the first plurality of nanostructure channel layers, removing a portion of the p-type metal layer from the second plurality of nanostructure channel layers, wherein a remaining portion of the p-type metal layer surrounding the first plurality of nanostructure channel layers corresponds to a first gate structure; after removing the portion of the p-type metal layer, removing the mask layer; after removing the mask layer, performing an oxidation operation to form a metal oxide layer on the p-type metal layer of the first gate structure; and after forming the metal oxide layer, forming an n-type metal layer of a second gate structure such that the n-type metal layer surrounds the second plurality of nanostructure channel layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 FIG. is a block diagram depicting an example environment in which the systems and / or methods described in the present disclosure may be implemented;

[0008] Figure 2 FIG. is a schematic diagram depicting an example semiconductor device described in the present disclosure;

[0009] Figure 3A AND Figure 3B FIG. is a schematic diagram depicting an example implementation of a fin formation process described in the present disclosure;

[0010] Figure 4A AND Figure 4B FIG. is a schematic diagram depicting an example implementation of a shallow trench isolation (STI) process described in the present disclosure;

[0011] Figure 5 FIG. is a schematic diagram depicting an example implementation of a dummy gate structure formation process described in the present disclosure;

[0012] Figure 6 FIG. is a schematic diagram depicting an example implementation of a dummy gate structure formation process described in the present disclosure;

[0013] Figures 7A to 7D FIG. is a schematic diagram depicting an example implementation of a source / drain recess formation process and an internal spacer formation process described in the present disclosure;

[0014] Figure 8 A schematic diagram showing an exemplary embodiment of the source / drain region formation process described in this disclosure;

[0015] Figure 9 A schematic diagram showing an exemplary embodiment of the interlayer dielectric layer formation process described in this disclosure;

[0016] Figures 10A to 10L A schematic diagram showing an exemplary embodiment of the replacement gate process described in this disclosure;

[0017] Figure 11 A schematic diagram showing an example of the n-type metal thickness of various types of p-metal oxidation techniques described in this disclosure;

[0018] Figure 12 A diagram showing an example of the flat-band voltage of the p-type gate structure for various types of p-metal oxidation techniques described in this disclosure;

[0019] Figure 13 A schematic diagram showing the example elements of one or more devices described in this disclosure;

[0020] Figure 14 And Figure 15 A flowchart showing an example process associated with forming the semiconductor element described in this disclosure;

[0021] Figure 16A And Figure 16B A schematic diagram showing an exemplary embodiment of the replacement gate process described in this disclosure.

[0022]

Symbol Description

[0023] 100: Exemplary environment

[0024] 102 - 112: Semiconductor processing tools

[0025] 102: Deposition tool

[0026] 104: Exposure tool

[0027] 106: Development tool

[0028] 108: Etching tool

[0029] 110: Planarization tool

[0030] 112: Electroplating tool

[0031] 114: Wafer / die transfer tool

[0032] 200: Semiconductor element

[0033] 205: Semiconductor substrate

[0034] 210, 210a, 210b: Boss region

[0035] 215: Shallow trench isolation region

[0036] 220, 220a, 220b: Nanostructure channel

[0037] 225: Source / drain region

[0038] 230: Buffer

[0039] 235 Overlayer

[0040] 240: Gate structure

[0041] 240a: n-type gate structure

[0042] 240b: p-type gate structure

[0043] 245: Inner spacer

[0044] 250: Interlayer dielectric

[0045] 300, 400, 500, 600, 700, 800, 900, 1000, 1600: Example embodiments

[0046] 305: Stack

[0047] 310: First layer

[0048] 315: Second layer

[0049] 320: Hard mask layer

[0050] 325: Overlayer

[0051] 330: Oxide layer

[0052] 335: Nitride layer

[0053] 340: Portion

[0054] 345, 345a, 345b: Fin structure

[0055] 405: Pad

[0056] 410: Dielectric layer

[0057] 505:Dummy gate structure

[0058] 510: Gate electrode layer

[0059] 515: Hard mask layer

[0060] 520: Spacer layer

[0061] 525: Gate dielectric layer

[0062] 705: Source / drain groove

[0063] 710: Cavity

[0064] 715: Insulating layer

[0065] 805: Etch stop layer

[0066] 1005: Opening

[0067] 1010a: High-k dielectric liner

[0068] 1010b: Adhesion liner

[0069] 1015: p-type metal layer

[0070] 1020: Photoresist layer

[0071] 1025: Oxidation operation

[0072] 1030: Metal oxide layer

[0073] 1035: n-type metal layer

[0074] 1040: Capping layer

[0075] 1045: Gate layer

[0076] 1100,1200: Embodiment

[0077] 1110,1115,1120,1125,1210,1215,1220: Reference numeral

[0078] 1300: Device

[0079] 1310: Bus

[0080] 1320: Processor

[0081] 1330: Memory

[0082] 1340: Input element

[0083] 1350: Output element

[0084] 1360: Communication element

[0085] 1400: Process

[0086] 1410,1420,1430,1440,1450,1460,1470,1480: Block

[0087] 1500: Process

[0088] D1, D2, D3, D4, D5, D6, D7, D8, D9, D10: Dimensions Detailed implementation manners

[0089] The following disclosure provides many different implementation manners or embodiments for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an implementation manner of forming the first feature and the second feature in direct contact, and may also include an implementation manner of forming an additional feature between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various implementation manners and / or configurations discussed.

[0090] In addition, for ease of description, the present disclosure may use spatial relativity terms such as "below", "beneath", "lower", "above", "upper", "top", "bottom" and similar terms to describe the relationship between one element or feature and another element or feature shown in the figures. Except for the orientations depicted in the figures, the spatial relativity terms are intended to cover different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and thus the spatial relativity descriptors used in this disclosure may be interpreted similarly.

[0091] The nanostructure transistor may include a gate structure surrounding a plurality of nanostructure channels. Among other embodiments, the gate structure surrounding the nanostructure channels increases the control of the gate structure over the conductive channels in the nanostructure channels, increases the drive current of the nanostructure transistor, and / or may reduce the short-channel effect (SCE) of the nanostructure transistor. In some cases, the semiconductor element may include p-type metal-oxide-semiconductor (PMOS) nanostructure transistors and n-type metal-oxide-semiconductor (NMOS) nanostructure transistors. Integrating PMOS nanostructure transistors and NMOS nanostructure transistors into the same semiconductor element enables the implementation of complementary metal-oxide-semiconductor (CMOS) integrated circuits in the semiconductor element. There are many applications of CMOS integrated circuits in the semiconductor industry, including microprocessors (such as central processing units (CPUs), graphics processing units (GPUs)), memories, digital logic circuits, image sensors (such as CMOS image sensors), and / or radio frequency (RF) circuits, etc.

[0092] The threshold voltage (V of the nanostructure transistor t) is the gate voltage required to selectively turn on or off the nanostructure transistor. If the threshold voltage of the nanostructure transistor is too low (meaning the gate voltage used to activate the nanostructure transistor is too low), then when the nanostructure transistor is turned off, the nanostructure transistor may experience a large amount of current leakage. Conversely, if the threshold voltage of the nanostructure transistor is too high, the power efficiency of the nanostructure transistor may be reduced because a higher gate voltage is required to operate the nanostructure transistor. For PMOS nanostructure transistors and NMOS nanostructure transistors, the type of metal used for the gate structure can directly affect the threshold voltages of the PMOS nanostructure transistor and the NMOS nanostructure transistor. Adjusting the work function of the gate structure ( ) The metal to achieve the best performance of the PMOS nanostructure transistor may result in a large bandgap between the work function of the gate structure of the NMOS nanostructure transistor and the conduction band (EC), resulting in a high threshold voltage (and low power efficiency) of the NMOS nanostructure transistor. The metal that adjusts the work function of the gate structure to obtain the best performance of the NMOS nanostructure transistor may result in a large bandgap between the work function of the gate structure of the PMOS nanostructure transistor and the valence band (EV), resulting in a high threshold voltage (and low power efficiency) of the PMOS nanostructure transistor.

[0093] Some embodiments described in this disclosure provide semiconductor manufacturing techniques and related semiconductor structures for forming PMOS nanostructure transistors and NMOS nanostructure transistors in semiconductor devices. The techniques described in this disclosure include forming various (different) types of gate metals for the PMOS nanostructure transistor and maintaining the intrinsic NMOS nanostructure transistor of the semiconductor device. A p-type gate metal can be formed around the nanostructure channel of the PMOS nanostructure transistor. Then, the surface of the p-type gate metal can be oxidized to form a metal oxide layer on the p-type gate metal. During the formation of the n-type gate metal around the nanostructure channel of the NMOS nanostructure transistor, the metal oxide layer on the p-type gate metal prevents the formation of the n-type gate metal on the p-type gate metal. This results in little or no deposition of the n-type gate metal on the p-type gate metal, thereby minimizing the impact of the p-type threshold voltage (PV t ) on the PMOS nanostructure transistor. In this way, the techniques described in this disclosure enable the adjustment of the work functions of the NMOS nanostructure transistor and the PMOS nanostructure transistor to achieve the desired threshold voltages of the NMOS nanostructure transistor and the PMOS nanostructure transistor. This enables the NMOS nanostructure transistor and the PMOS nanostructure transistor to achieve low leakage current and enables the NMOS nanostructure transistor and the PMOS nanostructure transistor to achieve high operating efficiency.

[0094] Figure 1 is a diagram of an example environment 100 in which the systems and / or methods described in this disclosure can be implemented. As Figure 1 shown, the example environment 100 can include multiple semiconductor processing tools 102 - 112 and a wafer / die transfer tool 114. The multiple semiconductor processing tools 102 - 112 can include a deposition tool 102, an exposure tool 104, a development tool 106, an etch tool 108, a planarization tool 110, an electroplating tool 112, and / or another type of semiconductor processing tool. In addition to other embodiments, the tools included in the example environment 100 can be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility.

[0095] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more components capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a high density plasma CVD (HDP - CVD) tool, a sub - atmospheric pressure CVD (SACVD) tool, a low pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form layers and / or regions of components by epitaxial growth. In some embodiments, the example environment 100 includes multiple types of deposition tools 102.

[0096] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme ultraviolet light (EUV) source, etc.), an x - ray source, an electron beam (e - beam) source, etc. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern can include one or more semiconductor component layer patterns for forming one or more semiconductor components, can include a pattern for forming one or more structures of a semiconductor component, can include a pattern for etching various parts of a semiconductor component. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0097] The developing tool 106 is a semiconductor processing tool that can develop a photoresist layer that has been exposed to a radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0098] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials on a substrate, wafer, or semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber that can be filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 uses plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which can involve using an ionized gas to etch the one or more portions isotropically or directionally. In some embodiments, the etching tool 108 includes a plasma-based asher to remove photoresist material and / or another material.

[0099] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing the layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or electroplated material. The planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of the semiconductor device. The planarization tool 110 can be used in combination with a polishing pad and a retainer ring (e.g., typically having a larger diameter than the semiconductor device) with an abrasive and corrosive chemical slurry. The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and held in place by the retainer ring. The dynamic polishing head can rotate about different axes of rotation to remove material and flatten any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

[0100] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the electroplating tool 112 can include a copper electroplating element, an aluminum electroplating element, a nickel electroplating element, a tin electroplating element, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating element, and / or an electroplating element for one or more other types of conductive materials, metals, and / or similar types of materials.

[0101] The wafer / die transport tool 114 includes a mobile robot, a robotic arm, a tram or a rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or another type of element configured to transfer substrates and / or semiconductor components between semiconductor processing tools 102-112, which are configured to transfer substrates and / or semiconductor components between processing chambers of the same semiconductor processing tool, and / or configured to transfer substrates and / or semiconductor components to and from other locations, such as wafer racks, storage rooms, etc. In some embodiments, the wafer / die transport tool 114 can be a program element configured to travel a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer / die transport tools 114.

[0102] For example, the wafer / die transport tool 114 can be incorporated in a cluster tool or another type of tool that includes multiple processing chambers and can be configured to transfer substrates and / or semiconductor components between multiple processing chambers, to transfer substrates and / or semiconductor components between a processing chamber and a buffer, to transfer substrates and / or semiconductor components between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or, among other examples, to transport substrates and / or semiconductor components between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)). In some embodiments, the wafer / die transport tool 114 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or by-products from substrates and / or semiconductor components) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport tool 114 is configured to transfer substrates and / or semiconductor components between the processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the processing chambers and / or between the processing operations in the deposition tool 102, as described in this disclosure.

[0103] As described in this disclosure, semiconductor processing tools 102-112 can perform a combination of operations to form one or more portions of a nanostructure transistor. In some embodiments, the combination of operations includes forming a first plurality of nanostructure channel layers arranged substantially perpendicular to the direction of the semiconductor substrate of the semiconductor element; and forming the first plurality of nanostructure channel layers. Forming a second plurality of nanostructure channel layers arranged substantially perpendicular to the direction of the semiconductor substrate; forming a p-type metal layer of the first gate structure such that the p-type metal layer coats each of the first plurality of nanostructure channel layers; forming a metal oxide layer on the p-type metal layer; and / or forming an n-type metal layer of the second gate structure after forming the metal oxide layer such that the n-type metal layer surrounds each of the second plurality of nanostructure channel layers, etc.

[0104] In some embodiments, the combination of operations includes forming a first plurality of nanostructure channel layers arranged substantially perpendicular to the direction of the semiconductor substrate of the semiconductor element; forming a second plurality of nanostructure channel layers arranged substantially perpendicular to the direction of the semiconductor substrate; forming a p-type metal layer such that the p-type metal layer surrounds each of the first plurality of nanostructure channel layers and each of the second plurality of nanostructure channel layers; forming a mask layer over the first plurality of nanostructure channel layers; when the mask layer is over the first plurality of nanostructure channel layers, removing a portion of the p-type metal layer from the second plurality of nanostructure channel layers, wherein the remaining portion of the p-type metal layer surrounds the nanostructure channel layers corresponding to the first gate structure around the first plurality of nanostructure channel layers; after removing the portion of the p-type metal layer, removing the mask layer; after removing the mask layer, performing an oxidation operation to form a metal oxide layer on the p-type metal layer of the first gate structure; and / or forming an n-type metal layer of the second gate structure after forming the metal oxide layer such that the n-type metal layer surrounds each of the second plurality of nanostructure channel layers, etc.

[0105] In some embodiments, the combination of operations includes combining Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figures 7A to 7D , Figure 8 , Figure 9 , Figures 10A to 10L , Figure 15 and / or Figure 16A , Figure 16B one or more operations described in one or more of and other embodiments.

[0106] Figure 1 The number and arrangement of the devices shown are provided as one or more embodiments. In fact, there may be more than Figure 1Additional devices, fewer devices, different devices, or devices in a different arrangement as shown. Additionally, Figure 1 Two or more of the devices shown can be implemented within a single device or a single device Figure 1 The devices shown can be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of example environment 100 can perform one or more functions described as being performed by another set of devices of example environment 100.

[0107] Figure 2 is a diagram of semiconductor element 200 of an embodiment described in this disclosure. Semiconductor element 200 includes one or more semiconductors. The one or more semiconductors can include nanostructure transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge-channel transistors, nanoribbon transistors, and / or other types of nanostructure transistors. Semiconductor element 200 can include Figure 2 One or more additional elements, structures, and / or layers not shown in. For example, semiconductor element 200 can include additional layers and / or grains formed on layers above and / or below that portion. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor elements can be formed in the same layer of an electronic component or integrated circuit (IC) that includes a semiconductor element as Figure 2 shown. Semiconductor element 200 is as Figure 2 shown. Figures 3A to 12 can include Figure 2 Schematic cross-sectional views of the respective portions of semiconductor element 200 shown, and corresponding to the respective processing stages of the nanostructure transistors forming semiconductor element 200.

[0108] The semiconductor component 200 includes a semiconductor substrate 205. The semiconductor substrate 205 includes a silicon (Si) substrate, a substrate formed of a silicon-containing material, a group III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The semiconductor substrate 205 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. The semiconductor substrate 205 may include a compound semiconductor and / or an alloy semiconductor. The semiconductor substrate 205 may include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., n-type wells, p-type wells) may be formed in regions of the semiconductor substrate 205 designed for different component types (e.g., p-type metal-oxide-semiconductor (PMOS) nanostructure transistors, n-type metal-oxide-semiconductor (NMOS) nanostructure crystals). Suitable doping may include ion implantation and / or diffusion processes of dopants. Additionally, the semiconductor substrate 205 may include an epitaxial layer, may be strained for performance enhancement, and / or may have other suitable enhancement features. The semiconductor substrate 205 may include a portion of a semiconductor wafer on which other semiconductor components are formed.

[0109] A pedestal region 210 is included above (and / or extends above) the semiconductor substrate 205. The pedestal region 210 provides a structure on which nanostructures of the semiconductor component 200 are formed, such as nanostructure channels, surrounding nanostructure gate portions. Among other embodiments, each nanostructure channel and / or sacrificial nanostructure. In some embodiments, one or more pedestal regions 210 are formed in fin structures (e.g., silicon fin structures) in the semiconductor substrate 205 and / or are formed by fin structures (e.g., silicon fin structures). The pedestal region 210 may include the same material as the semiconductor substrate and be formed from the semiconductor substrate 205. In some embodiments, the pedestal region 210 is doped to form different types of nanostructure transistors, such as p-type nanostructure transistors and / or n-type nanostructure transistors. In some embodiments, the pedestal region 210 includes a silicon (Si) material or another elemental semiconductor material such as germanium (Ge). In some embodiments, the pedestal region 210 includes an alloy semiconductor material, such as silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0110] The boss region 210 is fabricated by appropriate semiconductor processing techniques, such as photomasks, shadow masks, and / or etching processes, etc. As an example, a fin structure can be formed by etching away a portion of the semiconductor substrate 205 to form a groove in the semiconductor substrate 205. The groove can then be filled with an isolation material, which is recessed or etched back to form a shallow trench isolation (STI) region 215 over the semiconductor substrate 205 and between the fin structures. Source / drain grooves can be formed in the fin structures, which results in the formation of the boss region 210 between the source / drain grooves. However, other fabrication techniques for the shallow trench isolation region 215 and / or for the boss region 210 can be used.

[0111] The shallow trench isolation region 215 can electrically isolate adjacent fin structures and can provide a layer for other layers and / or structures on which semiconductor elements 200 are formed. The shallow trench isolation region 215 can comprise a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. The shallow trench isolation region 215 can comprise a multi-layer structure, such as having one or more liner layers.

[0112] The semiconductor element 200 includes a plurality of nanostructure channels 220 that extend between source / drain regions 225 and are electrically coupled to the source / drain regions 225. The "source / drain region" can refer to the source or the drain individually, or collectively depending on the context. The nanostructure channels 220 are arranged substantially perpendicular to the direction of the semiconductor substrate 205. In other words, the nanostructure channels 220 are vertically arranged or stacked above the semiconductor substrate 205.

[0113] The nanostructure channels 220 comprise silicon-based nanostructures (e.g., nanosheets or nanowires, etc.) that serve as the semiconductor channels of the nanostructure transistors of the semiconductor element 200. In some embodiments, the nanostructure channels 220 can comprise silicon germanium (SiGe) or another silicon-based material. The source / drain regions 225 comprise silicon (Si) with one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), etc.), an n-type material (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Thus, the semiconductor element 200 can comprise p-type metal oxide semiconductor (PMOS) nanostructure transistors comprising p-type source / drain regions, n-type metal oxide semiconductor (NMOS) nanostructure transistors comprising n-type source / drains, and / or other types of nanostructure transistors.

[0114] In some embodiments, buffer 230 is incorporated below source / drain region 225, between source / drain region 225 and the fin structure above semiconductor substrate 205. Buffer 230 can provide isolation between source / drain region 225 and adjacent pedestal region 210. Buffer 230 can include reducing, minimizing, and / or preventing electrons from passing through pedestal region 210 (e.g., instead of through nanostructure channel 220, thereby reducing current leakage), and / or can be included to reduce, minimize, and / or prevent dopants from entering pedestal region 210 from source / drain region 225 (which reduces short-channel effects).

[0115] Capping layer 235 can be included on and / or over source / drain region 225. Capping layer 235 can include silicon, silicon germanium, doped silicon, doped silicon germanium, and / or another material. Capping layer 235 can be included to reduce dopant diffusion and to protect source / drain region 225 during semiconductor processing operations of semiconductor device 200 prior to contact formation. Additionally, capping layer 235 can facilitate the formation of a metal-semiconductor (e.g., silicide) alloy.

[0116] At least a subset of nanostructure channels 220 extends through one or more gate structures 240. Gate structure 240 can be formed of one or more metal materials, one or more high dielectric constant (high-k) materials, and / or and / or one or more other types of materials. In some embodiments, a dummy gate structure (e.g., a polysilicon (PO) gate structure or another type of gate structure) is formed in the location of gate structure 240 (e.g., prior to the formation of gate structure 240) such that one or more other layers and / or structures of semiconductor device 200 can be formed prior to the formation of gate structure 240. This reduces and / or prevents damage to gate structure 240 that would otherwise be caused by the formation of one or more layers and / or structures. A replacement gate process (RGP) is then performed to remove the dummy gate structure and replace the dummy gate structure with gate structure 240 (e.g., a replacement gate structure).

[0117] As Figure 2 Further shown, portions of gate structure 240 are formed in an alternating vertical arrangement between pairs of nanostructure channels 220. In other words, semiconductor device 200 includes alternating nanostructure channels 220 and one or more vertically stacked portions of gate structure 240, as Figure 2 shown. In this manner, gate structure 240 surrounds the associated nanostructure channels 220 on multiple sides of nanostructure channels 220, which increases the control of nanostructure channels 220, increases the drive current of the nanostructure transistors of semiconductor device 200, and reduces the short-channel effect (SCE) of the nanostructure transistors of semiconductor device 200.

[0118] Some source / drain regions 225 and gate structures 240 may be shared between two or more nanoscale semiconductors of the semiconductor device 200. In these embodiments, one or more source / drain regions 225 and gate structures 240 may be connected or coupled to a plurality of nanostructure channels 220, as Figure 2 shown in the embodiments of

[0119] An internal spacer (InSP) 245 may be included between the source / drain region 225 and an adjacent gate structure 240. Specifically, the internal spacer 245 may be included between the source / drain region 225 and the following portion of the gate structure 240 that surrounds the plurality of nanostructure channels 220. The internal spacer 245 is included on the end portions of the portion of the gate structure 240 that surrounds the plurality of nanostructure channels 220. The internal spacer 245 is included in a cavity formed between the end portions. The internal spacer 245 is included to reduce parasitic capacitance and protect the source / drain region 225 from being etched during the nanosheet release operation to remove sacrificial nanosheets between the nanostructure channels 220. The internal spacer 245 includes silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or other dielectric materials.

[0120] The semiconductor device 200 may further include an interlayer dielectric (ILD) layer 250 over the shallow trench isolation region 215. The interlayer dielectric layer 250 may be referred to as the ILD0 layer. By analogy, the interlayer dielectric layer 250 surrounds the gate structure 240 to provide electrical isolation and / or insulation between the gate structure 240 and / or the source / drain region 225. Conductive structures such as contacts and / or interconnects may be formed through the interlayer dielectric layer 250 to reach the source / drain region 225 and the gate structure 240 to provide control of the source / drain region 225 and the gate structure 240.

[0121] As described above, provided Figure 2 as an example. Other embodiments may be different from those described with respect to Figure 2 .

[0122] Figure 3A and Figure 3B are diagrams of an example embodiment 300 of a fin formation process described in this disclosure. The example embodiment 300 includes embodiments of forming fin structures of the semiconductor device 200 or a portion thereof. The semiconductor device 200 may include Figure 3A andFigure 3B one or more additional elements, structures, and / or layers not shown. The semiconductor element 200 may include additional layers and / or wafers formed on layers above and / or below portions of the semiconductor element 200 shown Figure 3A and Figure 3B shown. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor elements may be formed in the same layer as the electronic component including the semiconductor element 200.

[0123] Figure 3A A perspective view and a cross-sectional view along line A-A in the perspective view of the semiconductor element 200 are shown. As shown, with reference Figure 3A , the processing of the semiconductor element 200 is performed in conjunction with the semiconductor substrate 205. A stack 305 is formed on the semiconductor substrate 205. The stack 305 may be referred to as a superlattice. In some embodiments, one or more operations related to the semiconductor substrate 205 are performed before forming the stack 305. For example, an anti-punchthrough (APT) implantation operation may be performed. The APT implantation operation may be performed in one or more regions of the semiconductor substrate 205 where the nanostructure channel 220 will be formed. Performing the APT implantation operation, for example, is to reduce and / or prevent punchthrough or unwanted diffusion into the semiconductor substrate 205.

[0124] The stack 305 includes a plurality of alternating layers arranged in a direction generally perpendicular to the semiconductor substrate 205. For example, the stack 305 includes a vertical alternating layer of a first layer 310 and a second layer 315 above the semiconductor substrate 205. Figure 3A The illustrated embodiment is the number of the first layer 310 and the number of the second layer 315, and other numbers of the first layer 310 and the second layer 315 are also within the scope of the present disclosure. In some embodiments, the first layer 310 and the second layer 315 are formed with different thicknesses. For example, the second layer 315 may be formed with a thickness greater than that of the first layer 310. In some embodiments, the first layer 310 (or a subset thereof) is formed with a thickness in the range of about 4 nanometers to about 7 nanometers. In some embodiments, the second layer 315 (or a subset thereof) is formed with a thickness in the range of about 8 nanometers to about 12 nanometers. However, other values of the thickness of the first layer 310 and the thickness of the second layer 315 are also within the scope of the present disclosure.

[0125] The first layer 310 includes a first material component, and the second layer 315 includes a second material component. In some embodiments, the first material component and the second material component are the same material component. In some embodiments, the first material component and the second material component are different material components. As an example, the first layer 310 may include silicon germanium (SiGe) and the second layer 315 may include silicon (Si). In some embodiments, the first material composition and the second material composition have different oxidation rates and / or etching selectivities.

[0126] As described in this disclosure, the second layer 315 can be processed to form a nanostructure channel 220 for a nanostructure transistor to be subsequently formed of the semiconductor device 200. The first layer 310 is a sacrificial nanostructure that is ultimately removed and used to define a vertical distance. And between adjacent nanostructure channels 220 of the gate structure 240 for the subsequently formed semiconductor device 200. Thus, the first layer 310 is referred to as a sacrificial layer in this disclosure, and the second layer 315 can be referred to as a channel layer.

[0127] The deposition tool 102 deposits and / or grows alternating layers of the stack 305 on the semiconductor substrate 205 to include nanostructures (e.g., nanosheets). For example, the deposition tool 102 grows the alternating layers by epitaxial growth. However, other processes can be used to form the alternating layers of the stack 305. The epitaxial growth process of the alternating layers of the stack 305 can be performed by molecular beam epitaxy (MBE) process, metalorganic chemical vapor deposition (MOCVD), and / or another suitable epitaxial growth process. In some embodiments, an epitaxial growth layer such as the second layer 315 includes the same material as the material of the semiconductor substrate 205. In some embodiments, the first layer 310 and / or the second layer 315 include materials different from the material of the semiconductor substrate 205. As described above, in some embodiments, the first layer 310 includes an epitaxial grown silicon germanium (SiGe) layer, and the second layer 315 includes an epitaxial grown silicon (Si) layer. Alternatively, the first layer 310 and / or the second layer 315 can include other materials such as germanium (Ge), compound semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (IAs), indium antimonide (InSb), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), alloy semiconductors such as indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), and / or combinations thereof. The material of the first layer 310 and / or the material of the second layer 315 can be selected based on providing different oxidation characteristics, different etching selectivity characteristics, and / or other different characteristics.

[0128] As Figure 3AFurther shown, the deposition tool 102 can form one or more additional layers on and / or over the stack 305. For example, a hard mask (HM) layer 320 can be formed on and / or over the stack 305. On the stack 305 (e.g., on the topmost second layer 315 of the stack 305). As another example, a capping layer 325 can be formed on and / or over the hard mask layer 320. As another example, another hard mask layer including an oxide layer 330 and a nitride layer 335 can be formed on and / or over the capping layer. One or more hard mask layers 320, 325, and 330 can be used to form one or more structures of the semiconductor device 200. The oxide layer 330 can serve as an adhesion layer between the stack 305 and the nitride layer 335 and can serve as an etch stop layer for etching the nitride layer 335. One or more hard mask layers 320, 325, and 330 can include silicon germanium (SiGe), silicon nitride (SixNy), silicon oxide (SiOx), and / or other materials. The capping layer 325 can include silicon (Si) and / or other materials. In some embodiments, the capping layer 325 is formed of the same material as the semiconductor substrate 205. In some embodiments, one or more additional layers are thermally grown, deposited by CVD, PVD, ALD, and / or formed using another deposition technique.

[0129] Figure 3B A perspective view and a cross-sectional view taken along line A-A of the semiconductor device 200 are shown. As Figure 3B shown, the stack 305 and the semiconductor substrate 205 are etched to remove portions of the stack 305 and portions of the semiconductor substrate 205. The portion 340 of the stack 305 and the pedestal region 210 (also referred to as a silicon pedestal or pedestal portion) remaining after the etching operation are referred to as fin structures 345 above the semiconductor substrate 205 of the semiconductor device 200. The fin structures 345 include the portion 340 of the stack 305 on and / or over the semiconductor substrate 205 of the semiconductor device 200. The pedestal region 210 is formed in and / or above the semiconductor substrate 205. The fin structures 345 can be formed by any suitable semiconductor processing technique. For example, the deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108 can use one or more lithography processes (including double patterning or multi-patterning processes) to form the fin structures 345. Generally, double patterning or multi-patterning processes combine lithography processes with self-alignment processes, thereby allowing the creation of patterns having, for example, a smaller pitch than can be obtained using a single direct lithography process. For example, a sacrificial layer can be formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures.

[0130] In some embodiments, a deposition tool 102 forms a photoresist layer over and / or on top of a hard mask layer that includes an oxide layer 330 and a nitride layer 335. An exposure tool 104 exposes the photoresist layer to radiation (e.g., deep ultraviolet (UV) radiation, extreme ultraviolet (EUV) radiation), performs a post-exposure bake process (e.g., to remove residual solvents from the photoresist layer), and a development tool 106 develops the photoresist layer to form a mask element (or pattern) in the photoresist layer. In some embodiments, patterning the photoresist layer to form a mask element is performed using an electron beam (e-beam) lithography process. The mask element can then be used to protect portions of the semiconductor substrate 205 and portions of the stack 305 during an etching operation such that portions of the semiconductor substrate 205 and portions of the stack 305 remain unetched to form fin structures 345. The unprotected portions of the substrate and the unprotected portions of the stack 305 are etched (e.g., by an etching tool 108) to form channels in the semiconductor substrate 205. The etching tool can etch the unprotected portions of the substrate and the unprotected portions of the stack 305. A dry etching technique (e.g., reactive ion etching), a wet etching technique, and / or a combination thereof are used to form the stack 305.

[0131] In some embodiments, another fin formation technique is used to form the fin structures 345. For example, a fin region can be defined (e.g., by a mask or an isolation region), and the portion 340 can be epitaxially grown in such a way that, in some embodiments, forming the fin structures 345 includes a trimming process to reduce the width of the fin structures 345. Among other examples, the trimming process can include a wet and / or dry etching process.

[0132] As Figure 3B Further shown, fin structures 345 can be formed for different types of nanostructure transistors of the semiconductor device 200. Specifically, a first subset of fin structures 345a can be formed for p-type nanostructure transistors (e.g., p-type metal-oxide-semiconductor (PMOS) nanostructure transistors). A second subset of fin structures 345b can be formed for n-type nanostructure transistors (e.g., n-type metal-oxide-semiconductor (NMOS) nanostructure transistors). The second subset of fin structures 345b can be doped with a p-type dopant (e.g., boron (B) and / or germanium (Ge), etc.), and the first subset of fin structures 345a can be doped with an n-type dopant (e.g., phosphorus (P) and / or arsenic (As), etc.). Additionally or alternatively, a p-type source / drain region can be subsequently formed for the p-type nanostructure transistors that include the first subset of fin structures 345a, and an n-type source / drain region can be subsequently formed for the n-type nanostructure transistors that include the second subset of fin structures 345b.

[0133] A first subset of fin structures 345a of a fin structure (e.g., a PMOS fin structure) and a second subset of fin structures 345b of a fin structure (e.g., an NMOS fin structure) may be formed to include similar characteristics and / or different characteristics. For example, the first subset of fin structures 345a may be formed to a first height and the second subset of fin structures 345b may be formed to a second height, where the first height and the second height are different heights. As another example, the first subset of fin structures 345a may be formed to a first width and the second subset of fin structures 345b may be formed to a second width, where the first width and the second width are different widths. In Figure 3B the illustrated embodiment, the second width of the second subset of fin structures 345b (e.g., for an NMOS nanostructure transistor) is greater than the first width of the first subset of fin structures 345a (e.g., for a PMOS nanostructure transistor). However, other embodiments are also within the scope of this disclosure.

[0134] As described above, Figure 3A and Figure 3B is one embodiment. Other embodiments may be different from those described in Figure 3A and Figure 3B Example implementation 300 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to those operations described in connection with Figure 3A and Figure 3B .

[0135] Figure 4A and Figure 4B are diagrams of example implementation 400 of a STI formation process described in this disclosure. Example implementation 400 includes an embodiment of forming a shallow trench isolation region 215 between fin structures 345 for a semiconductor element 200 or a portion thereof. The semiconductor element 200 may include Figure 4A and / or Figure 4B one or more additional devices, structures, and / or layers not shown in Figure 4A and Figure 4B . The semiconductor element 200 may include additional layers and / or dies formed on layers above and / or below the portion of the semiconductor element 200 shown in Figure 3A and Figure 3B . Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor elements may be formed in the same layer to include the semiconductor element 200 in an electronic device. In some implementations, the operations described in connection with example implementation 400 are performed after the processes described in connection with Figure 3A and Figure 3B .

[0136] Figure 4A shows a perspective view and a cross-sectional view along line A-A of the semiconductor element 200. As Figure 4AAs shown, a liner 405 and a dielectric layer 410 are formed over a semiconductor substrate 205 and inserted (e.g., therebetween) into fin structures 345. A deposition tool 102 can deposit the liner 405 and the dielectric layer 410 on the semiconductor substrate 205 and in channels between the fin structures 345. The deposition tool 102 can form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is substantially the same as the height of the top surface of the nitride layer 335.

[0137] Alternatively, the deposition tool 102 can form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is greater relative to the height of the top surface of the nitride layer 335, as Figure 4A shown. In this way, the channels between the fin structures 345 are overfilled with the dielectric layer 410 to ensure that the channels are completely filled with the dielectric layer 410. Subsequently, a planarization tool 110 can perform a planarization or polishing operation (e.g., a CMP operation) to planarize the dielectric layer 410. The nitride layer 335 of the hard mask layer can act as a CMP stop layer in this operation. In other words, the planarization tool 110 planarizes the dielectric layer 410 until it reaches the nitride layer 335 of the hard mask layer. Thus, after the operation, the height of the top surface of the dielectric layer 410 and the height of the top surface of the nitride layer 335 are substantially equal.

[0138] The deposition tool 102 can use a conformal deposition technique to deposit the liner 405. The deposition tool 102 can use a CVD technique (e.g., a flowable CVD (FCVD) technique or another CVD technique), a PVD technique, an ALD technique, and / or another deposition technique to deposit the dielectric layer. In some embodiments, after depositing the liner 405, the semiconductor device 200 is annealed to improve the quality of the liner 405.

[0139] The liner 405 and the dielectric layer 410 each comprise a dielectric material such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. In some embodiments, the dielectric layer 410 can comprise a multi-layer structure, e.g., having one or more liner layers.

[0140] Figure 4B A perspective view and a cross-sectional view along line A-A of the semiconductor device 200 are shown. As Figure 4BAs shown, an etch-back operation is performed to remove portions of the liner 405 and the dielectric layer 410 to form the shallow trench isolation region 215. The etch tool 108 can etch the liner 405 and the dielectric layer 410. The etch-back operation forms the shallow trench isolation region 215. The etch tool 108 etches the liner 405 and the dielectric layer 410 based on a hard mask layer (e.g., a hard mask layer including an oxide layer 330 and a nitride layer 335). The etch tool 108 etches the liner 405 and the dielectric layer 410 such that the height of the shallow trench isolation region 215 is less than or approximately equal to the height of the bottom of the portion 340 of the stack 305. Thus, the stack 305 extends over the shallow trench isolation region 215. In some embodiments, the liner 405 and the dielectric layer 410 are etched such that the height of the shallow trench isolation region 215 is less than the height of the top surface of the boss region 210.

[0141] In some embodiments, the etch tool 108 uses a dry etching technique to etch the liner 405 and the dielectric layer 410. Ammonia (NH 3 ), hydrofluoric acid (HF), and / or another etchant can be used. A plasma-based dry etching technique can cause a reaction between the etchant and the materials of the liner 405 and the dielectric layer 410, including:

[0142] SiO 2 +4HF→Si F 4+2H 2 O

[0143] wherein the silicon dioxide (SiO 2 ) of the liner 405 and the dielectric layer 410 reacts with hydrofluoric acid to form a by-product containing silicon tetrafluoride (SiF 4 ) and water (H 2 O). The silicon tetrafluoride is further decomposed by hydrofluoric acid and ammonia to form ammonium fluorosilicate ((NH 4 ) 2 SiF 6 ) by-product:

[0144] SiF 4 +2HF+2NH 3 →(NH 4 ) 2 SiF 6

[0145] The ammonium fluorosilicate by-product is removed from the processing chamber of the etch tool 108. After removing the ammonium fluorosilicate, a post-treatment temperature in the range of about 100 degrees Celsius to about 250 degrees Celsius is used to sublimate the ammonium fluorosilicate into components of silicon tetrafluoride, ammonia, and hydrofluoric acid.

[0146] In some embodiments, the etch tool 108 etches the liner 405 and the dielectric layer 410 such that the height of the shallow trench isolation region 215 between a first subset of the fin structures 345a (e.g., for PMOS nanostructure transistors) is greater than the height of the shallow trench isolation region 215 between a second subset of the fin structures 345b (e.g., for NMOS nanostructure transistors). This occurs mainly because the width of the fin structures 345b is greater relative to the width of the fin structures 345a. Additionally, this causes the top surface of the shallow trench isolation region 215 between the fin structures 345a and the fin structures 345b to be tilted or skewed (e.g., sloping downward from the fin structures 345a to the fin structures 345b as shown in the embodiment of Figure 4A . Due to the etchant for the liner 405 and the dielectric layer 410 first undergoing physical adsorption (e.g., physical bonding of the liner 405 and the dielectric layer 410) due to the van der Waals force between the etchant and the surfaces of the liner 405 and the dielectric layer 410. The etchant is captured by the dipole movement force. Then the etchant attaches to the dangling bonds of the liner 405 and the dielectric layer 410, and chemisorption begins. Here, the chemisorption of the etchant on the surfaces of the liner 405 and the dielectric layer 410 results in the etching of the liner 405 and the dielectric layer 410. The larger width of the channels between the second subset of the fin structures 345b provides a larger area for chemisorption to occur on the surface, which results in a greater etching rate between the second subset of the fin structures 345b. The greater etching rate causes the height of the shallow trench isolation region 215 between the second subset of the fin structures 345b to be less than the height of the shallow trench isolation region 215 between the first subset of the fin structures 345a.

[0147] As described above, Figure 4A and Figure 4B is an embodiment. Other embodiments may be different from those described in Figure 4A and Figure 4B . The example embodiment 400 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to those operations described in connection with Figure 4A and Figure 4B .

[0148] Figure 5 is a schematic diagram of an example embodiment 500 of a dummy gate formation process described herein. The example embodiment 500 includes an embodiment of forming a dummy gate structure of a semiconductor element 200 or a portion thereof. The semiconductor element 200 may include Figure 5 one or more additional devices, structures, and / or layers not shown. The semiconductor element 200 may be included in Figure 5Additional layers and / or dies are formed on a layer above and / or below a portion of the semiconductor device 200 shown. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of the electronic device that includes the semiconductor device 200. In some embodiments, the operations described in connection with example embodiment 500 are performed after the process described in connection with Figures 3A to 4B is performed.

[0149] Figure 5 A perspective view of the semiconductor device 200 is shown. As Figure 5 shown, a dummy gate structure 505 (also referred to as a dummy gate stack or a temporary gate structure) is formed over the fin structure 345. The dummy gate structure 505 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack (e.g., the gate structure 240) in a subsequent processing stage of the semiconductor device 200. The portion of the fin structure 345 below the dummy gate structure 505 may be referred to as the channel region. The dummy gate structure 505 may also define source / drain (S / D) regions of the fin structure 345, e.g., regions of the fin structure 345 that are adjacent to and on opposite sides of the channel region.

[0150] The dummy gate structure 505 may include a gate electrode layer 510, a hard mask layer 515 on and / or over the gate electrode layer 510, and spacer layers 520 on opposite sides of and on opposite sides of the gate electrode layer 510. The dummy gate structure 505 may be formed on a gate dielectric layer 525 between the topmost second layer 315 and the dummy gate structure 505. The gate electrode layer 510 includes polysilicon (polysilicon or PO) or other materials. The hard mask layer 515 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO 2 )) or other materials) and a nitride layer (e.g., a pad nitride layer that may include silicon). Nitride (e.g., Si 3 N 4 or other materials) is formed over the oxide layer. The spacer layers 520 include silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 525 may include silicon oxide (e.g., SiO x , such as SiO 2 ), silicon nitride (e.g., Si x N y , such as Si 3 N 4 ), a high-k dielectric material, and / or another suitable material.

[0151] The layers of the dummy gate structure 505 can be formed using various semiconductor processing techniques, such as deposition (e.g., by deposition tool 102), patterning (e.g., by exposure tool 104 and development tool 106), and / or etching (e.g., by etching tool 108), etc. Such as CVD, PVD, ALD, thermal oxidation, electron beam evaporation, lithography, electron beam lithography, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), dry etching (e.g., reactive ion etching), and / or wet etching, etc.

[0152] In some embodiments, the gate dielectric layer 525 is conformally deposited on the semiconductor element 200 and then selectively removed from portions of the semiconductor element 200 (e.g., source / drain regions). Then the gate electrode layer 510 is deposited on the remaining portion of the gate dielectric layer 525. Then the hard mask layer 515 is deposited on the gate electrode layer 510. The spacer layer 520 can be conformally deposited and etched back in a manner similar to the gate dielectric layer 525 such that the spacer layer 520 remains on the sidewalls of the dummy gate structure 505. In some embodiments, the spacer layer 520 includes multiple types of spacer layers. For example, the spacer layer 520 can include a seal spacer layer formed on the sidewalls of the dummy gate structure 505 and a body spacer layer formed on the seal spacer layer. The seal spacer layer and the body spacer layer can be formed of similar materials or different materials. In some embodiments, the body spacer layer is formed without a plasma surface treatment for the seal spacer layer. In some embodiments, the body spacer layer is formed to a greater thickness than the thickness of the seal spacer layer. In some embodiments, the gate dielectric layer 525 is omitted from the dummy gate structure formation process and instead the gate dielectric layer 525 is formed in an alternative gate process.

[0153] Figure 5 Reference cross-sections used in the subsequent figures described in this disclosure are shown. Cross-section A-A is located in the x-z plane (referred to as the y-section) of the fin structure 345 across the source / drain regions of the semiconductor element 200. Cross-section B-B is located in the y-z plane (referred to as the x-section). Cross-section C-C is located in the x-z plane perpendicular to cross-section A-A and across the dummy gate structure 505 in the source / drain regions of the semiconductor element 200. Cross-section C-C is located parallel to cross-section A-A and perpendicular to cross-section B-B and along the dummy gate structure 505. For clarity, the subsequent figures refer to these reference cross-sections. In some figures, some reference numerals of the components or features shown therein may be omitted to avoid obscuring other components or features for the convenience of depicting the figures.

[0154] As described above, provided Figure 5 as an example. Other embodiments may relate toFigure 5 The description is different. Example embodiment 500 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to the operations described in connection with Figure 5 Those described.

[0155] Figure 6 FIG. is a diagram of an example embodiment 600 of the semiconductor device 200 described in this disclosure. Figure 6 Includes cross-sectional views along Figure 5 Cross-sections A-A, B-B, and C-C of. As shown in Figure 6 Cross-sections B-B and C-C in, a dummy gate structure 505 is formed above the gate structure. Fin structure 345. As shown in Figure 6 In cross-section C-C in, a portion of the gate dielectric layer 525 and a portion of the gate electrode layer 510 are formed in a groove above the fin structure 345, which is formed by removing the hard mask layer 320.

[0156] As described above, provide Figure 6 As an example. Other embodiments may be different from those described in connection with Figure 6 The description. Example embodiment 600 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to those described in connection with Figure 6 Those described.

[0157] Figures 7A to 7D FIG. is a diagram of an example embodiment 700 of the source / drain recess formation process and the internal spacer formation process described in this disclosure. Example embodiment 700 includes an example of forming source / drain recesses and internal spacers 245 for the semiconductor device 200. Figures 7A to 7D Is illustrated from multiple perspectives shown in Figure 5 , including Figure 5 The perspective of cross-section A-A in, Figure 5 The perspective of cross-section B-B in, and Figure 5 The perspective of cross-section C-C in. In some embodiments, the operations described in connection with example embodiment 700 are performed after the process described in connection with Figures 3A to 6 Those described.

[0158] As shown in Figure 7AAs shown in cross-sections A-A and B-B in [description], during the etching operation, source / drain trenches 705 are formed in portion 340 of fin structure 345. The source / drain trenches 705 are formed to provide space in which source / drain regions 225 will be formed on opposite sides of dummy gate structure 505. The etching operation can be performed by etching tool 108 and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0159] In some embodiments, source / drain trenches 705 also extend into a portion of the pedestal region 210 of fin structure 345. In these embodiments, source / drain trenches 705 can penetrate into the well portion (e.g., p-type well, n-type well) of fin structure 345. In embodiments where semiconductor substrate 205 includes silicon (Si) material having a (100) orientation, a (111) plane is formed at the bottom of source / drain trenches 705, resulting in a V-shaped or triangular cross-section at the bottom of source / drain trenches 705. In some embodiments, wet etching using tetramethylammonium hydroxide (TMAH) and / or chemical dry etching using hydrochloric acid (HCl) are used to form the V-shaped profile. However, the cross-section at the bottom of source / drain trenches 705 can include other shapes, such as circular or semi-circular, etc.

[0160] As Figure 5 shown in cross-sections B-B and C-C in [description], portions of the first layer 310 and portions of the second layer 315 of stack 305 are etched in the operation to form source / drain trenches 705. The portion of the second layer 315 below the dummy gate structure 505 forms the nanostructure channel 220 of the nanostructure transistor of semiconductor device 200. The nanostructure channel 220 extends between adjacent source / drain trenches 705.

[0161] As Figure 7B shown in cross-section B-B in [description], the first layer 310 is etched laterally (e.g., in a direction generally parallel to the length of the first layer 310) during the etching operation, thereby forming cavities 710 between portions of the nanostructure channel 220. Specifically, etching tool 108 laterally etches the ends of the first layer 310 below the dummy gate structure 505 through the source / drain trenches 705 to form cavities 710 between the ends of the nanostructure channel 220. In embodiments where the first layer 310 is silicon germanium (SiGe) and the second layer 315 is silicon (Si), etching tool 108 can selectively etch the first layer 310 using a wet etchant, such as a mixed solution containing hydrogen peroxide (H 2 O 2 ), acetic acid (CH 3COOH) and / or hydrogen fluoride (HF), and then cleaned with water (H 2 O). The mixed solution and water can be provided into the source / drain recess 705 to etch the first layer 310 from the source / drain recess 705. In some embodiments, the etching by the mixed solution and the cleaning by water are repeated about 10 to about 20 times. In some embodiments, the etching time of the mixed solution is in the range of about 1 minute to about 2 minutes. The mixed solution can be used at a temperature in the range of about 60°C to about 90°C. However, other values of the parameters of the etching operation are also within the scope of this disclosure.

[0162] The cavity 710 can be formed in an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or another shape. In some embodiments, the depth of one or more cavities 710 (e.g., the dimension of the cavity extending from the source / drain recess 705 into the first layer 310) is in the range of about 0.5 nanometers to about 5 nanometers. In some embodiments, the depth of one or more cavities 710 is in the range of about 1 nanometer to about 3 nanometers. However, other values of the depth of the cavity 710 are also within the scope of this disclosure. In some embodiments, the etching tool 108 forms the cavity 710 to a certain length (e.g., the dimension of the cavity extending from the nanostructure channel 220 below the first layer 310 to another nanostructure channel 220 above the first layer 310), such that the cavity 710 partially extends to the side of the nanostructure channel 220 (e.g., such that the width or length of the cavity 710 is greater than the thickness of the first layer 310). In this way, the internal spacer to be formed in the cavity 710 can extend to a part of the end of the nanostructure channel 220.

[0163] As Figure 7C shown in cross-sections A-A and B-B in x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or another dielectric material. The insulating layer 715 can comprise a material different from that of the spacer layer 520.

[0164] Deposition tool 102 forms the insulating layer 715 to a thickness sufficient to fill the cavity 710 between the nanostructure channels 220 with the insulating layer 715. For example, the insulating layer 715 can be formed to a thickness in the range of about 1 nanometer to about 10 nanometers. As another example, the insulating layer 715 can be formed to a thickness in the range of about 2 nanometers to about 5 nanometers. However, other values for the thickness of the insulating layer 715 are also within the scope of this disclosure.

[0165] As Figure 7D shown in cross-sections A-A and B-B in

[0166] , a portion of the insulating layer 715 is removed such that the remaining portion of the insulating layer 715 corresponds to the internal spacer 245 in the cavity 710. Etching tool 108 can perform an etching operation to partially remove the insulating layer 715.

[0167] As described above, Figures 7A to 7D is provided as an example. Other examples may be different from Figures 7A to 7D those described in Figures 7A to 7D . Example embodiment 700 can include additional operations, fewer operations, different operations, and / or a different order of operations compared to those operations described in connection with

[0168] Figure 8 is a diagram of an example embodiment 800 of a source / drain region formation process described in this disclosure. Example embodiment 800 includes an example of forming a source / drain region 225 in the source / drain recesses 705 of the semiconductor element 200.

[0169] Figure 8 From Figure 5 multiple perspectives shown in Figure 5 , including the perspective of cross-section A-A in Figure 5 , the perspective of cross-section B-B in Figure 5 , and the perspective of cross-section C-C in Figures 3A to 7D . In some embodiments, the operations described in connection with example embodiment 800 are performed after the process described in connection with

[0170] As shown Figure 8 in cross-section B-B and cross-section B-B of Figure 8 , one or more layers are used to fill the source / drain recesses 705 to form source / drain regions 225 in the source / drain. For example, the deposition tool 102 may deposit a buffer layer 230 at the bottom of the source / drain recesses 705, the deposition tool 102 may deposit the source / drain regions 225 on the buffer layer 230, and the deposition tool 102 may deposit a contact etch stop layer (CESL) 805 on the source / drain regions 225. In some embodiments, a capping layer 235 (not shown) is deposited on the source / drain regions 225 before forming the etch stop layer 805.

[0171] The buffer layer 230 may include silicon (Si), boron-doped silicon (SiB), or another dopant, and / or another material. The buffer layer 230 may be included to reduce, minimize, and / or prevent dopant migration and / or current leakage from the source / drain regions 225 to the pedestal regions 210, which may otherwise cause short-channel effects in the semiconductor device 200. For example, the buffer layer 230 may improve the performance of the semiconductor device 200 and / or improve the yield of the semiconductor device 200. In some embodiments, the buffer layer 230 is omitted from one or more of the source / drain regions 225.

[0172] The source / drain regions 225 may include one or more layers of epitaxially grown material. For example, the deposition tool 102 may epitaxially grow a first layer of source / drain regions 225 (referred to as L1) above the buffer layer 230, and may epitaxially grow a second layer of source / drain regions 225 (referred to as L2, L2-1, and / or L2-2) on the first layer.

[0173] In some embodiments, a p-type source / drain region is formed for the PMOS nanostructure transistor (e.g., PMOS field effect transistor (PFET)) of the semiconductor device 200, and an n-type source / drain region is formed for the NMOS nanostructure transistor (e.g., NMOS field effect transistor (NFET)) of the semiconductor device 200. The p-type source / drain region may include doped semiconductor material (e.g., silicon (Si), silicon germanium (SiGe)). Examples of p-type dopants include boron (B) (e.g., boron-doped silicon (SiB) and / or boron-doped silicon germanium (SiGeB)). Additionally and / or alternatively, the p-type source / drain region may include silicon germanium (SiGe). The n-type source / drain region may include undoped silicon (Si) and / or silicon doped with an n-type dopant, such as phosphorus (P) (e.g., phosphorus-doped silicon) and / or arsenic (As) (arsenic-doped silicon, SiAs).

[0174] In some embodiments, an etch stop layer 805 is conformally deposited (e.g., using deposition tool 102) on the source / drain regions 225 before forming the interlayer dielectric layer 250. Then, the interlayer dielectric layer 250 is formed on the etch stop layer 805. When forming contacts or vias for the source / drain regions 225, the etch stop layer 805 can provide a mechanism to stop the etching process. The etch stop layer 805 can be formed of a dielectric material having a different etch selectivity from adjacent layers or components. The etch stop layer 805 can comprise or can be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Additionally, the etch stop layer 805 can comprise or can be silicon nitride (SixNy), silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiOCO), or a combination thereof, etc. Deposition techniques such as ALD, CVD, or other deposition techniques can be used to deposit the etch stop layer 805.

[0175] As described above, provide Figure 8 As an example. Other embodiments may be different from Figure 8 those described in. Example embodiment 800 can include additional operations, fewer operations, different operations, and / or an operation sequence different from the operations described in conjunction with Figure 8 description.

[0176] Figure 9 is a schematic diagram of an example embodiment 900 of the ILD formation process described in this disclosure. Figure 9 is illustrated from Figure 5 multiple perspectives shown in, including Figure 5 the perspective of cross-section A-A in, Figure 5 the perspective of cross-section B-B in, and Figure 5 the perspective of cross-section C-C in. In some embodiments, the operations described in conjunction with example embodiment 900 are performed after the operations described in conjunction with Figures 3A to 8 description.

[0177] As Figure 9 shown in cross-section A-A and cross-section B-B in, an interlayer dielectric layer 250 is formed on the source / drain regions 225. In particular, the interlayer dielectric layer 250 can be formed on the etch stop layer 805 above the source / drain regions 225. The interlayer dielectric layer 250 fills the regions between the dummy gate structures 505 and the regions above the source / drain regions 225. The interlayer dielectric layer 250 is formed to reduce and / or prevent damage to the source / drain regions 225 during the replacement gate process. The interlayer dielectric layer 250 can be referred to as an ILD zero (ILD0) layer or another interlayer dielectric layer.

[0178] The deposition tool 102 can be used to use PVD technology, ALD technology, CVD technology, oxidation technology, in combinationFigure 1 Another type of deposition technique described and / or another suitable deposition technique is used to deposit the interlayer dielectric layer 250. The interlayer dielectric layer 250 can be deposited in one or more deposition operations. In some embodiments, the planarization tool 110 can be used to planarize the interlayer dielectric layer 250 after depositing the interlayer dielectric layer.

[0179] As described above, Figure 9 The number and arrangement of the operations and devices shown are provided as one or more examples. In practice, compared with the Figure 9 operations and devices shown, there may be additional operations and elements, fewer operations and devices, different operations and instruments, or different arrangements of operations and devices.

[0180] Figures 10A to 10L is a diagram of an exemplary embodiment 1000 of the replacement gate (RPG) process described in this disclosure. Exemplary embodiment 1000 includes an example of a replacement gate process for replacing the dummy gate structure 505 with a gate structure 240 (e.g., a replacement gate structure) of the semiconductor element 200. Figures 10A to 10L is illustrated from multiple perspectives shown in Figure 5 , including the perspective of cross-section A-A in Figure 5 , the perspective of cross-section B-B in Figure 5 , and the perspective of cross-section C-C in Figure 5 . In some embodiments, the operations described in connection with exemplary embodiment 1000 are performed after the operations described in connection with Figures 3A to 9 .

[0181] As Figure 10A shown in cross-section B-B and cross-section C-C in, a replacement gate operation (e.g., by one or more of the semiconductor processing tools 102-112) is performed to remove the dummy gate structure 505 from the semiconductor element 200. The removal of the dummy gate structure 505 leaves an opening (or recess) 1005 between the interlayer dielectric layers 250 on the source / drain regions 225. The dummy gate structure 505 can be removed in one or more etching operations. Such etching operations can include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0182] Removal of the dummy gate structure 505 exposes a stack of bump regions 210a arranged in the z - direction in the semiconductor device 200 and nanostructured channels 220a located above the bump region 210b. Removal of the dummy gate structure 505 also exposes a stack of bump regions 210b arranged in the z - direction in the semiconductor device 200 and nanostructured channels 220b located above the bump region 210a. The bump region 210a and the nanostructured channel 220a can be exposed to prepare for forming an n - type gate structure of an NMOS nanostructured transistor of the semiconductor device 200 around the nanostructured channel 220a. The bump region 210b and the nanostructured channel 220b can be exposed to prepare for forming an n - type gate structure of a PMOS nanostructured transistor of the semiconductor device 200 around the nanostructured channel 220b.

[0183] As Figure 10B shown in cross - section B - B and cross - section C - C in

[0184] As Figure 10B further shown, the nanostructured channel 220a (e.g., NMOS nanostructured channel) can have an x - direction width indicated as dimension Dl in Figure 10B and the nanostructured channel 220b (e.g., PMOS nanostructured channel) can have an x - direction width indicated as dimension D2 in Figure 10B In some embodiments, dimension D1 and dimension D2 have approximately the same width. In some embodiments, dimension D1 and dimension D2 are different widths. For example, dimension D2 can be greater than dimension D1, or dimension D1 can be greater than dimension D2. In some embodiments, both dimension D1 and dimension D2 are in the range of about 8 nanometers to about 70 nanometers. However, other values of this range are also within the scope of this disclosure.

[0185] As Figures 10C to 10LAs shown in the cross-section C-C, a gate structure 240 (e.g., replacement gate structure) is formed in the opening 1005 between the source / drain regions 225 of the nanostructure transistors of the semiconductor device 200. Specifically, an n-type gate structure 240a is formed in the region between and around the nanostructure channels 220a of the NMOS nanostructure transistors for the semiconductor device 200. The n-type gate structure 240a occupies the region previously occupied by the first layer 310, such that the n-type gate structure 240a surrounds the nanostructure channel 220a and surrounds the nanostructure channel 220a on at least three sides of the nanostructure channel 220a. In some embodiments, the n-type gate structure 240a completely encapsulates the nanostructure channel 220a and surrounds the nanostructure channel 220a on all four sides of the nanostructure channel 220a. A p-type gate structure 240b is formed in the region between and around the nanostructure channels 220b of the PMOS nanostructure transistors for the semiconductor device 200. The p-type gate structure 240b occupies the region previously occupied by the first layer 310, such that the p-type gate structure 240b surrounds the nanostructure channel 220b and surrounds the nanostructure channel 220b on at least three sides of the nanostructure channel 220b. In some embodiments, the p-type gate structure 240b completely encapsulates the nanostructure channel 220b and surrounds the nanostructure channel 220b on all four sides of the nanostructure channel 220b.

[0186] As Figure 10C shown, one or more conformal liners may be deposited onto the exposed portions of the boss regions 210a, the exposed portions of the boss regions 210b, the nanostructure channels 220a, and the nanostructure channels 220b. The one or more conformal liners may include a high-k dielectric liner 1010a, an adhesion liner 1010b, and / or another type of liner. The high-k dielectric liner 1010a may serve as a gate dielectric layer between the n-type gate structure 240a and the nanostructure channel 220a and between the p-type gate structure 240b and the nanostructure channel 220b. The adhesion liner 1010b may facilitate adhesion between the high-k dielectric liner 1010a and one or more metal layers of the n-type gate structure 240a and the p-type gate structure 240b. A deposition tool 102 may be used to deposit the high-k dielectric liner 1010a and the adhesion liner 1010b, each using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combined Figure 1 with another type of deposition technique as described. The high-k dielectric liner 1010a and the adhesion liner 1010b may both be deposited in one or more deposition operations.

[0187] The high-k dielectric liner 1010a may include one or more high-k materials (e.g., having a dielectric constant greater than that of silicon dioxide (SiO 2a dielectric material having a dielectric constant of about 3.9). For example, lanthanum oxide (La x O y , for example, among other embodiments, hafnium oxide (HfO x , for example, HfO 2 ), zirconium oxide (ZrO x , for example, ZrO 2 ), and / or aluminum oxide (Al x O y , for example, Al 2 O 3 ). Additionally and / or alternatively, silicon dioxide (SiO 2 ) and / or another dielectric material can be used to replace the high-k dielectric liner. In some embodiments, the high-k dielectric liner 1010a can have a thickness in the range of about 0.5 nanometers to about 3 nanometers. However, other values within this range are within the scope of the present disclosure. The adhesion liner 1010b can comprise tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable adhesion liner materials.

[0188] Such as Figure 10CFurther shown, a p-type metal layer 1015 is formed on the high-k dielectric liner 1010a and / or on the adhesion liner 1010b. The p-type metal layer 1015 is formed on the exposed portions of the bosses 210a and 210b and on the nanostructure channels 220a and 220b such that the p-type metal layer 1015 surrounds the nanostructure channels 220a and 220b. In some embodiments, the p-type metal layer 1015 surrounding the nanostructure channels 220a and 220b merges between the nanostructure channels 220a and 220b. In some embodiments, the p-type metal layer 1015 surrounding the nanostructure channels 220a and 220b does not merge between the nanostructure channels 220a and 220b. The p-type gate structure 240b includes a metal gate structure. Different from a polysilicon gate structure whose work function can be adjusted by doping a polysilicon material with a p-type dopant and / or an n-type dopant, the work function adjustment of the metal gate structure can be performed by including one or more work function adjusting metals in the metal gate structure. The p-type metal layer 1015 can be incorporated into the p-type gate structure 240b to adjust the work function of the p-type gate structure 240b. The p-type metal layer 1015 can include one or more p-type metals such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or another metal with processability. Among other examples, the function is greater than about 4.7 eV. The p-type metal layer 1015 can be included to adjust the work function of the PMOS nanostructure transistor such that the work function is adjusted to be close to the valence band of the material of the nanostructure channel 220b. This enables the PMOS nanostructure transistor to achieve a relatively low threshold voltage while enabling the PMOS nanostructure transistor to achieve a relatively low leakage current.

[0189] The deposition tool 102 can be used to deposit the p-type metal layer 1015 using PVD technology, ALD technology, CVD technology, oxidation technology, combined Figure 1 with another type of deposition technology described, and / or another suitable deposition technology. The p-type metal layer 1015 can be deposited in one or more deposition operations. In some embodiments, the p-type metal layer 1015 is formed to have a thickness in the range of about 0.5 nanometers to about 20 nanometers. However, other values within this range are also within the scope of the present disclosure.

[0190] As described above, the p-type metal layer 1015 is formed around the nanostructure channels 220a and 220b. This is because the p-type metal layer 1015 is formed without using a mask layer around the nanostructure channel 220a. If the p-type metal layer 1015 remains around the nanostructure channel 220a, the p-type metal layer 1015 may otherwise cause the work function of the n-type gate structure 240a to be too far from the conduction band of the material of the nanostructure channel 220a. Thus, as shown. Refer to Figures 10D to 10FAfter forming the p-type metal layer 1015, the p-type metal layer 1015 is removed from the nanostructured channel 220a.

[0191] As Figure 10D shown, a photoresist layer 1020 can be formed over the semiconductor element 200. The photoresist layer 1020 can be formed over the p-type metal layer 1015 on the bump regions 210a, 210b, the nanostructured channel 220a, and the nanostructured channel 220b. A deposition tool 102 can be used to deposit the photoresist layer 1020 using a spin coating technique and / or another deposition technique.

[0192] As Figure 10E shown, a pattern is formed in the photoresist layer 1020. The n-type gate structure 240a is exposed through the pattern in the photoresist layer 1020. This enables the photoresist layer 1020 to be used to remove the p-type metal layer 1015 from the bump region 210a and the nanostructured channel 220a, without removing the p-type metal layer 1015 from the bump region 210b and the nanostructured channel 220b. An exposure tool 104 can be used to expose the photoresist layer 1020 to a radiation source to pattern the photoresist layer 1020. A development tool 106 can be used to develop and remove portions of the photoresist layer 1020 over the bump region 210a and the nanostructured channel 220a.

[0193] As Figure 10F shown, portions of the p-type metal layer 1015 exposed through the pattern in the photoresist layer 1020 are removed from the bump region 210a and the nanostructured channel 220a. The photoresist layer 1020 over the p-type gate structure 240b protects portions of the p-type metal layer 1015 from being removed from the bump region 210b and the nanostructured channel 220b. An etch tool 108 can be used to etch the p-type metal layer 1015 based on the pattern in the photoresist layer 1020 to remove portions of the p-type metal layer 1015 from the bump region 210a and the nanostructured channel 220a. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a hard mask layer is used as an alternative technique to remove portions of the p-type metal layer 1015 from the bump region 210a and the nanostructured channel 220a based on the pattern.

[0194] As Figure 10G shown, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer 1020. A chemical stripper, plasma ashing, and / or another technique can be used to remove the remaining portion of the photoresist layer 1020. Removal of the remaining portion of the photoresist layer 1020 exposes the p-type metal layer 1015 on the bump region 210b and the nanostructured channel 220b.

[0195] As Figure 10HAs shown, an oxidation operation 1025 is performed on the semiconductor element 200. The oxidation operation 1025 is performed to oxidize the surface of the p-type metal layer 1015, which results in the formation of a metal oxide layer 1030 on the surface of the p-type metal layer 1015. Since the metal oxide layer 1030 is formed by oxidizing the surface of the p-type metal layer 1015, the metal oxide layer 1030 contains a material (e.g., a metal oxide material) that contains the oxide of the p-type metal of the p-type metal layer 1015. For example, if the p-type metal layer 1015 contains titanium nitride (TiN), the metal oxide layer 1030 may contain titanium oxide (TiO x ). As another example, if the p-type metal layer 1015 contains tungsten (W), the metal oxide layer 1030 may contain tungsten oxide (WO x ). Another example, if the p-type metal layer 1015 contains cobalt (Co), the metal oxide layer 1030 may contain cobalt oxide (CoO x ). In some embodiments, the metal oxide layer 1030 is formed between the nanostructured channels 220b.

[0196] Performing the oxidation operation 1025 enables the formation of the metal oxide layer 1030 on the p-type gate structure 240b without forming the metal oxide layer 1030 on the nanostructured channel 220a. In this way, by selectively forming the metal oxide layer, additional semiconductor processing steps can be omitted, such as masking the nanostructured channel 220a with a mask layer and / or performing a subsequent etch to remove the metal oxide layer 1030 from the nanostructured channel 220a. By performing the oxidation operation 1025, the metal oxide layer 1030 is formed on the p-type gate structure 240b. This reduces the cost, time, and manufacturing complexity of forming the semiconductor element 200 and reduces the likelihood of damaging the high-k dielectric liner 1010a and / or the adhesion liner 1010b.

[0197] Various oxidation techniques can be used to perform the oxidation operation 1025. In some embodiments, a deposition tool 102 and / or another type of semiconductor processing tool is used, and ozone (O dissolved in deionized water is used 3) The solution is used to perform an oxidation treatment operation on the surface of the p-type metal layer 1015. The p-type metal layer 1015 can be immersed in the solution for a period of time so that the oxygen in the solution oxidizes the surface of the p-type metal layer 1015. The ozone concentration in the solution can be in the range of about 0.1 ppm to about 107 ppm. However, values in other ranges are also within the scope of this disclosure. The ozone concentration and / or duration can be selected to achieve a specific amount of oxidation on the surface of the p-type metal layer 1015. For example, the greater the ozone concentration and / or the longer the duration in the solution, the greater the amount of oxidation on the surface of the p-type metal layer 1015, and the smaller the ozone concentration and / or the shorter the duration in the solution, the smaller the amount of oxidation on the surface of the p-type metal layer 1015.

[0198] In some embodiments, an oxidation operation 1025 is performed using an oxygen-containing gas. For example, the p-type metal layer 1015 can be exposed to a gas containing ozone (O 3 ), nitrous oxide (N 2 O), and / or another type of oxygen-containing gas for a period of time to oxidize the surface of the p-type metal layer 1015.

[0199] In some embodiments, a plasma treatment operation is performed for the oxidation operation 1025. The deposition tool 102 (e.g., a plasma-based deposition tool) and the etching tool 108 (e.g., a plasma-based etching tool), and / or another type of plasma-based semiconductor processing tool can be used to perform an oxygen (O 2 ) plasma and / or an oxygen-containing plasma treatment operation. The oxygen ions in the oxygen plasma bombard the surface of the p-type metal layer 1015, causing the surface of the p-type metal layer 1015 to be oxidized.

[0200] In some embodiments, thermal oxidation techniques are used to perform the oxidation operation 1025. The thermal oxidation techniques can include a baking operation, in which the p-type metal layer 1015 is exposed to a high temperature for a period of time to promote oxidation. The surface of the p-type metal layer 1015. During the baking operation, the p-type metal layer 1015 can be exposed to an atmosphere containing oxygen, such that the oxygen in the atmosphere combines with the elevated temperature, resulting in the oxidation of the surface of the p-type metal layer 1015.

[0201] The p-type metal layer 1015 may be exposed to heat during the baking operation. The temperature of the baking operation may be in the range of about 230 degrees Celsius to about 300 degrees Celsius. If the temperature of the baking operation is lower than about 230 degrees Celsius, the metal oxide layer 1030 may be insufficient to inhibit the growth of the n-type metal layer on the p-type gate structure 240b, because the metal oxide layer 1030 may not form to a sufficient thickness. This may cause the n-type metal layer on the p-type gate structure 240b to cause the work function of the p-type gate structure 240b to be too far from the valence band of the material of the nanostructure channel 220b, which may cause the p-type threshold voltage (PV t ) of the PMOS nanostructure transistor to be too high. If the temperature of the baking operation is greater than about 300 degrees Celsius, this may cause temperature instability of the NMOS nanostructure transistor and / or the PMOS nanostructure transistor (e.g., may cause an increase in negative bias temperature instability (NTBI)). This may cause an increase in the threshold voltage of the NMOS nanostructure transistor and / or the PMOS nanostructure transistor. If the temperature of the baking operation is in the range of about 230 degrees Celsius to about 300 degrees Celsius, the threshold voltage of the NMOS nanostructure transistor and / or the PMOS nanostructure transistor may enable low leakage current. The NMOS nanostructure transistor and / or the PMOS nanostructure transistor structure, while enabling the NMOS nanostructure transistor and / or the PMOS nanostructure transistor to achieve high operating efficiency. However, other values of the temperature of the baking operation and ranges other than about 230 degrees Celsius to about 300 degrees Celsius are also within the scope of this disclosure.

[0202] In some embodiments, the above-described various oxidation techniques and / or another oxidation technique are used in the oxidation operation 1025 to oxidize the surface of the p-type metal layer 1015. For example, a plasma treatment technique may be employed in the thermal oxidation technique oxidation operation 1025 to oxidize the surface of the p-type metal layer 1015.

[0203] In some embodiments, the duration of the oxidation operation 1025 may be in the range of about 60 seconds to about 180 seconds. If the duration is less than about 60 seconds, the metal oxide layer 1030 may not be sufficient to inhibit the growth of the n-type metal layer on the p-type gate structure 240b, because the metal oxide layer 1030 may not form to a sufficient thickness. This may cause the n-type metal layer on the p-type gate structure 240b to cause the work function of the p-type gate structure 240b to be too far from the valence band of the material of the nanostructure channel 220b, which may cause the p-type threshold voltage (PV t ) of the PMOS nanostructure transistor to be too high. If the duration is greater than about 180 seconds, oxidation silicon (SiO x) Regrowth, which may lead to a degradation in the performance of other components in the semiconductor element 200. Performing the oxidation operation 1025 for a duration in the range of about 60 seconds to about 180 seconds can minimize the regrowth of silicon oxide (SiO x ), while enabling the metal oxide layer 1030 to form to a sufficient thickness to inhibit the growth of the n-type metal layer on the p-type gate structure 240b. However, other values of the duration and ranges other than about 60 seconds to about 180 seconds are also within the scope of this disclosure.

[0204] As Figure 10I shown, after performing the oxidation operation 1025 to form the metal oxide layer 1030 on the p-type gate structure 240b, an n-type metal layer 1035 is formed on the n-type gate structure 240a. The n-type metal layer 1035 is formed such that the n-type metal layer 1035 surrounds each nanostructure channel 220a. The n-type metal layer 1035 is also formed on the exposed portion of the boss region 210a below the nanostructure channel 220a. The deposition tool 102 and / or the electroplating tool 112 can be used to deposit the n-type metal layer 1035 and / or another suitable deposition technique using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, another deposition technique described in conjunction with Figure 1 above. The n-type metal layer 1035 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the n-type metal layer 1035 is deposited on the seed layer.

[0205] The n-type metal layer 1035 comprises one or more metal materials that adjust or modulate the work function of the n-type gate structure 240a near the conduction band of the material of the nanostructure channel 220a. In some embodiments, the n-type metal layer 1035 comprises titanium aluminum (TiAl). In some embodiments, the n-type metal layer 1035 comprises titanium aluminum carbon (TiAlC). In some embodiments, the n-type metal layer 1035 comprises another aluminum-containing metal. In some embodiments, another n-type metal material is included in the n-type metal layer 1035.

[0206] An n-type metal layer 1035 is also formed on the p-type gate structure 240b because no mask layer covers the p-type gate structure 240b during the formation of the n-type metal layer 1035. However, the growth of the n-type metal layer 1035 on the p-type gate structure 240b is inhibited by the metal oxide layer 1030 formed during the oxidation operation 1025. Therefore, the thickness of the n-type metal layer 1035 on the p-type gate structure 240b is less than the thickness of the n-type metal layer 1035 on the n-type gate structure 240a. In some embodiments, the metal oxide layer 1030 can inhibit the growth of the n-type metal layer 1035 because the bonding energy for bonding the atoms of the n-type metal layer 1035 to the metal oxide layer 1030 can be higher than the bonding energy of the n-type metal layer 1035. The energy for bonding the atoms of the n-type metal layer 1035 to the p-type metal layer 1015. The smaller thickness of the n-type metal layer 1035 on the p-type gate structure 240b results in a smaller effect of the n-type metal layer 1035 on the work function of the p-type gate structure 240b compared to the effect of the n-type metal layer 1035 on the work function of the n-type gate structure 240a. Specifically, the smaller thickness of the n-type metal layer 1035 on the p-type gate structure 240b causes the work function of the p-type gate structure 240b to be closer to the valence band of the material of the nanostructure channel 220b than the work function of the n-type gate structure 240a. If no metal oxide layer 1030 is formed on the p-type gate structure 240b. Therefore, the metal oxide layer 1030 enables the work function of the p-type gate structure 240b to be adjusted to achieve the p-type threshold voltage (PV t ) of the PMOS nanostructure transistor, which enables the PMOS nanostructure transistor to operate efficiently and with low leakage current.

[0207] As Figure 10J shown, a capping layer 1040 can be formed on the n-type gate structure 240a and / or the p-type gate structure 240b. In some embodiments, the capping layer 1040 is omitted from the n-type gate structure 240a and / or the p-type gate structure 240b. The capping layer 1040 can comprise titanium nitride (TiN) and / or another suitable capping material. The capping layer 1040 can be formed on the n-type metal layer 1035 on the n-type gate structure 240a, and / or can be formed on the n-type metal layer 1035 on the p-type gate structure 240b. A deposition tool 102 and / or an electroplating tool 112 can be used to deposit the capping layer 1040 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, another deposition technique described above in conjunction with Figure 1 and / or another suitable deposition technique. The capping layer 1040 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited and the capping layer 1040 is deposited on the seed layer.

[0208] AsFigure 10K As shown, the semiconductor element 200 may include one dimension or multiple dimensions. Embodiment dimension D3 includes the thickness of the n-type metal layer 1035 of the n-type gate structure 240a. Specifically, dimension D3 corresponds to the thickness of the n-type metal layer 1035 on the top surface of the n-type gate structure 240a. In some embodiments, dimension D3 is in the range of about 0.5 nanometers to about 20 nanometers. If dimension D3 is less than about 0.5 nanometers, the work function of the n-type gate structure 240a may be too far from the conduction band of the material of the nanostructure channel 220a, which may result in too high a work function of the n-type gate structure 240a. Type threshold voltage (NVt). If dimension D3 is greater than about 20 nanometers, the work function of the n-type gate structure 240a may be too close to the conduction band of the material of the nanostructure channel 220a, which may result in too low a work function of the n-type gate structure 240a. Threshold voltage (NV t ). If dimension D3 is in the range of about 0.5 nanometers to about 20 nanometers, the work function of the n-type gate structure 240a can enable the NMOS nanostructure transistor to achieve low leakage current while enabling high operating efficiency. Realization of the NMOS nanostructure transistor. However, other values of dimension D3 and ranges other than about 0.5 nanometers to about 20 nanometers are also within the scope of this disclosure.

[0209] Another embodiment dimension D4 includes the thickness of the n-type metal layer 1035 on the p-type gate structure 240b. Specifically, dimension D4 corresponds to the thickness of the n-type metal layer 1035 on the top surface of the p-type gate structure 240b. In some embodiments, dimension D4 is in the range of about 0.1 nanometers to about 16 nanometers. If dimension D4 is greater than about 16 nanometers, the work function of the p-type gate structure 240b may be too far from the valence band of the material of the nanostructure channel 220b, which may result in too high a p-type threshold voltage (PV t ). Type. If dimension D4 is about 16 nanometers or less, the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling the PMOS nanostructure transistor to achieve high operating efficiency. However, other values of dimension D4 and ranges other than about 0.1 nanometers to about 16 nanometers are also within the scope of this disclosure.

[0210] In some embodiments, the ratio of dimension D3 to dimension D4 (e.g., D3:D4) is greater than about 1.2:1. If the ratio is less than about 1.2:1, the work function of the p-type gate structure 240b may be too far from the valence band of the material of the nanostructure channel 220b, which may result in too high a work function of the p-type gate structure 240b. Type threshold voltage (PV t) and the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling the PMOS nanostructure transistor to achieve high operating efficiency if the ratio is greater than about 1.2:1. However, other values of the difference between dimension D3 and dimension D4 are also within the scope of this disclosure.

[0211] Another example dimension D5 includes the thickness of the n-type metal layer 1035 of the n-type gate structure 240a. Specifically, dimension D5 corresponds to the thickness of the n-type metal layer 1035 on the sidewalls of the n-type gate structure 240a. In some embodiments, dimension D5 is in the range of about 0.5 nanometers to about 20 nanometers. If dimension D5 is less than about 0.5 nanometers, the work function of the n-type gate structure 240a may be too far from the conduction band of the material of the nanostructure channel 220a, which may result in a too high n-type threshold voltage (NV t ). If dimension D5 is greater than about 20 nanometers, the work function of the n-type gate structure 240a may be too close to the conduction band of the material of the nanostructure channel 220a, which may result in a too low n-type threshold voltage (NV t ). If dimension D5 is in the range of about 0.5 nanometers to about 20 nanometers, the work function of the n-type gate structure 240a can enable the NMOS nanostructure transistor to achieve low leakage current while enabling high operating efficiency. The implementation of the NMOS nanostructure transistor. However, other values of dimension D5 and ranges other than about 0.5 nanometers to about 20 nanometers are also within the scope of this disclosure. In some embodiments, the n-type metal layer 1035 is conformally deposited such that dimension D3 is substantially equal to dimension D5.

[0212] Another example dimension D6 includes the thickness of the n-type metal layer 1035 on the p-type gate structure 240b. Specifically, dimension D6 corresponds to the thickness of the n-type metal layer 1035 on the top surface of the p-type gate structure 240b. In some embodiments, dimension D6 is in the range of about 0.1 nanometers to about 16 nanometers. If dimension D6 is greater than about 16 nanometers, the work function of the p-type gate structure 240b may be too far from the valence band of the material of the nanostructure channel 220b, which may result in a too high p-type threshold voltage (PV t ). If dimension D6 is about 16 nanometers or less, the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling the PMOS nanostructure transistor to achieve high operating efficiency. However, other values of dimension D6 and ranges other than about 0.1 nanometers to about 16 nanometers are also within the scope of this disclosure. In some embodiments, the n-type metal layer 1035 is conformally deposited such that dimension D6 is substantially equal to dimension D4.

[0213] In some embodiments, the ratio of dimension D5 to dimension D6 (e.g., D5:D6) is greater than about 1.2:1. If the ratio is less than about 1.2:1, the work function of the p-type gate structure 240b may be too far from the valence band of the material of the nanostructure channel 220b, which may result in a p-type threshold voltage (PV t ) being too high. The work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling the PMOS nanostructure transistor to achieve high operating efficiency if the ratio is greater than about 1.2:1. However, other values of the difference between dimension D5 and dimension D6 are also within the scope of this disclosure.

[0214] In some embodiments, the ratio of dimension D3 to dimension D5 (e.g., D3:D5) is in the range of about 0.1:1 to about 0.5:1. However, other values of the difference between dimension D3 and dimension D5 are also within the scope of this disclosure. In some embodiments, the ratio of dimension D4 to dimension D6 (e.g., D4:D6) is in the range of about 0.1:1 to about 0.8:1. However, other values of the difference between dimension D4 and dimension D6 are also within the scope of this disclosure.

[0215] Another example dimension D7 includes the thickness of the metal oxide layer 1030 on the p-type metal layer 1015 of the p-type gate structure 240b. Specifically, dimension D7 corresponds to the thickness of the metal oxide layer 1030 on the top surface of the p-type gate structure 240b. In some embodiments, dimension D7 is in the range of about 0.9 nanometers to about 1.4 nanometers. If dimension D7 is less than about 0.9 nanometers, the metal oxide layer 1030 may be insufficient to inhibit the growth of the n-type metal layer 1035 on the p-type gate structure 240b. This may cause the n-type metal layer 1035 on the p-type gate structure 240b to make the work function of the p-type gate structure 240b too far from the valence band of the material of the nanostructure channel 220b, which may result in a p-type threshold voltage (PV t ) being too high. If dimension D7 is greater than about 1.4 nanometers, the gate resistance of the p-type gate structure 240b will increase, resulting in a higher p-type threshold voltage (PV t ) of the PMOS nanostructure transistor. If dimension D7 is in the range of about 0.9 nanometers to about 1.4 nanometers, the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling the realization of high operating efficiency. Realization of the PMOS nanostructure transistor. However, other values of dimension D7 and ranges other than about 0.9 nanometers to about 1.4 nanometers are also within the scope of this disclosure.

[0216] Another example dimension D8 includes the thickness of the metal oxide layer 1030 on the p-type metal layer 1015 of the p-type gate structure 240b. Specifically, dimension D7 corresponds to the thickness of the metal oxide layer 1030 on the sidewalls of the p-type gate structure 240b. In some embodiments, dimension D8 is in the range of about 0.7 nanometers to about 1.3 nanometers. If dimension D8 is less than about 0.7 nanometers, the metal oxide layer 1030 may be insufficient to inhibit the growth of the n-type metal layer 1035 on the p-type gate structure 240b. This may cause the n-type metal layer 1035 on the p-type gate structure 240b to cause the work function of the p-type gate structure 240b to be too far from the valence band of the material of the nanostructure channel 220b, which may result in too high a p-type threshold voltage (PV t ) of the PMOS nanostructure transistor. If dimension D8 is greater than about 1.3 nanometers, the gate resistance of the p-type gate structure 240b will increase, resulting in a relatively high p-type threshold voltage (PV t ) of the PMOS nanostructure transistor. If dimension D8 is in the range of approximately 0.7 nanometers to approximately 1.3 nanometers, the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling high operating efficiency. Realization of the PMOS nanostructure transistor. However, other values of dimension D8 and ranges other than about 0.7 nanometers to about 1.3 nanometers are also within the scope of this disclosure.

[0217] Another example dimension D9 includes the thickness of the p-type metal layer 1015 of the p-type gate structure 240b. Specifically, dimension D9 corresponds to the thickness of the p-type metal layer 1015 on the top surface of the p-type gate structure 240b. In some embodiments, dimension D9 is in the range of about 0.5 nanometers to about 20 nanometers. If dimension D9 is less than about 0.5 nanometers, the work function of the p-type gate structure 240b may be too far from the valence band of the material of the nanostructure channel 220b, which may result in too high a p-type threshold voltage (PVt). If dimension D9 is greater than about 20 nanometers, the work function of the p-type gate structure 240b may be too close to the valence band of the material of the nanostructure channel 220b, which may result in too low a p-type threshold voltage (PV t ). If dimension D9 is in the range of approximately 0.5 nanometers to approximately 20 nanometers, the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling high operating efficiency. Realization of the PMOS nanostructure transistor. However, other values of dimension D9 and ranges other than about 0.5 nanometers to about 20 nanometers are also within the scope of this disclosure. In some embodiments, the p-type metal layer 1015 is deposited conformally such that dimension D9 is substantially equal to dimension D10.

[0218] Another example dimension D10 includes the thickness of the p-type metal layer 1015 of the p-type gate structure 240b. Specifically, dimension D10 corresponds to the thickness of the p-type metal layer 1015 on the sidewalls of the p-type gate structure 240b. In some embodiments, dimension D10 is in the range of from about 0.5 nanometers to about 20 nanometers. If dimension D10 is less than about 0.5 nanometers, the work function of the p-type gate structure 240b may be too far from the valence band of the material of the nanostructure channel 220b, which may result in a p-type threshold voltage (PV t ) being too high. If dimension D10 is greater than about 20 nanometers, the work function of the p-type gate structure 240b may be too close to the valence band of the material of the nanostructure channel 220b, which may result in a p-type threshold voltage (PV t ) being too low. If dimension D10 is in the range of from about 0.5 nanometers to about 20 nanometers, the work function of the p-type gate structure 240b can enable the PMOS nanostructure transistor to achieve low leakage current while enabling high operating efficiency. Realization of the PMOS nanostructure transistor. However, other values of dimension D10 and ranges other than from about 0.5 nanometers to about 20 nanometers are also within the scope of this disclosure.

[0219] As Figure 10L shown, the gate layers 1045 of the n-type gate structure 240a and the p-type gate structure 240b are formed over the n-type metal layer 1035 and over the p-type metal layer 1015. The gate layer 1045 includes one or more metal materials such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), etc. The deposition tool 102 and / or the electroplating tool 112 can be used to deposit the gate layer 1045 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, another deposition technique described above in connection with Figure 1 and / or another suitable deposition technique. The gate layer 1045 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited and the gate layer 1045 is deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the gate layer 1045 after depositing the gate layer 1045.

[0220] In this manner, the semiconductor device 200 can include a plurality of nanostructured channels 220a arranged in a z-direction substantially perpendicular to the semiconductor substrate 205 of the semiconductor device 200, and a plurality of nanostructured channels 220b arranged in the z-direction. The z-direction is approximately perpendicular to the semiconductor substrate 205 of the semiconductor device 200. The nanostructured channels 220a and 220b can be adjacent to each other in the semiconductor device 200. The semiconductor device 200 can include a surrounding n-type gate structure 240a. A p-type gate structure 240b surrounds the nanostructured channel 220a and surrounds the nanostructured channel 220b. The p-type gate structure 240b can include a p-type metal layer 1015 and a metal oxide layer 1030 on the p-type metal layer 1015. The metal oxide layer 1030 includes a material containing an oxide of a p-type metal, the p-type metal layer 1015. The n-type gate structure 240a can include an n-type metal layer 1035, where the n-type metal layer 1035 is also above the metal oxide layer 1030 of the p-type gate structure 240b.

[0221] As described above, Figures 10A to 10L the number and arrangement of operations and elements shown in are provided as one or more embodiments. In fact, compared with Figures 10A to 10L the operations and elements shown in, there may be more operations and elements, fewer operations and elements, different operations and elements, or different arrangements.

[0222] Figure 11 is a diagram of Embodiment 1100 of the n-type metal thickness 1105 of various types of p-metal oxidation techniques described in this disclosure. The n-type metal thickness 1105 corresponds to the thickness of the n-type metal layer on various p-type gate structures. The reference numeral 1110 corresponds to the n-metal thickness 1105 of the n-type metal layer on a p-type gate structure on which the metal oxide layer 1030 is not formed. Referring to the n-metal thickness 1105 of the n-type metal layer on the p-type gate structure, for this p-type gate structure, in Figure 10H the oxidation operation 1025 described, the metal oxide layer 1030 is formed using a thermal oxidation technique (such as a baking operation). The reference numeral 1120 corresponds to the n-type metal thickness 1105 of the n-type metal layer on the p-type gate structure, for this p-type gate structure, in Figure 10H the oxidation operation 1025 described, the metal oxide layer 1030 is formed using a thermal oxidation technique (such as a baking operation). The duration of the baking operation associated with the reference numeral 1120 is greater than the duration of the baking operation associated with the reference numeral 1115. The reference numeral 1125 corresponds to the n-type metal thickness 1105 of the n-type metal layer on the p-type gate structure, for this p-type gate structure, in Figure 10H the oxidation operation 1025 described, a plasma treatment technique (such as using oxygen (O 2)Plasma treatment with plasma and / or oxygen-containing plasma) forms the metal oxide layer 1030.

[0223] As Figure 11 shown, the oxidation operation 1025 results in an n-metal thickness 1105 (corresponding to reference numerals 1115, 1120, and 1125) that is less than the n-metal thickness 1105 without the oxidation operation 1025 (corresponding to reference numeral 1110). Although the plasma treatment technique (corresponding to reference numeral 1125) can result in the lowest n-metal thickness 1105 of the n-type metal layer on the p-type gate structure, the baking operation technique (corresponding to reference numerals 1115 and 1120) can also provide sufficient oxidation of the p-type metal layer on the p-type gate structure to inhibit the growth of the n-type metal layer on the p-type gate structure.

[0224] As described above, provided Figure 11 as an example. Other examples may be different from those Figure 11 described.

[0225] Figure 12 is a diagram of Example 1200 of the flat-band voltage (Vf b ) 1205 of the p-type gate structure for various types of p-metal oxidation techniques described in this disclosure. As Figure 12 shown, the flat-band voltage 1205 of the p-type gate structure without the formation of the metal oxide layer 1030 (corresponding to reference numeral 1210) and the p-type gate structure with the formation of the metal oxide layer 1030 (corresponding to reference numerals 1215 and 1220) are shown. By using the thermal oxidation technique in combination with Figure 10H the oxidation operation 1025 described. Reference numeral 1215 corresponds to the flat-band voltage 1205 of the p-type gate structure, where the p-type metal layer is deposited at a temperature higher than the temperature at which the p-type metal layer of the p-type gate structure related to reference numeral 1220 is deposited.

[0226] As Figure 12 shown, the metal oxide layer 1030 enables the flat-band voltage 1205 of the p-type gate structure to be closer to zero (0) than the flat-band voltage 1205 of the p-type gate structure. The flat-band voltage 1205 corresponds to the voltage that can be applied to the p-type gate structure to achieve the flat-band state of the semiconductor channel between the p-type gate structure and the metal oxide layer 1030. The flat-band state refers to the energy state where the energy bands (such as the conduction band and valence band) are flat at the interface between the semiconductor channel and the gate dielectric between the semiconductor channel and the p-type gate structure. The flat-band state can enable a surface electric field with an approximately zero magnitude to be achieved in the semiconductor channel. Therefore, the oxidation operation 1025 for forming the metal oxide layer 1030 can enable the flat-band state between the p-type gate structure and the semiconductor channel to be achieved using a smaller flat-band voltage 1205.

[0227] As described above, provided Figure 12 as an example. Other examples may differ with respect to Figure 12 those described.

[0228] Figure 13 is a diagram of example components of device 1300 described in this disclosure. In some implementations, one or more of semiconductor processing tools 102 - 112 and / or wafer / die transfer tools 114 may include one or more of devices 1300 and / or one or more components of device 1300. As Figure 13 shown, device 1300 may include a bus 1310, a processor 1320, a memory 1330, an input element 1340, an output element 1350, and / or a communication element 1360.

[0229] Bus 1310 may include one or more components that enable wired and / or wireless communication between components of device 1300. Bus 1310 may couple Figure 13 two or more components together, such as via operative coupling, communication coupling, electrical coupling, and / or electro - coupling. For example, bus 1310 may include electrical connections (e.g., wires, traces, and / or leads) and / or a wireless bus. Processor 1320 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field - programmable gate array, an application - specific integrated circuit, and / or another type of processing component. Processor 1320 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 1320 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere in this disclosure.

[0230] Memory 1330 may include volatile and / or non-volatile memory. For example, memory 1330 may include random access memory (RAM), read-only memory (ROM), hard disk, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical fiber memory). Memory 1330 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1330 may be a non-transitory computer-readable medium. Memory 1330 may store information related to the operation of device 1300, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1330 may include one or more memories coupled, e.g., via bus 1310 (e.g., communicatively coupled) to one or more processors (e.g., processor 1320). The communicative coupling between processor 1320 and memory 1330 may enable processor 1320 to read and / or process information stored in processor 1320. Memory 1330 and / or store information in memory 1330.

[0231] Input component 1340 may enable device 1300 to receive input, such as user input and / or sensed input. For example, input component 1340 may include a touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, global positioning system sensor, global navigation satellite system sensor, accelerometer, gyroscope, and / or actuator. Output component 1350 may enable device 1300 to provide output, such as via a display, speaker, and / or light-emitting diode. Communication component 1360 may enable device 1300 to communicate with other devices via a wired connection and / or a wireless connection. For example, communication component 1360 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0232] Device 1300 may perform one or more operations or processes described in this disclosure. For example, a non-transitory computer-readable medium (e.g., memory 1330) may store a set of instructions (e.g., one or more instructions or program codes) for execution by processor 1320. Processor 1320 may execute this group of instructions to perform one or more operations or processes described in this disclosure. In some embodiments, execution of the group of instructions by one or more processors 1320 causes one or more processors 1320 and / or device 1300 to perform one or more operations or processes described in this disclosure. In some embodiments, hardwired circuitry may be used in place of or in combination with the instructions to perform one or more operations or processes described in this disclosure. Additionally or alternatively, processor 1320 may be configured to perform one or more operations or processes described in this disclosure. Thus, the implementations described in this disclosure are not limited to any specific combination of hardware circuitry and software.

[0233] Figure 13 The number and arrangement of the components shown are provided as examples. Device 1300 may include additional components, fewer components, different components, or components in a different arrangement than Figure 13 shown. Additionally or alternatively, a group of components (e.g., one or more components) of device 1300 may perform one or more functions described as being performed by another group of components of device 1300.

[0234] Figure 14 is a flowchart of an example process 1400 related to forming a semiconductor element described in this disclosure. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 - 112) are used to perform Figure 14 one or more processing blocks. Additionally or alternatively, Figure 14 one or more processing blocks may be performed using one or more components of device 1300, such as processor 1320, memory 1330, input element 1340, output element 1350, and / or communication element 1360.

[0235] As Figure 14 shown, process 1400 may include forming a first plurality of nanostructure channel layers (block 1410) arranged along a direction substantially perpendicular to the semiconductor substrate of the semiconductor element. For example, one or more of semiconductor processing tools 102 - 112 may be used to form the first plurality of nanostructure channel layers (e.g., nanostructure channels 220b), which are arranged substantially perpendicular to the semiconductor substrate (e.g., semiconductor substrate 205) of the semiconductor element (e.g., semiconductor element 200), as described in this disclosure.

[0236] As Figure 14Further shown, process 1400 may include forming a second plurality of nanostructured channel layers (block 1420) arranged along a direction approximately perpendicular to the semiconductor substrate. For example, one or more of semiconductor processing tools 102 - 112 may be used to form the second plurality of nanostructured channel layers (e.g., nanostructured channels 220a) which are arranged approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 205), as described in this disclosure.

[0237] As Figure 14 Further shown, process 1400 may include forming a p-type metal layer of a first gate structure such that the p-type metal layer coats each of the first plurality of nanostructured channel layers (block 1430). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the p-type metal layer (e.g., p-type metal layer 1015) of the first gate structure (e.g., p-type gate structure 240b) such that the p-type metal layer surrounds each of the first plurality of nanostructured channel layers, as described in this disclosure.

[0238] As Figure 14 Further shown, process 1400 may include forming a metal oxide layer on the p-type metal layer (block 1440). For example, one or more of semiconductor processing tools 102 - 112 may be used to form a metal oxide layer (e.g., metal oxide layer 1030) on the p-type metal layer, as described in this disclosure.

[0239] As Figure 14 Further shown, process 1400 may include forming an n-type metal layer of a second gate structure after forming the metal oxide layer such that the n-type metal layer surrounds each nanostructured channel layer in the second plurality of gate structures (block 1450). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the n-type metal layer (e.g., n-type metal layer 1035) of the second gate structure (e.g., n-type gate structure 240a) after forming the metal oxide layer. Such that the n-type metal layer surrounds each of the second plurality of nanostructured channel layers, as described in this disclosure.

[0240] Process 1400 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0241] In a first embodiment, forming the metal oxide layer includes oxidizing the surface of the p-type metal layer to form the metal oxide layer.

[0242] In a second embodiment, alone or in combination with the first embodiment, oxidizing the surface of the p-type metal layer includes using ozone (O 3) solution, perform an oxide treatment operation (e.g., oxidation operation 1025) on the surface of the p-type metal layer.

[0243] In the third embodiment, alone or in combination with one or more of the first and second embodiments, oxidizing the surface of the p-type metal layer includes performing a baking operation (e.g., oxidation operation 1025) to oxidize the surface of the p-type metal layer.

[0244] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, oxidizing the surface of the p-type metal layer includes performing a plasma treatment operation (e.g., oxidation operation 1025) on the surface to oxidize the surface of the p-type metal layer.

[0245] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, oxidizing the surface of the p-type metal layer includes performing an oxide treatment operation (e.g., oxidation operation 1025) on the surface of the p-type metal layer using an oxygen-containing gas.

[0246] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the p-type metal layer includes titanium nitride (Ti x N y ), and the metal oxide layer includes titanium oxide (TiO x ).

[0247] Although Figure 14 illustrates an example block of process 1400, in some implementations, process 1400 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks compared to those depicted in Figure 14 . Additionally or alternatively, two or more blocks of process 1400 can be executed in parallel.

[0248] Figure 15 is a flowchart of an example process 1500 associated with forming the semiconductor device described in this disclosure. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 - 112) are used to perform Figure 15 one or more processing blocks. Additionally or alternatively, Figure 15 one or more processing blocks of

[0249] can be performed using one or more components of device 1300, such as processor 1320, memory 1330, input element 1340, output element 1350, and / or communication element 1360. Figure 15As shown, process 1500 may include forming a first plurality of nanostructured channel layers (block 1510) arranged along a direction substantially perpendicular to the semiconductor substrate of the semiconductor element. For example, one or more of semiconductor processing tools 102 - 112 may be used to form the first plurality of nanostructured channel layers (e.g., nanostructured channels 220b), which are arranged approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 205) of the semiconductor element (e.g., semiconductor element 200), as described in this disclosure.

[0250] As Figure 15 As further shown, process 1500 may include forming a second plurality of nanostructured channel layers (block 1520) arranged along a direction approximately perpendicular to the semiconductor substrate. For example, one or more of semiconductor processing tools 102 - 112 may be used to form the second plurality of nanostructured channel layers (e.g., nanostructured channels 220a), which are arranged approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 205), as described in this disclosure.

[0251] As Figure 15 As further shown, process 1500 may include forming a p-type metal layer such that the p-type metal layer surrounds each of the first plurality of nanostructured channel layers and each of the second plurality of nanostructured channel layers around the channel layers (block 1530). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the p-type metal layer (e.g., p-type metal layer 1015) such that the p-type metal layer surrounds each of the first plurality of nanostructured channel layers and each of the second plurality of nanostructured channel layers, as described in this disclosure.

[0252] As Figure 15 As further shown, process 1500 may include forming a mask layer above the first plurality of nanostructured channel layers (block 1540). For example, one or more of semiconductor processing tools 102 - 112 may be used to form the mask layer (e.g., photoresist layer 1020) above the first plurality of nanostructured channel layers, as described in this disclosure.

[0253] As Figure 15 As further shown, process 1500 may include removing a portion of the p-type metal layer from the second plurality of nanostructured channel layers when the mask layer is located above the first plurality of nanostructured channel layers (block 1550). For example, one or more semiconductor processing tools 102 - 112 may be used to remove a portion of the p-type metal layer from the second plurality of nanostructured channel layers when the mask layer is located above the first plurality of nanostructured channel layers, as described in this disclosure. In certain embodiments, the remaining portion of the p-type metal layer surrounding the first plurality of nanostructured channel layers corresponds to the first gate structure (e.g., p-type gate structure 240b).

[0254] As Figure 15 Further shown, process 1500 may include removing the mask layer (block 1560) after removing a portion of the p-type metal layer. For example, as described in this disclosure, one or more of semiconductor processing tools 102-112 may be used to remove the mask layer after removing a portion of the p-type metal layer.

[0255] As Figure 15 Further shown, process 1500 may include performing an oxidation operation after removing the mask layer to form a metal oxide layer on the p-type metal layer of the first gate structure (block 1570). For example, one or more semiconductor processing tools 102-112 may be used to perform an oxidation operation (e.g., oxidation operation 1025) after removing the mask layer to form a metal oxide layer (e.g., metal oxide layer 1030) on the p-type metal layer of the first gate structure, as described in this disclosure.

[0256] As Figure 15 Further shown, process 1500 may include forming an n-type metal layer of the second gate structure after forming the metal oxide layer such that the n-type metal layer surrounds each of the second plurality of nanostructure channel layers (block 1580). For example, one or more semiconductor processing tools 102-112 may be used to form an n-type metal layer (e.g., n-type metal layer 1035) of the second gate structure (e.g., n-type gate structure 240a) after forming the metal oxide layer such that the n-type metal layer surrounds each of the second plurality of nanostructure channel layers, as described in this disclosure.

[0257] Process 1500 may include other embodiments, such as any single embodiment or any combination of embodiments described below, and / or embodiments related to one or more other processes described elsewhere in this disclosure.

[0258] In a first embodiment, performing the oxidation operation includes performing a baking operation to oxidize the surface of the p-type metal layer.

[0259] In a second embodiment, either alone or in combination with the first embodiment, performing the baking operation includes performing the baking operation at a temperature in the range of about 230 degrees Celsius to about 300 degrees Celsius.

[0260] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, a portion of the n-type metal layer is formed on the metal oxide layer, and the thickness (e.g., dimension D4, dimension D6) of the portion of the n-type metal layer on the metal oxide layer is less than the thickness (e.g., dimension D3, dimension D5) of the n-type metal layer surrounding each of the second plurality of nanostructure channel layers.

[0261] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, performing an oxidation operation includes performing the oxidation operation using at least one of ozone (O 3 ) gas or nitrous oxide (N 2 O) gas.

[0262] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, performing an oxidation operation includes performing the oxidation operation using oxygen (O 2 ) plasma.

[0263] Although Figure 15 shows example blocks of process 1500, in some embodiments, process 1500 includes more blocks, fewer blocks, different blocks, or differently arranged blocks than those described in Figure 15 . Additionally, or alternatively, two or more blocks of process 1500 may be executed concurrently.

[0264] Figure 16A and Figure 16B are schematic diagrams of an example embodiment 1600 of the RPG process described in this disclosure. Example embodiment 1600 includes an example of a replacement gate process for replacing a dummy gate structure 505 with a gate structure 240 (e.g., a replacement gate structure) of a semiconductor element 200. Figure 16A and Figure 16B are illustrated from multiple perspectives as described in Figure 5 , including the perspective of cross-section A-A in Figure 5 , the perspective of cross-section B-B in Figure 5 , and the perspective of cross-section C-C in Figure 5 . In some embodiments, the operations related to example embodiment 1600 are performed after the operations related to Figures 3A to 9 .

[0265] As Figure 16A shows, a high-k dielectric liner 1010a, an adhesion liner 1010b, and / or another type of liner are formed on the nanostructure channels 220a and 220b. The high-k dielectric liner 1010a and the adhesion liner 1010b may be formed in a manner similar to that described above in connection with Figure 10C .

[0266] As Figure 16A further shows, a p-type metal layer 1015 is formed on the high-k dielectric liner 1010a and / or the adhesion liner 1010b. The p-type metal layer 1015 is formed in a manner similar to that described above in Figure 10C , except that the p-type metal layer 1015 surrounding the nanostructure channels 220a and 220b does not merge between the nanostructure channels 220a and 220b.

[0267] As Figure 16B shown, operations related to Figures 10D to 10L can be performed to form an n-type gate structure 240a around the nanostructure channel 220a and a p-type gate structure 240b around the nanostructure channel 220b. However, in Figure 16B , since the p-type metal layer 1015 surrounding the nanostructure channel 220b does not merge between the nanostructure channels 220b, the metal oxide layer 1030 of the p-type gate structure 240b is formed between the nanostructure channels 220b.

[0268] As described above, Figure 16A and Figure 16B the number and arrangement of the operations and devices shown in Figure 16A and Figure 16B are provided as one or more embodiments. In fact, compared with the operations and elements shown in

[0269] there may be more operations and elements, fewer operations and elements, different operations and elements, or different arrangements.

[0269] In this way, PMOS nanostructure transistors and NMOS nanostructure transistors can be formed in a semiconductor element. The techniques described in this disclosure include forming various (different) types of gate metals for PMOS nanostructure transistors and maintaining the intrinsic NMOS nanostructure transistors of the semiconductor element. A p-type gate metal can be formed around the nanostructure channel of the PMOS nanostructure transistor. Then, the surface of the p-type gate metal can be oxidized to form a metal oxide layer on the p-type gate metal. During the formation of the n-type gate metal around the nanostructure channel of the NMOS nanostructure transistor, the metal oxide layer on the p-type gate metal prevents the n-type gate metal from forming on the p-type gate metal. This results in little or no n-type gate metal deposition on the p-type gate metal, thereby minimizing the impact of the p-type threshold voltage (PV t ) on the PMOS nanostructure transistor. In this way, the techniques described in this disclosure enable the work functions of the NMOS nanostructure transistors and PMOS nanostructure transistors to be adjusted to achieve the desired threshold voltages of the NMOS nanostructure transistors and PMOS nanostructure transistors. This enables the NMOS nanostructure transistors and PMOS nanostructure transistors to achieve low leakage current and enables the NMOS nanostructure transistors and PMOS nanostructure transistors to achieve high operating efficiency.

[0270] As described in more detail herein, some embodiments described herein include a method. The method includes forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. The method includes forming a second plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate. The method includes forming a p-type metal layer of a first gate structure such that the p-type metal layer coats each of the first plurality of nanostructured channel layers. The method includes forming a metal oxide layer on the p-type metal layer. The method includes forming an n-type metal layer of a second gate structure after forming the metal oxide layer such that the n-type metal layer coats each of the second plurality of nanostructured channel layers.

[0271] As described in more detail herein, some embodiments described herein include a semiconductor device. The semiconductor device includes a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers, arranged in a direction substantially perpendicular to the semiconductor substrate. The semiconductor device includes a first gate structure surrounding the first plurality of nanostructured channel layers, the first gate structure including a p-type metal layer and a metal oxide layer, the metal oxide layer including a material that is an oxide of the p-type metal of the p-type metal layer. The semiconductor device includes a second gate structure surrounding each of the second plurality of nanostructured channel layers, including an n-type metal layer, where the n-type metal layer is on the metal oxide layer of the first gate structure.

[0272] As described in more detail herein, some embodiments described herein include a method. The method includes forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. The method includes forming a second plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate. The method includes forming a p-type metal layer such that the p-type metal layer surrounds each of the first plurality of nanostructured channel layers and each of the second plurality of nanostructured channel layers. The method includes forming a mask layer over the first plurality of nanostructured channel layers. The method includes removing a portion of the p-type metal layer from the second plurality of nanostructured channel layers while the mask layer is over the first plurality of nanostructured channel layers, where a remaining portion of the p-type metal layer wraps around the first plurality of nanostructured channel layers corresponding to the first gate structure. The method includes removing the mask layer after removing the portion of the p-type metal layer. The method includes performing an oxidation operation after removing the mask layer to form a metal oxide layer on the p-type metal layer of the first gate structure. The method includes forming an n-type metal layer of a second gate structure after forming the metal oxide layer such that the n-type metal layer coats each of the second plurality of nanostructured channel layers.

[0273] As described in more detail in this disclosure, some embodiments described in this disclosure include methods. This method includes forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate of the semiconductor device. This method includes forming a second plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate. This method includes forming a first type of metal layer surrounding each of the first plurality of nanostructured channel layers. This method includes forming a metal oxide layer on the first type of metal layer. This method includes forming a second type of metal layer on the metal oxide layer and on the second plurality of nanostructured channel layers. The first thickness of the second type of metal layer on the metal oxide layer is different from the second thickness of the second type of metal layer on the second plurality of nanostructured channel layers.

[0274] In one or more embodiments of this disclosure, forming the metal oxide layer includes: oxidizing the surface of the first type of metal layer to form a metal oxide layer.

[0275] In one or more embodiments of this disclosure, oxidizing the surface of the first type of metal layer includes: using a solution containing ozone (O 3 ) dissolved in deionized water to perform an oxidation treatment operation on the surface of the first type of metal layer.

[0276] In one or more embodiments of this disclosure, oxidizing the surface of the first type of metal layer includes: performing a baking operation to oxidize the surface of the first metal layer.

[0277] In one or more embodiments of this disclosure, oxidizing the surface of the first type of metal layer includes: performing a plasma treatment operation on the surface of the first type of metal layer to oxidize the surface of the first type of metal layer.

[0278] In one or more embodiments of this disclosure, oxidizing the surface of the first type of metal layer includes: using an oxygen-containing gas to perform an oxidation treatment operation on the surface of the first type of metal layer.

[0279] In one or more embodiments of this disclosure, the first type of metal layer includes titanium nitride (Ti x N y ). And the metal oxide layer includes titanium oxide (TiO x ).

[0280] In one or more embodiments of this disclosure, the p-type metal of the p-type metal layer includes at least one of the following: tungsten, cobalt, tungsten nitride, or titanium nitride.

[0281] In one or more embodiments of this disclosure, the p-type metal of the p-type metal layer has a work function greater than about 4.7 eV.

[0282] In one or more embodiments of the present disclosure, a thickness of a first portion of an n-type metal layer located on a sidewall of a first gate structure is less than a thickness of a second portion of the n-type metal layer located on a sidewall of a second gate structure.

[0283] In one or more embodiments of the present disclosure, a thickness of a first portion of an n-type metal layer located on a top surface of a first gate structure is less than a thickness of a second portion of the n-type metal layer located on a top surface of a second gate structure.

[0284] In one or more embodiments of the present disclosure, a ratio of a thickness of a portion of an n-type metal layer located on a top surface of a second gate structure to a thickness of another portion of the n-type metal layer located on a top surface of a first gate structure is greater than about 1.2:1.

[0285] In one or more embodiments of the present disclosure, a ratio of a thickness of a portion of an n-type metal layer located on a side surface of a second gate structure to a thickness of another portion of the n-type metal layer located on a side surface of a first gate structure is greater than about 1.2:1.

[0286] In one or more embodiments of the present disclosure, performing an oxidation operation includes: performing a baking operation to oxidize a surface of a p-type metal layer.

[0287] In one or more embodiments of the present disclosure, performing the baking operation includes: performing the baking operation at a temperature in a range of about 230 degrees Celsius to about 300 degrees Celsius.

[0288] In one or more embodiments of the present disclosure, a portion of the n-type metal layer is formed on a metal oxide layer. And a thickness of the portion of the n-type metal layer on the metal oxide layer is less than a thickness of the n-type metal layer surrounding a second plurality of nanostructure channel layers.

[0289] In one or more embodiments of the present disclosure, performing the oxidation operation includes: using ozone (O 3 ) gas or nitrous oxide (N 2 O) gas or at least one of them to perform the oxidation operation.

[0290] In one or more embodiments of the present disclosure, performing the oxidation operation includes: using oxygen (O 2 ) plasma to perform the oxidation operation.

[0291] The terms "about" and "substantially" may indicate that a value of a given quantity or magnitude varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are only examples and are not intended to be limiting. It should be understood that, according to the present disclosure, the terms "about" and "substantially" may refer to a percentage of a given quantity value.

[0292] The features of several embodiments were outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor element, characterized in that: Include: forming a first plurality of nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor element; forming a second plurality of nanostructure channel layers arranged in the direction substantially perpendicular to the semiconductor substrate; forming a first type metal layer surrounding each of the first plurality of nanostructure channel layers; forming a metal oxide layer on the first type metal layer; as well as forming a second type metal layer on the metal oxide layer and on the second plurality of nanostructure channel layers, A first thickness of the second type metal layer on the metal oxide layer is different from a second thickness of the second type metal layer on the second plurality of nanostructure channel layers.

2. The method for forming a semiconductor device according to claim 1, wherein: Forming the metal oxide layer comprises: A surface of the first type metal layer is oxidized to form the metal oxide layer.

3. The method for forming a semiconductor device according to claim 1, wherein: The first type metal layer includes titanium nitride (Ti x N y );as well as The metal oxide layer comprises titanium monoxide (TiO x ).

4. A semiconductor element, characterized in that: Include: A first plurality of nanostructured channel layers are arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor element; a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and arranged in the direction substantially perpendicular to the semiconductor substrate; A first gate structure, surrounding the first plurality of nanostructure channel layers, comprises: a p-type metal layer; a metal oxide layer comprising a material comprising an oxide of a p-type metal of the p-type metal layer; and a second gate structure surrounding each of the second plurality of nanostructured channel layers, comprising an n-type metal layer, The n-type metal layer is included on the metal oxide layer of the first gate structure.

5. The semiconductor device according to claim 4, wherein: The p-type metal of the p-type metal layer includes at least one of the following: Tungsten, cobalt, Tungsten nitride, or Titanium nitride.

6. The semiconductor device according to claim 4, wherein: A thickness of a first portion of the n-type metal layer located on a sidewall of the first gate structure is less than a thickness of a second portion of the n-type metal layer located on a sidewall of the second gate structure.

7. The semiconductor device according to claim 4, wherein: A thickness of a first portion of the n-type metal layer on a top surface of the first gate structure is less than a thickness of a second portion of the n-type metal layer on a top surface of the second gate structure.

8. A method for forming a semiconductor element, characterized in that: Include: Forming a first plurality of nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor element; forming a second plurality of nanostructure channel layers arranged in the direction substantially perpendicular to the semiconductor substrate; Forming a p-type metal layer so that the p-type metal layer surrounds each of the first plurality of nanostructure channel layers and each of the second plurality of nanostructure channel layers; forming a mask layer over the first plurality of nanostructure channel layers; removing a portion of the p-type metal layer from the second plurality of nanostructured channel layers when the mask layer is located above the first plurality of nanostructured channel layers, wherein a remaining portion of the p-type metal layer surrounding the first plurality of nanostructure channel layers corresponds to a first gate structure; After removing the portion of the p-type metal layer, removing the mask layer; After removing the mask layer, performing an oxidation operation to form a metal oxide layer on the p-type metal layer of the first gate structure; and After forming the metal oxide layer, an n-type metal layer of a second gate structure is formed so that the n-type metal layer surrounds each of the second plurality of nanostructure channel layers.

9. The method for forming a semiconductor device according to claim 8, wherein: Carrying out the oxidation operation comprises: A baking operation is performed to oxidize a surface of the p-type metal layer.

10. The method for forming a semiconductor device according to claim 8, wherein: A portion of the n-type metal layer is formed on the metal oxide layer; and A thickness of the portion of the n-type metal layer on the metal oxide layer is smaller than a thickness of the n-type metal layer surrounding each of the second plurality of nanostructure channel layers.

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