Method for manufacturing stacked transistor, stacked transistor, and semiconductor device

Abstract

The application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. The method comprises the following steps: forming a fin structure on a semiconductor substrate, the fin structure comprising a first fin structure and a second fin structure; based on the first fin structure, sequentially forming a first source-drain structure, a first gate structure and a first source-drain metal; based on the second fin structure, sequentially forming a second source-drain structure, a second gate structure and a second source-drain metal; forming a back surface via structure and a back surface power rail on the second gate structure and the second source-drain metal to obtain a back surface transistor, the back surface power rail being in communication with the second source-drain metal and the first gate structure through the back surface via structure; and forming a front surface via structure and a front surface power rail on the first gate structure and the first source-drain metal to obtain a front surface transistor, the front surface power rail being in communication with the first source-drain metal and the second gate structure through the front surface via structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. BACKGROUND

[0002] At present, it is a hot issue in the industry to continue to promote the miniaturization of transistors as Moore's law continues to deepen. Stacked transistors, which integrate two or more layers of transistors in the vertical space, can further improve the integration density of transistors and become one of the important technologies to continue the miniaturization of integrated circuits.

[0003] In some schemes for preparing stacked transistors, the active regions of two layers of homologous transistors are formed by etching, and the stacked transistors are prepared on the front and back surfaces of the wafer by developing. This can also be referred to as a "self-aligned flip transistor" scheme. However, the front and back structures of the "self-aligned flip transistor" have a mirror symmetry relationship, which makes the internal wiring of the transistor complex and extremely difficult to prepare during the process of forming decap cells based on the "self-aligned flip transistor", and is not conducive to the miniaturization of integrated circuits. SUMMARY

[0004] The present application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device to realize the staggered design of the front power rail and the back power rail, so that the interconnection lines inside the decap capacitor can be realized through the front via structure and the back via structure, thereby effectively reducing the preparation difficulty and not increasing the size of the transistor unit, which helps to further improve the integration level of the circuit.

[0005] In a first aspect, the embodiments of the present application provide a preparation method of a stacked transistor, comprising: forming a fin structure on a semiconductor substrate, wherein the fin structure comprises a first fin structure and a second fin structure stacked along a first direction; based on the first fin structure, sequentially forming a first source-drain structure, a first gate structure and a first source-drain metal, wherein the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther away from the second fin structure than the first source-drain structure; based on the second fin structure, sequentially forming a second source-drain structure, a second gate structure and a second source-drain metal, wherein the second source-drain structure and the first source-drain structure are stacked along the first direction, and the second gate structure and the first gate structure are stacked along the first direction; the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther away from the first fin structure than the second source-drain structure; forming a backside via structure and a backside power rail on the second gate structure and the second source-drain metal to obtain a backside transistor, wherein the backside power rail is in communication with the second source-drain metal and the first gate structure through the backside via structure; forming a frontside via structure and a frontside power rail on the first gate structure and the first source-drain metal to obtain a frontside transistor, wherein the frontside power rail is in communication with the first source-drain metal and the second gate structure through the frontside via structure; the frontside power rail is located on a first side of the fin structure in a second direction, the backside power rail is located on a second side of the fin structure in the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

[0006] In some possible implementation manners, based on the second fin structure, the second source-drain structure, the second gate structure and the second source-drain metal are sequentially formed, comprising: based on the second fin structure, sequentially forming the second source-drain structure and the second gate structure; removing a first part of the second gate structure and retaining a second part of the second gate structure to form a backside trench, and depositing an insulating material in the backside trench to form a backside isolation structure; wherein the first part of the second gate structure and the second part of the second gate structure are arranged along a second direction; forming the second source-drain metal on the second source-drain structure; forming the backside via structure and the backside power rail on the second gate structure and the second source-drain metal, comprising: forming a backside dielectric layer on the backside isolation structure, the second gate structure and the second source-drain metal; etching the backside dielectric layer until the second source-drain metal is exposed to form a backside source-drain metal via, and etching the backside dielectric layer and the backside isolation structure until the first gate structure is exposed to form a backside gate metal via; depositing a metal in the backside source-drain metal via and the backside gate metal via to form a backside source-drain via structure and a backside gate via structure, respectively; wherein the backside source-drain via structure and the backside gate via structure are included in the backside via structure; forming the backside power rail on the backside dielectric layer, wherein the backside power rail is in communication with the second source-drain metal through the backside source-drain via structure, and the backside power rail is in communication with the first gate structure through the backside gate via structure.

[0007] In some possible implementation manners, the forming the first source-drain structure, the first gate structure and the first source-drain metal in sequence based on the first fin structure comprises: forming the first source-drain structure and the first gate structure in sequence based on the first fin structure; removing a first part of the first gate structure and leaving a second part of the first gate structure to form a front side trench, and depositing an insulating material in the front side trench to form a front side isolation structure; wherein the first part of the first gate structure and the second part of the second gate structure are arranged along the second direction; the front side isolation structure is located at the first side of the fin structure, and the back side isolation structure is located at the second side of the fin structure; and the first source-drain metal is formed on the first source-drain structure.

[0008] In some possible implementation manners, the forming the front side via structure and the front side power rail on the first gate structure and the first source-drain metal comprises: forming a front side dielectric layer on the front side isolation structure, the first gate structure and the first source-drain metal; etching the front side dielectric layer until the first source-drain metal is exposed to form a front side source-drain metal via, and etching the front side dielectric layer and the front side isolation structure until the second gate structure is exposed to form a front side gate metal via; depositing metal in the front side source-drain metal via and the front side gate metal via to form a front side source-drain via structure and a front side gate via structure, respectively; wherein the front side source-drain via structure and the front side gate via structure are included in the front side via structure; and forming the front side power rail on the front side dielectric layer, wherein the front side power rail is in communication with the first source-drain metal through the front side source-drain via structure, and the front side power rail is in communication with the second gate structure through the front side gate via structure.

[0009] In some possible implementation manners, after the forming the back side metal interconnection layer on the second gate structure and the second source-drain metal, the method further comprises: forming a back side insulating layer on the back side metal interconnection layer; bonding the back side handle wafer to the back side insulating layer, and flipping the bonded back side handle wafer; and before the forming the front side via structure and the front side power rail on the first gate structure and the first source-drain metal, the method further comprises: removing the back side handle wafer and the back side insulating layer to expose the first gate structure and the first source-drain metal.

[0010] In some possible implementation manners, the extending direction of the front side power rail and the back side power rail is a third direction, the third direction is perpendicular to the first direction and the second direction; a projection of the front side via structure along the first direction falls within a projection of the front side power rail along the first direction; and a projection of the back side via structure along the first direction falls within a projection of the back side power rail along the first direction.

[0011] In a second aspect, the embodiments of the present application provide a stacked transistor, comprising: a front-side transistor, the front-side transistor comprising: a first source-drain structure, a first gate structure, a first source-drain metal, and a front-side metal interconnection layer; a back-side transistor, the back-side transistor comprising: a second source-drain structure, a second gate structure, a second source-drain metal, and a back-side metal interconnection layer; the front-side transistor and the back-side transistor are arranged in a first direction; wherein the front-side metal interconnection layer comprises a front-side power rail and a front-side via structure, the front-side power rail is in communication with the first source-drain metal and the second gate structure through the front-side via structure; the back-side metal interconnection layer comprises a back-side power rail and a back-side via structure, the back-side power rail is in communication with the second source-drain metal and the first gate structure through the back-side via structure; the front-side power rail is located on a first side of the fin structure in a second direction, the back-side power rail is located on a second side of the fin structure in the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

[0012] In some possible implementation manners, the extending direction of the front-side power rail and the back-side power rail is a third direction, the third direction is perpendicular to the first direction and the second direction; a projection of the front-side via structure along the first direction falls within a projection of the front-side power rail along the first direction; a projection of the back-side via structure along the first direction falls within a projection of the back-side power rail along the first direction.

[0013] In some possible implementation manners, the front-side via structure comprises: a front-side source-drain via structure and a front-side gate via structure; the front-side power rail is in communication with the first source-drain metal through the front-side source-drain via structure, and the front-side power rail is in communication with the second gate structure through the front-side gate via structure; the back-side via structure comprises: a back-side source-drain via structure and a back-side gate via structure; the back-side power rail is in communication with the second source-drain metal through the back-side source-drain via structure, and the back-side power rail is in communication with the first gate structure through the back-side gate via structure.

[0014] In a third aspect, the embodiments of the present application provide a semiconductor device, comprising: the stacked transistor as described in the above embodiments.

[0015] In the embodiments of the present application, based on the first fin structure and the second fin structure stacked along the first direction, the front-side transistor and the back-side transistor can be respectively prepared, so as to realize the self-alignment flip stacking of the transistors. In the process of forming the back-end metal interconnection layer of the front-side transistor and the back-side transistor, the first side of the fin structure is prepared to form the front-side power rail, and the second side opposite to the first side is prepared to form the back-side power rail, so that on one side of the stacked transistors, the front-side power rail is respectively communicated with the first source-drain metal and the second gate structure through the front-side via structure; on the other side of the stacked transistors, the back-side power rail is respectively communicated with the second source-drain metal and the first gate structure through the back-side via structure. It can be seen that the front-side power rail and the back-side power rail adopt the staggered design, so that the internal interconnection lines of the decoupling capacitor can be realized through the front-side via structure and the back-side via structure, on the one hand, the complex back-end metal line is no longer needed, and the complexity of the preparation process is effectively reduced; on the other hand, the area of the transistor does not need to be increased, and the integration performance of the stacked transistors is effectively improved.

[0016] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings incorporated into the specification and constituting a part of the specification, show embodiments consistent with the present application, and together with the specification, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of a circuit composition of the decoupling capacitor in the embodiments of the present application;

[0019] Figure 2 A schematic diagram of a layout of the decoupling capacitor in the embodiments of the present application; Figure 1

[0020] An implementation flowchart of a preparation method of the stacked transistors in the embodiments of the present application; Figure 3

[0021] A schematic diagram of a preparation process of the stacked transistors in the embodiments of the present application. Figures 4 to 18 The above figures: 11, front-side transistor; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 116, front-side metal interconnection layer; 12, back-side transistor; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, back-side metal interconnection layer;

[0022]

[0023] ​20, semiconductor substrate; 21, fin structure; 211, first fin structure; 212, second fin structure; 22, shallow trench isolation structure; 23, first dummy gate structure; 24, front side isolation structure; 25, front side insulating layer; 26, front side handle wafer; 27, second dummy gate structure; 28, back side isolation structure; 29, back side dielectric layer; 30, back side source / drain via structure; 31, back side gate via structure; 32, back side power rail; 33, back side insulating layer; 34, back side handle wafer; 35, front side dielectric layer; 36, front side source / drain via structure; 37, front side gate via structure; 38, front side power rail. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, like reference numerals refer to like elements, unless the context clearly dictates otherwise. The following exemplary embodiments described herein are not meant to represent all embodiments consistent with the present application.

[0025] In the context of Moore's Law, continuing to push the scaling of transistor size is a hot issue in the industry. Stacked transistors, by stacking transistors in three dimensions, can integrate two or more layers of transistors in the vertical space, helping to further improve transistor integration density and circuit performance, and is considered one of the important technologies to continue the scaling of integrated circuits.

[0026] In an embodiment, there are two schemes for the preparation process of stacked transistors, the first being monolithic and the second being sequential.

[0027] The first scheme fabricates N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs) on the same substrate without using wafer bonding technology. This determines that the same layer of transistors must be of the same type, i.e., NFET or PFET. Moreover, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) complex process, requiring a large amount of process technology development and optimization; (2) fixed polarity of each layer of transistors, which must rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, with poor design flexibility.

[0028] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are vertically stacked by bonding a wafer on top of the lower layer of transistors that have been fabricated. However, the temperature needs to be strictly controlled during the thermal process of processing the upper layer of transistors to avoid affecting the lower layer of transistors and the interconnection lines. The advantage of this solution is that, thanks to wafer bonding, the device structures, channel crystal orientations, and even channel materials of the upper and lower layers of transistors can be optimized accordingly to obtain better and more matched device performance.

[0029] To solve the technical problems of the above two solutions, a "self-aligned flip transistor" solution is proposed. The "self-aligned flip transistor" solution forms the active regions of the upper and lower layer of transistors by etching, and realizes the fabrication of stacked transistors on the front and back surfaces of the wafer by flipping, to overcome the disadvantages of the above two solutions.

[0030] For a complementary field-effect transistor (CFET) formed by using the above "self-aligned flip transistor" solution, since the power lines and signal lines are arranged on the front surface of the transistor, for relatively complex metal interconnections, such as the formation of a decoupling capacitor using a cross-coupled structure, there may be difficulties in wiring and process. At the same time, for the industry mainstream CFET with a common gate, there may also be a problem of increased standard cell design area, so it is urgent to provide a decoupling capacitor design solution that can overcome the above difficulties.

[0031] In some embodiments, the decoupling capacitor is a capacitor installed on the power end of an element in a circuit, which can provide a relatively stable power supply and also reduce the noise of the element coupled to the power end, thereby indirectly reducing the influence of the noise of the element on other elements.

[0032] In some embodiments, the decoupling capacitor can be composed of N-type metal-oxide-semiconductor (NMOS) transistors and P-type metal-oxide-semiconductor (PMOS) transistors in parallel.

[0033] To this end, the embodiments of the present application provide a preparation method of a stacked transistor, a stacked transistor, and a semiconductor device, to realize the use of

[0034] Figure 1 For a schematic diagram of a circuit composition of the decoupling capacitor in the embodiments of the present application, see Figure 1As shown, between the power rail VDD and the power rail VSS, two transistors with opposite polarities can be arranged in parallel to form a decoupling capacitor. Among them, one of the two transistors is an NMOS transistor, and the other is a PMOS transistor. The source and drain of the NMOS transistor are short-circuited and connected to the power rail VSS, and the gate is connected to the power rail VDD. The source and drain of the PMOS transistor are short-circuited and connected to the power rail VDD, and the gate is connected to the power rail VSS.

[0035] Figure 2 For the preparation method of the stacked transistor in the embodiments of the present application Figure 1 A schematic diagram of a layout of the decoupling capacitor is shown in FIG. 3. As shown in FIG. 3, an NMOS transistor and a PMOS transistor are shown. The NMOS transistor and the PMOS transistor can be composed of a fin structure, a gate structure, a source-drain metal, a single diffusion isolation structure, a metal interconnection layer, a gate metal structure, and a source-drain metal structure. Among them, the metal interconnection layer includes the power rail VDD and the power rail VSS. Figure 2 Figure 2 An NMOS transistor and a PMOS transistor are shown in FIG. 4. The NMOS transistor and the PMOS transistor can be composed of a fin structure, a gate structure, a source-drain metal, a single diffusion isolation structure, a metal interconnection layer, a gate metal structure, and a source-drain metal structure. Among them, the metal interconnection layer includes the power rail VDD and the power rail VSS.

[0036] Here, according to the layout shown in FIG. 5, the NMOS transistor and the PMOS transistor are stacked transistors. Figure 2

[0037] In a first aspect, the embodiments of the present application provide a preparation method of a stacked transistor. Figure 3 An implementation flowchart of the preparation method of the stacked transistor in the embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, to prepare and form the structure shown in FIG. 3, the preparation method of the stacked transistor can include: Figure 3 Figures 1 to 2 As shown in FIG. 6, to prepare and form the structure shown in FIG. 3, the preparation method of the stacked transistor can include:

[0038] Step S301: Forming a fin structure on a semiconductor substrate, wherein the fin structure includes a first fin structure and a second fin structure stacked along a first direction;

[0039] Step S302: Forming a first source-drain structure, a first gate structure, and a first source-drain metal in sequence based on the first fin structure, wherein the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther away from the second fin structure than the first source-drain structure;

[0040] Step S303: Forming a second source-drain structure, a second gate structure, and a second source-drain metal in sequence based on the second fin structure, wherein the second source-drain structure and the first source-drain structure are stacked along the first direction, the second gate structure and the first gate structure are stacked along the first direction; the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther away from the first fin structure than the second source-drain structure;

[0041] ​​​Step S304: forming a backside via structure and a backside power rail on the second gate structure and the second source-drain metal to obtain a backside transistor, wherein the backside power rail is in communication with the second source-drain metal and the first gate structure through the backside via structure respectively;

[0042] Step S305: forming a frontside via structure and a frontside power rail on the first gate structure and the first source-drain metal to obtain a frontside transistor, wherein the frontside power rail is in communication with the first source-drain metal and the second gate structure through the frontside via structure respectively; the frontside power rail is located on a first side of the fin structure in a second direction, and the backside power rail is located on a second side of the fin structure in the second direction, the first side and the second side are opposite, and the second direction is perpendicular to the first direction.

[0043] It should be noted that, Figure 3 The steps shown in the above embodiments are not exclusive, and other steps can be performed before, after or between any of the steps shown in the embodiments; Figure 3 The order of the steps shown in the above embodiments can be adjusted according to actual needs.

[0044] In step S301, a fin structure is formed on a semiconductor substrate.

[0045] In some embodiments, when the stacked transistor is prepared, a semiconductor substrate can be provided first. The semiconductor substrate can be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, etc. Then, a plurality of fin structures can be formed on the semiconductor substrate.

[0046] In some embodiments, when the stacked transistor is a fin field effect transistor, step S301 can include: forming a semiconductor epitaxial layer on the surface of the semiconductor substrate by an epitaxial growth process; etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the substrate, thereby forming a plurality of fin structures.

[0047] In some embodiments, when the stacked transistor is a full-surrounding gate transistor, step S301 can include: performing a material layer deposition, epitaxial growth or other process on the semiconductor substrate to form a stack structure on the semiconductor substrate. Then, a one-time etching process is used to etch the stack structure to form a fin structure on the semiconductor substrate.

[0048] In the embodiment of the present application, since the stacked transistors include the upper and lower transistors (comprising the front-side transistor and the back-side transistor), and the active structures of the upper and lower transistors are formed by the same etching process, that is, the first active structure of the front-side transistor and the second active structure of the back-side transistor are formed by the same etching process. Therefore, a larger etching depth can be used when etching the semiconductor substrate. For example, the height of the fin structure obtained by etching can be greater than 100 nm. It should be noted that the height of the fin structure can be set according to actual conditions, and the embodiment of the present application does not limit this.

[0049] In some embodiments, the fin structure includes a first fin structure and a second fin structure. The first fin structure and the second fin structure are stacked along a first direction (a direction perpendicular to the semiconductor substrate), and the second fin structure is closer to the semiconductor substrate relative to the first fin structure. It can be understood that the first fin structure is used to form the active region of the front-side transistor in the subsequent steps; and the second fin structure is used to form the active region of the back-side transistor in the subsequent steps.

[0050] In step S302, based on the first fin structure, a first source-drain structure, a first gate structure and a first source-drain metal are sequentially formed.

[0051] It can be understood that based on the first fin structure, the first source-drain structure, the first gate structure and the first source-drain metal can be sequentially prepared by using a semiconductor standard preparation process. Among them, the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther away from the second fin structure than the first source-drain structure.

[0052] It should be noted that the preparation process of the first source-drain structure, the first gate structure and the first source-drain metal can be selected according to actual needs, and the embodiment of the present application does not limit this.

[0053] In some embodiments, step S302 can include: based on the first fin structure, sequentially forming a first source-drain structure and a first gate structure; removing a first part of the first gate structure and retaining a second part of the first gate structure to form a front-side trench, and depositing an insulating material in the front-side trench to form a front-side isolation structure. The first source-drain metal is formed on the first source-drain structure.

[0054] In an embodiment, the first part of the first gate structure and the second part of the second gate structure are arranged along the second direction. In an embodiment, the first part of the first gate structure is removed and the second part of the first gate structure is retained by using a gate cutting process.

[0055] In an embodiment, the first part of the first gate structure is located on one side of the first fin structure in the second direction, and the second part of the first gate structure can wrap the first fin structure.

[0056] In some embodiments, the first gate structure can be composed of a first gate dielectric layer and a first gate electrode layer.

[0057] In some embodiments, the materials of the first gate dielectric layer and the first gate electrode layer can be set according to actual needs, which are not limited in the embodiments of the present application. For example, the first gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thicknesses of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In an example, the first gate dielectric layer can include a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0058] In some embodiments, the front surface isolation structure is used to electrically isolate two adjacent transistor units. Alternatively, the front surface isolation structure is used to isolate the front surface gate via structure and the first gate structure.

[0059] In an embodiment, the insulating material forming the front surface isolation structure can be silicon nitride (Si3N4).

[0060] In some embodiments, based on the first fin structure, the first source-drain structure and the first gate structure are sequentially formed, including: depositing an insulating material on the semiconductor substrate to form a shallow trench isolation (STI) structure. Based on the first fin structure, a dummy gate structure is formed in the gate region of the stacked transistor on the STI structure. After forming the first source-drain structure in the source-drain region of the stacked transistor, the dummy gate structure is removed to form the first gate structure at the position where the dummy gate structure is removed.

[0061] In an embodiment, the insulating material forming the shallow trench isolation structure can be silicon-based oxide (SiOx, x is the number of oxygen atoms), for example, silicon dioxide (SiO2).

[0062] In some embodiments, the material forming the dummy gate structure can be a dummy gate material such as polysilicon or amorphous silicon.

[0063] In some embodiments, after forming the dummy gate structure, an insulating material can be deposited on the sidewall of the dummy gate structure to form a dummy gate sidewall covering the sidewall of the dummy gate structure.

[0064] In an embodiment, the insulating material forming the dummy gate sidewall can be silicon dioxide.

[0065] In some embodiments, forming the first source-drain metal on the first source-drain structure comprises: etching the first interlayer dielectric layer wrapping the first source-drain structure until the first source-drain structure is exposed to form a first source-drain metal recess; and depositing a metal material in the first source-drain metal recess to form the first source-drain metal. Here, the length of the first source-drain metal in the second direction can be selected according to actual needs, so that the first source-drain metal is located below the front side source-drain metal via hole formed in the subsequent preparation.

[0066] In some embodiments, after step S302, the method can comprise: depositing an insulating material on the first gate structure and the first source-drain metal to form a front side insulating layer; bonding the front side handle wafer with the front side insulating layer, and flipping the bonded front side handle wafer.

[0067] In step S303, based on the second fin structure, a second source-drain structure, a second gate structure and a second source-drain metal are sequentially formed.

[0068] It can be understood that based on the second fin structure, the second source-drain structure, the second gate structure and the second source-drain metal can be sequentially prepared by using a semiconductor standard preparation process. Among them, the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther away from the first fin structure than the second source-drain structure.

[0069] Among them, the second source-drain structure and the first source-drain structure are stacked along the first direction, and the second gate structure and the first gate structure are stacked along the first direction.

[0070] In some embodiments, step S303 can comprise: sequentially forming the second source-drain structure and the second gate structure based on the second fin structure; removing a first part of the second gate structure and retaining a second part of the second gate structure to form a back side trench, and depositing an insulating material in the back side trench to form a back side isolation structure. The second source-drain metal is formed on the second source-drain structure.

[0071] In some embodiments, the second source-drain metal and the first source-drain metal are staggered in the first direction. Among them, the second source-drain metal is close to the side where the back side power rail is located in the second direction, and the first source-drain metal is close to the side where the front side power rail is located in the second direction.

[0072] In some embodiments, the first part of the second gate structure and the second part of the second gate structure are arranged along the second direction. In an embodiment, the first part of the second gate structure is removed by using a gate cutting process, and the second part of the second gate structure is retained.

[0073] In an embodiment, the first part of the second gate structure is located at one side of the second fin structure in the second direction, and the second part of the second gate structure can wrap around the second fin structure. It should be noted that the first part of the second gate structure can be arranged opposite to the second part of the first gate structure, and the second part of the second gate structure can be arranged opposite to the first part of the first gate structure. That is, the front isolation structure is located at the first side of the fin structure in the second direction, and the back isolation structure is located at the second side of the fin structure in the second direction.

[0074] In some embodiments, the second gate structure can be composed of a second gate dielectric layer and a second gate electrode layer. The materials of the second gate dielectric layer and the second gate electrode layer can be set according to actual needs, and the embodiments of the present application do not limit this.

[0075] In some embodiments, the back isolation structure is used to electrically isolate two adjacent transistor units. Alternatively, the back isolation structure is used to isolate the back gate via structure and the second gate structure.

[0076] In an embodiment, the insulating material forming the back isolation structure can be the same as the insulating material forming the front isolation structure. In an embodiment, the insulating material forming the back isolation structure can be different from the insulating material forming the front isolation structure.

[0077] In some embodiments, based on the second fin structure, the second source / drain structure and the second gate structure are sequentially formed, including: removing the semiconductor substrate to expose the shallow trench isolation structure. Thinning the shallow trench isolation structure to expose the second fin structure; based on the second fin structure, forming a dummy gate structure in the gate region of the stacked transistor. After forming the second source / drain structure in the source / drain region of the stacked transistor, the dummy gate structure is removed to form the second gate structure at the position where the dummy gate structure is removed.

[0078] In some embodiments, forming the second source / drain metal on the second source / drain structure includes: etching the second interlayer dielectric layer wrapping the second source / drain structure until the second source / drain structure is exposed to form a second source / drain metal groove; depositing a metal material in the second source / drain metal groove to form a second source / drain metal. Here, the length of the second source / drain metal in the second direction can be selected according to actual needs, so that the second source / drain metal is located below the back source / drain metal via formed in the subsequent preparation.

[0079] In step S304, the back via structure and the back power rail are formed on the second gate structure and the second source / drain metal.

[0080] It can be understood that after the second gate structure and the second source-drain metal are formed, the back surface via structure can be formed, and then the standard post-process of semiconductor manufacturing (such as interconnection line medium deposition, metal line formation, lead pad formation, etc.) can be performed on the second gate structure and the second source-drain metal to form a back surface metal interconnection layer. The back surface metal interconnection layer includes a back surface power rail and a first metal line (M0 metal line). The back surface power rail can be in communication with the second source-drain metal and the first gate structure through the back surface via structure, respectively.

[0081] In some embodiments, step S304 can include: forming a back surface medium layer on the back surface isolation structure, the second gate structure and the second source-drain metal; etching the back surface medium layer until the second source-drain metal is exposed to form a back surface source-drain metal via, and etching the back surface medium layer and the back surface isolation structure until the first gate structure is exposed to form a back surface gate metal via; depositing metal in the back surface source-drain metal via and the back surface gate metal via to form a back surface source-drain via structure and a back surface gate via structure, respectively; and forming a back surface power rail on the back surface medium layer.

[0082] It can be understood that, according to the position of the back surface power rail, etching the back surface medium layer (i.e., the back surface medium layer located on the second source-drain metal) until the second source-drain metal is exposed can form a back surface source-drain metal via. According to the position of the back surface power rail, etching the back surface medium layer (i.e., the back surface medium layer located on the back surface isolation structure) and the back surface isolation structure until the first gate structure is exposed can form a back surface gate metal via.

[0083] The back surface source-drain via structure and the back surface gate via structure are included in the back surface via structure. The back surface power rail is in communication with the second source-drain metal through the back surface source-drain via structure, and the back surface power rail is in communication with the first gate structure through the back surface gate via structure.

[0084] In an embodiment, the back surface source-drain via structure and the back surface gate via structure can be directly connected. In an embodiment, the back surface source-drain via structure and the back surface gate via structure can be indirectly connected through the back surface power rail.

[0085] In some embodiments, the back surface power rail can be connected to a positive power pin and has a positive power voltage. In an embodiment, the back surface power rail can be a power rail VDD. In some embodiments, the back surface power rail is a power rail VDD arranged in the back surface metal interconnection layer. It can be understood that the back surface metal interconnection layer can be a conductive layer stacked inside the transistor for signal transmission and power distribution. In an embodiment, the back surface metal interconnection layer further includes a metal line different from the back surface power rail, which can also be referred to as an M0 metal line.

[0086] In some embodiments, the material forming the backside dielectric layer can be a dielectric material, such as silicon nitride, aluminum oxide, or the like.

[0087] In an embodiment, after forming the backside metal interconnect layer, the second source / drain structure, the second gate structure, the second source / drain metal, the backside via structure, and the backside metal interconnect layer collectively form a backside transistor.

[0088] In some embodiments, after step S304, the method can further include: forming a backside insulating layer on the backside metal interconnect layer; bonding the backside handle wafer to the backside insulating layer, and flipping the bonded backside handle wafer.

[0089] It can be understood that flipping the bonded backside handle wafer can allow the backside transistor to be located at a lower layer, facilitating the preparation of the frontside transistor.

[0090] In an embodiment, the deposition of the insulating material on the backside metal interconnect layer can form a backside insulating layer. In an embodiment, the insulating material forming the backside insulating layer can be set according to actual needs, which is not limited in the present embodiment.

[0091] In step S305, a frontside via structure and a frontside power rail are formed on the first gate structure and the first source / drain metal.

[0092] It can be understood that after forming the backside transistor, the frontside transistor can be prepared. After forming the first gate structure and the first source / drain metal, the backside via structure can be formed, and then the standard back-end-of-line process of semiconductor preparation (such as deposition of interconnection line dielectric, formation of metal lines, formation of lead pads, etc.) is used to form a frontside metal interconnect layer. The frontside metal interconnect layer includes a frontside power rail and a first metal line (M0 metal line). The frontside power rail is in communication with the first source / drain metal and the second gate structure through the frontside via structure, respectively; the frontside power rail is located at a first side of the fin structure, and the backside power rail is located at a second side of the fin structure.

[0093] In some embodiments, step S305 can include: forming a frontside dielectric layer on the frontside isolation structure, the first gate structure, and the first source / drain metal; etching the frontside dielectric layer until the first source / drain metal is exposed to form a frontside source / drain metal via, and etching the frontside dielectric layer and the frontside isolation structure until the second gate structure is exposed to form a frontside gate metal via; depositing a metal in the frontside source / drain metal via and the frontside gate metal via to form a frontside source / drain via structure and a frontside gate via structure, respectively; and forming a frontside power rail on the frontside dielectric layer.

[0094] It can be understood that, according to the location of the front power rail, etching the front dielectric layer (i.e., the front dielectric layer located above the first source-drain metal) until the first source-drain metal is exposed, a front source-drain metal via hole can be formed. According to the location of the front power rail, etching the front dielectric layer (i.e., the front dielectric layer located above the front isolation structure) and the front isolation structure until the second gate structure is exposed, a front gate metal via hole can be formed.

[0095] The front source-drain via hole structure and the front gate via hole structure are included in the front via hole structure. The front power rail is in communication with the first source-drain metal through the front source-drain via hole structure, and the front power rail is in communication with the second gate structure through the front gate via hole structure.

[0096] In an embodiment, the front source-drain via hole structure and the front gate via hole structure can be directly connected. In an embodiment, the front source-drain via hole structure and the front gate via hole structure can be indirectly connected through the front power rail.

[0097] In some embodiments, the front power rail can be connected to a negative power pin and have a negative power voltage. In an embodiment, the front power rail can be the power rail VSS. In some embodiments, the back power rail is the power rail VSS disposed in the front metal interconnection layer. It can be understood that the front metal interconnection layer can be a conductive layer stacked inside the transistor for signal transmission and power distribution. In an embodiment, the front metal interconnection layer further includes a metal line different from the back power rail, which can also be referred to as the M0 metal line.

[0098] In some embodiments, the material forming the front dielectric layer can be a dielectric material, such as silicon nitride, aluminum oxide, etc.

[0099] In some embodiments, before step S305, it can include: removing the front wafer carrier and the front insulating layer to expose the first gate structure and the first source-drain metal.

[0100] In an embodiment, after the front metal interconnection layer is formed, the first source-drain structure, the first gate structure, the first source-drain metal, the front via hole structure, and the front metal interconnection layer collectively constitute a front transistor.

[0101] In this embodiment, based on the first and second fin structures stacked along a first direction, front-side transistors and back-side transistors can be fabricated respectively, thereby achieving self-aligned flip-chip stacking of transistors. During the formation of the back-end metal interconnect layers for the front and back-side transistors, a front-side power rail is formed on the first side of the fin structure, and a back-side power rail is formed on the second side opposite to the first side. This allows the front-side power rail to connect to the first source / drain metal and the second gate structure via a front-side via structure on one side of the stacked transistor; and the back-side power rail to connect to the second source / drain metal and the first gate structure via a back-side via structure on the other side of the stacked transistor. As can be seen, the front and back power rails are staggered, allowing interconnects within the decoupling capacitor to be realized through the front and back via structures. This eliminates the need for complex back-end metal lines, effectively reducing the complexity of the fabrication process; and it also eliminates the need to increase the transistor area, effectively improving the integration performance of the stacked transistors.

[0102] The following is a specific example illustrating the fabrication method of the stacked transistors in the embodiments of this application. Figures 4 to 18 This is a schematic diagram illustrating one fabrication process of the stacked transistors in an embodiment of this application. For ease of understanding, Figures 4 to 18 (a) shows along Figure 2 A cross-sectional view along the direction of the dashed line AA'. Figures 4 to 18 (b) shows the route along Figure 2 A cross-sectional view along the direction of the dashed line BB'. Figures 4 to 18 (c) shows the path along Figure 2 A cross-sectional view along the direction of the dashed line CC'. (Combined with...) Figures 1 to 18 The fabrication method of stacked transistors may include:

[0103] First step, see Figure 4 As shown, the fin structure 21 is formed on the semiconductor substrate 20 (silicon wafer) using an etching process. The fin structure 21 includes a first fin structure 211 and a second fin structure 212 stacked along a first direction, with the second fin structure 212 close to the semiconductor substrate 20. The first direction is the stacking direction of the stacked transistors.

[0104] Step 2, see Figure 5As shown, insulating material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 22 covering the fin structures 21, and the shallow trench isolation structure 22 is subjected to a chemical-mechanical planarization (CMP) process to ensure that the shallow trench isolation structure 22 has the same height in any region. Subsequently, the shallow trench isolation structure 22 is etched using an etching process until the first fin structure 211 is exposed. Here, the etched shallow trench isolation structure 22 can expose the first fin structure 211 and wrap the second fin structure 212.

[0105] In the third step, as shown in FIG. 2C, a pseudo-gate material such as polysilicon, monocrystalline silicon, etc. is deposited in the gate region to form a first pseudo-gate structure 23. Subsequently, a pseudo-gate sidewall can be formed on the sidewall of the first pseudo-gate structure 23. Here, the pseudo-gate sidewall formed on the sidewall of the first pseudo-gate structure 23 can constitute a first pseudo-gate sidewall of the front-side transistor 11. The first pseudo-gate sidewall is used to electrically isolate the first gate structure and the active structure in the front-side transistor 11. Figure 6 In the fourth step, as shown in FIG. 2D, the first fin structure 211 in the source-drain region is etched using the first pseudo-gate structure 23 as a hard mask to form a first source-drain recess, and a first source-drain structure 112 is formed in the first source-drain recess by epitaxy; a dielectric material is deposited on the first source-drain structure 112 to form an initial first interlayer dielectric layer, and the initial first interlayer dielectric layer is subjected to a mechanical planarization process to obtain a first interlayer dielectric layer 113, and the upper surface of the first interlayer dielectric layer 113 is flush with the upper surface of the first pseudo-gate structure 23.

[0106] Figure 7 In the fifth step, as shown in FIG. 2E, the first pseudo-gate structure 23 is removed, and a gate dielectric material and a gate metal material are sequentially deposited at the position where the first pseudo-gate structure 23 is removed to form a first gate dielectric layer and a first gate electrode layer, respectively, thereby obtaining a first gate structure 114; a first portion of the first gate structure is removed, and a second portion of the first gate structure is retained to form a front-side trench, and an insulating material is deposited in the front-side trench to form a front-side isolation structure 24.

[0107] In the fifth step, as shown in FIG. 2E, the first pseudo-gate structure 23 is removed, and a gate dielectric material and a gate metal material are sequentially deposited at the position where the first pseudo-gate structure 23 is removed to form a first gate dielectric layer and a first gate electrode layer, respectively, thereby obtaining a first gate structure 114; a first portion of the first gate structure is removed, and a second portion of the first gate structure is retained to form a front-side trench, and an insulating material is deposited in the front-side trench to form a front-side isolation structure 24. Figure 8 Here, the first portion of the first gate structure and the second portion of the first gate structure are arranged along a second direction. The second direction is perpendicular to the first direction.

[0108] In the sixth step, as shown in FIG. 2F, the first interlayer dielectric layer 113 is etched until the first source-drain structure 112 is exposed to form a first source-drain metal recess, and a metal material is deposited in the first source-drain metal recess to form a first source-drain metal 115 of the front-side transistor 11.

[0109] Figure 9 In the sixth step, as shown in FIG. 2F, the first interlayer dielectric layer 113 is etched until the first source-drain structure 112 is exposed to form a first source-drain metal recess, and a metal material is deposited in the first source-drain metal recess to form a first source-drain metal 115 of the front-side transistor 11. ​​

[0110] Here, the length of the first source-drain metal recess in the second direction can be set according to actual needs. In the embodiment, the first source-drain metal recess in the second direction can extend from the first source-drain structure 112 to the area where the front side isolation structure 24 is located, so that the first source-drain metal 115 is in contact with the front side isolation structure 24. In this way, the source-drain via structures formed subsequently can be arranged in the third direction with the gate via structures formed in the front side isolation structure 24, so that the front side power rail only needs to be arranged along the third direction, effectively reducing the complexity of preparation of the front side power rail.

[0111] Step 7, referring to Figure 10 as shown, an insulating material is deposited on the first source-drain metal 115, the first gate structure 114, and the front side isolation structure 24 to form a front side insulating layer 25, the front side wafer wafer 26 is bonded to the front side insulating layer 25, and the bonded front side wafer wafer 26 is flipped. Subsequently, a chemical mechanical planarization process is used to remove the semiconductor substrate 20 until the shallow trench isolation structure 22 is exposed.

[0112] Step 8, referring to Figure 11 as shown, the shallow trench isolation structure 22 is thinned to expose the second fin structure 212.

[0113] Here, the thinned shallow trench isolation structure 22 is located on the side of the junction of the first fin structure 211 and the second fin structure 212. The thinned shallow trench isolation structure 22 is used to electrically isolate the front side transistor 11 and the back side transistor 12.

[0114] Step 9, referring to Figure 12 as shown, a polysilicon, single crystal silicon or other pseudo-gate material is deposited in the gate region to form a second pseudo-gate structure 27. Subsequently, a pseudo-gate sidewall can be formed on the sidewall of the second pseudo-gate structure 27. Here, the pseudo-gate sidewall formed on the sidewall of the second pseudo-gate structure 27 can constitute the second pseudo-gate sidewall of the back side transistor 12. The second pseudo-gate sidewall is used to electrically isolate the second gate structure 124 and the active structure in the back side transistor 12.

[0115] Step 10, referring to Figure 13 as shown, the second fin structure 212 in the source-drain region is etched with the second pseudo-gate structure 27 as a hard mask to form a second source-drain recess, and the second source-drain structure 122 is epitaxially generated in the second source-drain recess; a dielectric material is deposited on the second source-drain structure 122 to form an initial second interlayer dielectric layer, and a mechanical planarization process is performed on the initial second interlayer dielectric layer to obtain a second interlayer dielectric layer 123, and the upper surface of the second interlayer dielectric layer 123 is flush with the upper surface of the second pseudo-gate structure 27.

[0116] Step 11, referring to Figure 14As shown, the second dummy gate structure 27 is removed, and a gate dielectric material and a gate metal material are sequentially deposited at the location where the second dummy gate structure 27 is removed to form a second gate dielectric layer and a second gate electrode layer, respectively, thereby obtaining a second gate structure 124; the first part of the second gate structure is removed, and the second part of the second gate structure is retained to form a back trench, and an insulating material is deposited in the back trench to form a back isolation structure 28.

[0117] In this configuration, the first portion of the second gate structure and the second portion of the second gate structure are arranged along a second direction. The front trench is located on the first side of the fin structure in the second direction, and the back trench is located on the second side of the fin structure in the second direction, with the first and second sides facing away from each other. Therefore, staggered front and back trenches can be formed in the stacked transistor. This can also be understood as the projection of the front trench along the first direction not coinciding with the projection of the back trench along the first direction.

[0118] Step 12, see Figure 15 As shown, the second interlayer dielectric layer 123 is etched until the second source / drain structure 122 is exposed to form a second source / drain metal groove, and metal material is deposited in the second source / drain metal groove to form the second source / drain metal 125 of the second transistor.

[0119] Here, the length of the groove in the second source / drain metal 125 in the second direction can be set according to actual needs. In this embodiment, the groove in the second source / drain metal 125 can extend from the second source / drain structure 122 to the area where the back isolation structure 28 is located in the second direction, so that the second source / drain metal 125 is connected to the back isolation structure 28. In this way, the source / drain via structure subsequently formed can be arranged in the third direction with the gate via structure formed in the back isolation structure 28, so that the back power rail only needs to be arranged in the third direction, effectively reducing the fabrication complexity of the back power rail.

[0120] Step thirteen, see Figure 16 As shown, a back dielectric layer 29 is formed over the back isolation structure 28, the second gate structure 124, and the second source / drain metal 125. The back dielectric layer 29 is etched until the second source / drain metal 125 is exposed to form a back source / drain metal via, and the back dielectric layer 29 and the back isolation structure 28 are etched until the first gate structure 114 is exposed to form a back gate metal via. Metal is deposited in the back source / drain metal via and the back gate metal via to form a back source / drain via structure 30 and a back gate via structure 31, respectively. After forming the back source / drain via structure 30 and the back gate via structure 31, a metal layer is fabricated over the back dielectric layer 29 to form a back power rail 32.

[0121] The projection of the back via structure along the first direction falls within the projection of the back power rail along the first direction. The back via structure includes a back source / drain via structure 30 and a back gate via structure 31. The back power rail 32 is connected to the second source / drain metal 125 through the back source / drain via structure 30, and the back power rail 32 is connected to the first gate structure 114 through the back gate via structure 31.

[0122] Step fourteen, see Figure 17 As shown, after the back metal interconnect layer 126 is fabricated, an insulating material is deposited on the back metal interconnect layer 126 to form a back insulating layer 33. The back wafer 34 is then bonded to the back insulating layer 33, and the bonded back wafer 34 is flipped. Subsequently, a chemical mechanical planarization process is used to remove the front wafer 26 and the front insulating layer 25 to expose the first source / drain metal 115, the first gate structure 114, and the front isolation structure 24.

[0123] Step 15, see Figure 18 As shown, a front dielectric layer 35 is formed over the first source / drain metal 115, the first gate structure 114, and the front isolation structure 24. The front dielectric layer 35 is etched until the first source / drain metal 115 is exposed to form a front source / drain metal via, and the front dielectric layer 35 and the front isolation structure 24 are etched until the second gate structure 124 is exposed to form a front gate metal via. Metal is deposited in the front source / drain metal via and the front gate metal via to form a front source / drain via structure 36 and a front gate via structure 37, respectively. After forming the front source / drain via structure 36 and the front gate via structure 37, a metal layer is fabricated over the front dielectric layer 35 to form a front power rail 38. The front power rail 38 is contained in the front metal interconnect layer 116.

[0124] The projection of the front via structure along the first direction falls into the projection of the front power rail 38 along the first direction. The front via structure includes a front source / drain via structure 36 and a front gate via structure 37. The front power rail 38 is connected to the first source / drain metal 115 through the front source / drain via structure 36, and the front power rail 38 is connected to the second gate structure 124 through the front gate via structure 37.

[0125] This completes the fabrication of stacked transistors.

[0126] In this embodiment, after the front source / drain metal is formed, a first flip-chip is performed to complete the fabrication of the back transistor. The first gate structure is directly connected to the back power rail using a back gate via structure. After the back transistor is fabricated, a second flip-chip is performed to complete the fabrication of the front transistor. Similarly, the second gate structure is directly connected to the front power rail using a front gate via structure, thereby obtaining a decoupling capacitor.

[0127] In a second aspect, the embodiments of the present application provide a stacked transistor. Referring to Figure 18 As shown in the figure, the front transistor 11 and the back transistor 12; the front transistor 11 comprises: a first source-drain structure 112, a first gate structure 114, a first source-drain metal 115 and a front metal interconnection layer 116; the back transistor 12 comprises: a second source-drain structure 122, a second gate structure 124, a second source-drain metal 125 and a back metal interconnection layer 126; the front transistor 11 and the back transistor 12 are arranged in a first direction.

[0128] Wherein, the front metal interconnection layer 116 comprises a front power rail 38 and a front via structure, the front power rail 38 communicates with the first source-drain metal 115 and the second gate structure 124 through the front via structure respectively; the back metal interconnection layer 126 comprises a back power rail 32 and a back via structure, the back power rail 32 communicates with the second source-drain metal 125 and the first gate structure 114 through the back via structure respectively; the front power rail 38 is located at a first side of the fin structure in a second direction, the back power rail 32 is located at a second side of the fin structure in the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

[0129] It can be understood that the first side of the fin structure in the stacked transistor is prepared to form the front power rail 38, and the second side opposite to the first side is prepared to form the back power rail 32, so that the front power rail 38 communicates with the first source-drain metal 115 and the second gate structure 124 through the front via structure on one side of the stacked transistor, and the back power rail 32 communicates with the second source-drain metal 125 and the first gate structure 114 through the back via structure on the other side of the stacked transistor. It can be seen that the front power rail 38 and the back power rail 32 adopt an interleaved design, so that the decoupling capacitor can be realized through the front via structure and the back via structure, on the one hand, the complex back-end metal line is no longer needed, effectively reducing the complexity of the preparation process; on the other hand, the area of the transistor does not need to be increased, effectively improving the integration performance of the stacked transistor.

[0130] In some embodiments, the extension direction of the front power rail 38 and the back power rail 32 is a third direction, the third direction is perpendicular to the first direction and the second direction; the projection of the front via structure along the first direction falls within the projection of the front power rail 38 along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail 32 along the first direction.

[0131] It can be understood that the front power rail 38 and the back power rail 32 can be arranged in only one direction, thereby reducing the complexity of manufacturing the power rail. Further, since the first source-drain metal 115 can be extended below the front power rail 38 in the second direction by the first source-drain structure 112, the projection of the front via structure connecting the first source-drain metal 115 along the first direction can fall within the projection of the front power rail 38 along the first direction, which indicates that the connection between the front via structure and the front power rail 38 can be achieved by only increasing the area of the first source-drain metal 115, without increasing the area of the front transistor 11, thereby ensuring the integration performance of the stacked transistor. Similarly, the projection of the back via structure along the first direction falls within the projection of the back power rail 32 along the first direction, which can also ensure the integration performance of the stacked transistor.

[0132] In some embodiments, the front via structure includes a front source-drain via structure 36 and a front gate via structure 37; the front power rail 38 is in communication with the first source-drain metal 115 through the front source-drain via structure 36, and the front power rail 38 is in communication with the second gate structure 124 through the front gate via structure 37.

[0133] In some embodiments, the back via structure includes a back source-drain via structure 30 and a back gate via structure 31; the back power rail 32 is in communication with the second source-drain metal 125 through the back source-drain via structure 30, and the back power rail 32 is in communication with the first gate structure 114 through the back gate via structure 31.

[0134] In the embodiments of the present application, the front power rail 38 and the back power rail 32 adopt an interleaved design, so that the internal interconnection line of the decoupling capacitor formed by the stacked transistor (including one NMOS and one PMOS) can be achieved by only using the source-drain via structure (including the front source-drain via structure 36 and the back source-drain via structure 30) and the gate via structure (including the front gate via structure 37 and the back gate via structure 31), without the help of a complex back-end metal line (such as an M0 metal line).

[0135] Based on this, the embodiments of the present application can make the internal interconnection line of the decoupling capacitor not need the help of a complex back-end metal line, and the stacked transistor can be completed within 2 contact pitch (CPP), without wasting additional area.

[0136] In one or more embodiments of the above preparation of the stacked transistor, the stacked transistor also has self-alignment, which on one hand solves the long-standing problems of process complexity and alignment difficulty existing in the current mainstream technical solutions of the stacked transistor, and realizes the industrialization of the stacked transistor technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are connected through the interconnection of the stacked transistor. Without changing the design of the 4T track unit of the extreme miniaturization, the metal wiring resources are greatly released.

[0137] Finally, the scheme of the upper and lower transistors realized by the flip chip is compatible with the existing mainstream device architecture, and can realize front-back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs) without special process development for specific device architectures. It has strong flexibility and strong extendability from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and is practical, and has a wide development prospect.

[0138] In a third aspect, the embodiments of the present application provide a semiconductor device, comprising: the stacked transistor as described above. The specific limitations of the stacked transistor can be at least referred to the structure shown in the above Figure 18 , and will not be repeated here.

[0139] In a fourth aspect, the embodiments of the present application provide an electronic device, comprising: a circuit board and a semiconductor device as described above, the semiconductor device being arranged on the circuit board. The semiconductor device comprises the stacked transistor described above. The specific limitations of the stacked transistor can be at least referred to the structure shown in the above Figure 18 , and will not be repeated here.

[0140] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, the skilled in the art can combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0141] The above merely provides preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A method of fabricating a stack of transistors, comprising: The method comprises: forming a fin structure on a semiconductor substrate, wherein the fin structure comprises a first fin structure and a second fin structure stacked along a first direction; forming a first source-drain structure, a first gate structure and a first source-drain metal in sequence based on the first fin structure, wherein the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther away from the second fin structure than the first source-drain structure; forming a second source-drain structure, a second gate structure and a second source-drain metal in sequence based on the second fin structure, wherein the second source-drain structure and the first source-drain structure are stacked along the first direction, the second gate structure and the first gate structure are stacked along the first direction; the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther away from the first fin structure than the second source-drain structure; forming a backside via structure and a backside power rail on the second gate structure and the second source-drain metal to obtain a backside transistor, wherein the backside power rail is in communication with the second source-drain metal and the first gate structure through the backside via structure respectively; forming a frontside via structure and a frontside power rail on the first gate structure and the first source-drain metal to obtain a frontside transistor, wherein the frontside power rail is in communication with the first source-drain metal and the second gate structure through the frontside via structure respectively; the frontside power rail is located at a first side of the fin structure in a second direction, the backside power rail is located at a second side of the fin structure in the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

2. The production method according to claim 1, characterized by, The method of forming a second source-drain structure, a second gate structure and a second source-drain metal in sequence based on the second fin structure comprises: forming the second source-drain structure and the second gate structure in sequence based on the second fin structure; removing a first part of the second gate structure and retaining a second part of the second gate structure to form a backside trench, and depositing an insulating material in the backside trench to form a backside isolation structure; wherein the first part of the second gate structure and the second part of the second gate structure are arranged along the second direction; forming a second source-drain metal on the second source-drain structure; The method of forming a backside via structure and a backside power rail on the second gate structure and the second source-drain metal comprises: forming a backside dielectric layer on the backside isolation structure, the second gate structure and the second source-drain metal; etching the backside dielectric layer until the second source-drain metal is exposed to form a backside source-drain metal via, and etching the backside dielectric layer and the backside isolation structure until the first gate structure is exposed to form a backside gate metal via; depositing a metal in the backside source-drain metal via and the backside gate metal via to form a backside source-drain via structure and a backside gate via structure respectively; wherein the backside source-drain via structure and the backside gate via structure are included in the backside via structure. forming the backside power rail on the backside dielectric layer, wherein the backside power rail is in communication with the second source / drain metal through the backside source / drain via structure, and the backside power rail is in communication with the first gate structure through the backside gate via structure.

3. The production method according to claim 2, characterized by, forming, based on the first fin structure, a first source / drain structure, a first gate structure, and a first source / drain metal in sequence, comprises: forming, based on the first fin structure, the first source / drain structure and the first gate structure in sequence; removing a first portion of the first gate structure and retaining a second portion of the first gate structure to form a frontside trench, and depositing an insulating material in the frontside trench to form a frontside isolation structure; wherein the first portion of the first gate structure and the second portion of the second gate structure are arranged along the second direction; the frontside isolation structure is located on a first side of the fin structure, and the backside isolation structure is located on a second side of the fin structure; forming the first source / drain metal on the first source / drain structure.

4. The production method according to claim 3, characterized by, forming, on the first gate structure and the first source / drain metal, a frontside via structure and a frontside power rail, comprises: forming a frontside dielectric layer on the frontside isolation structure, the first gate structure, and the first source / drain metal; etching the frontside dielectric layer until the first source / drain metal is exposed to form a frontside source / drain metal via, and etching the frontside dielectric layer and the frontside isolation structure until the second gate structure is exposed to form a frontside gate metal via; depositing metal in the frontside source / drain metal via and the frontside gate metal via to form a frontside source / drain via structure and a frontside gate via structure, respectively; wherein the frontside source / drain via structure and the frontside gate via structure are included in the frontside via structure; forming a frontside power rail on the frontside dielectric layer, wherein the frontside power rail is in communication with the first source / drain metal through the frontside source / drain via structure, and the frontside power rail is in communication with the second gate structure through the frontside gate via structure.

5. The preparation method according to claim 1, characterized in that, after forming, on the second gate structure and the second source / drain metal, a backside via structure and a backside power rail, the method further comprises: forming a backside insulating layer on the backside metal interconnection layer; bonding a backside carrier wafer to the backside insulating layer, and flipping the bonded backside carrier wafer; before forming, on the first gate structure and the first source / drain metal, a frontside via structure and a frontside power rail, the method further comprises: removing the backside carrier wafer and the backside insulating layer to expose the first gate structure and the first source / drain metal.

6. The method of claim 1, wherein, the extension direction of the frontside power rail and the backside power rail is a third direction, the third direction is perpendicular to the first direction and the second direction; a projection of the frontside via structure along the first direction falls within a projection of the frontside power rail along the first direction; a projection of the backside via structure along the first direction falls within a projection of the backside power rail along the first direction.

7. A stacked transistor, comprising: comprises: A front transistor comprising: a first source-drain structure, a first gate structure, a first source-drain metal, and a front metal interconnection layer; A back transistor comprising: a second source-drain structure, a second gate structure, a second source-drain metal, and a back metal interconnection layer; the front transistor and the back transistor are arranged in a stack along a first direction; The front metal interconnection layer comprises a front power rail and a front via structure, the front power rail is in communication with the first source-drain metal and the second gate structure through the front via structure respectively; the back metal interconnection layer comprises a back power rail and a back via structure, the back power rail is in communication with the second source-drain metal and the first gate structure through the back via structure respectively; the front power rail is located at a first side of a fin structure along a second direction, the back power rail is located at a second side of the fin structure along the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

8. The stacked transistor of claim 7, wherein, The extension direction of the front power rail and the back power rail is a third direction, and the third direction is perpendicular to the first direction and the second direction; The projection of the front via structure along the first direction falls within the projection of the front power rail along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail along the first direction.

9. The stacked transistor of claim 8, wherein: The front via structure comprises: a front source-drain via structure and a front gate via structure; the front power rail is in communication with the first source-drain metal through the front source-drain via structure, and the front power rail is in communication with the second gate structure through the front gate via structure; The back via structure comprises: a back source-drain via structure and a back gate via structure; the back power rail is in communication with the second source-drain metal through the back source-drain via structure, and the back power rail is in communication with the first gate structure through the back gate via structure.

10. A semiconductor device, characterized by comprising: The stacked transistor of any one of claims 7 to 9. The stacked transistor of any one of claims 7 to 9.

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