Method for improving utilization rate of mask in image sensor manufacturing process

Abstract

The invention discloses a method for improving the utilization rate of a mask in an image sensor manufacturing process. The method comprises the following steps: providing a substrate; forming a dielectric layer with a height difference on the substrate; forming an anti-reflection layer and a photoresist layer on the dielectric layer; through exposure and development, forming corresponding patterned photoresist layers in a plurality of areas of the substrate; through etching, structures corresponding to a plurality of areas of the substrate are formed, so that the utilization rate of the mask is improved. According to the invention, on the basis of the dielectric layer with the height difference, required structures can be formed in a plurality of areas of the substrate only by illuminating the mask once, so that the utilization rate of the mask is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving the utilization rate of a mask in the manufacturing process of an image sensor. Background Art

[0002] In the manufacturing process of an image sensor, polysilicon with different thicknesses is usually deposited in the pixel region and the peripheral logic region of the image sensor to arrange different devices.

[0003] In the prior art, the pixel region and the peripheral logic region are generally etched separately through at least two light exposure masks to form polysilicon with different thicknesses in these two regions respectively; it can be seen that the utilization rate of the light exposure mask in the prior art is low. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for improving the utilization rate of a mask in the manufacturing process of an image sensor. Based on a dielectric layer with a height difference, the required structures can be formed in multiple regions of the substrate only through one light exposure mask, thereby effectively improving the utilization rate of the mask.

[0005] To achieve the above purpose, the present invention is realized through the following technical solutions:

[0006] A method for improving the utilization rate of a mask in the manufacturing process of an image sensor, comprising:

[0007] Providing a substrate;

[0008] Forming a dielectric layer with a height difference on the substrate;

[0009] Forming an anti-reflection layer and a photoresist layer on the dielectric layer;

[0010] Through exposure and development, forming a corresponding patterned photoresist layer in multiple regions of the substrate;

[0011] Through etching, forming structures corresponding to multiple regions of the substrate, thereby improving the utilization rate of the mask.

[0012] Optionally, the step of forming a dielectric layer with a height difference on the substrate includes:

[0013] Forming a patterned hard mask layer on the substrate;

[0014] Etching the substrate to form island-like structures arranged in an array in the pixel region of the image sensor and first trenches communicating with each other therebetween, and forming second trenches in the peripheral logic region of the image sensor; and at least part of the upper part of the island-like structures is connected to the upper part of the adjacent island-like structures through a cantilever structure;

[0015] Form an epitaxial layer on the surfaces of the first trench and the second trench through at least one epitaxial process;

[0016] Form an oxide layer on the surface of the epitaxial layer, and deposit polysilicon to fill the first trench and the second trench;

[0017] Etch the polysilicon to the patterned hard mask layer;

[0018] Deposit a first dielectric layer on the substrate, thereby forming the dielectric layer with a height difference.

[0019] Optionally, the step of etching the substrate to form an array of island structures in the pixel region of the image sensor and a first trench communicating therebetween, and a second trench in the peripheral logic region of the image sensor includes:

[0020] Etch the substrate to form a third trench according to the patterned hard mask layer;

[0021] Form a dielectric protection layer on the surface of the third trench;

[0022] Continue to etch the bottom of the dielectric protection layer and the substrate to form the second trench in the peripheral logic region; and by adjusting the etching process conditions, form the island structures in the pixel region, protect the upper parts of the island structures from being etched through the dielectric protection layer, form the first trench for interconnecting the lower parts of the island structures, and form the cantilever structure.

[0023] Optionally, the dielectric layer with a height difference includes a low part and a high part, and corresponding low parts are formed in the non-cantilever structure regions corresponding to the first trenches between the island structures and the regions corresponding to the second trenches in the peripheral logic region that need to be connected to a negative voltage, and corresponding high parts are formed in the regions corresponding to the cantilever structures and the regions of the substrate where no trenches are provided.

[0024] Optionally, the antireflection layer includes a first antireflection layer formed on the low part and a second antireflection layer formed on the first antireflection layer and the high part.

[0025] Optionally, the multiple regions of the substrate at least include: the region corresponding to the cantilever structure and the region corresponding to the second trench in the peripheral logic region that needs to be connected to a negative voltage.

[0026] Optionally, the step of forming a corresponding patterned photoresist layer in multiple regions of the substrate through exposure and development includes:

[0027] Through exposure and development, corresponding photoresist patterns are formed in the area corresponding to the suspension beam structure, the non-suspension beam structure area corresponding to the first trench between the island structures, and the area that needs to be connected to a negative voltage corresponding to the second trench in the peripheral logic area;

[0028] Remove the photoresist pattern in the non-suspension beam structure area corresponding to the first trench between the island structures, thereby forming the patterned photoresist layer.

[0029] Optionally, the patterned photoresist layer includes a first photoresist portion corresponding to the suspension beam structure and a second photoresist portion corresponding to the second trench; the first photoresist portion has a first line width, the second photoresist portion has a second line width, and the second line width is greater than the first line width.

[0030] Optionally, the step of forming the structures corresponding to multiple regions of the substrate by etching includes:

[0031] By etching, expose the polysilicon in the first trench and the second trench; and the upper surface of the polysilicon in the first trench is lower than the upper surface of the substrate, and the upper surface of the polysilicon in the second trench is higher than the upper surface of the polysilicon in the first trench;

[0032] Use the suspension beam structure to form a transistor;

[0033] Apply a negative voltage to the polysilicon in the second trench.

[0034] Optionally, the step of exposing the polysilicon in the first trench by etching includes:

[0035] Using the patterned photoresist layer as a mask, remove the exposed second anti-reflection layer;

[0036] Using the patterned photoresist layer and the first anti-reflection layer as a mask, etch the dielectric layer to a first target position;

[0037] Using the patterned photoresist layer as a mask, remove the exposed first anti-reflection layer;

[0038] Remove the patterned photoresist layer and the second anti-reflection layer located below the patterned photoresist layer;

[0039] Using the remaining first anti-reflection layer as a mask, etch the dielectric layer to a second target position to expose the polysilicon in the first trench;

[0040] Remove the second anti-reflection layer, and continue to etch the dielectric layer and the polysilicon in the first trench to expose the polysilicon in the second trench, and make the upper surface of the polysilicon in the second trench higher than the upper surface of the polysilicon in the first trench, and make the upper surface of the polysilicon in the first trench lower than the upper surface of the substrate.

[0041] On the other hand, the present invention also provides an image sensor manufactured by the method described above.

[0042] The present invention has at least one of the following advantages compared with the prior art:

[0043] The present invention provides a method for improving the utilization rate of a mask in the manufacturing process of an image sensor. A dielectric layer with a height difference is formed on a substrate; then an anti-reflection layer and a photoresist layer are formed on the dielectric layer; then through exposure and development, corresponding patterned photoresist layers are formed in multiple regions of the substrate; subsequently, through etching, corresponding structures in multiple regions of the substrate are formed. Based on the dielectric layer with a height difference, the present invention can form the required structures (such as depositing polysilicon with different thicknesses in pixel regions and peripheral logic regions) in multiple regions of the substrate only through the patterned photoresist layer (i.e., one-time light exposure mask), which can effectively improve the utilization rate of the mask.

[0044] The patterned photoresist layer in the present invention includes a first photoresist portion corresponding to the cantilever structure and a second photoresist portion corresponding to the second trench; and the second line width of the second photoresist portion is greater than the first line width of the first photoresist portion, so that in the subsequent etching process, the etching degrees of the region corresponding to the cantilever structure and the region corresponding to the second trench that needs to be connected with a negative voltage are different under the same etching conditions, further ensuring that the required structures can be formed in multiple regions of the substrate only through the patterned photoresist layer and the dielectric layer with a height difference. Description of the Drawings

[0045] Figure 1 is a flowchart of a method for improving the utilization rate of a mask in the manufacturing process of an image sensor provided by an embodiment of the present invention;

[0046] Figures 2 to 11 is a cross-sectional view taken along the A-A direction in the process of a method for improving the utilization rate of a mask in the manufacturing process of an image sensor provided by an embodiment of the present invention as Figure 12 shown in;

[0047] Figure 12 is a top view in the process of a method for improving the utilization rate of a mask in the manufacturing process of an image sensor provided by an embodiment of the present invention. Detailed Embodiments

[0048] The following further elaborates in detail on an etching method based on a light mask proposed by the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and all use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. In order to make the purpose, features, and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be noted that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have any technical substance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the efficacy that the present invention can produce and the purpose that can be achieved, should still fall within the scope that the technical content disclosed by the present invention can cover.

[0049] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or also includes elements inherent to such a process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

[0050] Combined with the attached Figures 1 to 12 As shown, this embodiment provides a method for improving the utilization rate of a mask in the manufacturing process of an image sensor, including: Step S1, providing a substrate 100; Step S2, forming a dielectric layer 200 with a height difference on the substrate 100; Step S3, forming an anti-reflection layer 300 and a photoresist layer on the dielectric layer 200; Step S4, through exposure and development, forming corresponding patterned photoresist layers 400 in multiple regions of the substrate 100; Step S5, through etching, forming structures corresponding to multiple regions of the substrate 100, thereby improving the utilization rate of the mask.

[0051] Specifically, when preparing the image sensor based on the substrate 100, the substrate 100 can be divided into a pixel region and a peripheral logic region. Transistors for converting optical signals into electrical signals can be arranged in the pixel region, and a circuit for supplying power to the transistors can be arranged in the peripheral logic region. When a negative voltage is applied to the peripheral logic region, the circuit supplies power to the transistors. More specifically, in this embodiment, based on the dielectric layer 200 with a height difference, the desired structures (such as depositing polysilicon with different thicknesses in the pixel region and the peripheral logic region) can be formed in multiple regions of the substrate 100 only through the patterned photoresist layer 400 (i.e., a single exposure mask), thereby effectively improving the utilization rate of the mask.

[0052] In one embodiment, the substrate 100 includes a first substrate 1001 and a second substrate 1002 located on the first substrate 1001. Optionally, the first substrate 1001 doped with P-type and the second substrate 1002 doped with N-type are generally selected to form the substrate 100, but the present invention is not limited thereto.

[0053] Please also refer to Figures 1 to 5 , the step S2 includes: Step S21, forming a patterned hard mask layer 110 on the substrate 100; Step S22, etching the substrate 100 according to the patterned hard mask layer 100 to form an array of island-like structures 120 in the pixel region of the image sensor and form a first trench 101 communicating with each other between at least some of the island-like structures 120, and form a second trench 102 in the peripheral logic region of the image sensor; and at least some of the upper parts of the island-like structures 120 in the pixel region are connected to the upper parts of the adjacent island-like structures 120 through a cantilever structure 103 to prevent lattice mismatch between the island-like structures 120 in subsequent processes; Step S23, forming an epitaxial layer 107 on the surfaces of the first trench 101 and the second trench 102 through at least one epitaxial process, as Figure 3 shown; Step S24, forming an oxide layer 108 on the surface of the epitaxial layer 107 and depositing polysilicon 109 to fill the first trench 101 and the second trench 102; Step S25, etching the polysilicon 109 to the patterned hard mask layer 110; Step S26, depositing a first dielectric layer on the substrate 100 to form a dielectric layer 200 with a height difference.

[0054] Specifically, in one embodiment, in step S21, the patterned hard mask layer 110 may include a patterned first silicon nitride layer 1101 and a patterned first silicon oxide layer 1102; wherein the patterned first silicon nitride layer 1101 is formed on the second substrate 1002, and the patterned first silicon oxide layer 1102 is formed on the patterned first silicon nitride layer 1101.

[0055] Specifically, in one embodiment, step S22 includes: step S221, etching the substrate 100 to form a third trench 104 according to the patterned hard mask layer 110, as Figure 2 shown; step S222, forming a dielectric protection layer 105 on the surface of the third trench 104, as Figure 2 shown; step S223, continuously etching the bottom of the dielectric protection layer 105 and the substrate 100 to form the second trench 102 in the peripheral logic region; and by adjusting the etching process conditions (including etching direction, etching time, etc.), forming the island structure 120 in the pixel region, protecting the upper part of the island structure 120 from being etched by the dielectric protection layer 104, forming the first trench 101 that connects the lower parts of the island structures 120 to each other, and forming the cantilever structure 103, as Figure 3 shown. More specifically, when forming the cantilever structure 103, the substrate 100 may be etched first to form the island structure 120 and a connection structure (not shown in the figure) located between the island structures 120. At this time, the trenches on both sides of the connection structure are not connected to each other; then, through isotropic lateral etching, the widths of the trenches on both sides of the connection structure are increased, that is, the bottom or middle of the trench is widened so that the bottoms of the trenches on both sides of the connection structure are connected to each other, thereby making the connection structure suspended. At this time, the suspended connection structure is the cantilever structure 103, and the trenches connected on both sides of the connection structure are the first trench 101, but the present invention is not limited thereto.

[0056] In some embodiments, in step S223, while forming the second trench 102 in the peripheral logic region, a fourth trench 106 having a structure similar to that of the second trench 102 may also be formed in a partial region of the pixel region, as Figure 3 shown. In addition, after forming the first trench 101, the second trench 102, the cantilever structure 103, and the fourth trench 106 through step S22, the corresponding dielectric protection layer 105 needs to be removed, but the present invention is not limited thereto.

[0057] Specifically, in one embodiment, step S23 further includes forming the epitaxial layer 107 on the surface of the fourth trench 106, as Figure 3As shown; in the step S24, polysilicon 109 is further filled into the fourth trench 106 to above the hard mask layer 110, as Figure 3 shown.

[0058] More specifically, in the step S24, after filling polysilicon 109 into the corresponding trench to above the hard mask layer 110, the polysilicon in the non-cantilever structure region corresponding to the first trench 101, the region corresponding to the second trench 102, and the region corresponding to the fourth trench 106 will naturally collapse to a certain extent to form a recess 111, as Figure 4 shown. In the step S25, the polysilicon 109 can be etched to the patterned first silicon oxide layer 1102, and at this time the recess 111 still exists and moves downward, as Figure 5 shown. In the step S26, the deposited first dielectric layer may include a second silicon nitride layer (not shown in the figure) formed on the substrate 100 and the polysilicon 109 and a second silicon oxide layer (not shown in the figure) formed on the second silicon nitride layer; due to the existence of the recess 111, both the second silicon nitride layer and the second silicon oxide layer have a height difference, and at this time the second silicon nitride layer with a height difference and the second silicon oxide layer with a height difference constitute the dielectric layer 200 with a height difference.

[0059] Furthermore, it can be seen from the above that the dielectric layer 200 with a height difference includes a low position part 2001 and a high position part 2002, and the corresponding low position part 2001 is formed in the non-cantilever structure region corresponding to the first trench 101 between the island structures 120 and the region corresponding to the second trench 102 in the peripheral logic region that needs to be connected with a negative voltage (i.e., the region corresponding to the recess 111), and the corresponding high position part 2002 is formed in the region corresponding to the cantilever structure 103 and the region of the substrate 100 where no trench is provided. In addition, the corresponding low position part 2001 can also be formed in the region corresponding to the fourth trench 106, but the present invention is not limited thereto.

[0060] Specifically, in one embodiment, as Figure 5As shown, in step S3, first, the anti-reflection layer 300 is formed on the dielectric layer 200, and the upper surface of the anti-reflection layer 300 is a flat surface, that is, after the anti-reflection layer 300 fills the low portion 2001, it has a first preset thickness; then, the photoresist layer is formed on the anti-reflection layer 300, and the photoresist layer has a second preset thickness. More specifically, the anti-reflection layer 300 includes a first anti-reflection layer 3001 formed on the low portion 2001 and a second anti-reflection layer 3002 formed on the first anti-reflection layer 3001 and the high portion 2002, and the upper surface of the second anti-reflection layer 3002 is the upper surface of the anti-reflection layer 300, and the thickness of the second anti-reflection layer 3002 is the first preset thickness. Optionally, the first preset thickness is 600 Å to 700 Å; preferably, the first preset thickness is 650 Å. Optionally, the second preset thickness is 4000 Å to 5000 Å; preferably, the second preset thickness is 4900 Å, but the present invention is not limited thereto.

[0061] Please continue to refer to Figure 1 and Figure 5 , multiple regions of the substrate 100 at least include: the region corresponding to the cantilever structure 103, and the region corresponding to the second trench 102 in the peripheral logic region that needs to be connected to a negative voltage.

[0062] It can be understood that step S4 includes: step S41, through exposure and development, corresponding photoresist patterns are formed in the region corresponding to the cantilever structure 103, the non-cantilever structure region corresponding to the first trench 101 between the island structures 120, and the region corresponding to the second trench 102 in the peripheral logic region that needs to be connected to a negative voltage; step S42, removing the photoresist pattern in the non-cantilever structure region corresponding to the first trench 101 between the island structures 120, so as to form the patterned photoresist layer 400.

[0063] Specifically, in one embodiment, as Figure 5 shown, the patterned photoresist layer 400 includes a first photoresist portion 4001 corresponding to the cantilever structure 103 and a second photoresist portion 4002 corresponding to the second trench 102; the first photoresist portion 4001 has a first line width, the second photoresist portion 4002 has a second line width, and the second line width is greater than the first line width, so that in the subsequent etching process, the etching degrees of the region corresponding to the cantilever structure 103 and the region corresponding to the second trench 102 that needs to be connected to a negative voltage are different under the same etching conditions, further ensuring that the required structures can be formed in multiple regions of the substrate 100 only through the patterned photoresist layer 400 and the dielectric layer 200 with a height difference, thereby effectively improving the utilization rate of the mask, but the present invention is not limited thereto.

[0064] Please also refer to Figures 6 to 11 wherein the step S5 includes: step S51, exposing the polysilicon in the first trench 101 and the second trench 102 through etching; and the upper surface of the polysilicon in the first trench 101 is lower than the upper surface of the substrate 100, and the upper surface of the polysilicon in the second trench 102 is higher than the upper surface of the polysilicon in the first trench 101; step S52, using the cantilever structure 103 to form a transistor; step S53, applying a negative voltage to the polysilicon in the second trench of the peripheral logic region.

[0065] Specifically, in one embodiment, the step S51 includes: step S511, using the patterned photoresist layer 400 as a mask to remove the exposed second anti-reflection layer 3002, as Figure 6 shown; step S512, using the patterned photoresist layer 400 and the first anti-reflection layer 3001 as masks to etch the dielectric layer 200 to a first target position, as Figure 7 shown; and the first target position does not expose the hard mask layer 100; step S513, continuing to use the patterned photoresist layer 400 as a mask to remove the exposed first anti-reflection layer 3001, as Figure 8 shown; step S514, removing the patterned photoresist layer 400 and the second anti-reflection layer 3002 located below the patterned photoresist layer 400, as Figure 9 shown; step S515, using the remaining first anti-reflection layer 3001 as a mask to etch the dielectric layer 200 to a second target position to expose the polysilicon in the first trench 101, as Figure 10 shown; step S516, removing the remaining first anti-reflection layer 3001 and continuing to etch the dielectric layer 200 and the polysilicon in the first trench 101 to expose the polysilicon in the second trench 102, and making the upper surface of the polysilicon in the second trench 102 higher than the upper surface of the polysilicon in the first trench 101, and making the upper surface of the polysilicon in the first trench 101 lower than the upper surface of the substrate 100, as Figure 11 shown.

[0066] Specifically, in one embodiment, in the step S511, the exposed second anti-reflection layer 3002 includes the non-cantilever structure region corresponding to the first trench between the island structures, the region corresponding to the fourth trench 106, and the second anti-reflection layer 3002 above the region of the substrate 100 without trenches, as Figure 5 shown.

[0067] In the step S513, the exposed first anti-reflection layer 3001 includes a non-suspension beam structure area corresponding to a first trench between the island structures, and a second anti-reflection layer 3002 above the area corresponding to the fourth trench 106, as Figure 6 shown.

[0068] In the step S514, since the second line width corresponding to the second photoresist portion 4002 is greater than the first line width corresponding to the first photoresist portion 4001, when removing the patterned photoresist layer 400 and the second anti-reflection layer 3002 located below the patterned photoresist layer 400, it can be ensured that the first anti-reflection layer 3001 below the second photoresist portion 4002 (i.e., above the area corresponding to the second trench 102) is not removed, thereby providing a necessary condition for the polysilicon in the second trench 102 and the polysilicon in the first trench 101 to have different thicknesses, as Figure 8 shown.

[0069] In the step S515, the remaining first anti-reflection layer 3001 includes the first anti-reflection layer 3001 above the area corresponding to the second trench 102, and the dielectric layer 200 can be etched to the second target position by using a self-aligned etching technique, and the second target position exposes the polysilicon in the first trench 101, as Figure 9 shown.

[0070] In the step S516, the upper surface of the polysilicon in the second trench 102 is higher than the upper surface of the polysilicon in the first trench 101, so that the polysilicon in the second trench 102 and the polysilicon in the first trench 101 have different thicknesses, as Figure 11 shown.

[0071] On the other hand, this embodiment also provides an image sensor prepared by using the method described above.

[0072] In summary, this embodiment provides a method for improving the utilization rate of a mask in the manufacturing process of an image sensor. A dielectric layer with a height difference is formed on a substrate; then an anti-reflection layer and a photoresist layer are formed on the dielectric layer; then, through exposure and development, a corresponding patterned photoresist layer is formed in multiple regions of the substrate; subsequently, through etching, structures corresponding to multiple regions of the substrate are formed. Based on the dielectric layer with a height difference, the present invention can form the required structures (such as depositing polysilicon with different thicknesses in pixel regions and peripheral logic regions) in multiple regions of the substrate only through the patterned photoresist layer (i.e., one-time light exposure mask), which can effectively improve the utilization rate of the mask. In this embodiment, the patterned photoresist layer includes a first photoresist portion corresponding to the cantilever structure and a second photoresist portion corresponding to the second trench; and the second line width of the second photoresist portion is greater than the first line width of the first photoresist portion, so that in the subsequent etching process, under the same etching conditions, the etching degrees of the region corresponding to the cantilever structure and the region corresponding to the second trench that needs to be connected with a negative voltage are different, further ensuring that the required structures can be formed in multiple regions of the substrate only through the patterned photoresist layer and the dielectric layer with a height difference.

[0073] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and substitutions to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method for improving the utilization rate of a mask plate in the manufacturing process of an image sensor, characterized in that, it includes: providing a substrate; forming a dielectric layer with a height difference on the substrate; forming an anti-reflection layer and a photoresist layer on the dielectric layer; forming corresponding patterned photoresist layers in multiple regions of the substrate through exposure and development; forming corresponding structures in multiple regions of the substrate through etching, thereby improving the utilization rate of the mask plate.

2. The method according to claim 1, characterized in that, the step of forming a dielectric layer with a height difference on the substrate includes: forming a patterned hard mask layer on the substrate; etching the substrate to form an array of island structures in the pixel region of the image sensor and a first trench communicating with each other therebetween, and forming a second trench in the peripheral logic region of the image sensor; and at least part of the upper part of the island structure is connected to the upper part of the adjacent island structure through a cantilever structure; forming an epitaxial layer on the surfaces of the first trench and the second trench through at least one epitaxial process; forming an oxide layer on the surface of the epitaxial layer and depositing polysilicon to fill the first trench and the second trench; etching the polysilicon to the patterned hard mask layer; depositing a first dielectric layer on the substrate, thereby forming the dielectric layer with a height difference.

3. The method according to claim 2, characterized in that, the step of etching the substrate to form an array of island structures in the pixel region of the image sensor and a first trench communicating with each other therebetween, and forming a second trench in the peripheral logic region of the image sensor includes: etching the substrate to form a third trench according to the patterned hard mask layer; forming a dielectric protection layer on the surface of the third trench; continuing to etch the bottom of the dielectric protection layer and the substrate to form the second trench in the peripheral logic region; and by adjusting the etching process conditions, forming the island structures in the pixel region, protecting the upper parts of the island structures from being etched through the dielectric protection layer, forming the first trench for connecting the lower parts of the island structures, and forming the cantilever structure.

4. The method according to claim 2, characterized in that, the dielectric layer with a height difference includes a low part and a high part, and corresponding low parts are formed in the non-cantilever structure regions corresponding to the first trenches between the island structures and the regions corresponding to the second trenches in the peripheral logic region that need to be connected to a negative voltage, and corresponding high parts are formed in the regions corresponding to the cantilever structures and the regions of the substrate where no trenches are provided.

5. The method according to claim 4, characterized in that, the anti-reflection layer includes a first anti-reflection layer formed on the low part and a second anti-reflection layer formed on the first anti-reflection layer and the high part.

6. The method according to claim 5, characterized in that, multiple regions of the substrate at least include: the regions corresponding to the cantilever structures and the regions corresponding to the second trenches in the peripheral logic region that need to be connected to a negative voltage.

7. The method according to claim 6, characterized in that, The step of forming corresponding patterned photoresist layers in multiple regions of the substrate through exposure and development includes: Through exposure and development, forming corresponding photoresist patterns in the regions corresponding to the cantilever structure, the non-cantilever structure regions corresponding to the first trenches between the island structures, and the regions that need to be connected to a negative voltage corresponding to the second trenches in the peripheral logic region; Removing the photoresist patterns in the non-cantilever structure regions corresponding to the first trenches between the island structures, thereby forming the patterned photoresist layers.

8. The method according to claim 7, wherein, the patterned photoresist layers include a first photoresist portion corresponding to the cantilever structure and a second photoresist portion corresponding to the second trenches; the first photoresist portion has a first line width, the second photoresist portion has a second line width, and the second line width is greater than the first line width.

9. The method according to claim 7, wherein, the step of forming the structures corresponding to multiple regions of the substrate through etching includes: Through etching, exposing the polysilicon in the first trenches and the second trenches; and the upper surface of the polysilicon in the first trenches is lower than the upper surface of the substrate, and the upper surface of the polysilicon in the second trenches is higher than the upper surface of the polysilicon in the first trenches; Using the cantilever structure to form a transistor; Applying a negative voltage to the polysilicon in the second trenches.

10. The method according to claim 9, wherein, the step of exposing the polysilicon in the first trenches through etching includes: Using the patterned photoresist layers as a mask to remove the exposed second anti-reflection layer; Using the patterned photoresist layers and the first anti-reflection layer as a mask to etch the dielectric layer to a first target position; Using the patterned photoresist layers as a mask to remove the exposed first anti-reflection layer; Removing the patterned photoresist layers and the second anti-reflection layer located under the patterned photoresist layers; Using the remaining first anti-reflection layer as a mask to etch the dielectric layer to a second target position to expose the polysilicon in the first trenches; Removing the second anti-reflection layer and continuing to etch the dielectric layer and the polysilicon in the first trenches to expose the polysilicon in the second trenches, and making the upper surface of the polysilicon in the second trenches higher than the upper surface of the polysilicon in the first trenches, and making the upper surface of the polysilicon in the first trenches lower than the upper surface of the substrate.

11. An image sensor is prepared by using the method according to any one of claims 1 to 10.

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