Substrate for semiconductor device

Abstract

A substrate for a semiconductor device according to the present invention is provided with: a silicon nitride ceramic substrate having a first surface and a second surface; a brazing filler metal layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, the copper plate having a region in which the hardness decreases in the thickness direction of the copper plate from the interface between the bonding layer and the copper plate.

Description

Technical Field

[0001] The present invention relates to a substrate for a semiconductor device. Background Art

[0002] As a substrate for a semiconductor device such as a power transistor module, a substrate having a copper plate on the surface of a silicon nitride ceramic substrate via an adhesive is known (for example, Patent Document 1).

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Unexamined Patent Application Publication No. 2022-173209 Summary of the Invention Technical Problem to be Solved by the Invention However, in a substrate for a semiconductor device, durability in thermal cycling has become an issue, and there has been a long-felt need for a substrate for a semiconductor device that can suppress copper plate peeling even in the above-described environment. The present invention has been completed to solve this problem, and an object thereof is to provide a substrate for a semiconductor device that can suppress copper plate peeling even under thermal cycling.

[0004] Technical Solution for Solving the Technical Problem Item 1. A substrate for a semiconductor device, comprising: A ceramic substrate having a first surface and a second surface; A solder layer disposed on the first surface and the second surface; and A copper plate disposed on the bonding layer, wherein the thickness of the copper plate is 0.3 mm or more, and the copper plate has a region where the hardness decreases along the thickness direction of the copper plate between the interface between the bonding layer and the copper plate and a position 100 μm away from the interface along the thickness direction.

[0005] Item 2. The substrate for a semiconductor device according to Item 1, wherein at least one of the copper plates is patterned.

[0006] Item 3. The substrate for a semiconductor device according to Item 1 or 2, wherein in the copper plate, the nanoindentation hardness at a first position 10 μm away from the interface along the thickness direction is 1.2 GPa to 2.3 GPa, and the nanoindentation hardness at a position further away from the interface than the first position is lower than the nanoindentation hardness at the first position.

[0007] Item 4. The substrate for a semiconductor device according to any one of Items 1 to 3, wherein in the copper plate, the nanoindentation hardness at a second position 30 μm away from the interface along the thickness direction is 0.7 GPa to 1.3 GPa, The nanoindentation hardness at a position away from the interface by more than the above-described second position is lower than the nanoindentation hardness at the above-described second position.

[0008] Item 5. The substrate for a semiconductor device according to any one of Items 1 to 4, wherein in the above-described copper plate, the nanoindentation hardness at a third position 100 μm away from the interface in the above-described thickness direction is 0.5 GPa to 1.1 GPa. The nanoindentation hardness at a position more away from the interface than the above-described third position is lower than the nanoindentation hardness at the above-described third position.

[0009] Advantages of the Invention According to the substrate for a semiconductor device of the present invention, a bonding substrate with high thermal cycling durability can be obtained, and peeling of the copper plate caused by temperature changes can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. is a cross-sectional view showing an embodiment of a semiconductor device having the substrate for a semiconductor device of the present invention.

[0011] Figure 2 FIG. is a cross-sectional view showing the interface between the copper plate and the bonding layer.

[0012] Figure 3 FIG. is a flowchart showing a method for manufacturing a substrate for a semiconductor device.

[0013] Figure 4 FIG. is a cross-sectional view showing a manufacturing process of a substrate for a semiconductor device.

[0014] Figure 5 FIG. is a cross-sectional view showing a manufacturing process of a substrate for a semiconductor device.

[0015] Figure 6 FIG. is a cross-sectional view showing a manufacturing process of a substrate for a semiconductor device.

[0016] Figure 7 FIG. is the temperature distribution in the manufacturing process of the substrate for a semiconductor device.

[0017] Figure 8 FIG. is a schematic graph showing the relationship between the stress when a force acts in the direction of peeling the plate from the bonding layer and the distance from the end of the circuit pattern in the planar direction.

[0018] Figure 9 FIG. is for explaining Figure 8 the horizontal axis of. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, an embodiment of the substrate for a semiconductor device of the present invention will be described with reference to the drawings.Figure 1 This is a cross-sectional view of an example of a semiconductor device having a substrate for a semiconductor device according to the present embodiment.

[0020] <1. Outline of Semiconductor Device> The semiconductor device according to the present embodiment is used as a power component in various electronic devices such as smartphones, personal computers, large white goods, railways, electric vehicles, power generation (wind power generation, solar power generation, fuel cells, etc.), air conditioners, industrial robots, commercial elevators, household microwave ovens, IH rice cookers, and UPS (uninterruptible power supplies).

[0021] As Figure 1 shown, the semiconductor device 1 according to the present embodiment includes a substrate for a semiconductor device 2, a first bonding member 5, a second bonding member 5', a semiconductor chip 6, bonding wires 7, and a heat sink 8.

[0022] The substrate for a semiconductor device 2 includes a plate-shaped ceramic substrate 3 as an insulator, a first copper plate 4 bonded to its upper surface (first surface) via a bonding layer 9, and a second copper plate 4' bonded to its lower surface (second surface) via a bonding layer 9. As the ceramic substrate 3, for example, an alumina substrate, a aluminum nitride substrate, or silicon nitride can be used.

[0023] The bonding layer 9 can contain an active metal. The active metal can be, for example, at least one active metal selected from titanium and zirconium. Alternatively, the bonding layer 9 can also contain a metal other than the active metal. The metal other than the active metal contained in the bonding layer 9 is, for example, at least one metal selected from silver, copper, indium, and tin. In addition, the bonding layer 9 can contain nitrogen and / or silicon supplied from the ceramic substrate 3, and the supplied nitrogen and / or silicon can also form a compound with the active metal. Further, the bonding layer 13 can also contain copper supplied from the copper plate 12.

[0024] The first copper plate 4 is patterned to form a transmission circuit. On the other hand, the second copper plate 4' is formed in a flat plate shape.

[0025] On the upper surface of the substrate for a semiconductor device 2, that is, a part of the upper surface of the first copper plate 4, a semiconductor chip 6 is bonded via the first bonding member 5. In addition, the semiconductor chip 6 is connected to the first copper plate 4 by the bonding wires 7.

[0026] On the other hand, on the lower surface of the substrate for a semiconductor device 2, that is, the lower surface of the second copper plate 4', a heat sink 8 is bonded via the second bonding member 5'. The heat sink 8 is a well-known heat sink and can be made of a metal such as copper, for example.

[0027] It should be noted that the thicknesses of the ceramic substrate 3, the copper plates 4 and 4', and the bonding layer 9 are not particularly limited. For example, the thickness of the ceramic substrate is preferably 0.2 mm to 0.65 mm. The thickness of the copper plate is 0.3 mm or more, preferably 0.5 mm or more, and more preferably 0.8 mm or more. If the thickness of the copper plate is large, the heat dissipation performance is improved. In addition, the upper limit of the thickness of the copper plate is not particularly limited. For example, it can be 2.0 mm or less. In addition, the thickness of the bonding layer is preferably 0.1 μm to 20 μm.

[0028] <2. Features of the substrate for semiconductor devices> In the substrate 2 for semiconductor devices according to the present embodiment, as Figure 2 shown, it is characterized in that, in the range between the interface of the bonding layer 9 and each of the copper plates 4 and 4' and at least a position 100 μm away from the interface, along the thickness direction of each of the copper plates 4 and 4', the hardness becomes lower. The specific hardness distribution is not particularly limited. For example, it is preferably configured as follows.

[0029] (1) In the copper plates 4 and 4', the nanoindentation hardness at the first position 10 μm away from the interface with the bonding layer 9 in the thickness direction is 1.2 GPa to 2.3 GPa.

[0030] (2) In the copper plates 4 and 4', the nanoindentation hardness at the second position 30 μm away from the interface with the bonding layer 9 in the thickness direction is 0.7 GPa to 1.3 GPa.

[0031] (3) In the copper plates 4 and 4', the nanoindentation hardness at the third position 100 μm away from the interface with the bonding layer 9 in the thickness direction is 0.5 GPa to 1.1 GPa.

[0032] The above (1) to (3) are examples. It is preferable to satisfy (1), more preferably to satisfy (1) and (2), and preferably to satisfy all of (1) to (3). In the present embodiment, at least in the region from the interface to 100 μm (the third position), the hardness becomes lower as it is farther away from the interface. However, for example, in the case of satisfying the above (1), as long as the nanoindentation hardness on the third position side from the first position is lower than the nanoindentation hardness of the first position. That is, the nanoindentation hardnesses of the second position and the third position do not necessarily have to be the nanoindentation hardnesses shown in the above (2) and (3). In the case of satisfying the above (1) and (2), as long as the nanoindentation hardness on the third position side from the second position is lower than the nanoindentation hardness of the second position. That is, the nanoindentation hardness of the third position does not necessarily have to be the nanoindentation hardness shown in the above (3).

[0033] The nanoindentation hardness can be measured as follows. First, on the surfaces of the copper plates 4 and 4' of the semiconductor device substrate 2, an area capable of ensuring a length of 10 mm or more is selected. That is, an area on the copper plates 4 and 4' that is not truncated due to patterning and can ensure a length of 10 mm or more is selected. Next, a length of 10 mm is selected, and the semiconductor device substrate 2 is cut so that a cross-section including the midpoint thereof is exposed. Then, the cut surface is polished by ion milling.

[0034] Next, as Figure 2 shown, in the polished cross-section, three lines sandwiching the above midpoint are determined. The first line is a line passing through the above midpoint and extending perpendicularly in the thickness direction from the interface. The second line is a line 30 μm away from the first line. The third line is a line 30 μm away from the first line on the side opposite to the second line across the first line.

[0035] Next, on each line, at the first position 10 μm away from the interface, the second position 30 μm away from the interface, and the third position 100 μm away from the interface, the nanoindentation hardness is measured using a nanoindenter. Then, the nanoindentation hardness measured at the first position, the second position, and the third position on each line is averaged, and this is taken as the nanoindentation hardness at the first position, the second position, and the third position.

[0036] As Figure 1 shown, the above measurement method and measurement results can be applied to either the semiconductor device substrate obtained by patterning the copper plates 4 and 4' or the semiconductor device substrate without patterning.

[0037] <3. Manufacturing method of semiconductor device substrate> Next, the manufacturing method of the semiconductor device substrate will be described. Figure 3 is a flowchart showing the manufacturing method of the semiconductor device substrate of the present embodiment. Figure 4 , Figure 5 and Figure 6 are schematic cross-sectional views of intermediate products obtained during the manufacturing process of the semiconductor device substrate.

[0038] First, a ceramic substrate 3 is prepared (step S1). Next, as Figure 4As shown, a solder layer 9i is formed on the upper and lower surfaces of the ceramic substrate 3 (step S2). At this time, as the solder layer 9i, a paste containing an active metal solder, a binder, and a solvent is prepared. This paste may also contain a dispersant, an antifoaming agent, etc. Next, the prepared paste is printed on the upper and lower surfaces of the ceramic substrate 3 by screen printing. Thereby, a screen printing film is formed on each surface of the ceramic substrate 3. Next, the solvent contained in the formed screen printing film is volatilized. Thereby, the screen printing film is changed into the solder layer 9i. The solder layer 9i contains an active metal solder and a binder. However, the solder layer 9i can also be formed by a method different from this method.

[0039] The active metal solder contains a hydrogenated active metal powder and a metal powder. The hydrogenated active metal powder contains a hydride of an active metal selected from at least one of titanium and zirconium. The metal powder contains silver. The metal powder may also contain a metal other than silver. The metal other than silver is a metal selected from at least one of copper, indium, and tin. When the active metal solder contains a metal selected from at least one of copper, indium, and tin, the melting point of the active metal solder is lowered.

[0040] The active metal solder preferably contains a powder having an average particle size of 0.1 μm or more and 20 μm or less. The average particle size can be obtained by measuring the particle size distribution using a commercially available laser diffraction type particle size distribution measuring device and calculating D50 (median particle size) based on the measured particle size distribution. By making the active metal solder contain such a powder having a small average particle size, the solder layer 9i can be made thinner.

[0041] The solder layer 9i preferably has a thickness of 0.1 μm or more and 20 μm or less, and more preferably has a thickness of 0.1 μm or more and 5 μm or less.

[0042] Next, as Figure 5 shown, copper plates 4, 4' are arranged on the formed solder layer 9i (step S3). Thereby, an intermediate product 2i including the ceramic substrate 3, the copper plates 4, 4', and the solder layer 9i is obtained.

[0043] Next, the obtained intermediate product 2i is subjected to a heat and pressure treatment (step S4). Thereby, as Figure 6 shown, a bonding layer 9 is generated. As a result, a semiconductor device substrate 2 including the ceramic substrate 3, the copper plates 4, 4', and the bonding layer 9 as Figure 6 shown is obtained. The copper plates 4, 4' are bonded to the ceramic substrate 3 through the bonding layer 9.

[0044] When the intermediate product 2i is subjected to a heat and pressure treatment, heating is performed according to the Figure 7 shown temperature distribution. As Figure 7As shown, the temperature inside the furnace is raised in a vacuum atmosphere so that the temperature of the intermediate product 2i becomes 800°C to 900°C Max. The heating rate at this time can be set, for example, to 2°C / min to 10°C / min. During this process, in the temperature range of the bonding layer formation temperature of approximately 750°C or higher to the time zone for nitrogen replacement, the vacuum atmosphere inside the furnace is adjusted to be 10 -2 Pa. The intermediate product 2i is pressurized during the heating process and before the cooling is completed. At this time, the surface pressure applied to the intermediate product 2i can be adjusted, for example, from 0.2 Pa to 22 MPa. Pressurization enables the ceramic, the bonding layer, and the copper plate to come into reliable contact and react, and a bonding layer can be formed.

[0045] Next, after maintaining the temperature of the intermediate product 2i at 800°C to 900°C for 30 to 60 minutes, the intermediate product 2i is cooled. Then, when the temperature of the intermediate product reaches 650°C to 800°C, an inert gas such as nitrogen is injected into the furnace, and the temperature is lowered in an inert gas atmosphere. The pressure at this time is preferably equivalent to atmospheric pressure or higher. The bonding layer 9 is formed in a vacuum atmosphere.

[0046] During the process of cooling the intermediate product 2i, it is rapidly cooled from 800°C to 900°C to 200°C to 300°C at approximately 2.8°C / min to 12°C / min. After rapid cooling, it is slowly cooled to room temperature.

[0047] Next, patterning is performed on the copper plates 4 and the bonding layer 9 by an etching method or the like (step S5). As a result, the copper plate 4 is changed to Figure 1 the patterned copper plate 4 shown in the figure. In addition, the bonding layer 9 is also changed to Figure 1 the patterned bonding layer 13 shown in the figure.

[0048] <4. Features> As described above, in the present embodiment, in the range between the interface of the bonding layer 9 and the copper plates 4, 4' and at least 100 μm away from the interface, the hardness becomes lower along the thickness direction of the copper plates 4, 4'. That is, it is configured such that near the interface between the bonding layer 9 and the copper plates 4, 4', the hardness becomes lower as the distance from the interface increases along the thickness direction, so that peeling of the copper plates 4, 4' can be suppressed. Regarding this point, refer to Figure 8 and Figure 9 for explanation.

[0049] Figure 8 shows the stress distribution generated at the bonding interface during the thermal cycling process. In addition, Figure 9 is a diagram for explaining Figure 8 the horizontal axis of. During thermal cycling, due to the thermal expansion difference between the copper 4, 4' and the ceramic substrate 3, high stress is generated at the bonding interface. As shown in Figure 8As shown, if the copper plates 4 and 4' have a gradient such that the hardness of the copper decreases, the force is dispersed and the peak value of the stress generated at the interface is reduced. Therefore, the peak value of the stress near the edges of the copper plates 4 and 4' (especially Figure 8 and Figure 9 in the region close to X = 0) is lower than the threshold value for spalling, and spalling of the edges of the copper plates 4 and 4' can be suppressed.

[0050] Also, if the thickness of the copper plates 4 and 4' is large, the heat dissipation performance is improved. On the other hand, the possibility of spalling of the copper plates 4 and 4' occurring under thermal cycling becomes greater. However, in the present embodiment, since the copper plates 4 and 4' have the hardness gradient as described above, even when the thickness of the copper plates 4 and 4' becomes large, spalling caused by thermal cycling can be effectively suppressed.

[0051] Examples Hereinafter, examples of the present invention will be described. However, the present invention is not limited to the following examples.

[0052] <1. Fabrication of a substrate for a semiconductor device> A silicon nitride ceramic substrate with a thickness of 0.32 mm and a copper plate with a thickness of 0.8 mm were prepared. In addition, a solder with a thickness of 0.1 μm or more and 20 μm or less, containing an active metal solder, was prepared. The active metal solder contains 40 wt% or more and 95 wt% or less of silver and titanium hydride. Then, this solder was coated on the upper and lower surfaces of the silicon nitride ceramic substrate by screen printing, and the copper plate was disposed thereon to form an intermediate product.

[0053] Next, this intermediate product was placed in a furnace and heated according to the Figure 7 temperature distribution shown. In the heating process, it was heated to about 850 °C at a rate of about 5 °C / min, and pressurized at about 20 MPa when the temperature exceeded 750 °C. Then, it was cooled at the cooling rates shown in Tables 2 to 5, and when the temperature was reduced to about 250 °C, it was slowly cooled to room temperature. In this way, the substrates for semiconductor devices according to Examples 1 to 9 and Comparative Example 1 were completed. That is, in the examples, three substrates for semiconductor devices were fabricated at one cooling rate. It should be noted that no patterning of the copper plate was performed on these semiconductor substrates.

[0054] <2. Evaluation> For the substrates for semiconductor devices according to Examples 1 to 9 and Comparative Example 1, the nanoindentation hardness at the above-mentioned first to third positions was measured. The measurement conditions are shown in Table 1, and the results are shown in Table 2.

[0055] [Table 1] [Table 2] [Table 3] [Table 4] [Table 5] Next, a thermal cycle test was performed on the substrates for semiconductor devices involved in these Examples 1 to 9 and Comparative Example 1. That is, after repeating heating and cooling cycles 3000 times between -40°C and 175°C, an ultrasonic flaw detection test was conducted, and exfoliation at the end of the copper plate was confirmed. In the ultrasonic flaw detection test, an ultrasonic flaw detector FSesIII manufactured by Hitachi Power Solutions Co., Ltd. was used for inspection by the reflection method. The results are as follows. The case where exfoliation could not be confirmed was set as OK, and the case where exfoliation could not be confirmed was set as NO. In the image obtained by the ultrasonic flaw detection test, since a gap was generated between the copper plate and the bonding layer at the exfoliated part, this gap was photographed as white, so exfoliation could be confirmed.

[0056] [Table 6] From the results in Table 6, it was confirmed that: if the copper plate has a hardness gradient in which the nanoindentation hardness decreases from the first position to the third position, there is no exfoliation in the thermal cycle test. On the other hand, exfoliation of the copper plate occurred in Comparative Example 1 that does not have such a hardness gradient. Therefore, it can be seen that if the copper plate has the above-described hardness gradient, exfoliation of the copper plate can be suppressed.

[0057] Description of Reference Numerals 2... Substrate for semiconductor device 3... Ceramic substrate 4, 4'... Copper plate 9... Bonding layer.

Claims

1. A semiconductor device substrate, comprising: A ceramic substrate having a first surface and a second surface; a bonding layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, The thickness of the copper plate is greater than 0.3 mm. The copper plate has a region where hardness is low along the thickness direction of the copper plate, between a position 100 μm away from an interface between the bonding layer and the copper plate in the thickness direction and the interface.

2. The semiconductor device substrate according to claim 1, wherein At least one side of the copper plate is patterned.

3. The semiconductor device substrate according to claim 1 or 2, wherein: In the copper plate, the nanoindentation hardness at the first position 10 μm away from the interface in the thickness direction is 1.2 GPa to 2.3 GPa, The nanoindentation hardness at a position farther from the interface than the first position is lower than the nanoindentation hardness at the first position.

4. The semiconductor device substrate according to claim 3, wherein: In the copper plate, the nanoindentation hardness at a second position 30 μm away from the interface in the thickness direction is 0.7 GPa to 1.3 GPa, The nanoindentation hardness at a position farther from the interface than the second position is lower than the nanoindentation hardness at the second position.

5. The semiconductor device substrate according to claim 4, wherein: In the copper plate, the nanoindentation hardness at a third position 100 μm away from the interface in the thickness direction is 0.5 GPa to 1.1 GPa, The nanoindentation hardness at a position farther from the interface than the third position is lower than the nanoindentation hardness at the third position.

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