Preparation method of piezoresistive high-temperature pressure sensor based on TSV (Through Silicon Via) of silicon column

Abstract

The invention relates to a preparation method of a piezoresistive high-temperature pressure sensor based on a TSV (Through Silicon Via) of a silicon column. The preparation method comprises the following steps: 1, preparing an annular isolation groove filled with polycrystalline silicon on a low-resistance double-parabolic silicon wafer; 2, preparing a TSV silicon column and a bonding boss on the double-polished silicon wafer; 3, preparing a P-type voltage dependent resistor and an inner lead on the top layer silicon of the SOI silicon wafer; 4, preparing a closed annular groove at the periphery of the SOI silicon wafer, and preparing a semi-closed annular groove at the corresponding position of the TSV silicon column; 5, aligning and bonding the double-polished silicon wafer and the SOI silicon wafer; 6, preparing a TSV cap layer metal electrode from the bonded P-type double-polished silicon wafer; and 7, preparing a pressure sensitive film structure on the lower surface of the bonded SOI silicon wafer. The high-temperature pressure sensor has the beneficial effects that the TSV silicon column process, the dielectric isolation piezoresistive process and the thermal expansion buffer tank process suitable for the high-temperature working environment form an all-silicon structure of the high-temperature pressure sensor, the thermal stress matching is good, and the influence of high-temperature stress on the device performance can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of MEMS sensor chip structures, and particularly to a high-temperature pressure sensor structure. Background Art

[0002] In fields such as aerospace, national defense, petrochemical industry, and automotive industry, it is often necessary to measure and control pressure in high-temperature environments. High-performance high-temperature pressure sensors are one of the key devices in the above fields. Currently, the widely used silicon piezoresistive pressure sensors adopt P-N junction isolation strain bridges and strain membranes, with mature processes and excellent performance. However, the leakage current of the P-N junction increases sharply with the increase in temperature. When the temperature exceeds 120 °C, the performance of the sensor will deteriorate severely or even fail. In addition, silicon will undergo plastic deformation and current leakage at 600 °C, resulting in extreme misalignment of the signal processing system and circuit.

[0003] Using SOI wafers to fabricate piezoresistors on the silicon oxide dielectric layer has a significant effect on improving the high-temperature performance of pressure sensors, but there are still some problems. For example, due to the mechanical stress caused by the bonding surface and the thermal stress caused by the inconsistent thermal parameters of the chip thin-film materials and the packaging interface materials, it will be conducted to the pressure-sensitive structure, resulting in device performance degradation or even function loss in high-temperature environments. In addition, the traditional packaging wire bonding method is to use gold wire thermocompression bonding to connect the chip and the pads of the packaging case, which is prone to fatigue fracture failure in high-temperature and high-vibration environments. Cited Documents

[0004] Chinese Patent: A High-Temperature Pressure Sensor Chip Based on MEMS Process (Patent Application No.: 201910654802.7) The present invention includes a chip base, a P-type epitaxial layer, a pressure-sensitive thin film, piezoresistive elements, a connection support frame, a piezoresistive element isolation layer, an ohmic contact window, a metal layer, and a metal protective layer; the front surface of the chip base bears the piezoresistive elements, the pressure-sensitive film is formed by etching the back surface of the chip base, the piezoresistive elements and the connection bracket are formed by etching the N-type epitaxial layer, the piezoresistive element isolation layer covers the piezoresistive elements and the connection bracket, the metal layer and the piezoresistive elements are connected to each other through the ohmic contact window etched out by the piezoresistive element isolation layer, and the connection height between the piezoresistive elements and the metal varies with the thickness of the piezoresistive element isolation layer. This pressure sensor chip can not only work stably at high temperatures but also effectively avoid the problem of oxidation failure of the piezoresistive elements and the metal layer.

[0005] Chinese Patent: A High-Temperature Pressure Sensor Chip and Manufacturing Method Adapted to Multiple Packaging Methods (Patent Application No.: 202011425174.4) The present invention is provided with four varistors on an insulating layer. The four varistors are isolated from each other by microchannels, and the four varistors are connected to form a Wheatstone bridge. The four varistors and the insulating layer are covered by a passivation layer to avoid chip failure caused by an increase in leakage current between the resistors under high-temperature environments. A sealing area is added to the chip surface. The chip and the upper sealing glass are connected through a sealing process to ensure airtight isolation between the sensitive resistors of the chip and the external environment. A sealing connection area is designed to enable electrical connection of multiple devices, ensuring uniform distribution of the externally applied electric field during the implementation of the electrostatic sealing process and improving the chip yield after sealing. This chip can adapt to various packaging forms and has wide applicability. Summary of the Invention

[0006] The object of the present invention is to provide a preparation method for a silicon pillar TSV piezoresistive high-temperature pressure sensor. The present invention applies the TSV silicon pillar process, the dielectric isolation piezoresistive process, and the thermal expansion buffer groove process suitable for high-temperature working environments to the preparation of high-temperature pressure sensors, forming a fully silicon structure for high-temperature pressure sensors with good thermal stress matching, which can effectively reduce the influence of high-temperature stress on device performance.

[0007] It adopts the following technical solutions: A preparation method for a silicon pillar TSV piezoresistive high-temperature pressure sensor, including the preparation of a TSV capping layer and a pressure-sensitive structure layer, comprising the following steps: S1. Take a P-type low-resistance double-polished silicon wafer (100), and use photolithography and TSV deep groove etching to form an upper and lower unconnected annular isolation groove; S2. Use a thermal oxidation process to grow SiO2 on the inner wall of the annular isolation groove and the upper surface of the double-polished silicon wafer, and then use polysilicon to fill the annular isolation groove; S3. Use CMP to remove the polysilicon on the upper surface of the P-type double-polished silicon wafer to expose SiO2, and prepare an annular dielectric isolation groove filled with polysilicon; S4. Use photolithography and etching on the upper surface of the P-type double-polished silicon wafer to prepare TSV silicon pillars and bonding bosses, and form a shallow cavity between the bonding bosses; S5. Take an N-type SOI silicon wafer (200), and use photolithography and etching processes to form a preparation area with a piezoresistive Wheatstone bridge structure with dielectric isolation in a specific area of the top silicon of the SOI silicon wafer (100); S6. Prepare P-type varistors in the preparation area of the Wheatstone bridge structure of the N-type top silicon of the SOI silicon wafer 200 through photolithography, boron impurity implantation, and diffusion annealing processes; prepare heavily doped single-crystalline silicon as an inner lead in the remaining part of the preparation area of the Wheatstone bridge structure through photolithography, boron implantation, and diffusion annealing processes; S7. Thermally oxidize the surface of the SOI wafer 200, and then form a fully enclosed annular groove around the SOI wafer 200 through photolithography and deep trench etching. Form a C-shaped semi-enclosed annular groove at the corresponding position of the TSV silicon pillar as a thermal expansion buffer groove, where a channel for the inner lead to pass through is formed at the opening of the semi-enclosed annular groove, and the depth of the thermal expansion buffer groove is greater than the thickness of the pressure-sensitive film; S8. Use photolithography and etching processes to remove the SiO2 oxide layer on the P-type top silicon of the SOI wafer (200) except for the dielectric isolation piezoresistive Wheatstone bridge structure, forming a bonding surface of the SOI wafer; S9. Align and bond the TSV silicon pillar and the bonding convex surface of the above P-type double-polished silicon wafer with the SOI wafer to form a vacuum-sealed cavity structure, and vertically connect the TSV silicon pillar with the inner lead of the pressure-sensitive structure layer; Align and bond the bonding convex surface of the above P-type double-polished silicon wafer with the bonding surface on the N-type top silicon surface of the SOI wafer to form a vacuum-sealed cavity structure, and at the same time vertically bond and connect the TSV silicon pillar with the inner lead of the pressure-sensitive structure layer; S10. Grind and polish the upper surface of the bonded P-type double-polished silicon wafer to expose the TSV silicon pillar; S11. Complete the preparation of the TSV capping layer metal electrode through thermal oxidation, photolithography, etching, metal sputtering, and etching processes; S12. Finally, perform photolithography and etching on the lower surface of the bonded SOI wafer to form a back cavity, forming a pressure-sensitive film structure.

[0008] The process parameters adopted in the technical solution of the present invention are conventional techniques in the art and will not be elaborated here.

[0009] The beneficial effects of the present invention compared with the prior art: The present invention applies the TSV silicon pillar process, the dielectric isolation piezoresistive process, and the thermal expansion buffer groove process suitable for high-temperature working environments to the preparation of high-temperature pressure sensors, forming a fully silicon structure of high-temperature pressure sensors. The thermal stress matching is good, which can effectively reduce the influence of high-temperature stress on the device performance; by vertically leading out the chip PAD point through the silicon pillar TSV, it can meet the requirements of the leadless packaging structure, avoid using wire bonding, and has high stability and reliability. Moreover, it avoids the complex packaging process and the use of commercially confidential metal glass pastes. This structure does not significantly increase the process processing difficulty of high-temperature pressure sensors, is fully compatible with the existing process technologies, has strong manufacturability, and is easy to mass-produce. Description of the Drawings

[0010] Figure 1 It is a schematic diagram of step S1 of the present invention; Figure 2 It is a schematic diagram of step S2 of the present invention; Figure 3It is a schematic diagram of step S3 of the present invention; Figure 4 It is a schematic diagram of step S4 of the present invention; Figure 5 It is a schematic diagram of step S5 of the present invention; Figure 6 It is a schematic diagram of step S6 of the present invention; Figure 7 It is a schematic diagram of step S7 of the present invention; Figure 8 It is a schematic diagram of step S8 of the present invention; Figure 9 It is a schematic diagram of step S9 of the present invention; Figure 10 It is a schematic diagram of step S10 of the present invention; Figure 11 It is a schematic diagram of step S11 of the present invention; Figure 12 It is a schematic diagram of step S12 of the present invention; Figure 13 It is the final schematic diagram after the preparation of the present invention is completed; Figure 14 is Figure 6 the alternative structure of Figure 15 is Figure 14 the final structure.

[0011] To make the present invention more clear and understandable, the following further describes a preparation method of a silicon pillar TSV piezoresistive high-temperature pressure sensor of the present invention with reference to the accompanying drawings. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Embodiment 1

[0012] A preparation method of a silicon pillar TSV piezoresistive high-temperature pressure sensor, which includes the following steps: S1. As Figure 1 shown, take a P-type low-resistance double-polished silicon wafer 100, and form an upper and lower unconnected annular isolation groove 101 on the double-polished silicon wafer by photolithography and TSV deep etching; S2. As Figure 2 shown, grow a SiO2 insulating layer 102 on the inner wall and upper surface of the annular isolation groove by thermal oxidation, and then fill the annular isolation groove 101 with polysilicon 103; S3. As Figure 3 shown, remove the polysilicon 103 on the upper surface of the P-type double-polished silicon wafer 100 by CMP to expose the SiO2 insulating layer 102, and prepare an annular dielectric isolation groove 104 filled with polysilicon; S4. As Figure 4As shown in the figure, on the upper surface of the P-type double-polished silicon wafer 100, partial TSV silicon pillars 105 located between isolation grooves 104 and bonding bumps 106 around the double-polished silicon wafer 100 are prepared by photolithography and etching. A shallow cavity 107 is formed between the bonding bumps; S5. As Figure 5 shown, take an N-type SOI silicon wafer 200, and use photolithography and etching processes to form a preparation area 202 with a piezoresistive Wheatstone bridge structure with a dielectric isolation layer in a specific area of the N-type top silicon 201 of the SOI silicon wafer 200; S6. As Figure 6 shown, first remove the top dielectric isolation layer, and prepare a P-type piezoresistor 203 in the preparation area of the Wheatstone bridge structure of the N-type top silicon 201 of the SOI silicon wafer 200 through photolithography, boron impurity implantation, and diffusion annealing processes; prepare heavily doped single-crystalline silicon as an inner lead 204 in the remaining part of the preparation area of the Wheatstone bridge structure through photolithography, boron implantation, and diffusion annealing processes; S7. As Figure 7 shown, thermally oxidize the surface of the N-type SOI silicon wafer 200 to form an oxide layer covering the structural layers 201, 203, and 204, and then cover an isolation dielectric layer on the oxide layer.

[0013] Then, through photolithography and deep trench etching, a fully enclosed annular groove 205 is formed around the SOI silicon wafer 200, and a C-shaped semi-enclosed annular groove 206 is formed at the corresponding position of the TSV silicon pillar as a thermal expansion buffer groove. A channel for the inner lead 204 to pass through is formed at the opening of the semi-enclosed annular groove 206. The depth of the thermal expansion buffer groove is greater than the thickness of the pressure-sensitive film (i.e., the groove depth reaches the bottom silicon 200); S8. As Figure 8 shown, use photolithography and etching processes to remove the SiO2 oxide layer on the N-type top silicon 201 of the SOI silicon wafer 200 except for the dielectric isolation layer and the piezoresistive Wheatstone bridge structure, forming a silicon-silicon bonding connection surface 207 corresponding to the bonding bump 106 around the SOI silicon wafer 200, and a silicon-silicon bonding connection surface 207a corresponding to and mating with the silicon pillar 105 on the lead 204; S9. As Figure 9 shown, align and bond the bonding bump 106 surface of the above-mentioned P-type double-polished silicon wafer 100 with the bonding connection surface 207 on the surface of the N-type top silicon of the SOI silicon wafer to form a vacuum-sealed cavity structure 208, and at the same time vertically bond and connect the TSV silicon pillar 105 with the inner lead 204 of the pressure-sensitive structure layer; S10. As Figure 10 shown, grind and polish the upper surface of the bonded P-type double-polished silicon wafer 100 to expose the TSV silicon pillar 105; S11. As Figure 11As shown, first, a thermal oxide layer is formed on the upper surface of the P-type double-polished silicon wafer 100, and then the metal electrode 109 connected to the TSV silicon pillar 105 is fabricated through photolithography, etching, metal sputtering, and etching processes to form the final TSV capping layer 108. S12. As Figure 12 shown, finally, photolithography and etching are performed on the lower surface of the bonded SOI silicon wafer 200 to form a back cavity 209, thereby forming a pressure-sensitive film structure 210.

[0014] Through the manufacturing method of the present invention, the TSV silicon pillar process, the dielectric isolation piezoresistive process, and the thermal expansion buffer groove process applicable to high-temperature working environments are applied to the preparation of high-temperature pressure sensors, forming an all-silicon structure of high-temperature pressure sensors with good thermal stress matching, which can effectively reduce the influence of high-temperature stress on device performance; by vertically leading out the chip PAD points through the silicon pillar TSV, the requirements of the leadless package structure can be met, avoiding the use of gold wire bonding, having high stability and reliability, and avoiding the use of complex packaging processes and commercially confidential metal glass slurries. This structure does not significantly increase the process difficulty of high-temperature pressure sensors, is fully compatible with existing process technologies, has strong manufacturability, and is easy to mass-produce. Example Two

[0015] In step S6 of Example One, as Figure 14 shown, a P-type piezoresistor 203 is fabricated in the preparation area of the Wheatstone bridge structure of the N-type top silicon 201 of the SOI silicon wafer 200 through photolithography, boron impurity implantation, and diffusion annealing processes; polysilicon deposition, metal deposition, photolithography, etching, and high-temperature annealing processes are used to prepare metal silicide as the internal lead 204, thereby forming a piezoresistive Wheatstone bridge structure to replace the structure shown in Example One Figure 6 shown, and the finally formed structure is as Figure 15 shown.

[0016] The remaining steps are the same as those in Example One.

[0017] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And these obvious changes or modifications derived from the essence of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for preparing a silicon pillar TSV piezoresistive high-temperature pressure sensor, comprising the preparation of a TSV cap layer and a pressure sensitive structure layer, comprising the following steps: S1. On a P-type low-resistance double-polished silicon wafer, photolithography and TSV deep trench etching are used to form an annular isolation groove that is not connected from top to bottom; S2, using a thermal oxidation process to grow SiO2 on the inner wall of the annular isolation groove and the upper surface of the double-polished silicon wafer, and then using polysilicon to fill the annular isolation groove; S3, using CMP to remove the polysilicon on the upper surface of the P-type double-polished silicon wafer to expose SiO2, and prepare a polysilicon-filled annular dielectric isolation groove; S4, preparing TSV silicon pillars and bonding bosses on the upper surface of the P-type double-polished silicon wafer by photolithography and etching, and forming a shallow cavity between the bonding bosses; S5. On an N-type SOI silicon wafer, a preparation area of ​​a piezoresistive Wheatstone bridge structure with dielectric isolation is formed in a specific area of ​​the top silicon of the SOI silicon wafer by using photolithography and etching processes; S6, preparing a P-type varistor in the preparation area of ​​the Wheatstone bridge structure of the top silicon of the SOI silicon wafer by photolithography, implantation of boron impurities and diffusion annealing processes; preparing heavily doped single crystal silicon as inner leads in the remaining part of the preparation area of ​​the Wheatstone bridge structure by photolithography, implantation of boron and diffusion annealing processes; S7, thermally oxidizing the surface of the SOI silicon wafer 200, and then forming a fully closed annular groove around the SOI silicon wafer 200 by photolithography and deep groove etching, and forming a C-shaped semi-closed annular groove at the corresponding position of the TSV silicon column as a thermal expansion buffer groove, wherein a channel for the inner lead to pass through is formed at the opening of the semi-closed annular groove, and the groove depth of the thermal expansion buffer groove is greater than the thickness of the pressure sensitive film; S8, using photolithography and etching processes to remove the SiO2 oxide layer outside the dielectric isolation piezoresistive Wheatstone bridge structure on the top silicon of the SOI silicon wafer to form a bonding surface of the SOI silicon wafer; S9, aligning and bonding the TSV silicon pillars and bonding protrusions of the P-type double-polished silicon wafer and the SOI silicon wafer to form a vacuum sealed cavity structure, and vertically connecting the TSV silicon pillars to the leads in the pressure sensitive structure layer; Align and bond the bonding protrusion surface of the P-type double-polished silicon wafer with the bonding connection surface of the N-type top silicon surface of the SOI silicon wafer to form a vacuum sealed cavity structure, and vertically bond the TSV silicon column to the lead wire in the pressure sensitive structure layer; S10, grinding and polishing the upper surface of the bonded P-type double-polished silicon wafer to expose the TSV silicon pillars; S11, completing the preparation of the TSV cap layer metal electrode through thermal oxidation, photolithography, etching, metal sputtering, and etching processes; S12. Finally, photolithography and etching are performed on the lower surface of the bonded SOI silicon wafer to form a back cavity to form a pressure sensitive membrane structure.

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