Power supply time sequence management method and power supply equipment

Abstract

The invention provides a power supply time sequence management method and power supply equipment, and the method comprises the steps: obtaining a PG signal of each power supply module through a CPLD chip, determining a target power supply module with power-on / power-off abnormity through monitoring the PG signal state of each power supply by the CPLD chip, obtaining the current state information of the target power supply module, and storing the current state information of the target power supply module in the CPLD chip; and recording the current state information in the CPLD chip, and triggering a black box to record the current state information. By means of the method, the CPLD chip can be used for replacing an ADM1166 chip to achieve power source time sequence management.

Description

Technical Field

[0001] This specification relates to the field of communication technologies, and particularly to a method for managing power supply timing and a power supply device. Background Art

[0002] CPLD: Complex Programmable Logic Device, a complex programmable logic device with a large scale and complex structure, belonging to the scope of large-scale integrated circuits. A digital integrated circuit in which users can construct logical functions according to their respective needs. Its basic design method is to generate corresponding target files by means of an integrated development software platform, using methods such as schematic diagrams and hardware description languages, and transfer the code to the target chip through a download cable to achieve specific functions.

[0003] Power-on and power-off timing: The timing relationship and sequence of various power supply voltages and signals during the power-on (boot-up) and power-off (shutdown) processes of an electronic system or device. Power-on timing and power-off timing are very important, especially in complex electronic devices, because incorrect timing may cause device damage or abnormal functions.

[0004] Black box recording: A device or function for recording various key data and events during the operation of a power supply system. Its main purpose is to provide detailed operation data when a fault, abnormality, or other important event occurs in the power supply system, helping engineers and maintenance personnel conduct fault analysis, diagnosis, and troubleshooting, and improving the stability and reliability of the power supply system.

[0005] Under the background of the changing current international situation and increasingly fierce technological competition, the importance of the localization process of Chinese electronic components has become increasingly prominent. This process is of great significance for enhancing the country's scientific and technological independent innovation ability, ensuring supply chain security, and achieving high-quality economic development.

[0006] For a long time, China has been highly dependent on imports in the field of electronic components, especially in high-end chips and key components. This dependence not only puts domestic manufacturing at a disadvantage in global competition but also increases the risk of supply chain disruptions. Summary of the Invention

[0007] To overcome the problems existing in the related technologies, this specification provides a method for managing power supply timing and a power supply device.

[0008] According to the first aspect of the embodiments of this specification, a method for managing power supply timing is provided, and the method includes:

[0009] Obtain the PG signals of each power supply module by using a CPLD chip;

[0010] The CPLD chip determines the target power supply module with abnormal power-on / off by monitoring the PG signal status of each power supply.

[0011] Obtain the current status information of the target power supply module, record the current status information in the CPLD chip, and trigger the black box to record the current status information.

[0012] Among them, the obtaining of the PG signals of each power supply module by using the CPLD chip includes:

[0013] The CPLD chip obtains the PG signals of each power supply module.

[0014] Among them, the CPLD chip determines the target power supply module with abnormal power-on / off by monitoring the PG signal status of each power supply, including:

[0015] The CPLD chip monitors the PG signal status of each power supply. When the PG signal is monitored to be in an abnormal state, the power supply module corresponding to the PG signal in the abnormal state is determined as the target power supply module.

[0016] Among them, obtaining the current status information of the target power supply module and recording the current status information in the CPLD chip includes:

[0017] Lock the current status information of the target power supply module and record the current status information in the register of the CPLD chip.

[0018] Among them, triggering the black box to record the current status information includes:

[0019] Trigger to write the current status information recorded in the register of the CPLD chip into the EEPROM.

[0020] It can be seen from the above embodiments that through the CPLD chip, the monitoring of each power supply module can be realized. When a target power supply module with abnormal power-on / off is found, the black box recording can be triggered, so that the use of the CPLD to replace the ADM1166 to complete the power-on / off control and black box recording functions is realized.

[0021] According to the second aspect of the embodiments of the present specification, a power supply device is provided. The power supply device includes: a plurality of power supply modules and a CPLD chip.

[0022] The CPLD chip is connected to each power supply module to obtain the PG signals of each power supply module.

[0023] The CPLD chip monitors the PG signal status of each power supply through a monitoring module to determine the target power supply module with abnormal power-on / off.

[0024] The CPLD chip obtains the current status information of the target power supply module, records the current status information in the CPLD chip, and triggers the black box to record the current status information.

[0025] Among them, the CPLD chip obtains the PG signal of each power supply module through the filtering module.

[0026] Among them, the CPLD chip monitors the status of the PG signal of each power supply. When it monitors that the PG signal is in an abnormal state, it determines that the power supply module corresponding to the PG signal in the abnormal state is the target power supply module.

[0027] Among them, the CPLD chip locks the current status information of the target power supply module and records the current status information in the register of the CPLD chip.

[0028] Among them, the CPLD chip triggers to write the current status information recorded in the register into the EEPROM.

[0029] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. Brief Description of the Drawings

[0030] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.

[0031] Figure 1 is a schematic diagram of power management through the ADM1166 chip shown according to an exemplary embodiment of this specification.

[0032] Figure 2 is a schematic flowchart of a method for managing power supply timing shown according to an exemplary embodiment of this specification.

[0033] Figure 3 is a schematic logic diagram of power management through the CPLD chip shown according to an exemplary embodiment of this specification.

[0034] Figure 4 is a schematic logic diagram of black box recording shown according to an exemplary embodiment of this specification. Detailed Embodiments

[0035] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0036] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the", and "said" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0037] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to a determination".

[0038] As Figure 1 shown, a circuit diagram for power management through the ADM1166 chip is shown. Among them, Module 1: VX&VP pins. These pins have analog and digital detection functions and can accurately read the power supply voltage. A threshold is set for these pins, and if the voltage exceeds the threshold, the power supply is considered abnormal and the power-down process is entered. Module 2: PDO pins. These pins are power-on / off control pins for the power supply. Outputting a low level turns off the power supply, and a high level turns on the power supply. Module 3: I2C. The I2C pins are mainly used to read the black box information recorded by the device, which is convenient for locating power problems.

[0039] It can be seen from the above embodiments that in the prior art, power management is completely achieved by using the ADM1166 chip.

[0040] However, to accelerate the process of localization, domestic enterprises have increased their investment in technology research and development. With the continuous enhancement of the investment in human resources and resources, the technical strength has been gradually improved. Driven by market demand, some enterprises have achieved the transformation from low-end products to mid- to high-end products, and gradually reduced their dependence on foreign advanced technologies and products. This not only enhances the self-sufficiency ability of the domestic market but also provides a stronger foundation for participating in international competition.

[0041] In addition, the localization process has also promoted the integration of industry, academia, and research. Through the participation of universities and research institutions, it has driven the research, development, and application of innovative technologies. At the same time, the importance of talent cultivation has become increasingly evident, and an increasing number of high-quality scientific and technological talents have injected vitality into the development of the domestic electronic component industry.

[0042] In summary, the localization of electronic components is a systematic project that requires not only policy support and corporate efforts but also collaborative innovation across the entire industry. In future development, increasing the localization rate and technological autonomy will enable China to gain more discourse power and initiative in the global technology landscape, while achieving stronger economic development resilience and sustainability. The current power sequence controller manufacturer is from the United States, and there is no domestic alternative chip. To solve the above technical problems, the embodiments of the present disclosure provide a method for managing power sequence, as Figure 2 shown, the method includes:

[0043] S201 Obtain the PG signals of each power module using a CPLD chip;

[0044] S202 The CPLD chip determines the target power module with abnormal power-on / off by monitoring the status of the PG signals of each power supply;

[0045] S203 Obtain the current status information of the target power module, record the current status information in the CPLD chip, and trigger the black box to record the current status information.

[0046] In this embodiment, when implementing power sequence management through a CPLD, it can include two aspects. One is power-on / off control, and the other is black box recording, which realizes the functions of power-on / off timing control and recording power supply abnormalities through code.

[0047] Among them, power-on control: complete the delay function through a timer, control the power supply EN, and meet the requirements of the power supply power-on sequence in the manual.

[0048] Among them, power-off control: judge the status of the power supply PG signal, enter the power-off state machine, and complete the power-off function.

[0049] Among them, black box recording: CPLD + EEPROM (SPI protocol), latch the PG status at the moment of power supply abnormality, store it in the EEPROM to complete the black box recording, and the software indirectly accesses the EEPROM to read the record and store it in the diag for R & D positioning and analysis. In case of repeated power-on / off of the damaged single board, a dedicated device can also be used to read the EEPROM.

[0050] In this embodiment, the logic code completes the black box recording and single board power-off by judging the jump of the PG signal state machine. To avoid mis-power-off or recording caused by interference of the PG signal, the PG signal needs to be filtered for 100 us before use, asFigure 3 As shown, the CPLD chip can obtain the PG signals of each power supply module through a 100us filtering module (in other embodiments, different filtering modules can be selected according to user requirements). Among them, the CPLD chip enables functions such as 12V detection, power-on process monitoring, and power-off process monitoring. In this embodiment, the bit width of the filtering module is 4 bits. If there are multiple PGs, the corresponding code is called multiple times.

[0051] In this embodiment, the timing control function can be divided into two parts: power-on and power-off. In the same always statement, the same delay counter is shared.

[0052] Among them, in the power-on timing design, when count_PG_delay counts to a certain time, the corresponding power supply EN is turned on. If there are multiple power supplies, multiple else if statements are added to achieve the purpose of delay.

[0053] In the power-off timing design, the power-off timing code is basically the same as the power-on and power-off, only the delay time is different. When the power supply is abnormal, the PG outputs a low level. The logic code determines that if PG is 0, it enters the power-off process and the single board is powered off. The PG signal is judged in both the pre-monitor and monitor states.

[0054] In this embodiment, the CPLD chip monitors the status of the PG signals of each power supply by configuring the corresponding code. When it monitors that the PG signal is in an abnormal state, it determines that the power supply module corresponding to the PG signal in the abnormal state is the target power supply module.

[0055] When it is determined that there is a target power supply module with an abnormal PG signal, the CPLD chip can lock the current status information (i.e., the fault status information) of the target power supply module and record this current status information in the register of the CPLD chip.

[0056] In this embodiment, when the CPLD chip records the status information of the target power supply module in the register of the CPLD chip, it triggers the black box recording function. Specifically, it writes the current status information recorded in the register of the CPLD chip into the EEPROM.

[0057] In this embodiment, as Figure 4 shown, the black box recording function can be divided into four parts: writing to the black box, clearing the black box, reading the black box, and reading the power-off count.

[0058] Among them, the write black box state machine: has the highest priority. In the monitoring state, it judges the power supply PG status, immediately latches the PG status when an abnormality is found and triggers the write black box, and records the PG in the EEPROM. The black box recording is designed to write 4 items. After writing full, even if there is still a power-off, no more data is written to avoid overwriting the earliest power-off information.

[0059] Clear black box state machine: After reading the black box records, store them in the software log and clear the current records to reserve space for the next power-off.

[0060] Read black box state machine: Read the power status stored in the EEPROM.

[0061] Read power-off times: After the single board powers off, it is used to obtain how many times the power has abnormally powered off last time. This power-off continues to offset backward based on the last time to avoid overwriting the last power-off information.

[0062] Specifically, in the write black box state machine, mainly according to the timing sequence of the EEPROM, the waveform is simulated. The write operation requires two steps. The first step is to change the state of the EEPROM and enable the write. The write black box action is triggered by the power-on and power-off timing state machine. In the pre-monitoring and monitoring states, it is judged whether the power PG is abnormal. If it is abnormal, the state machine is triggered to enter the write black box process.

[0063] The second step is to write data: There are many pieces of data, and the delay for single write is at least 5ms. Since there is a large amount of data to write to the black box, the continuous write mode can be adopted.

[0064] In an example, the data corresponding to the EEPROM address is 8 bits, and 8 power statuses can be stored each time. Considering the complexity of the single board, 8 registers are reserved, with a total of 64 power statuses. Actually, 9 registers are reserved, and the first register is used to store the power-off times.

[0065] In this embodiment, clear black box: The actual waveform and timing of clearing the black box are the same as those of writing the black box. The only difference is that when writing the black box, the real power status is written, while when clearing the black box, all 1s are written to achieve the function of clearing the records. The main reason for doing this is that the EEPROM does not have the page erasure function and can only be overwritten by writing all 1s.

[0066] In this embodiment, read black box: It is used to read the power status information stored in the EEPROM. Among them, there is no delay requirement for the read timing sequence, and the single read method is adopted.

[0067] Among them, read power-off times: A total of 4 groups of power information can be stored. The read times are used to obtain how many times the power-off was stored last time and how much space is left for storage during this power-on. The code is designed not to store anymore after filling 4 groups, and it must be cleared before continuing to store.

[0068] In an example, the software read black box process: The SPI protocol is used between the CPLD and the EEPROM, and other protocols can be used between the CPU and the CPLD to indirectly access the EEPROM to obtain the black box data.

[0069] As can be seen from the above embodiments, the present disclosure can monitor each power supply module through a CPLD chip. When a target power supply module with abnormal power-on / off is detected, a black box record can be triggered, thereby realizing the replacement of ADM1166 with a CPLD to complete the power-on / off control and black box record functions.

[0070] Based on the above method embodiments, the embodiments of the present disclosure also provide a power supply device, which includes: a plurality of power supply modules and a CPLD chip.

[0071] The CPLD chip is connected to each power supply module to obtain the PG signal of each power supply module.

[0072] The CPLD chip monitors the PG signal status of each power supply through a monitoring module to determine a target power supply module with abnormal power-on / off.

[0073] The CPLD chip obtains the current status information of the target power supply module, records the current status information in the CPLD chip, and triggers a black box to record the current status information.

[0074] Among them, the CPLD chip obtains the PG signal of each power supply module through a 100us filtering module.

[0075] Among them, the CPLD chip monitors the PG signal status of each power supply through a monitoring module. When it monitors that the PG signal is in an abnormal state, it determines that the power supply module corresponding to the abnormal PG signal is the target power supply module.

[0076] Among them, the CPLD chip locks the current status information of the target power supply module and records the current status information in the register of the CPLD chip.

[0077] Among them, the CPLD chip triggers to write the current status information recorded in the register into the EEPROM.

[0078] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial descriptions of the method embodiments. The device embodiments described above are only illustrative. The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution in this specification. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0079] The above describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0080] Those skilled in the art will readily conceive of other embodiments of this specification after considering the specification and practicing the invention herein. This specification is intended to cover any variations, uses, or adaptations of this specification, which follow the general principles of this specification and include common general knowledge or conventional technical means in the technical field not claimed in this specification. The specification and examples are only to be considered as exemplary, and the true scope and spirit of this specification are pointed out by the following claims.

[0081] It should be understood that this specification is not limited to the exact structures described above and shown in the figures, and various modifications and changes can be made without departing from its scope. The scope of this specification is only limited by the appended claims.

[0082] The above are only the preferred embodiments of this specification and are not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of protection of this specification.

Claims

1. A method for managing power sequence, characterized in that: The method comprises: Use CPLD chip to obtain PG signal of each power module; The CPLD chip monitors the PG signal status of each power supply to determine the target power supply module with power-on / power-off anomalies; The current state information of the target power module is obtained, the current state information is recorded in the CPLD chip, and the black box is triggered to record the current state information.

2. The method according to claim 1, characterized in that The method of obtaining the PG signal of each power module by using the CPLD chip includes: The CPLD chip obtains the PG signal of each power module through the filter module.

3. The method according to claim 1, characterized in that The CPLD chip determines the target power module with power-on / power-off anomaly by monitoring the PG signal status of each power supply, including: The CPLD chip monitors the PG signal status of each power supply, and when it is monitored that the PG signal is in an abnormal state, it is determined that the power module corresponding to the PG signal in the abnormal state is the target power module.

4. The method according to claim 1, characterized in that: Acquiring current status information of a target power module and recording the current status information in the CPLD chip includes: The current status information of the target power module is locked and recorded in the register of the CPLD chip.

5. The method according to claim 4, characterized in that Trigger the black box to record the current status information, including: The trigger writes the current status information recorded in the register of the CPLD chip into the EEPROM.

6. A power supply device, characterized in that: The power supply device includes: a plurality of power supply modules and a CPLD chip, The CPLD chip is connected to each power module to obtain the PG signal of each power module: The CPLD chip monitors the PG signal status of each power supply through the monitoring module, and determines the target power supply module with power-on / power-off abnormality; The CPLD chip acquires current status information of the target power module, records the current status information in the CPLD chip, and triggers the black box to record the current status information.

7. The power supply device according to claim 6, characterized in that: The CPLD chip obtains the PG signal of each power module through the filter module.

8. The power supply device according to claim 6, characterized in that: The CPLD chip monitors the PG signal status of each power supply, and when it is monitored that the PG signal is in an abnormal state, determines that the power module corresponding to the PG signal in the abnormal state is the target power module.

9. The power supply device according to claim 6, characterized in that: The CPLD chip locks the current state information of the target power module and records the current state information in a register of the CPLD chip.

10. The power supply device according to claim 9, characterized in that: The CPLD chip triggers the current state information recorded in the register to be written into the EEPROM.

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