Analog multiplier with high linearity and large output swing

Abstract

The present invention belongs to the field of multipliers, and specifically relates to an analog multiplier with high linearity and large output swing. The analog multiplier includes a first common-mode level adjustable single-ended-to-differential circuit, a second common-mode level adjustable single-ended-to-differential circuit, and a folded CMOS Gilbert cell. The first common-mode level adjustable single-ended-to-differential circuit receives an analog input signal A and a common-mode level VCMA at its two input terminals, and outputs differential signals AP and AN to the first two input terminals of the folded CMOS Gilbert cell at its two output terminals. The second common-mode level adjustable single-ended-to-differential circuit receives an analog input signal B and a common-mode level VCMB at its two input terminals, and outputs differential signals BP and BN to the second two input terminals of the folded CMOS Gilbert cell at its two output terminals. The folded CMOS Gilbert cell outputs analog output signals OUTP and OUTN at its two output terminals. The present invention can significantly improve the linearity and output swing of the analog multiplier's output signal.

Description

Technical Field

[0001] The present invention relates to an analog multiplier, in particular to an analog multiplier with high linearity and large output swing. Background Art

[0002] In recent years, with the rapid development of signal processing systems and related technologies, the demand for high-performance signal processing components has increased significantly. As a common unit in signal processing components, the demand for analog multipliers has also increased accordingly. Traditional analog multipliers include Gilbert cells and CMOS four-quadrant analog multipliers.

[0003] Conventional Gilbert cells typically use transistors or MOS devices as core components, requiring at least four devices to be stacked in the path from power to ground. This results in a narrow linear output range when operating at low voltages, significantly limiting the linearity and output swing of the output signal. CMOS four-quadrant analog multipliers can output larger swings, but require differential input signals, and the common-mode levels of the two differential pairs must be consistent, which greatly inconveniences their application. Summary of the Invention

[0004] The purpose of the present invention is to solve the technical problems that the existing analog multiplier has a small linear output range when operating at low voltage, which greatly restricts the linearity and output swing of the output signal; or the required input signal is a differential signal, and the common mode levels of the two pairs of differential signals need to be consistent, which brings great inconvenience to its application. The present invention provides an analog multiplier with high linearity and large output swing.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] An analog multiplier with high linearity and large output swing, whose special features are:

[0007] It includes a first common-mode level adjustable single-ended to differential conversion circuit, a second common-mode level adjustable single-ended to differential conversion circuit, and a folded CMOS Gilbert unit;

[0008] The two input terminals of the first common-mode level adjustable single-ended to differential conversion circuit are respectively used to receive an external analog input signal A and a common-mode level VCMA, and the two output terminals respectively output a differential signal AP and a differential signal AN to the two first input terminals of the folded CMOS Gilbert cell;

[0009] The two input terminals of the second common-mode level adjustable single-ended-to-differential conversion circuit are respectively used to receive an external analog input signal B and a common-mode level VCMB, and the two output terminals respectively output a differential signal BP and a differential signal BN to the two second input terminals of the folded CMOS Gilbert cell;

[0010] The differential signal AP, the differential signal AN, the differential signal BP, and the differential signal BN satisfy the following equations respectively:

[0011]

[0012] The two output terminals of the folded CMOS Gilbert cell are used to output an analog output signal OUTP and an analog output signal OUTN respectively.

[0013] Furthermore, the first common-mode level adjustable single-ended-to-differential circuit and the second common-mode level adjustable single-ended-to-differential circuit each include a first amplifier module, a second amplifier module, a third amplifier module, a fourth amplifier module, and a fifth amplifier module;

[0014] The input end of the first amplifier module serves as one of the input ends of the first common-mode level adjustable single-ended to differential conversion circuit or the second common-mode level adjustable single-ended to differential conversion circuit, and is used to receive an external analog input signal A or an analog input signal B;

[0015] The output end of the first amplifier module is connected to the input end of the second amplifier module and the third amplifier module respectively, and the input end of the second amplifier module serves as another input end of the first common-mode level adjustable single-ended to differential circuit or the second common-mode level adjustable single-ended to differential circuit, for receiving an external common-mode level VCMA or a common-mode level VCMB;

[0016] The output ends of the second amplifier module and the third amplifier module are commonly connected to the input end of the fourth amplifier module;

[0017] The output end of the fourth amplifier module serves as one of the output ends of the first common-mode level adjustable single-ended to differential conversion circuit or the second common-mode level adjustable single-ended to differential conversion circuit, and is used to output the differential signal AP or the differential signal BP;

[0018] The input end of the fifth amplifier module is connected to the output end of the fourth amplifier module, and receives the external analog input signal A or the analog input signal B at the same time; the output end of the fifth amplifier module serves as another output end of the first common-mode level adjustable single-ended to differential circuit or the second common-mode level adjustable single-ended to differential circuit, and is used to output the differential signal AN or the differential signal BN.

[0019] Furthermore, the first amplifier module includes a first amplifier U1, a resistor R1, and a resistor R2; the second amplifier module includes a second amplifier U2, a resistor R3, and a resistor R4; the third amplifier module includes a third amplifier U3; the fourth amplifier module includes a fourth amplifier U4, a resistor R5, a resistor R6, a resistor R7, and a resistor R8; the fifth amplifier module includes a fifth amplifier U5, a resistor R9, a resistor R10, a resistor R11, and a resistor R12;

[0020] The IP terminal of the first amplifier U1 serves as the input terminal of the first amplifier module, and is used to receive the external analog input signal A or analog input signal B; the output terminal of the first amplifier U1 is connected to one end of the resistor R1 and the resistor R4, and is also connected to the IN terminal thereof;

[0021] One end of the resistor R3 is used to receive the external common-mode voltage level VCMA or VCMB. The other ends of the resistors R3 and R4 are connected together and then connected to the IP terminal of the second amplifier U2. The output terminal of the second amplifier U2 is connected to one end of the resistor R5 and also to its IN terminal.

[0022] The other end of the resistor R1 and one end of the resistor R2 are connected to the IP terminal of the third amplifier U3, and the other end of the resistor R2 is grounded; the output end of the third amplifier U3 is connected to one end of the resistor R6 and also to its IN terminal;

[0023] The other ends of the resistors R5 and R6 are commonly connected to the IP terminal of the fourth amplifier U4; one end of the resistor R7 is grounded, and the other end of the resistor R7 and one end of the resistor R8 are commonly connected to the IN terminal of the fourth amplifier U4; the other end of the resistor R8 and the output terminal of the fourth amplifier U4 are commonly connected to one end of the resistor R10, and are used to output the differential signal AP or the differential signal BP;

[0024] The other end of the resistor R10 and one end of the resistor R9 are commonly connected to the IP terminal of the fifth amplifier U5, and the other end of the resistor R9 is grounded; one end of the resistor R11 and one end of the resistor R12 are commonly connected to the IN terminal of the fifth amplifier U5; the other end of the resistor R11 is used to receive an external analog input signal A or an analog input signal B; the other end of the resistor R12 is connected to the output terminal of the fifth amplifier U5, and is used to output a differential signal AN or a differential signal BN.

[0025] Further, the folded CMOS Gilbert cell includes a transistor PM1, a transistor PM2, a transistor PM3, a transistor PM4, a transistor NM1, a transistor NM2, a transistor NM3, a transistor NM4, a transistor NM5, a transistor NM6, a current source IS, a resistor RX, a resistor RY, an input port 1, an input port 2, an input port 3, an input port 4, an output port 5, and an output port 6;

[0026] Input port 1 and input port 2 are two first input terminals of the folded CMOS Gilbert cell, connected to two output terminals of the first common-mode level-adjustable single-ended-to-differential conversion circuit; input port 3 and input port 4 are two second input terminals of the folded CMOS Gilbert cell, connected to two output terminals of the second common-mode level-adjustable single-ended-to-differential conversion circuit; output port 5 and output port 6 are two output terminals of the folded CMOS Gilbert cell;

[0027] The sources of the transistors PM1, PM2, PM3 and PM4 are connected to an external power supply VDD;

[0028] The gate of transistor PM1 is connected to the gate of transistor PM2, the drain of transistor PM2 and the drain of transistor NM3 respectively, and the gate of transistor PM3 is connected to the drain of transistor PM3, the gate of transistor PM4 and the drain of transistor NM4 respectively;

[0029] The drain of transistor PM1 is connected to the drains of transistor NM1 and transistor NM2 respectively, and the drain of transistor PM4 is connected to the drains of transistor NM5 and transistor NM6 respectively;

[0030] The gate of transistor NM1 is connected to input port 3, and the source is connected to output port 5;

[0031] The gate of transistor NM2 is connected to input port 4, and the source is connected to output port 6;

[0032] The gate of transistor NM3 is connected to the input port 1, and the source is connected to the positive electrode of the current source IS;

[0033] The gate of transistor NM4 is connected to the input port 2, and the source is connected to the positive electrode of the current source IS;

[0034] The gate of transistor NM5 is connected to input port 4, and the source is connected to output port 5;

[0035] The gate of transistor NM6 is connected to input port 3, and the source is connected to output port 6;

[0036] The negative electrode of the current source IS is grounded;

[0037] One end of the resistor RX and the resistor RY are connected to the output port 5 and the output port 6 respectively, and the other ends are grounded.

[0038] Furthermore, the voltage V of the analog output signal OUTP and the analog output signal OUTN OUT All satisfy the following equations:

[0039] V OUT =R×g mp ×g mn ×A×B

[0040] Where: R represents the resistance value of resistor RX and resistor RY, and the resistance value of resistor RX and resistor RY is the same; g mp g represents the transconductance of transistor PM1, transistor PM2, transistor PM3 and transistor PM4, and the transconductance of transistor PM1, transistor PM2, transistor PM3 and transistor PM4 are the same; mndenoting the transconductance of transistors NM1 , NM2 , NM3 , NM4 , NM5 and NM6 , which are the same.

[0041] The beneficial effects of the present invention are:

[0042] By introducing a single-ended to differential converter with adjustable common-mode levels, the present invention can set the analog multiplier to an operating range with the highest linearity and maximum output swing, significantly improving the linearity and output swing of the analog multiplier's output signal. This improvement offers the advantages of high linearity and large output swing, making it suitable for applications requiring high linearity and output swing.

[0043] The present invention adopts a folded CMOS Gilbert cell with a low-voltage structure, which can achieve low-voltage operation, low power consumption and large output swing. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural diagram of an embodiment of the present invention;

[0045] Figure 2 1 is a schematic structural diagram of a first common-mode level adjustable single-ended to differential converter circuit according to an embodiment of the present invention;

[0046] Figure 3 is a schematic structural diagram of a folded CMOS Gilbert cell according to an embodiment of the present invention;

[0047] Figure 4 It is a three-temperature simulation diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0048] To make the objectives, advantages, and features of the present invention more apparent, the following further describes in detail an analog multiplier with high linearity and large output swing proposed by the present invention, in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following specific embodiments.

[0049] See also Figure 1 In this embodiment, an analog multiplier with high linearity and large output swing is constructed by two common-mode level-adjustable single-ended-to-differential circuits of the same structure and a folded CMOS Gilbert cell as the main body, which can realize the function of multiplying analog input signals.

[0050] The two common-mode level-adjustable single-ended-to-differential circuits are respectively a first common-mode level-adjustable single-ended-to-differential circuit and a second common-mode level-adjustable single-ended-to-differential circuit, and the first common-mode level-adjustable single-ended-to-differential circuit and the second common-mode level-adjustable single-ended-to-differential circuit have the same structure.

[0051] like Figure 2 As shown, taking the first common-mode level adjustable single-ended to differential circuit as an example, the circuit includes five amplifier modules, namely a first amplifier module, a second amplifier module, a third amplifier module, a fourth amplifier module and a fifth amplifier module.

[0052] If the analog input signal of the first common-mode level adjustable single-ended to differential converter is represented by A, and the common-mode level of the analog input signal A is represented by VCMA, then the output of the first amplifier module is VCMA, and the output of the second amplifier module is The output of the third amplifier module is The output of the fourth amplifier module is The output of the fifth amplifier module is The outputs of the fourth amplifier module and the fifth amplifier module are a pair of differential signals with the common mode level VCMA as the common mode, and the swing amplitude of the differential signal is consistent with the swing amplitude of the original analog input signal A.

[0053] Similarly, the analog input signal of the second common-mode level adjustable single-ended-to-differential circuit can be represented by B, the common-mode level of the analog input signal B can be represented by VCMB, and the outputs of each amplifier module in the second common-mode level adjustable single-ended-to-differential circuit refer to the outputs of each amplifier module in the first common-mode level adjustable single-ended-to-differential circuit.

[0054] The two pairs of differential signals after passing through the first common-mode adjustable single-ended to differential circuit and the second common-mode adjustable single-ended to differential circuit are represented by AP, AN, BP and BN respectively, and we can get:

[0055]

[0056] The first amplifier module includes a first amplifier U1, a resistor R1, and a resistor R2; the second amplifier module includes a second amplifier U2, a resistor R3, and a resistor R4; the third amplifier module includes a third amplifier U3; the fourth amplifier module includes a fourth amplifier U4, a resistor R5, a resistor R6, a resistor R7, and a resistor R8; the fifth amplifier module includes a fifth amplifier U5, a resistor R9, a resistor R10, a resistor R11, and a resistor R12.

[0057] The IP terminal of the first amplifier U1 serves as the input terminal of the first amplifier module and is used to receive an external analog input signal A. Similarly, when the second common-mode level-adjustable single-ended-to-differential circuit is used, the IP terminal of the first amplifier U1 is used to receive an analog input signal B. The output terminal of the first amplifier U1 is connected to one end of resistor R1 and resistor R4, as well as their IN terminals. One end of resistor R3 is used to receive an external common-mode level VCMA. Similarly, when the second common-mode level-adjustable single-ended-to-differential circuit is used, one end of resistor R3 is used to receive a common-mode level VCMB. After the other ends of the resistors R3 and R4 are connected, they are commonly connected to the IP end of the second amplifier U2; the output end of the second amplifier U2 is connected to one end of the resistor R5 and also to its IN end; the other end of the resistor R1 and one end of the resistor R2 are commonly connected to the IP end of the third amplifier U3, and the other end of the resistor R2 is grounded; the output end of the third amplifier U3 is connected to one end of the resistor R6 and also to its IN end; the other ends of the resistors R5 and R6 are commonly connected to the IP end of the fourth amplifier U4; one end of the resistor R7 is grounded, and the other end of the resistor R7 and one end of the resistor R8 are commonly connected to the IN end of the fourth amplifier U4; the other end of the resistor R8 and the output end of the fourth amplifier U4 are commonly connected to one end of the resistor R10, and simultaneously serve as the output of the fourth amplifier module, for outputting the differential signal AP. Similarly, when the second common-mode level-adjustable single-ended-to-differential circuit is used, it is used to output a differential signal BP. The other end of resistor R10 and one end of resistor R9 are jointly connected to the IP terminal of the fifth amplifier U5, and the other end of resistor R9 is grounded. One end of resistor R11 and one end of resistor R12 are jointly connected to the IN terminal of the fifth amplifier U5. The other end of resistor R11 is used to receive an external analog input signal A. Similarly, when the second common-mode level-adjustable single-ended-to-differential circuit is used, it is used to receive an analog input signal B. The other end of resistor R12 is connected to the output terminal of the fifth amplifier U5 and serves as the output terminal of the fifth amplifier module, outputting a differential signal AN. Similarly, when the second common-mode level-adjustable single-ended-to-differential circuit is used, it is used to output a differential signal BN.

[0058] like Figure 3 As shown, the folded CMOS Gilbert cell includes transistor PM1, transistor PM2, transistor PM3, transistor PM4, transistor NM1, transistor NM2, transistor NM3, transistor NM4, transistor NM5, transistor NM6, current source IS, resistor RX, resistor RY, input port 1, input port 2, input port 3, input port 4, output port 5 and output port 6.

[0059] The sources of transistors PM1, PM2, PM3 and PM4 are connected to the external power supply VDD; the gate of transistor PM1 is connected to the gate of transistor PM2, the drain of transistor PM2 and the drain of transistor NM3 respectively, the gate of transistor PM3 is connected to the drain of transistor PM3, the gate of transistor PM4 and the drain of transistor NM4 respectively; the drain of transistor PM1 is connected to the drains of transistors NM1 and NM2 respectively, the drain of transistor PM4 is connected to the drains of transistors NM5 and NM6 respectively; the gate of transistor NM1 The gate of transistor NM2 is connected to input port 3, and the source is connected to output port 5; the gate of transistor NM2 is connected to input port 4, and the source is connected to output port 6; the gate of transistor NM3 is connected to input port 1, and the source is connected to the positive electrode of current source IS; the gate of transistor NM4 is connected to input port 2, and the source is connected to the positive electrode of current source IS; the gate of transistor NM5 is connected to input port 4, and the source is connected to output port 5; the gate of transistor NM6 is connected to input port 3, and the source is connected to output port 6; the negative electrode of current source IS is grounded; one end of resistor RX and one end of resistor RY are connected to output port 5 and output port 6 respectively, and the other ends are both grounded.

[0060] Input port 1 and input port 2 are the two first input terminals of the folded CMOS Gilbert unit, which are connected to the output terminals of the fourth amplifier module and the fifth amplifier module in the first common-mode level-adjustable single-ended-to-differential circuit; input port 3 and input port 4 are the two second input terminals of the folded CMOS Gilbert unit, which are connected to the output terminals of the fourth amplifier module and the fifth amplifier module in the second common-mode level-adjustable single-ended-to-differential circuit; output port 5 and output port 6 are the two output terminals of the folded CMOS Gilbert unit, which are used to output the analog output signal OUTP and the analog output signal OUTN, respectively.

[0061] The gate signals of transistors NM1 and NM6 are differential signals BP, the gate signals of transistors NM2 and NM5 are differential signals BN, the gate signal of transistor NM3 is differential signal AP, and the gate signal of transistor NM4 is differential signal AN.

[0062] The voltage V of the analog output signal OUTP and the analog output signal OUTN output by the folded CMOS Gilbert cell OUT for:

[0063] V OUT =R×g mp ×g mn ×A×B.

[0064] Where: R represents the resistance value of resistor RX and resistor RY, and the resistance value of resistor RX and resistor RY is the same; g mpg represents the transconductance of transistor PM1, transistor PM2, transistor PM3 and transistor PM4, and the transconductance of transistor PM1, transistor PM2, transistor PM3 and transistor PM4 are the same; mn denoting the transconductance of transistors NM1 , NM2 , NM3 , NM4 , NM5 and NM6 , which are the same.

[0065] See also Figure 4 In this embodiment, the voltage value of the analog input signal A is fixed at 0.25V, and the voltage value of the analog input signal B varies from 0.1V to 0.25V, that is, the horizontal axis ( Figure 4 The horizontal axis is in mV. The vertical axis is the voltage value of the two analog output signals OUTP and OUTN ( Figure 4 The vertical axis unit is V), and the multiplier gain is 25. The three lines represent the three-temperature simulation curves, namely -40℃ (light blue), 25℃ (dark blue) and 85℃ (red). Figure 4 It can be seen that the analog multiplier of this embodiment achieves higher linearity and larger output swing.

Claims

1. An analog multiplier with high linearity and large output swing, characterized in that: It includes a first common-mode level adjustable single-ended to differential conversion circuit, a second common-mode level adjustable single-ended to differential conversion circuit, and a folded CMOS Gilbert unit; The two input terminals of the first common-mode level adjustable single-ended-to-differential converter are respectively used to receive an external analog input signal A and a common-mode level VCMA, and the two output terminals respectively output a differential signal AP and a differential signal AN to the two first input terminals of the folded CMOS Gilbert cell; The two input terminals of the second common-mode level adjustable single-ended-to-differential conversion circuit are respectively used to receive an external analog input signal B and a common-mode level VCMB, and the two output terminals respectively output a differential signal BP and a differential signal BN to the two second input terminals of the folded CMOS Gilbert cell; The first common-mode level adjustable single-ended to differential circuit and the second common-mode level adjustable single-ended to differential circuit each include a first amplifier module, a second amplifier module, a third amplifier module, a fourth amplifier module and a fifth amplifier module; The input end of the first amplifier module serves as one of the input ends of the first common-mode level adjustable single-ended to differential circuit or the second common-mode level adjustable single-ended to differential circuit, and is used to receive an external analog input signal A or an analog input signal B; The output end of the first amplifier module is connected to the input end of the second amplifier module and the third amplifier module respectively, and the input end of the second amplifier module serves as another input end of the first common-mode level adjustable single-ended to differential circuit or the second common-mode level adjustable single-ended to differential circuit, for receiving an external common-mode level VCMA or common-mode level VCMB; The output ends of the second amplifier module and the third amplifier module are commonly connected to the input end of the fourth amplifier module; The output end of the fourth amplifier module serves as one of the output ends of the first common-mode level adjustable single-ended to differential conversion circuit or the second common-mode level adjustable single-ended to differential conversion circuit, and is used to output a differential signal AP or a differential signal BP; The input end of the fifth amplifier module is connected to the output end of the fourth amplifier module, and receives the external analog input signal A or the analog input signal B; the output end of the fifth amplifier module serves as another output end of the first common-mode level adjustable single-ended to differential conversion circuit or the second common-mode level adjustable single-ended to differential conversion circuit, and is used to output the differential signal AN or the differential signal BN; The differential signal AP, the differential signal AN, the differential signal BP, and the differential signal BN satisfy the following equations respectively: The two output terminals of the folded CMOS Gilbert cell are used to output an analog output signal OUTP and an analog output signal OUTN respectively.

2. The analog multiplier with high linearity and large output swing according to claim 1, wherein: The first amplifier module includes a first amplifier U1, a resistor R1, and a resistor R2; the second amplifier module includes a second amplifier U2, a resistor R3, and a resistor R4; the third amplifier module includes a third amplifier U3; the fourth amplifier module includes a fourth amplifier U4, a resistor R5, a resistor R6, a resistor R7, and a resistor R8; the fifth amplifier module includes a fifth amplifier U5, a resistor R9, a resistor R10, a resistor R11, and a resistor R12; The IP terminal of the first amplifier U1 serves as the input terminal of the first amplifier module, and is used to receive the external analog input signal A or analog input signal B; the output terminal of the first amplifier U1 is connected to one end of the resistor R1 and the resistor R4, and is also connected to the IN terminal thereof; One end of the resistor R3 is used to receive the external common-mode level VCMA or VCMB. The other ends of the resistor R3 and the resistor R4 are connected together and connected to the IP terminal of the second amplifier U2. The output end of the second amplifier U2 is connected to one end of the resistor R5 and also to its IN terminal. The other end of the resistor R1 and one end of the resistor R2 are connected to the IP terminal of the third amplifier U3, and the other end of the resistor R2 is grounded; the output end of the third amplifier U3 is connected to one end of the resistor R6 and also to its IN terminal; The other ends of the resistors R5 and R6 are commonly connected to the IP terminal of the fourth amplifier U4; one end of the resistor R7 is grounded, and the other end of the resistor R7 and one end of the resistor R8 are commonly connected to the IN terminal of the fourth amplifier U4; the other end of the resistor R8 and the output terminal of the fourth amplifier U4 are commonly connected to one end of the resistor R10, and are used to output the differential signal AP or the differential signal BP; The other end of the resistor R10 and one end of the resistor R9 are commonly connected to the IP terminal of the fifth amplifier U5, and the other end of the resistor R9 is grounded; one end of the resistor R11 and one end of the resistor R12 are commonly connected to the IN terminal of the fifth amplifier U5; the other end of the resistor R11 is used to receive an external analog input signal A or an analog input signal B; the other end of the resistor R12 is connected to the output terminal of the fifth amplifier U5, and is used to output a differential signal AN or a differential signal BN.

3. The analog multiplier with high linearity and large output swing according to claim 1 or 2, characterized in that: The folded CMOS Gilbert cell includes a transistor PM1, a transistor PM2, a transistor PM3, a transistor PM4, a transistor NM1, a transistor NM2, a transistor NM3, a transistor NM4, a transistor NM5, a transistor NM6, a current source IS, a resistor RX, a resistor RY, an input port 1, an input port 2, an input port 3, an input port 4, an output port 5, and an output port 6; The input port 1 and the input port 2 are two first input terminals of the folded CMOS Gilbert unit, connected to the two output terminals of the first common-mode level-adjustable single-ended-to-differential circuit; the input port 3 and the input port 4 are two second input terminals of the folded CMOS Gilbert unit, connected to the two output terminals of the second common-mode level-adjustable single-ended-to-differential circuit; the output port 5 and the output port 6 are two output terminals of the folded CMOS Gilbert unit; The sources of the transistors PM1, PM2, PM3 and PM4 are connected to an external power supply VDD; The gate of the transistor PM1 is connected to the gate of the transistor PM2, the drain of the transistor PM2 and the drain of the transistor NM3 respectively, and the gate of the transistor PM3 is connected to the drain of the transistor PM3, the gate of the transistor PM4 and the drain of the transistor NM4 respectively; The drain of the transistor PM1 is connected to the drains of the transistor NM1 and the transistor NM2 respectively, and the drain of the transistor PM4 is connected to the drains of the transistor NM5 and the transistor NM6 respectively; The gate of the transistor NM1 is connected to the input port 3, and the source is connected to the output port 5; The gate of the transistor NM2 is connected to the input port 4, and the source is connected to the output port 6; The gate of the transistor NM3 is connected to the input port 1, and the source is connected to the positive electrode of the current source IS; The gate of the transistor NM4 is connected to the input port 2, and the source is connected to the positive electrode of the current source IS; The gate of the transistor NM5 is connected to the input port 4, and the source is connected to the output port 5; The gate of the transistor NM6 is connected to the input port 3, and the source is connected to the output port 6; The negative electrode of the current source IS is grounded; One end of the resistor RX and the resistor RY are connected to the output port 5 and the output port 6 respectively, and the other ends are both grounded.

4. The analog multiplier with high linearity and large output swing according to claim 3, wherein: The voltage V of the analog output signal OUTP and the analog output signal OUTN OUT All satisfy the following equations: In OUT =R×g mp ×g mn ×A×B Where: R represents the resistance value of resistor RX and resistor RY, and the resistance value of resistor RX and resistor RY are the same; g mp g represents the transconductance of transistor PM1, transistor PM2, transistor PM3 and transistor PM4, and the transconductance of transistor PM1, transistor PM2, transistor PM3 and transistor PM4 are the same; mn denoting the transconductance of transistors NM1 , NM2 , NM3 , NM4 , NM5 and NM6 , which are the same.

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