Task processing method, system on chip and electronic equipment

Abstract

The invention discloses a task processing method, a system-on-chip and electronic equipment, the electronic equipment comprises the system-on-chip, and the system-on-chip comprises a plurality of processor core clusters arranged in sequence; each processor core cluster comprises at least one first processor core, at least one second processor core, at least one third processor core and a second-level cache shared by the at least one first processor core, the at least one second processor core and the at least one third processor core; wherein the computing performances of the first processor core, the second processor core and the third processor core are different.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a task processing method, a system on a chip, and an electronic device. Background Art

[0002] In order to improve the processing performance of processors in electronic devices, multi-core processors are increasingly widely used.

[0003] In order to reduce the power consumption of electronic devices, different types of processor cores can be provided in a multi-core processor. The electronic device can select the required processor core according to the task execution requirements, or switch the task between multiple processor cores. In cases where the task needs to be switched from one processor core to another for execution, etc., task data needs to be transferred between different processor cores. However, currently, the latency of data interaction between different types of processor cores is relatively high, resulting in latency in task processing. Summary of the Invention

[0004] On the one hand, this application provides a system on a chip, including:

[0005] A plurality of processor core clusters arranged in sequence;

[0006] Wherein, each processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core, and a secondary cache shared by the at least one first processor core, at least one second processor core, and at least one third processor core;

[0007] Wherein, the computing performances of the first processor core, the second processor core, and the third processor core are different.

[0008] In a possible implementation, the system on a chip further includes: a tertiary cache shared by the plurality of processor core clusters.

[0009] In another possible implementation, a first subset composed of the at least one first processor core, a second subset composed of the at least one second processor core, and a third subset composed of the at least one third processor core are arranged in sequence.

[0010] In another possible implementation, the processor core cluster further includes: a core scheduling module communicatively connected to the first processor core, the second processor core, and the third processor core, configured to determine a first target processor core for processing the target task from the processor core cluster when the processor core cluster is determined to be a target processor core cluster that needs to process the target task, and the first target processor core belongs to at least one of the at least one first processor core, at least one second processor core, and at least one third processor core in the processor core cluster.

[0011] In yet another possible implementation, the first processor core, the second processor core, and the third processor core each have their own level-1 cache;

[0012] The first target processor core is configured to process the target task; during the process of processing the target task, determine a first cache mirror area from the level-2 cache corresponding to the processor core cluster; and synchronize the task data cached in its level-1 cache by the first target processor core to the first cache mirror area.

[0013] In yet another possible implementation, the core scheduling module is further configured to, if it is determined that the target task needs to be switched from the first target processor core to a second target processor core in the processor core cluster, send a first task switching command to the second target processor core, where the first task switching command is used to instruct to switch the target task processed by the first target processor core to the second target processor core;

[0014] wherein the second target processor core belongs to at least one first processor core, at least one second processor core, and at least one third processor core in the processor core cluster, and the second target processor core is different from the first target processor core;

[0015] The second target processor core is configured to, in response to the first task switching command, determine the first cache mirror area corresponding to the first target processor core; and process the target task based on the task data of the target task cached in the first cache mirror area.

[0016] In yet another possible implementation, the core scheduling module is further configured to, if it is determined that the target task needs to be switched from the first target processor core to a second target processor core in the processor core cluster, send a second task switching command to the first target processor core, where the second task switching command is used to indicate that the target task is to be switched to another processor core;

[0017] The first target processor core is further configured to, in response to the second task switching command, synchronize the task data in its level-1 cache that has not been synchronized to the first cache mirror area to the first cache mirror area.

[0018] In yet another possible implementation, the second target processor core is further configured to, when it is confirmed that the task data of the target task in the first cache mirror area has been read, send a mirror clearing indication to the first target processor core;

[0019] The first target processor core is further configured to, in response to the mirror clearing indication, clear the task data of the target task cached in the first cache mirror area.

[0020] In yet another possible implementation, the second target processor core is further configured to determine a second cache mirror area from its corresponding secondary cache during the process of processing the target task; and synchronize the task data cached by the second target processor core in its primary cache to the second cache mirror area.

[0021] In another aspect, the present application provides an electronic device, including: a system-on-chip, where the system-on-chip includes a plurality of processor core clusters arranged in sequence;

[0022] Wherein, each processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core, a core scheduling module, and a secondary cache shared by the at least one first processor core, the at least one second processor core, and the at least one third processor core;

[0023] Wherein, the computing performances of the first processor core, the second processor core, and the third processor core are different;

[0024] The system-on-chip is configured to run an operating system; determine a target processor core cluster for processing a target task from the plurality of processor core clusters through the operating system; determine a first target processor core for processing the target task from the target processor core cluster through the core scheduling module in the target processor core cluster; and process the target task through the first target processor core.

[0025] In another aspect, the present application provides a task processing method, including:

[0026] Determine a target processor core cluster for processing a target task from a plurality of processor core clusters, where the processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core, and a secondary cache shared by the first processor core and the second processor core, and the computing performances of the first processor core, the second processor core, and the third processor core are different;

[0027] Determine a first target processor core for processing the target task from the target processor core cluster through the core scheduling module in the target processor core cluster;

[0028] Process the target task through the first target processor core. Description of the Drawings

[0029] In combination with the accompanying drawings and with reference to the following specific embodiments, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic and the original elements and elements are not necessarily drawn to scale.

[0030] Figure 1 Schematic diagram of a composition structure of a system-on-chip provided in this application;

[0031] Figure 2 Another schematic diagram of a composition structure of a system-on-chip provided in this application;

[0032] Figure 3 Schematic example diagram of the composition structure of the system-on-chip provided in this application in an application scenario;

[0033] Figure 4 Schematic diagram of a composition structure of a processor core cluster in the system-on-chip provided in this application;

[0034] Figure 5 An interaction example diagram for controlling a task to switch between different processor cores in a processor core cluster in this application;

[0035] Figure 6 Schematic flowchart of a task processing method provided in this application;

[0036] Figure 7 Schematic diagram of a composition architecture of an electronic device provided in this application. Specific Embodiments

[0037] The following describes the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. The terms used in the embodiments part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0038] The terms "first", "second", etc. in the specification and claims of the present application and the above accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing when describing objects with the same attributes in the embodiments of the present application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device comprising a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices.

[0039] AsFigure 1 , which shows a schematic diagram of a composition architecture of a system on a chip provided by this application.

[0040] As Figure 1 can be seen, the system on a chip 10 includes a plurality of processor core clusters 11 arranged in sequence.

[0041] Among them, each processor core cluster includes: at least one first processor core 111, at least one second processor core 112, at least one third processor core 113, and a secondary cache 114 shared by the at least one first processor core, the at least one second processor core, and the at least one third processor core.

[0042] In this application, the processor cores in each processor core cluster belong to the same type of processor cores. Among them, based on the different types of the system on a chip, the types of processor cores to which the processor cores on the system on a chip belong are also different. For example, the processor cores in the processor core cluster can be central processing unit (CPU) cores, graphics processing unit (GPU) cores, or neural network processing unit (NPU) cores, etc., without limitation.

[0043] However, the first processor core, the second processor core, and the third processor core belong to different types of processor cores under the same type of processor. Therefore, the computing performances of the first processor core, the second processor core, and the third processor core are different.

[0044] For example, the first processor core has the highest processing performance but also higher power consumption; the processing performance of the second processor core is lower than that of the first processor core but higher than that of the third processor core, and the power consumption is relatively low; the third processor core has the lowest processing performance and the lowest power consumption. For example, the first processor core, the second processor core, and the third processor core can be performance cores (abbreviated as P cores), energy-efficient cores (abbreviated as E cores), and low-power energy-efficient cores (abbreviated as LPE cores), respectively.

[0045] Different from the current situation where a secondary cache is separately set inside each processor core, in this application, the processor cores within the same processor core cluster share the same secondary cache, so that the processor cores within the same processor core cluster can realize data interaction through the shared secondary cache without having to go through the tertiary cache to realize data interaction.

[0046] As can be seen from the above, in this application, the processor cores of the system-on-chip are arranged in the form of processor core clusters. Each processor core cluster includes a first processor core, a second processor core, and a third processor core with different computing performances, and the processor cores in the processor core cluster share the same level-2 cache. On this basis, the processor cores in the same processor core cluster can achieve data interaction through the level-2 cache in the processor core cluster, shortening the data transmission distance between the processor cores in the processor core cluster, thereby reducing the data interaction latency between the processor cores in the processor core cluster, and further reducing the task processing latency caused by the interaction of data between the processor cores.

[0047] In addition, since each type of processor core cluster includes multiple processor cores, and different processor core clusters are arranged in sequence on the system-on-chip, it is possible to effectively reduce the situation where the same type of processor cores are arranged concentratedly. For example, it can reduce the situation where the first processor cores with high power consumption are concentrated and closely arranged together, thereby reducing the impact on the heat dissipation of the processor cores due to the concentrated arrangement of the same type of processor cores, enabling the processor cores on the system-on-chip to dissipate heat better.

[0048] Furthermore, in order to enable the processor cores in the system-on-chip to dissipate heat better, in this application, in each processor core cluster, at least one first processor core forms a first subset, at least one second processor core forms a second subset, and the at least one third processor core forms a third subset, and the first subset, the second subset, and the third subset are arranged in sequence.

[0049] Since the same type of processor cores in the processor core cluster are concentratedly arranged together to form a subset, and different subsets are arranged in sequence, it can effectively avoid the situation where the same type of processor cores in different processor core clusters are concentratedly arranged in large numbers, which affects the heat dissipation of the processor cores.

[0050] Combined with Figure 1 for illustration, in Figure 1Taking the example that each processor core cluster 11 includes one first processor core, two second processor cores, and multiple third processor cores. On this basis, in each processor core cluster 11, they are arranged in the order of a first subset composed of one first processor core, a second subset composed of two second processor cores, and a third subset composed of multiple third processor cores. Based on this arrangement of the first subset, second subset, and third subset in the processor cores, it is possible to evenly distribute various processor cores in different processor core clusters, and the same processor core in different processor cores is not adjacent. For example, the first processor core in one processor core cluster is not adjacent to the first processor cores in other processor core clusters. Therefore, even if the power consumption of the first processor core is relatively high, since the first processor cores on the system-on-chip are not concentrated together, the heat dissipation efficiency of the first processor core can be greatly improved.

[0051] It should be noted that the number of each type of processor core in the processor core cluster can be set according to actual needs and is not limited in this regard. For example, in the processor core cluster, it can also be set to: two first processor cores, three second processor cores, and two third processor cores.

[0052] To facilitate the reasonable arrangement of each processor core cluster and reduce the design complexity of the system-on-chip, the number of the same type of processor core included in different processor core clusters can be the same. Of course, the number of the same type of processor core in different processor core clusters can also be different and is not limited in this regard.

[0053] It can be understood that in order to realize data interaction between the processor cores in different processor core clusters in the system-on-chip, the system-on-chip also includes a three-level cache. As Figure 2 shown, the system-on-chip also includes a three-level cache 12 shared by each processor core cluster. For example, the processor cores in each processor core cluster can be connected to this three-level cache through a bus or the like, and there is no limit to the specific way of establishing the connection between each processor core and the three-level cache.

[0054] On this basis, the processor cores within different processor core clusters can all obtain data from the three-level cache and cache data into the three-level cache, and the processor cores within different processor core clusters can achieve data interaction through the three-level cache.

[0055] It can be understood that considering that the processor core may need to cache data during operation, based on this, on the system-on-chip of the present application, the first processor core, second processor core, and third processor core in any one processor core cluster all have their own first-level caches. As Figure 2It can be seen that each processor core internally has its own level-1 cache 115. Based on this, the level-1 cache within each processor core, the level-2 cache shared by the processor cores in the processor core cluster, and the level-3 cache shared by different processor cores in the processor core cluster constitute the three-level cache system of the system-on-chip.

[0056] It can be understood that in practical applications, the system-on-chip may also be provided with other components. For example, the system-on-chip may also be provided with a memory controller, Low Power Double Data Rate (LPDDR) memory, and an integrated graphics processor, etc., without limitation.

[0057] For the sake of easy understanding of the composition and arrangement form of each processor core cluster in the system-on-chip of the present application, hereinafter, taking the first processor core as the P core, the second processor core as the E core, and the second processor core as the LPE core as an example, a possible composition structure of the system-on-chip of the present application will be described.

[0058] As Figure 3 , a schematic diagram of the composition architecture of the system-on-chip provided by the present application in an application scenario is shown.

[0059] From Figure 3 it can be seen that the system-on-chip 30 includes a plurality of processor core clusters 31 arranged in sequence. Each processor core cluster 31 includes one P core, two E cores, and two LPE cores.

[0060] Moreover, the two E cores are arranged adjacent to each other to form an E core subset, and the two LPE cores are arranged adjacent to each other to form an LPE core subset. Correspondingly, the P core, the E core subset formed by the two E cores, and the LPE core subset formed by the two LPE cores are arranged in sequence in the processor core cluster. Based on this arrangement, the P cores in different processor core clusters are separated by E cores and LPE cores, making the different P cores different from each other. Similarly, the E cores in different processor core clusters are not adjacent to each other, and the LPEs in different processor core clusters are not connected to each other, making various types of processor cores relatively evenly arranged on the system-on-chip, avoiding the situation of ineffective heat dissipation caused by the concentrated arrangement of high-performance processor cores, and being beneficial to improving the heat dissipation of the processor cores.

[0061] From Figure 3 it can be seen that a level-1 cache is provided inside each P core, E core, and LPE core. For the sake of easy distinction, in Figure 3 the level-1 cache within the P core is marked as level-1 cache P, the level-1 cache within the E core is marked as level-1 cache E, and the level-1 cache within the LPE core is marked as level-1 cache LP. For any processor core cluster 31, the P cores, E cores, and LPE cores within the processor core cluster 31 share a level-2 cache.

[0062] In addition, each processor core cluster shares a level-3 cache. Taking the level-3 cache including multiple level-3 cache modules, namely level-3 cache 1, level-3 cache 2, level-3 cache 3, and level-3 cache 4, as an example in Figure 3 it.

[0063] It can be understood that since the P cores, E cores, and LPE cores in the same processor core cluster share the same level-2 cache, these processor cores can achieve data interaction through the shared level-2 cache. Compared with the case where each processor core needs to perform data interaction through the level-3 cache of the system-on-chip, the communication distance between the P cores, E cores, and LPE cores within the processor core cluster is shortened, and the data interaction latency can be reduced.

[0064] It can be understood that in order to be able to allocate tasks to the processor cores within the processor core cluster and control the switching of tasks between different processor cores in the processor core cluster, in this application, each processor core cluster within the system-on-chip further includes: a core scheduling module communicatively connected to the first processor core, the second processor core, and the third processor core in the processor core cluster. As Figure 4 shown, it shows a schematic diagram of a composition architecture of a processor core cluster in the system-on-chip provided in this application.

[0065] From Figure 4 it can be seen that in addition to including at least one first processor core 111, at least one second processor core 112, at least one third processor core 113, and a level-2 cache 114, each processor core cluster further includes a core scheduling module 116 communicatively connected to each of the first processor core, the second processor core, and the third processor core.

[0066] Among them, the core scheduling module is configured to determine a first target processor core for processing the target task from the processor core cluster when the processor core cluster is determined to be a target processor core cluster that needs to process the target task. Among them, the first target processor core belongs to at least one of the first processor core, at least one of the second processor core, and at least one of the third processor core in the processor core cluster.

[0067] For example, an operating system can run on the system-on-chip, and the operating system can run on at least one processor core in at least one processor core cluster of the system-on-chip, without specific limitation. The system-on-chip can determine a target processor core cluster for processing the target task from multiple processor core clusters of the system-on-chip through the operating system.

[0068] The tasks mentioned in this application can be generated by applications in the electronic device where the system-on-chip is located. For example, an application can run one or more application processes, and each task can correspond to at least one application process that needs to be run in the application.

[0069] In this embodiment, for the convenience of distinction, when the core scheduling module obtains the target task to be allocated to the processor core cluster, the processor core to be processed for the target task is called the first target processor core.

[0070] Among them, there are various possible implementation manners for the core scheduling module to determine the first target processor core from the processor core cluster where it is located.

[0071] In one possible implementation manner, the core scheduling module may determine the first target processor core suitable for processing the target task based on the task type of the target task. For example, if the task type of the target task indicates that the target task is a task with high requirements for data processing speed, then the target task can be allocated to the first processor core with high processing performance and in an idle state in the processor core cluster. If the task type of the target task indicates that the target task has low requirements for data processing speed but needs to run for a long time, then the target task can be allocated to the second processor core with moderate processing performance but relatively low power consumption in the processor core cluster.

[0072] In another possible implementation manner, the core scheduling module may determine the power consumption requirement of the target task. For example, based on the source of the target task and the power consumption requirements of similar target applications in history, etc., determine the power consumption requirement of the target task. On this basis, based on the power consumption requirement of the target task, determine the first target processor core suitable for processing the target task from the processor core cluster. For example, if the power consumption requirement of the target task is high, determine the first target processor core from the first processor core in an idle state; if the power consumption requirement of the target task is relatively low, the first target processor core can be determined from the second processor core in an idle state; if the power consumption requirement of the target task is very low, determine the first target processor core from the third processor core in an idle state.

[0073] In another possible implementation manner, the core scheduling module may also determine the task processing complexity of the target task. For example, determine the task processing complexity based on the micro-instructions corresponding to the target task, etc. Based on the task processing complexity, determine the first target processor core from the processor core cluster.

[0074] Of course, in practical applications, the core scheduling module may also comprehensively determine the first target processor core by combining multiple types of information such as the task type, power consumption requirement, and task processing complexity of the target task, and there is no specific limitation.

[0075] It should be noted that in practical applications, a task may also need to be assigned to multiple processor cores for processing. In this case, there may be multiple first target processor cores. When there are multiple first target processor cores, the specific implementations of task processing and task switching on each first target processor core in this application are similar and will not be elaborated here.

[0076] It can be understood that there may be multiple tasks to be assigned by the system at the same time slice, but the processing of each task is similar to the process of allocating and processing the target task and will not be elaborated here.

[0077] It can be understood that there may be interactions of task data between different processor cores in the same processor core cluster. For example, during the process of the first target processor core processing the target task, the power consumption requirement of the target task may change. In this case, in order to make reasonable use of the processor core resources in the processor core cluster, it involves switching the target task from the first target processor core to other processor cores in the processor core cluster where the first target processor core is located. In this case, it will be necessary to share the task data generated by the first target processor core running the target task with the processor core to which the target task is to be switched. Of course, there may be other possibilities for the interaction of task data between different processor cores in the processor core cluster, and this is not restricted.

[0078] On the premise that the first processor core, the second processor core, and the third processor core all have their own level-1 caches, if other processor cores obtain data from the level-1 cache of the first target processor core, then the data needs to be transmitted from the level-1 cache of the first target processor core to the level-2 cache first, and then other processor cores can obtain the task data from the level-2 cache, resulting in a certain delay in data transmission.

[0079] Based on this, in order to further reduce the data delay of the interaction of task data between different processor cores in the processor core cluster, in this application, the first target processor core is used to process the target task; during the process of processing the target task, determine the first cache mirror area corresponding to the first target processor core from the level-2 cache corresponding to the processor core cluster; synchronize the task data cached in its level-1 cache by the first target processor core to the first cache mirror area.

[0080] Among them, the cache mirror area can also be called the level-1 cache mirror, which refers to the cache area determined (or constructed) by the processor core in the level-2 cache and used as the mirror of the level-1 cache of the processor core. For the convenience of distinction, the level-1 cache mirror determined by the first target processor core in the level-2 cache is called the first cache mirror area.

[0081] Such as Figure 4It can be seen that during the process of processing tasks by each processor core in the processor core cluster, a cache mirror area corresponding to the level-1 cache within the processor core can be determined in the level-2 cache. For the sake of easy distinction, in Figure 4 the cache mirror area corresponding to the first processor core is referred to as level-1 cache mirror a, the cache mirror area corresponding to the second processor core is referred to as level-1 cache mirror b, and the cache mirror area corresponding to the third processor core is referred to as level-1 cache mirror c.

[0082] It can be understood that since the first cache mirror area belongs to the level-2 cache, after the first target processor core synchronizes the task data cached in its level-1 cache to this first cache mirror area, other processor cores in the same processor core cluster as the first target processor core can directly obtain the task data generated by the first target processor core from this first cache mirror area. Therefore, when data interaction is required, other processor cores do not need to wait for the first target processor core to first transfer the task data to the level-2 cache, but can access the first cache mirror area of this level-2 cache, reducing data interaction latency and improving data interaction efficiency.

[0083] On this basis, considering that during the process of the first target processor core processing the target task, the power consumption requirement of the target task, etc. may change. On this basis, in order to be able to reasonably utilize the resources of the processor cores in the system-on-chip, in this application, it is also possible to control the switching of the target task from the first target processing core to other processor cores in the processor core cluster where the first target processor core is located.

[0084] For example, assume that the first target processor core is the first processing core with the highest processing performance and the highest power consumption in the processor core cluster. During the process of the first target processor core processing the target task, if the power consumption requirement of the target task decreases and the requirement for processing performance also decreases accordingly. In this case, if the target task is still processed by the first target processor core with a relatively high power consumption, it will cause waste of resources. On this basis, the target task can be switched to the second processor core with relatively low power consumption and moderate processing performance; if the target task is in the background running state and the power consumption requirement is extremely low, then the target task can also be switched to the third processor core with even lower power consumption.

[0085] Based on this, in this application, the core scheduling module 116 can also be used to send a first task switching command to the second target processor core if it is determined that the target task needs to be switched from the first target processor core to the second target processor core in the processor core cluster.

[0086] Wherein, the first task switching command is used to instruct to switch the target task processed by the first target processor core to the second target processor core.

[0087] Among them, the second target processor core belongs to at least one first processor core, at least one second processor core, and at least one third processor core in the processor core cluster where the first target processor core is located, and the second target processor core is different from the first target processor core. Generally, the type of the second target processor core is different from the type of the first target processor core. For example, if the first target processor core is a first processor core, then the second target processor core can be a second processor core or a third processor core.

[0088] Correspondingly, the second target processor core is configured to determine the first cache mirror area corresponding to the first target processor core in response to the first task switching command; and process the target task based on the task data of the target task cached in the first cache mirror area.

[0089] For example, the second target processor core can read the task processing of the target task from the first cache mirror area to process the target task.

[0090] Among them, there are multiple possible ways for the second target processor core to determine the first cache mirror area. For example, there is a communication connection between different processor cores in the system-on-chip. Therefore, the second target processor core can request the first target processor core for the location information of the first cache mirror area in the secondary cache. Another example is that the core scheduling module can confirm the cache mirror areas of each processor core in the secondary cache. On this basis, the first task switching command sent by the core scheduling module to the second target processing core can also indicate the location information of the first cache mirror area in the secondary cache corresponding to the second target processor core.

[0091] Furthermore, in order to reduce the situation that after the target task is switched from the first target processor core to the second target processor core, some task data related to the target task in the first target processor core is not synchronized to the first cache mirror area, resulting in delays in the second target processor core processing the target task. In this application, the core scheduling module is further configured to, if it is determined that the target task needs to be switched from the first target processor core to the second target processor core in the processor core cluster, send a second task switching command to the first target processor core.

[0092] Among them, the second task switching command is used to indicate that the target task is to be switched to other processor cores, so that the first target processor core can know that the target task needs to be transferred to other processor cores and needs to synchronize the task data to the first cache mirror area.

[0093] Correspondingly, the first target processor core is further configured to, in response to the second task switching command, synchronize the task data in its level-1 cache that has not been synchronized to the first cache mirror area to the first cache mirror area. Based on this, the first target processor core can timely synchronize all the task data of the target task to the first cache mirror area, which can reduce the situation where the second target processor core needs to wait for the first target processor core to synchronize the task data, and is beneficial to reducing the situation where the second target processor core cannot process the target task in a timely manner due to insufficient task data of the target task.

[0094] It can be understood that after the target task is transferred from the first target processor core to the second target processor core, if the second target processor core has already read all the task data related to the target task from the first cache mirror area, then the second target processor core does not need to access the task data of the target task in the first cache mirror area anymore.

[0095] Based on this, in order to reduce the consumption of storage resources, in this application, the second target processor core is further configured to, when it is confirmed that the task data of the target task in the first cache mirror area has been read, send a mirror clearing instruction to the first target processor core. The mirror clearing instruction is used to instruct to clear the task data of the target task.

[0096] Correspondingly, the first target processor core is further configured to, in response to the mirror clearing instruction, clear the task data of the target task cached in the first cache mirror area.

[0097] Furthermore, considering that during the process of the second target processor core processing the target task, considering that the power consumption requirement of the target task may still change, or other processor cores may have the possibility of obtaining the relevant data of the target task in the second target processor core, based on this, the second target processor core can also be used to, during the process of processing the target task, determine a second cache mirror area from its corresponding level-2 cache; synchronize the task data cached by the second target processor core in its level-1 cache to the second cache mirror area.

[0098] For the convenience of distinction, in this application, the level-1 cache mirror area created by the second target processor core in the level-2 cache is referred to as the second cache mirror area.

[0099] To facilitate the understanding of the situation of switching a task from one processor core in the processor core cluster to another processor core in this application, the following takes Figure 3 the architecture of the system-on-chip shown as an example and describes it in combination with a scenario.

[0100] Take Figure 3Taking a cluster of processor cores as an example, assume that during the process of a P-core in the cluster of processor cores handling a target task, it is found that the power consumption requirement of the target task decreases. For example, the target task may only need to run in the background, or the data to be processed by the target task decreases, etc. On this basis, considering that the P-core has a high power consumption, consumes a large amount of power, and generates a high amount of heat, therefore, the target task on the P-core can be transferred to the E-core for processing, and the E-core continues to process the target task.

[0101] In addition, from Figure 3 it can be seen that in a cluster of processor cores, each processor core can create a cache mirror area corresponding to the level-1 cache within the processor core in the level-2 cache during the process of running a task. For example, in Figure 3 , the P-core has a level-1 cache p, the E-core has a level-1 cache E, and the LPE-core has a level-1 cache LP. Correspondingly, the P-core can create a cache mirror area in the level-2 cache corresponding to the level-1 cache P, that is, the level-1 cache mirror P; similarly, the level-2 cache also has a level-1 cache mirror E corresponding to the level-1 cache E of the E-core, and a level-1 cache mirror LE corresponding to the LPE-core.

[0102] It should be noted that Figure 3 this is just an example. In reality, the level-1 cache mirrors corresponding to the same type of processor cores in the same cluster of processor cores are also different. For example, different P-cores in the same cluster of processor cores can have their own different level-1 cache mirrors (i.e., cache mirror areas) in the level-2 cache. In addition, if the processor core is not running a task, then there may not be a cache mirror area corresponding to the processor core in the level-2 cache.

[0103] Based on the above assumptions, during the process of the target task being switched from the P-core to the E-core, the interaction between the P-core and the E-core can be referred to Figure 5 as shown.

[0104] From Figure 5 it can be known that in step S501, during the process of the P-core running the target task, the P-core will mirror the task data of the target task cached in its level-1 cache to the level-1 cache mirror P corresponding to the P-core in the level-2 cache.

[0105] Of course, when the P-core determines that the target task needs to be switched to the E-core, it will also continue to synchronize the task data that has not been synchronized to the level-1 cache mirror P in its level-1 cache to the level-1 cache mirror P.

[0106] In step S502, when the E-core confirms that it needs to process the target task, the E-core will read the task data of the target task from the level-1 cache mirror P and continue to execute the target task.

[0107] In step S503, the E core confirms that all task data of the target task recorded in the first-level cache image P has been read, and the E core sends an image clearing instruction to the P core.

[0108] In step S504, in response to the image clearing instruction, the P core clears the data recorded in the first-level cache image P to release the first-level cache image P.

[0109] In step S505, the E core processes the target task, and during the process of processing the target task, mirrors the task data of the target task recorded in the first-level cache in the E core to the first-level cache image E corresponding to the E core in the second-level cache.

[0110] Of course, Figure 5 only taking one case as an example to illustrate, for the case of switching the target task on the P core to the LPE core, the operations performed by the LPE core Figure 5 are similar to those performed by the E core. In addition, when the power consumption requirement of the target task increases, the target task on the E core can be switched to the P core, and the specific processing is also similar, which will not be elaborated here.

[0111] Based on the composition structure and corresponding functions of the on-chip system of the present application, the present application also provides a task processing method. As Figure 6 , a schematic flowchart of a task processing method provided by the present application is shown. The method of this embodiment is applicable to an electronic device, and the electronic device includes the on-chip system mentioned above. The method of this embodiment includes:

[0112] S601, determine a target processor core cluster for processing a target task from multiple processor core clusters.

[0113] Among them, the target processor core cluster belongs to multiple processor core clusters in the on-chip system of the electronic device. Among them, each processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core, and a second-level cache shared by the first processor core and the second processor core. For the processor core cluster, reference can be made to the relevant introduction above, and details will not be elaborated here.

[0114] For example, the operating system can determine the target processor core cluster that needs to process the target task from the processor core cluster. Among them, the operating system can run on at least one processor core of at least one processor core cluster of the on-chip system, and there is no specific limitation.

[0115] Among them, there can be multiple specific implementations for determining the target processor core cluster, which are not specifically limited. For example, it can be comprehensively determined by combining the load conditions of each processor core in each processor core cluster in the system-on-chip, the number and types of processor cores in the idle state, as well as the task type and power consumption requirements of the target task, etc., to determine the target processor core cluster suitable for processing the target task.

[0116] S602, determine a first target processor core for processing the target task from the target processor core cluster through the core scheduling module in the target processor core cluster.

[0117] Among them, for the specific implementation of the core scheduling module in the target processor core cluster to determine the first target processor core, reference can be made to the relevant introduction above and will not be elaborated here.

[0118] S603, process the target task through the first target processor core.

[0119] In this application, after the electronic device determines the target processor core cluster for processing the target task from multiple processor core clusters in the system-on-chip, the core scheduling module in the target processor core cluster can determine a first target processor core for processing the target task from the target processor core cluster, and process the target task through the first target processor core, so as to realize the scheduling, allocation, and processing of tasks on the premise that multiple processor core clusters are deployed in the system-on-chip. Since each processor core in the processor core cluster shares the same secondary cache, each processor core in the same processor core cluster can achieve data interaction through the secondary cache in the processor core cluster. Therefore, during the process of the processor core in the processor core cluster processing tasks, the data transmission distance between the processor cores in the processor core cluster becomes shorter, thereby reducing the data interaction delay between the processor cores in the processor core cluster, and further reducing the situation of task processing delay caused by the interaction of data between the processor cores.

[0120] In a possible implementation manner, in order to further improve the data interaction efficiency between different processor cores in the processor core cluster, during the process of the first target processor core processing the target task, the first target processor core can also determine a first cache mirror area from the secondary cache corresponding to the processor core cluster, and synchronize the task data cached in its first-level cache to the first cache mirror area.

[0121] Furthermore, if it is determined by the core scheduling module that the target task needs to be switched from the first target processor core to a second target processor core in the processor core cluster, the core scheduling module can also send a first task switching command to the second target processor core, and the first task switching command is used to instruct to switch the target task processed by the first target processor core to the second target processor core.

[0122] Among them, the second target processor core belongs to at least one first processor core, at least one second processor core, and at least one third processor core in the processor core cluster, and the second target processor core is different from the first target processor core.

[0123] Correspondingly, in response to the first task switching command, the second target processor core will determine the first cache mirror area corresponding to the first target processor core, and process the target task based on the task data of the target task cached in the first cache mirror area.

[0124] In another possible implementation manner, in order to reduce the situation where the second target processor core needs to wait for task data to be synchronized to the first cache mirror area, in this application, if the core scheduling module determines that the target task needs to be switched from the first target processor core to the second target processor core in the processor core cluster, the core scheduling module may also send a second task switching command to the first target processor core, where the second task switching command is used to indicate that the target task is to be switched to other processor cores.

[0125] Correspondingly, in response to the second task switching command, the first target processor core may synchronize the task data in its level-1 cache that has not been synchronized to the first cache mirror area to the first cache mirror area.

[0126] In another possible implementation manner, in order to reduce the resource consumption of the level-2 cache, when it is confirmed that the second target processor core has completed reading the task data of the target task in the first cache mirror area, a mirror clearing instruction may also be sent to the first target processor core. Correspondingly, the first target processor core is further configured to clear the task data of the target task cached in the first cache mirror area in response to the mirror clearing instruction.

[0127] Furthermore, during the process of processing the target task, the second target processor core may also determine a second cache mirror area from its corresponding level-2 cache, and synchronize the task data cached in its level-1 cache by the second target processor core to the second cache mirror area.

[0128] On the other hand, this application also provides an electronic device. As Figure 7 , a schematic diagram of a composition architecture of the electronic device provided by this application is shown. The electronic device in this embodiment includes at least a system-on-chip 701.

[0129] Among them, there are multiple processor core clusters arranged in sequence in the system-on-chip;

[0130] Among them, each processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core, and a secondary cache shared by at least one first processor core, at least one second processor core, and at least one third processor core;

[0131] Among them, the computing performances of the first processor core, the second processor core, and the third processor core are different.

[0132] Among them, the system-on-chip is used to run an operating system; determine a target processor core cluster for processing a target task from multiple processor core clusters through the operating system; determine a first target processor core for processing the target task from the target processor core cluster through a core scheduling module in the target processor core cluster; and process the target task through the first target processor core.

[0133] Among them, for the composition and operations performed by the system-on-chip, reference can be made to the relevant introductions in any of the previous embodiments, which will not be elaborated here.

[0134] It can be understood that the electronic device may further include a display unit 702 and an input unit 703. Of course, the electronic device may further include more or fewer components, which are not specifically limited. Figure 7 More or fewer components, which are not specifically limited.

[0135] In an embodiment of the present application, there is also provided a computer program product, including computer-readable instructions. When the computer-readable instructions run on an electronic device, the electronic device is enabled to implement any one of the task processing methods provided in the embodiments of the present application.

[0136] In an embodiment of the present application, there is also provided a computer-readable storage medium. The storage medium carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device is enabled to implement any one of the task processing methods provided in the embodiments of the present application.

[0137] In addition, it should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the device embodiments provided in the present application, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines.

[0138] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be various, such as analog circuits, digital circuits or dedicated circuits, etc. However, for this application, software program implementation is a better embodiment in more cases. Based on such an understanding, the technical solution of this application, in essence or the part that makes contributions to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disc of a computer, etc., and includes several instructions to enable a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods described in various embodiments of this application.

[0139] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0140] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, training device or data center to another website, computer, training device or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

Claims

1. A system on chip, comprising: Multiple processor core clusters arranged in sequence; Each processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core, and a secondary cache shared by the at least one first processor core, at least one second processor core, and at least one third processor core; The computing performances of the first processor core, the second processor core and the third processor core are different.

2. The system on chip according to claim 1, wherein the first subset consisting of the at least one first processor core, the second subset consisting of the at least one second processor core, and the third subset consisting of the at least one third processor core are arranged in sequence.

3. The system on chip according to claim 1, wherein the processor core cluster further comprises: A core scheduling module that is communicatively connected to the first processor core, the second processor core, and the third processor core is used to determine, when the processor core cluster is determined to be a target processor core cluster that needs to process a target task, a first target processor core from the processor core cluster for processing the target task, the first target processor core belonging to at least one first processor core, at least one second processor core, and at least one third processor core in the processor core cluster.

4. The system on chip according to claim 3, wherein the first processor core, the second processor core and the third processor core each have their own level 1 cache; The first target processor core is used to process the target task; in the process of processing the target task, a first cache mirror area is determined from the secondary cache corresponding to the processor core cluster; and the task data cached by the first target processor core in its primary cache is synchronized to the first cache mirror area.

5. The system on chip according to claim 4, wherein the core scheduling module is further configured to send a first task switching command to the second target processor core if it is determined that the target task needs to be switched from the first target processor core to the second target processor core in the processor core cluster, wherein the first task switching command is used to instruct to switch the target task processed by the first target processor core to the second target processor core; in, The second target processor core belongs to at least one first processor core, at least one second processor core and at least one third processor core in the processor core cluster, and the second target processor core is different from the first target processor core; The second target processor core is used to determine a first cache mirror area corresponding to the first target processor core in response to the first task switching command; The target task is processed based on the task data of the target task cached in the first cache mirror area.

6. The system on chip according to claim 4 or 5, wherein the core scheduling module is further configured to send a second task switching command to the first target processor core if it is determined that the target task needs to be switched from the first target processor core to a second target processor core in the processor core cluster, wherein the second task switching command is used to indicate that the target task is to be switched to another processor core; The first target processor core is further configured to synchronize task data in its first-level cache that has not yet been synchronized to the first cache mirror area to the first cache mirror area in response to the second task switching command.

7. The system on chip according to claim 5, wherein the second target processor core is further configured to send a mirror clearing instruction to the first target processor core when confirming that the task data of the target task in the first cache mirror area has been read; The first target processor core is further configured to clear the task data of the target task cached in the first cache mirror area in response to the mirror clear instruction.

8. According to the system on chip of claim 5, the second target processor core is further used to determine a second cache mirror area from its corresponding secondary cache during processing of the target task; and synchronize the task data cached by the second target processor core in its first-level cache to the second cache mirror area.

9. An electronic device, comprising: A system on a chip, the system on a chip comprising a plurality of processor core clusters arranged in sequence; Each processor core cluster includes: at least one first processor core, at least one second processor core, at least one third processor core and a core scheduling module, and a secondary cache shared by the at least one first processor core, at least one second processor core and at least one third processor core; Wherein, the computing performances of the first processor core, the second processor core and the third processor core are different; The system on chip is used to run an operating system; determine a target processor core cluster for processing a target task from multiple processor core clusters through the operating system; determine a first target processor core for processing the target task from the target processor core cluster through a core scheduling module in the target processor core cluster; and process the target task through the first target processor core.

10. A task processing method, comprising: Determine a target processor core cluster for processing a target task from a plurality of processor core clusters, the processor core cluster comprising: at least one first processor core, at least one second processor core, at least one third processor core, and a secondary cache shared by the first processor core and the second processor core, the first processor core, the second processor core, and the third processor core having different computing performances; Determining a first target processor core for processing the target task from the target processor core cluster by a core scheduling module in the target processor core cluster; The target task is processed by the first target processor core.

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