Multiplexing device, multiplexing method and chip

Abstract

The invention provides a multiplexing device, a multiplexing method and a chip, which can be applied to the technical field of communication. The multiplexing device comprises a function selection module and a pin selection module, the function selection module is electrically connected with a plurality of pins and a mode selection end, the function selection module comprises a plurality of function ends, and each function end is used for at least one of a plurality of function modules. The function selection module is configured to communicate the plurality of function ends with at least one target pin in the plurality of pins according to a function selection signal and a mode selection signal from a mode selection end; the target pins comprise first target pins, the plurality of function ends comprise target function ends, and the pin selection module is configured to select the target function ends under the control of a function selection signal under the condition that the plurality of first target pins electrically connected with the plurality of target function ends are in the same input mode. And communicating the plurality of target function ends with a target function module in the plurality of function modules.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and more particularly, to a multiplexing device, method, and chip. Background Art

[0002] With the gradual increase in the integration level of chips, chip design becomes increasingly complex, the functions that can be realized are more and more, and the required external communication interfaces are more and more. Therefore, it has become an urgent problem to implement more communication functions on limited chip pins. Summary of the Invention

[0003] In view of this, the present disclosure provides a multiplexing device, method, and chip.

[0004] According to one aspect of the present disclosure, a multiplexing device is provided, which is applied to a chip. The chip includes a plurality of pins, a mode selection terminal, and a plurality of functional modules. The plurality of functional modules include at least one working functional module and at least one test functional module. The multiplexing device includes: a function selection module and a pin selection module. The function selection module is electrically connected to the plurality of pins and the mode selection terminal. The function selection module includes a plurality of function terminals, and each function terminal is for at least one of the plurality of functional modules. The function selection module is configured to connect at least one target pin among the plurality of pins to the plurality of function terminals according to a function selection signal and a mode selection signal from the mode selection terminal. The target pin includes a first target pin, and the plurality of function terminals include a target function terminal. The pin selection module is configured to connect the plurality of target function terminals to a target functional module among the plurality of functional modules under the control of the function selection signal when the plurality of first target pins respectively electrically connected to the plurality of target function terminals are in the same input mode.

[0005] For example, the above-mentioned target pins further include second target pins, and the above-mentioned multiple functional terminals further include first functional terminals and second functional terminals; the above-mentioned function selection module includes: first signal selectors and second signal selectors corresponding to each of the above-mentioned second target pins; each of the above-mentioned first functional terminals of the above-mentioned first signal selector is electrically connected to at least one of the above-mentioned working function modules, and multiple above-mentioned first functional terminals are connected to different above-mentioned working function modules, and the above-mentioned first signal selector is configured to connect a target first functional terminal among the above-mentioned multiple first functional terminals to the output terminal of the above-mentioned first signal selector according to the above-mentioned function selection signal; multiple second functional terminals of the above-mentioned second signal selector are electrically connected to the output terminal of the above-mentioned first signal selector and at least one of the above-mentioned test function modules, and the control terminal of the above-mentioned second signal selector is electrically connected to the above-mentioned mode selection terminal, and the above-mentioned second signal selector is configured to connect a target second functional terminal among the above-mentioned multiple second functional terminals of the above-mentioned second signal selector to the above-mentioned second target pin according to the above-mentioned mode selection signal.

[0006] For example, the above-mentioned multiple functional terminals further include third functional terminals and fourth functional terminals; the above-mentioned function selection module further includes: third signal selectors and fourth signal selectors corresponding to each of the above-mentioned first target pins; each of the above-mentioned third functional terminals of the above-mentioned third signal selector is electrically connected to at least one of the above-mentioned working function modules, and multiple above-mentioned third functional terminals are connected to different above-mentioned working function modules, and the above-mentioned third signal selector is configured to connect a target third functional terminal among the above-mentioned multiple third functional terminals to the input terminal of the above-mentioned third signal selector according to the above-mentioned function selection signal; a fourth signal selector, multiple fourth functional terminals of the above-mentioned fourth signal selector are electrically connected to the input terminal of the above-mentioned third signal selector and at least one of the above-mentioned test function modules, and the control terminal of the above-mentioned fourth signal selector is electrically connected to the above-mentioned mode selection terminal, and the above-mentioned fourth signal selector is configured to connect a target fourth functional terminal among the above-mentioned multiple fourth functional terminals of the above-mentioned fourth signal selector to the above-mentioned first target pin according to the above-mentioned mode selection signal, wherein the above-mentioned target third functional terminal or the above-mentioned target fourth functional terminal is the above-mentioned target functional terminal.

[0007] For example, the above-mentioned pin selection module includes multiple pin selection units, and each of the above-mentioned pin selection units includes: N cascaded fifth signal selectors, where N is an integer greater than 1; the first input terminals of the above-mentioned N fifth signal selectors are respectively electrically connected to the above-mentioned multiple target functional terminals; the second input terminal of the nth-level fifth signal selector is electrically connected to the output terminal of the (n + 1)th-level fifth signal selector; the above-mentioned multiple fifth signal selectors are configured to connect a target functional terminal connected to the above-mentioned mth-level fifth signal selector to the above-mentioned target function module when the above-mentioned function selection signal selects the mth-level fifth signal selector, where n is greater than or equal to 1 and less than N, and m is greater than or equal to 1 and less than or equal to N.

[0008] For example, the above-mentioned multiple first target pins are used to receive multiple external function signals for the same function module.

[0009] For example, the above-mentioned device further includes: a selection signal generation module, configured to parse the above-mentioned external control signal in response to receiving the external control signal to obtain the above-mentioned function selection signal.

[0010] For example, the above-mentioned multiple function modules further include an interrupt function module; the above-mentioned multiple function terminals further include an interrupt function terminal; the above-mentioned target pins further include a third target pin; the above-mentioned function selection signal includes a control signal, a first edge signal, and a second edge signal; the above-mentioned device further includes: an interrupt module, the interrupt module is electrically connected to the interrupt function module and multiple interrupt function terminals; the interrupt module is configured to, when multiple third target pins respectively electrically connected to multiple interrupt function terminals are in the same input interrupt mode, under the control of the above-mentioned control signal, obtain an interrupt signal according to multiple third edge signals, the above-mentioned first edge signal, and the above-mentioned second edge signal from the above-mentioned multiple third target pins, and output the interrupt signal to the above-mentioned interrupt function module.

[0011] For example, the above-mentioned control signal includes: a single-edge control signal, a double-edge control signal, and an interrupt mask signal; the above-mentioned interrupt module includes: a first trigger selector, multiple input terminals of the first trigger selector are respectively electrically connected to the above-mentioned multiple interrupt function terminals, the first trigger selector is configured to select one of the above-mentioned first edge signal, the above-mentioned second edge signal, and multiple third edge signals under the control of the above-mentioned single-edge control signal to obtain a single-edge trigger signal; an OR gate, configured to perform an OR operation on the above-mentioned first edge signal and the above-mentioned second edge signal to obtain a double-edge trigger signal; a second trigger selector, an input terminal of the second trigger selector is electrically connected to the output terminal of the first trigger selector and the output terminal of the OR gate, the second trigger selector is configured to select one of the above-mentioned single-edge trigger signal and the above-mentioned double-edge trigger signal as a target edge signal under the control of the above-mentioned double-edge control signal; an AND gate, an input terminal of the AND gate is electrically connected to the output terminal of the second trigger selector, an output terminal of the AND gate is electrically connected to the above-mentioned interrupt function module, the AND gate is configured to perform an AND operation on the above-mentioned interrupt mask signal and the above-mentioned target edge signal to obtain the above-mentioned interrupt signal.

[0012] For example, the above-mentioned test function module includes at least one of an analog test function module, a testable function module, and a debugging function module.

[0013] According to another aspect of the present disclosure, there is provided a chip, including: multiple pins; a mode selection terminal; multiple function modules; the above-mentioned multiplexing device, wherein the above-mentioned multiplexing device is electrically connected to the above-mentioned multiple pins, the above-mentioned mode selection terminal, and the above-mentioned multiple function modules.

[0014] According to another aspect of the present disclosure, a multiplexing method is provided, including: connecting at least one target pin among a plurality of pins to a plurality of function terminals according to a function selection signal and a mode selection signal from a mode selection terminal, wherein each of the above function terminals is used for at least one of a plurality of function modules, and the above plurality of function modules include at least one working function module and at least one test function module; when a plurality of first target pins respectively electrically connected to the plurality of target function terminals are in the same input mode, under the control of the above function selection signal, connecting the above plurality of target function terminals to a target function module among the above plurality of function modules, wherein the above target pins include the above first target pins, and the above plurality of function terminals include the above target function terminals.

[0015] According to an embodiment of the present disclosure, by using a technical means that a function selection module connects at least one target pin among a plurality of pins to a plurality of function terminals according to a function selection signal and a mode selection signal from a mode selection terminal, it is possible to connect the target pin among the plurality of pins to the plurality of function terminals in a time-division manner. Also, since each function terminal is used for at least one of a plurality of function modules, and the plurality of function modules include at least one working function module and at least one test function module, it is further possible to multiplex the target pin among the plurality of pins to a plurality of working function modules and / or a plurality of test function modules when connecting the target pin among the plurality of pins to the plurality of function terminals in a time-division manner. By using a technical means that a pin selection module connects a plurality of target function terminals to a target function module among a plurality of function modules under the control of a function selection signal when a plurality of first target pins respectively electrically connected to the plurality of target function terminals are in the same input mode, it is possible to connect the plurality of first target pins to the target function module in a time-division manner when the plurality of first target pins are in the same input mode, and multiplex the input interface of the target function module to the plurality of first target pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0017] Figure 1 Schematically shows a structural diagram of a multiplexing device according to an embodiment of the present disclosure;

[0018] Figure 2 Schematically shows a structural diagram of a function selection module according to an embodiment of the present disclosure;

[0019] Figure 3 Schematically shows a structural diagram of a function selection module according to another embodiment of the present disclosure;

[0020] Figure 4 Schematically shows a structural diagram of a function selection module according to another embodiment of the present disclosure;

[0021] Figure 5 Schematically shows a structural diagram of a pin selection module according to an embodiment of the present disclosure;

[0022] Figure 6 Schematically shows a structural diagram of a multiplexing device according to an embodiment of the present disclosure;

[0023] Figure 7 Schematically shows a structural diagram of an interrupt module according to an embodiment of the present disclosure;

[0024] Figure 8 Schematically shows a structural diagram of a chip according to an embodiment of the present disclosure; and

[0025] Figure 9 Schematically shows a flowchart of a multiplexing method according to an embodiment of the present disclosure. Detailed Embodiments

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0027] It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as any limitation to the present disclosure, but only as examples of the embodiments of the present disclosure. When it may cause confusion in the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.

[0029] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may mean that two components are directly connected, or may mean that two components are connected via one or more other components. In addition, these two components may be connected or coupled by wired or wireless means.

[0030] As the integration level of the chip gradually increases, the number of external communication interfaces required by the chip is increasing. The number of pins corresponding to the external communication interfaces used by the chip can be reduced by multiplexing the pins on the chip. The number of internal communication interfaces of the chip can be reduced by multiplexing the internal communication interfaces of the chip onto multiple pins.

[0031] Figure 1 A schematic structural diagram of a multiplexing device according to an embodiment of the present disclosure is schematically shown.

[0032] As Figure 1 shown, the multiplexing device 100 may include a function selection module 110 and a pin selection module 120.

[0033] The chip may include a plurality of pins 101, a mode selection terminal 102, and a plurality of function modules 103. The plurality of function modules 103 may include at least one working function module 1031 and at least one test function module 1032.

[0034] The working function module 1031 represents the function module that operates when the chip is in the working state. The test function module 1032 represents the module that operates when the chip is in the test state.

[0035] The number of at least one working function module 1031 and the number of at least one test function module 1032 can be selected according to the actual situation and are not limited herein. For example, the number of at least one working function module 1031 can be 8, 9, 10, 20, 30, or 100, etc. The number of at least one test function module 1032 can be 8, 10, 15, 25, 30, 50, or 150, etc.

[0036] The plurality of pins 101 can be respectively electrically connected to a plurality of peripherals 1001. The plurality of pins 101 can be used as the external communication interfaces of the chip to communicate with the plurality of peripherals 1001. The peripheral 1001 represents an external device that communicates with the chip.

[0037] The plurality of pins 101 may include pin 1, …, pin p, and the plurality of peripherals 1001 may include peripheral 1, …, peripheral p. Pin 1, …, pin p can be respectively electrically connected to peripheral 1, …, peripheral p. Wherein, p is an integer greater than 1.

[0038] The function selection module 110 can be electrically connected to the plurality of pins 101 and the mode selection terminal 102. The function selection module 110 may include a plurality of function terminals. Each function terminal can be used for at least one of the plurality of function modules 103

[0039] The function selection module 110 can be configured to connect multiple function terminals to at least one target pin among multiple pins 101 according to a function selection signal and a mode selection signal from the mode selection terminal 102.

[0040] For example, eight function terminals of the function selection module 110 respectively for the working function module 1031 can be connected to the same target pin, or ten function terminals of the function selection module 110 respectively for the test function module 1032 can be connected to the same target pin, or six function terminals of the function selection module 110 respectively for the working function module 1031 and three function terminals of the function selection module 110 respectively for the test function module 1032 can be connected to the same target pin.

[0041] For example, multiple function terminals can each be used for one of the multiple function modules 103. Multiple function terminals can each be used for at least two of the multiple function modules 103. Or a part of the multiple function terminals can each be used for one of the multiple function modules 103, and another part of the multiple function terminals can each be used for at least two of the multiple function modules 103.

[0042] The target pin can include a first target pin, and the multiple function terminals can include target function terminals. The pin selection module 120 can be configured to, when multiple first target pins respectively electrically connected to the multiple target function terminals are in the same input mode, under the control of the function selection signal, connect the multiple target function terminals to a target function module among the multiple function modules 103. Wherein, when the multiple target function terminals are connected to the target function module among the multiple function modules 103, the target function module can be connected to the multiple first target pins. The multiple first target pins are used to time-division transmit multiple external function signals of the same type to the target function module.

[0043] For example, the multiple function terminals can include a target function terminal 1, a target function terminal 2, and a target function terminal 3. The target function terminal 1, the target function terminal 2, and the target function terminal 3 represent function terminals for the same function module 103. The target function terminal 1, the target function terminal 2, and the target function terminal 3 can be respectively electrically connected to a first target pin 1, a first target pin 2, and a first target pin 3. When the first target pin 1, the first target pin 2, and the first target pin 3 are all in the same input mode, the pin selection module 120, under the control of the function selection signal, connects the target function terminal 1, the target function terminal 2, or the target function terminal 3 to the corresponding target function module among the multiple function modules 103.

[0044] For example, the target function terminal 1 can be connected to the target function module, and the target function module can be connected to the first target pin 1. The target function terminal 2 can be connected to the target function module, and the target function module can be connected to the first target pin 2. Or the target function terminal 3 can be connected to the target function module, and the target function module can be connected to the first target pin 3.

[0045] According to an embodiment of the present disclosure, by using the function selection module to connect at least one target pin among multiple pins to multiple function terminals according to the function selection signal and the mode selection signal from the mode selection terminal, the target pin among the multiple pins can be connected to the multiple function terminals in a time-division manner. Also, since each function terminal is used for at least one of multiple function modules, and the multiple function modules include at least one working function module and at least one test function module, thus when the target pin among the multiple pins is connected to the multiple function terminals in a time-division manner, the target pin among the multiple pins can be reused for at least one working function module and / or at least one test function module. By using the pin selection module to connect multiple target function terminals to the target function module among multiple function modules under the control of the function selection signal when multiple first target pins respectively electrically connected to the multiple target function terminals are in the same input mode, it is possible to connect the multiple first target pins to the target function module in a time-division manner when the multiple first target pins are in the same input mode, and reuse the input interface of the target function module for the multiple first target pins.

[0046] According to an embodiment of the present disclosure, according to Figure 1 The multiplexing device in can reuse the target pin among multiple pins for at least one working function module and at least one test function module, which can reduce the number of pins of the chip, and thus can reduce the cost and packaging complexity of the chip, and improve the flexibility and scalability of the chip.

[0047] According to an embodiment of the present disclosure, according to Figure 1 The multiplexing device in can reuse the target pin among multiple pins for at least one working function module and at least one test function module, and realize multiple different functions on the chip by using the same target pin, which can make the application range of the chip wider, and at the same time can also reduce the number of devices connected to the target pin in the chip, thereby improving the reliability and stability of the chip.

[0048] According to an embodiment of the present disclosure, by reusing the input interface of the target function module for multiple first target pins, the input interface of the target function module can be reduced, and the reliability and stability of the chip can be improved.

[0049] Figure 2 Schematically shows a structural diagram of a function selection module according to an embodiment of the present disclosure.

[0050] As Figure 2 shown, the target pin may further include a second target pin. The function selection module 110 may include a first signal selector 111 and a second signal selector 112 corresponding to each second target pin.

[0051] The multiple function terminals may further include a first function terminal and a second function terminal. The first function terminal is for at least one working function module 1031. The second function terminal is for at least one test function module 1032.

[0052] For example, the first function terminal may be for one working function module 1031. Or the first function terminal may be for at least two working function modules 1031. The second function terminal may be for one test function module 1032. Or the second function terminal may be for at least two test function modules 1032.

[0053] The test function module 1032 may include at least one of an analog test function module, a testable function module, and a debugging function module.

[0054] The number of the first function terminals and the number of the second function terminals may be selected according to actual situations and are not limited herein. For example, the number of the first function terminals may be 2, 3, 4, 6, 7, 8, or 9, etc. The number of the second function terminals may be 2, 4, 5, 6, 8, 9, or 10, etc.

[0055] Each first function terminal of the first signal selector 111 may be electrically connected to at least one working function module 1031. The multiple first function terminals are connected to different working function modules 1031. The first signal selector 111 may be configured to connect the target first function terminal among the multiple first function terminals to the output terminal out of the first signal selector 111 according to a function selection signal.

[0056] The multiple second function terminals of the second signal selector 112 may be electrically connected to the output terminal out of the first signal selector 111 and at least one test function module 1032. The control terminal of the second signal selector 112 may be electrically connected to the mode selection terminal 102. The second signal selector 112 may be configured to connect the target second function terminal among the multiple second function terminals of the second signal selector 112 to the second target pin according to a mode selection signal. Among them, the second target pin may be any one of pin 1, …, pin p.

[0057] For example, in Figure 2 , the number of the first function terminals may be 4. The 4 first function terminals may be a1, a2, a3, and a4 respectively. The number of the second function terminals may be 6. The 6 second function terminals may be b1, b2, b3, b4, b5, and b6 respectively.

[0058] A plurality of first functional terminals a1, a2, a3, and a4 can be electrically connected to a first working function module 1031_1, a second working function module 1031_2, a third working function module 1031_3, and a fourth working function module 1031_4 respectively.

[0059] When the target first functional terminal is the first functional terminal a1, the first signal selector 111 can connect the first functional terminal a1 to the output terminal out of the first signal selector 111 according to the function selection signal.

[0060] A plurality of second functional terminals b1, b2, b3, b4, b5, and b6 can be electrically connected to the output terminal out of the first signal selector 111, a first test function module 1032_1, a second test function module 1032_2, a third test function module 1032_3, a fourth test function module 1032_4, and a fifth test function module 1032_5 respectively.

[0061] When the target second functional terminal is the second functional terminal b1, the second signal selector 112 can connect the second functional terminal b1 to the second target pin according to the mode selection signal, and at the same time connect the first working function module 1031_1, the first functional terminal a1, and the second functional terminal b1 to the second target pin, so as to output the function signal of the first working function module 1031_1 by using the second target pin.

[0062] When the target second functional terminal is the second functional terminal b2, the second signal selector 112 can connect the second functional terminal b2 to the second target pin according to the mode selection signal, and at the same time connect the first test function module 1032_1 and the second functional terminal b2 to the second target pin, so as to output the function signal of the first test function module 1032_1 by using the second target pin.

[0063] Figure 3 Schematically shows a structural diagram of a function selection module according to another embodiment of the present disclosure.

[0064] Figure 3 And Figure 2The difference of the middle function selection module 110 is that multiple first function terminals a1, a2, a3, and a4 of the first signal selector 111 are electrically connected to a fifth working function module 1031_5, a sixth working function module 1031_6, a seventh working function module 1031_7, and an eighth working function module 1031_8 respectively. Multiple second function terminals b2, b3, b4, b5, and b6 of the second signal selector 112 are electrically connected to a sixth test function module 1032_6, a seventh test function module 1032_7, an eighth test function module 1032_8, a ninth test function module 1032_9, and a tenth test function module 1032_10 respectively.

[0065] For example, multiple first function terminals a1, a2, a3, and a4 of the first signal selector 111 can also be electrically connected to two working function modules 1031 respectively. Multiple second function terminals b1, b2, b3, b4, b5, and b6 of the second signal selector 112 can also be electrically connected to two test function modules 1032 respectively.

[0066] While multiple first function terminals a1, a2, a3, and a4 of the first signal selector 111 can be electrically connected to a first working function module 1031_1, a second working function module 1031_2, a third working function module 1031_3, and a fourth working function module 1031_4 respectively, multiple first function terminals a1, a2, a3, and a4 can also be electrically connected to a fifth working function module 1031_5, a sixth working function module 1031_6, a seventh working function module 1031_7, and an eighth working function module 1031_8 respectively.

[0067] While multiple second function terminals b1, b2, b3, b4, b5, and b6 of the second signal selector 112 can be electrically connected to the output terminal out of the first signal selector 111, a first test function module 1032_1, a second test function module 1032_2, a third test function module 1032_3, a fourth test function module 1032_4, and a fifth test function module 1032_5 respectively, multiple second function terminals b2, b3, b4, b5, and b6 of the second signal selector 112 can also be electrically connected to a sixth test function module 1032_6, a seventh test function module 1032_7, an eighth test function module 1032_8, a ninth test function module 1032_9, and a tenth test function module 1032_10 respectively.

[0068] According to an embodiment of the present disclosure, by electrically connecting each first functional terminal of the first signal selector to at least one working functional module, when multiple first functional terminals are connected to different working functional modules, the first signal selector is utilized to connect the target first functional terminal among the multiple first functional terminals to the output terminal of the first signal selector according to the function selection signal. When multiple second functional terminals of the second signal selector are electrically connected to the output terminal of the first signal selector and at least one test functional module, and the control terminal of the second signal selector is electrically connected to the mode selection terminal, the second signal selector is utilized to connect the target second functional terminal among the multiple second functional terminals of the second signal selector to the second target pin according to the mode selection signal. By means of this technique, when the second target pin is in the output mode, the second target pin can be connected to at least one working functional module and at least one test functional module in a time-sharing manner, and further the second target pin can be reused to output the functional signals of at least one working functional module and at least one test functional module.

[0069] Figure 4 Schematically shows a structural diagram of a function selection module according to another embodiment of the present disclosure.

[0070] As Figure 4 shown, the function selection module 110 may further include a third signal selector 113 and a fourth signal selector 114 corresponding to each first target pin.

[0071] The multiple functional terminals may further include a third functional terminal and a fourth functional terminal. The third functional terminal is for at least one working functional module 1031. The fourth functional terminal is for at least one test functional module 1032.

[0072] For example, the third functional terminal may be for one working functional module 1031. Or the third functional terminal may be for at least two working functional modules 1031. The fourth functional terminal may be for one test functional module 1032. Or the fourth functional terminal may be for at least two test functional modules 1032.

[0073] The number of the third functional terminals and the number of the fourth functional terminals can be selected according to the actual situation and are not limited herein. For example, the number of the third functional terminals may be 2, 3, 5, 6, 8, or 9, etc. The number of the fourth functional terminals may be 2, 3, 4, 6, 7, 9, or 10, etc.

[0074] Each third functional terminal of the third signal selector 113 can be electrically connected to at least one working functional module 1031, and multiple third functional terminals are connected to different working functional modules 1031. The third signal selector 113 can be configured to connect the target third functional terminal among the multiple third functional terminals to the input terminal in of the third signal selector 113 according to the function selection signal.

[0075] Multiple fourth functional terminals of the fourth signal selector 114 are electrically connected to the input terminal in of the third signal selector 113 and at least one test functional module 1032. The control terminal of the fourth signal selector 114 is electrically connected to the mode selection terminal 102. The fourth signal selector 114 can be configured to connect a target fourth functional terminal among the multiple fourth functional terminals of the fourth signal selector 114 to the first target pin according to the mode selection signal. Among them, the first target pin can be any one of pin 1, …, pin p. The target third functional terminal or the target fourth functional terminal is the target functional terminal.

[0076] For example, in Figure 4 the number of third functional terminals can be 4. The 4 third functional terminals can be c1, c2, c3, and c4 respectively. The number of fourth functional terminals can be 6. The 6 fourth functional terminals can be d1, d2, d3, d4, d5, and d6 respectively.

[0077] The multiple third functional terminals c1, c2, c3, and c4 can be electrically connected to the first working functional module 1031_1, the second working functional module 1031_2, the third working functional module 1031_3, and the fourth working functional module 1031_4 respectively.

[0078] When the target third functional terminal is the third functional terminal c1, the third signal selector 113 can connect the third functional terminal c1 to the input terminal in of the fourth signal selector 114 according to the function selection signal.

[0079] The multiple fourth functional terminals d1, d2, d3, d4, d5, and d6 can be electrically connected to the input terminal in of the third signal selector 113, the first test functional module 1032_1, the second test functional module 1032_2, the third test functional module 1032_3, the fourth test functional module 1032_4, and the fifth test functional module 1032_5 respectively.

[0080] When the target fourth functional terminal is the fourth functional terminal d1, the fourth signal selector 114 can connect the fourth functional terminal d1 to the first target pin according to the mode selection signal, and at the same time connect the first working functional module 1031_1, the third functional terminal c1, and the fourth functional terminal d1 to the first target pin, so as to input the external functional signal of the peripheral device to the first working functional module 1031_1 through the first target pin. At this time, the third functional terminal c1 is the target functional terminal.

[0081] When the target fourth functional terminal is the fourth functional terminal d2, the fourth signal selector 114 can connect the fourth functional terminal d2 to the first target pin according to the mode selection signal, and at the same time connect the first test function module 1032_1, the fourth functional terminal d2 to the first target pin, so as to input the external function signal of the peripheral device to the first test function module 1032_1 through the first target pin. At this time, the fourth functional terminal d2 is the target functional terminal.

[0082] According to an embodiment of the present disclosure, the first target pin and the second target pin may be the same or different. The functional module connected when the first target pin is in the input mode and the functional module connected when the second target pin is in the output mode may be the same or different.

[0083] According to an embodiment of the present disclosure, when any one of the multiple pins is determined as the second target pin and the second target pin is in the output mode, it may be based on Figure 2 or / and Figure 3 the first signal selector 111 and the second signal selector 112 in [[ ]], to connect the first target pin to multiple functional modules in a time-sharing manner, and multiplex the second target pin to output the functional signals of multiple functional modules in a time-sharing manner. When any one of the multiple pins is determined as the first target pin and the first target pin is in the input mode, it may be based on Figure 4 the third signal selector 113 and the fourth signal selector 114 in [[ ]], to connect the first target pin to multiple functional modules in a time-sharing manner, and multiplex the first target pin to input the multiple external function signals of multiple peripheral devices to the functional signals of multiple functional modules in a time-sharing manner.

[0084] According to an embodiment of the present disclosure, by electrically connecting each third functional terminal of the third signal selector to at least one working functional module, when multiple third functional terminals are connected to different working functional modules, using the third signal selector according to the function selection signal, to connect the target third functional terminal among the multiple third functional terminals to the input end of the third signal selector, and when multiple fourth functional terminals of the fourth signal selector are electrically connected to the input end of the third signal selector and at least one test function module, and the control end of the fourth signal selector is electrically connected to the mode selection end, using the fourth signal selector according to the mode selection signal, to connect the target fourth functional terminal among the multiple fourth functional terminals of the fourth signal selector to the first target pin, the technical means can connect the first target pin to at least one working functional module and at least one test function module in a time-sharing manner when the first target pin is in the input mode, and further multiplex the first target pin to input the multiple external function signals of multiple peripheral devices to at least one working functional module and at least one test function module in a time-sharing manner.

[0085] Figure 5A schematic structural diagram of a pin selection module according to an embodiment of the present disclosure is schematically shown.

[0086] As Figure 5 shown, the pin selection module 120 may include a plurality of pin selection units 121. Each pin selection unit 121 may include: N cascaded fifth signal selectors, where N is an integer greater than 1.

[0087] The first input terminals of the N fifth signal selectors may be electrically connected to a plurality of target function terminals respectively. The second input terminal of the nth - stage fifth signal selector may be electrically connected to the output terminal of the (n + 1)th - stage fifth signal selector. The plurality of fifth signal selectors may be configured to connect the target function terminal connected to the mth - stage fifth signal selector to the target function module when the function selection signal selects the mth - stage fifth signal selector, where n is greater than or equal to 1 and less than N, and m is greater than or equal to 1 and less than or equal to N.

[0088] N can be selected according to the actual situation and is not limited herein. For example, N can be 2, 4, 5, 6, or 8, etc.

[0089] The plurality of first target pins are used to receive a plurality of external function signals for the same function module.

[0090] For example, in Figure 5 it, N can be 4, and the 4 cascaded fifth signal selectors can be the fifth signal selector 1211, the fifth signal selector 1212, the fifth signal selector 1213, and the fifth signal selector 1214 respectively.

[0091] When the plurality of first target pins are pin 1, pin 2, pin 3, and pin 4, and pin 1, pin 2, pin 3, and pin 4 are in the same input mode, pin 1 can be used to receive the external function signal 1 for the target function module, pin 2 can be used to receive the external function signal 2 for the target function module, pin 3 can be used to receive the external function signal 3 for the target function module, and pin 4 can be used to receive the external function signal 4 for the target function module.

[0092] Pin 1, pin 2, pin 3, and pin 4 can be respectively connected to the target function terminals of their corresponding function selection modules 110. The input terminals of the fifth signal selector 1211, the fifth signal selector 1212, the fifth signal selector 1213, and the fifth signal selector 1214 can be respectively electrically connected to a plurality of target function terminals corresponding to pin 1, pin 2, pin 3, and pin 4 respectively.

[0093] The second input terminal of the fifth signal selector 1211 can be electrically connected to the output terminal of the fifth signal selector 1212. The second input terminal of the fifth signal selector 1212 can be electrically connected to the output terminal of the fifth signal selector 1213. The second input terminal of the fifth signal selector 1213 can be electrically connected to the output terminal of the fifth signal selector 1214.

[0094] A preset signal is input to the second input terminal of the fifth signal selector 1214. The preset signal can be selected according to the actual situation and is not limited herein. For example, the preset signal can be a signal with an amplitude of 0.

[0095] The fifth signal selector 1211, the fifth signal selector 1212, the fifth signal selector 1213, and the fifth signal selector 1214 are respectively used to receive the function selection signal 1, the function selection signal 2, the function selection signal 3, and the function selection signal 4.

[0096] When multiple fifth signal selectors select the fifth signal selector 1214 based on the function selection signal 1, the function selection signal 2, the function selection signal 3, and the function selection signal 4, the target function terminal connected to the fifth signal selector 1214 can be electrically connected to the target function module, and the external function signal 4 for the target function module received by the pin 4 is input to the target function module.

[0097] According to an embodiment of the present disclosure, by default, the smaller the number of the first target pin, the higher the priority, and the fewer the number of the multiple fifth signal selectors between the output terminal of the fifth signal selector connected to the first target pin and the target function module, so as to quickly transmit the external function signal received by the first target pin with a higher priority to the target function module and improve the signal transmission efficiency.

[0098] According to an embodiment of the present disclosure, since the first input terminals of N fifth signal selectors are electrically connected to a plurality of target function terminals respectively, and the plurality of target function terminals are respectively communicated with a plurality of first target pins, and the plurality of first target pins are used to receive a plurality of external function signals for the same function module, therefore, the first input terminals of the N fifth signal selectors can respectively receive a plurality of external function signals from the plurality of first target pins and for the same function module. By electrically connecting the second input terminal of the nth - stage fifth signal selector to the output terminal of the (n + 1)th - stage fifth signal selector, and using the technical means that when the function selection signal selects the mth - stage fifth signal selector among the plurality of fifth signal selectors, the target function terminal connected to the mth - stage fifth signal selector is electrically connected to the target function module, it is possible to input the external function signal received by the target function terminal connected to the mth - stage fifth signal selector from the corresponding first target pin into the target function module. Furthermore, when the plurality of first target pins are in the same input mode, the signal input terminal of the target function module can be time - division multiplexed among the plurality of first target pins.

[0099] Figure 6 Schematically shows a structural diagram of a multiplexing device according to an embodiment of the present disclosure.

[0100] As Figure 6 shown, the multiplexing device 600 may include a function selection module 610, a pin selection module 620, a selection signal generation module 630, and an interrupt module 640. Among them, Figure 6 the function selection module 610 and the pin selection module 620 in Figure 1 have similar structures and functions to the function selection module 110 and the pin selection module 120 in

[0101] The chip may include a plurality of pins 601, a mode selection terminal 602, and a plurality of function modules 603. The plurality of function modules 603 may include at least one working function module, at least one test function module, and an interrupt function module 6033. The plurality of pins 601 may include target pins. The target pins may include first target pins, second target pins, and third target pins. The first target pins, the second target pins, and the third target pins may be the same or different. The plurality of function terminals may further include interrupt function terminals.

[0102] The selection signal generation module 630 may be configured to parse the external control signal in response to receiving the external control signal to obtain a function selection signal. Among them, the function selection signal obtained by the selection signal generation module 630 may be used for the function selection module 610, the pin selection module 620, and the interrupt module 640.

[0103] For example, the selection signal generation module 630 can receive an external control signal based on the APB (Advanced Peripheral Bus).

[0104] According to an embodiment of the present disclosure, by using the selection signal generation module 630 to respond to the received external control signal, the external control signal is parsed to obtain a function selection signal, so that the selection signal generation module 630 can subsequently control the working mode, input / output function, and the way of interrupt generation of the pin based on the function selection signal.

[0105] The interrupt module 640 can be electrically connected to the interrupt function module 6033 and the function selection module 640. For example, the interrupt module 640 can be electrically connected to the interrupt function module 6033 and multiple interrupt function terminals. The interrupt module 640 can also be electrically connected to the selection signal generation module 630.

[0106] The function selection signal can include a control signal, a first edge signal, and a second edge signal.

[0107] The interrupt module 640 can be configured to, when multiple third target pins respectively electrically connected to multiple interrupt function terminals are in the same input interrupt mode, under the control of the control signal, obtain an interrupt signal according to multiple third edge signals, the first edge signal, and the second edge signal from the multiple third target pins, and output the interrupt signal to the interrupt function module 6033, so that the interrupt function module 6033 can perform an interrupt operation based on the interrupt signal. Among them, the third target pin can be any one of the multiple pins 601.

[0108] For example, the multiple third edge signals can include a high-level trigger signal and a low-level trigger signal opposite to the high-level trigger signal. The first edge signal can be a falling-edge trigger signal. The second edge signal can be a rising-edge trigger signal.

[0109] According to an embodiment of the present disclosure, when the edge signal of the input interrupt module 640 jitters, the input edge signal must remain valid for at least two denoising clock cycles for sampling. Any input pulse width less than one debounce clock cycle will not be sampled. Whether the edge signal with an input pulse width between one and two anti-jitter clock cycles is transmitted also depends on the phase relationship between the edge signal and the anti-jitter clock.

[0110] According to an embodiment of the present disclosure, by using an interrupt module, when multiple third target pins respectively electrically connected to multiple interrupt function terminals are in the same input interrupt mode, under the control of a control signal, according to multiple third edge signals, a first edge signal, and a second edge signal from the multiple third target pins, an interrupt signal is obtained. Different types of interrupt signals can be obtained. When the different types of interrupt signals are output to the interrupt function module, the interrupt function module can enable the corresponding function module 603 to perform different interrupt operations based on the different types of interrupt signals.

[0111] According to an embodiment of the present disclosure, the configured pin multiplexing information of the multiplexing device 600 can be utilized by means of documentation. The pin multiplexing information may include the multiplexing relationship, input / output attributes, and interrupt functions of each pin. When multiplexing each pin, based on the pin multiplexing information recorded in the documentation, the code for controlling pin multiplexing can be quickly integrated into the chip, so that the chip can input relevant external control signals into the multiplexing device 600 and input a mode selection signal into the mode selection terminal 602 by executing relevant programs. Furthermore, the multiplexing device 600 can control the pins in the chip to be in different multiplexing modes based on the external control signal and the mode selection signal.

[0112] Figure 7 Schematically shows a structural diagram of an interrupt module according to an embodiment of the present disclosure.

[0113] As Figure 7 shown, the interrupt module 640 may include a first trigger selector 641, an OR gate 642, a second trigger selector 643, and an AND gate 644.

[0114] The control signal may include a single-edge control signal, a double-edge control signal, and an interrupt mask signal

[0115] Multiple input terminals of the first trigger selector 641 may be respectively electrically connected to multiple interrupt function terminals. The first trigger selector 641 may be configured to select one of the first edge signal, the second edge signal, and multiple third edge signals under the control of the single-edge control signal to obtain a single-edge trigger signal.

[0116] The OR gate 642 may be configured to perform an OR operation on the first edge signal and the second edge signal to obtain a double-edge trigger signal.

[0117] The input terminal of the second trigger selector 643 may be electrically connected to the output terminal of the first trigger selector 641 and the output terminal of the OR gate 642. The second trigger selector 643 may be configured to select one of the single-edge trigger signal and the double-edge trigger signal as the target edge signal under the control of the double-edge control signal.

[0118] The input terminal of the AND gate 644 can be electrically connected to the output terminal of the second trigger selector 643, and the output terminal of the AND gate 644 is electrically connected to the interrupt function module 6033. The AND gate 644 can be configured to perform an AND operation on the interrupt mask signal and the target edge signal to obtain an interrupt signal.

[0119] According to an embodiment of the present disclosure, by using the first trigger selector 641 to select one of the first edge signal, the second edge signal, and a plurality of third edge signals under the control of the single-edge control signal, different types of single-edge trigger signals can be obtained. By performing an OR operation on the first edge signal and the second edge signal using an OR gate, a double-edge trigger signal can be obtained. By using the second trigger selector to select one of the single-edge trigger signal and the double-edge trigger signal under the control of the double-edge control signal, the single-edge trigger signal or the double-edge trigger signal can be used as the target edge signal. Furthermore, when performing an AND operation on the interrupt mask signal and the target edge signal using an AND gate to obtain an interrupt signal, the interrupt signal can be at least one of the single-edge trigger signal, the double-edge trigger signal, or the interrupt mask signal, so that a plurality of third target pins for the interrupt function module can be configured to input at least one interrupt signal of the single-edge trigger signal, the double-edge trigger signal, or the interrupt mask signal.

[0120] Figure 8 Schematically shows a schematic structural diagram of a chip according to an embodiment of the present disclosure.

[0121] As Figure 8 shown, the chip 800 may include a plurality of pins 810, a mode selection terminal 820, a plurality of function modules 830, and a multiplexing device 840.

[0122] The multiplexing device 840 can be electrically connected to the plurality of pins 810, the mode selection terminal 820, and the plurality of function modules 830.

[0123] The multiplexing device 840 can be connected to Figure 1 the multiplexing device 100 in Figure 6 or the multiplexing device 600 in

[0124] has a similar structure or function. For simplicity, it will not be described in detail here. Figure 1 The pin 810, the mode selection terminal 820, and the plurality of function modules 830 can respectively Figure 6 have a similar structure and function to the pin 101, the mode selection terminal 102, and the plurality of function modules 103 in

[0125] and can also respectively have a similar structure and function to the pin 601, the mode selection terminal 602, and the plurality of function modules 603 in

[0126] Figure 9 The flowchart of the multiplexing method according to the embodiment of the present disclosure is schematically shown.

[0127] like Figure 9 As shown, the multiplexing method includes operation S910 and operation S920.

[0128] In operation S910, multiple functional terminals are connected to at least one target pin among multiple pins according to a function selection signal and a mode selection signal from a mode selection terminal, wherein each functional terminal is used for at least one of multiple functional modules, and the multiple functional modules include at least one working functional module and at least one testing functional module.

[0129] In operation S920, when multiple first target pins electrically connected to multiple target functional terminals are in the same input mode, under the control of a function selection signal, the multiple target functional terminals are connected to a target functional module among multiple functional modules, wherein the target pins include a first target pin and the multiple functional terminals include a target functional terminal.

[0130] It should be noted that, unless it is explicitly stated that there is a sequence of execution between different operations shown in the flowchart in the embodiments of the present disclosure, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order of multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0131] It should also be noted that the multiplexing method in the embodiment of the present disclosure corresponds to the multiplexing device part in the embodiment of the present disclosure. For the specific description corresponding to the multiplexing method part, please refer to the multiplexing device part. For the sake of simplicity, it will not be repeated here.

[0132] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features recited in various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0133] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A multiplexing device, characterized in that: Applied to a chip, the chip includes a plurality of pins, a mode selection terminal and a plurality of functional modules, the plurality of functional modules include at least one working functional module and at least one testing functional module, the multiplexing device includes: a function selection module and a pin selection module, wherein, The function selection module is electrically connected to the plurality of pins and the mode selection terminal, the function selection module includes a plurality of function terminals, each of the function terminals is used for at least one of the plurality of function modules, and the function selection module is configured to connect the plurality of function terminals to at least one target pin among the plurality of pins according to a function selection signal and a mode selection signal from the mode selection terminal; The target pin includes a first target pin, the multiple functional ends include a target functional end, and the pin selection module is configured to connect the multiple target functional ends with a target functional module among the multiple functional modules under the control of the function selection signal when multiple first target pins electrically connected to the multiple target functional ends are in the same input mode.

2. The device according to claim 1, characterized in that The target pin further includes a second target pin, and the plurality of functional terminals further include a first functional terminal and a second functional terminal; the function selection module includes: a first signal selector and a second signal selector corresponding to each of the second target pins; Each of the first function terminals of the first signal selector is electrically connected to at least one of the working function modules, and a plurality of the first function terminals are connected to different working function modules, and the first signal selector is configured to connect a target first function terminal among the plurality of first function terminals to an output terminal of the first signal selector according to the function selection signal; The multiple second function terminals of the second signal selector are electrically connected to the output terminal of the first signal selector and at least one of the test function modules, the control terminal of the second signal selector is electrically connected to the mode selection terminal, and the second signal selector is configured to connect the target second function terminal among the multiple second function terminals of the second signal selector to the second target pin according to the mode selection signal.

3. The device according to claim 2, characterized in that The plurality of functional terminals further include a third functional terminal and a fourth functional terminal; the function selection module further includes: a third signal selector and a fourth signal selector corresponding to each of the first target pins; Each third function terminal of the third signal selector is electrically connected to at least one of the working function modules, and a plurality of the third function terminals are connected to different working function modules. The third signal selector is configured to connect a target third function terminal among the plurality of third function terminals to an input terminal of the third signal selector according to the function selection signal; The multiple fourth function terminals of the fourth signal selector are electrically connected to the input terminal of the third signal selector and at least one of the test function modules, the control terminal of the fourth signal selector is electrically connected to the mode selection terminal, and the fourth signal selector is configured to connect the target fourth function terminal among the multiple fourth function terminals of the fourth signal selector with the first target pin according to the mode selection signal, wherein the target third function terminal or the target fourth function terminal is the target function terminal.

4. The device according to any one of claims 1 to 3, characterized in that The pin selection module includes a plurality of pin selection units, each of which includes: N cascaded fifth signal selectors, where N is an integer greater than 1; The first input terminals of the N fifth signal selectors are electrically connected to the multiple target function terminals respectively; The second input terminal of the nth stage fifth signal selector is electrically connected to the output terminal of the n+1th stage fifth signal selector; The multiple fifth signal selectors are configured to electrically connect the target function terminal connected to the m-th level fifth signal selector with the target function module when the function selection signal selects the m-th level fifth signal selector, n is greater than or equal to 1 and less than N, and m is greater than or equal to 1 and less than or equal to N.

5. The device according to any one of claims 1 to 3, characterized in that: The plurality of first target pins are used to receive a plurality of external function signals for the same function module.

6. The device according to any one of claims 1 to 3, characterized in that Also includes: The selection signal generating module is configured to analyze the external control signal in response to receiving the external control signal to obtain the function selection signal.

7. The device according to any one of claims 1 to 3, characterized in that: The multiple functional modules further include an interrupt functional module; the multiple functional terminals further include an interrupt functional terminal; the target pin further includes a third target pin; the function selection signal includes a control signal, a first edge signal and a second edge signal; the device further includes: An interrupt module, the interrupt module being electrically connected to the interrupt function module and a plurality of interrupt function terminals; The interrupt module is configured to obtain an interrupt signal based on multiple third edge signals from the multiple third target pins, the first edge signal and the second edge signal under the control of the control signal when multiple third target pins respectively electrically connected to the multiple interrupt function terminals are in the same input interrupt mode, and output the interrupt signal to the interrupt function module.

8. The device according to claim 7, characterized in that The control signal includes: a single-edge control signal, a double-edge control signal and an interrupt shielding signal; the interrupt module includes: A first trigger selector, wherein a plurality of input terminals of the first trigger selector are electrically connected to the plurality of interrupt function terminals respectively, and the first trigger selector is configured to select the first edge signal, the second edge signal and one of a plurality of third edge signals under the control of the single edge control signal to obtain a single edge trigger signal; an OR gate, configured to perform an OR operation on the first edge signal and the second edge signal to obtain a double-edge trigger signal; a second trigger selector, wherein an input terminal of the second trigger selector is electrically connected to an output terminal of the first trigger selector and an output terminal of the OR gate, and the second trigger selector is configured to select one of the single-edge trigger signal and the double-edge trigger signal as a target edge signal under the control of the double-edge control signal; An AND gate, wherein the input end of the AND gate is electrically connected to the output end of the second trigger selector, the output end of the AND gate is electrically connected to the interrupt function module, and the AND gate is configured to perform an AND operation on the interrupt masking signal and the target edge signal to obtain the interrupt signal.

9. The device according to any one of claims 1 to 3, characterized in that: The test function module includes at least one of a simulation test function module, a testability function module and a debugging function module.

10. A chip, characterized in that: include: Multiple pins; Mode selection terminal; Multiple functional modules; The multiplexing device according to any one of claims 1 to 9, wherein the multiplexing device is electrically connected to the plurality of pins, the mode selection terminal and the plurality of functional modules.

11. A multiplexing method, characterized in that: include: Connecting the plurality of functional terminals to at least one target pin among the plurality of pins according to the function selection signal and the mode selection signal from the mode selection terminal, wherein each of the functional terminals is used for at least one of the plurality of functional modules, the plurality of functional modules including at least one working functional module and at least one testing functional module; When a plurality of first target pins electrically connected to a plurality of target functional terminals are in the same input mode, the plurality of target functional terminals are connected to a target functional module among the plurality of functional modules under the control of the function selection signal, wherein the target pins include the first target pins and the plurality of functional terminals include the target functional terminal.

Images