Wafer level chip system design space construction and fast parameter search method

Abstract

This invention discloses a method for constructing a wafer-level chip system design space and rapidly searching for parameters. The method includes: task graph definition, prefab parameter quantization, joint model construction based on task graph features and prefab features, and Bayesian optimization implementation strategy. The technical solution of this invention can guide the construction and searching of the design space, reducing the number of simulator calls and enabling the construction of the wafer-level chip system architecture design space, efficient parameter search, and performance evaluation. This method can be used for agile design and hardware implementation of multi-chip integrated wafer-level chip system architectures.

Description

Technical Field

[0001] This invention relates to the field of wafer-level chip system architecture design technology, specifically to a method for constructing a wafer-level chip system design space and searching for fast parameters. Background Technology

[0002] With the rapid development of integrated circuit technology, wafer-scale systems (WSS) have become an important direction in the field of high-performance computing. Compared with traditional chip design, wafer-scale systems significantly improve computing power and energy efficiency by integrating the functions of multiple chips onto a single wafer. However, this highly integrated design approach also brings enormous design complexity, including hardware and software co-design, task mapping and scheduling, performance optimization, and power management.

[0003] In wafer-level chip system design, design space exploration (DSE) is a critical task. Its goal is to find the optimal design that satisfies performance, power, area, and power consumption (PPA) constraints within a broad design parameter space. However, as design scale increases, the dimensionality and complexity of the parameter space also increase significantly. Traditional design space exploration methods often employ heuristic algorithms or experience-based manual tuning. While these methods are effective for small-scale designs, they often exhibit the following shortcomings when facing the extremely high-dimensional design space of wafer-level systems:

[0004] (1) Low computational efficiency: The number of parameter combinations grows exponentially, which means that traditional methods require a lot of computational resources to cover the design space; (2) Insufficient global optimization capability: Existing methods are often limited to local optimal solutions and lack the ability to effectively explore the global design space; (3) Difficult task mapping and resource scheduling: The mapping relationship between system-level tasks and hardware resources is complex and dynamic, and existing methods cannot effectively handle multi-task concurrency and hardware resource contention; (4) Lack of multimodal data processing capability: Wafer-level chip system design involves software and hardware interaction, multi-level performance indicators and multimodal data (such as structured task graphs and hardware parameters), and traditional methods have difficulty efficiently integrating and utilizing this information.

[0005] In recent years, the development of machine learning and optimization algorithms has provided new solutions for design space exploration. For example, Bayesian optimization algorithms have excellent global search capabilities, enabling efficient optimization even with high evaluation costs; Graph Neural Networks (GNNs) excel at processing structured data and can be used to represent task graphs or hardware topologies. However, the application of these two technologies in wafer-level chip system design still faces challenges: Bayesian optimization may suffer from slow convergence in high-dimensional parameter spaces, requiring improvements in the design of the acquisition function and computational efficiency; the training process of Graph Neural Networks is complex, and how to optimize them in conjunction with the specific needs of wafer-level design remains an open question. The integration and fusion of these two technologies requires the design of an efficient framework that also supports the interpretation and verification of design results.

[0006] Therefore, there is an urgent need for an intelligent design space exploration method that combines Bayesian optimization and graph neural networks, which can effectively handle complex multimodal input data, provide global optimization capabilities, and at the same time have both computational efficiency and interpretability to meet the needs of wafer-level chip system design. Summary of the Invention

[0007] The purpose of this invention is to provide a design space construction and fast parameter search method for wafer-level chip system architecture. This method combines Bayesian optimization algorithm and joint model, and performs iterative optimization through initialization, feature extraction, solution space generation, Bayesian optimization and model update. While ensuring high efficiency, it can significantly improve the performance of wafer-level chip system design, and is especially suitable for high-complexity system design and multi-task scheduling optimization.

[0008] This invention is achieved using the following technical solution:

[0009] The design space construction and parameter search method of this invention mainly includes the following five stages:

[0010] 1. Initialization Phase

[0011] In this phase, computational tasks are represented by a task graph. Each node in the task graph represents a computational task, and the edges between nodes represent the dependencies between tasks. Simultaneously, the prefabricated components are quantized, including both dynamic and static parameters.

[0012] 2. Feature Extraction Stage

[0013] Graph convolutional networks are used to extract features from the task graph. Each task node contains node features, primarily reflecting the task's computational resource requirements. Node features include, but are not limited to, information such as task computation latency, memory requirements, data transfer requirements, and computational load. Edges between tasks contain edge features, which mainly describe the data flow dependencies and priorities between tasks. These features play a crucial role in task scheduling, influencing the order and dependencies of task execution.

[0014] Hardware characteristics of a chip can be categorized into two types: static parameters and dynamic parameters. Static parameters include manufacturing process, number of cores, cache hierarchy, etc. These hardware characteristics are typically determined by the chip's physical structure and do not change with the task. Dynamic parameters reflect the impact of task load on hardware performance, including instruction cycle count, memory bandwidth utilization, power consumption curves, etc., and are usually obtained through simulation tools. Transformer networks are used to extract features from pre-fabricated parameters.

[0015] 3. Solution space generation stage

[0016] The main task of this stage is to input the features of the task graph and the prefabricated parameter features into the joint model to generate the solution space. The joint model uses a Dynamic Graph Neural Network (D-GNN) for feature fusion. The D-GNN can extract the features of nodes and edges in the graph structure, while capturing the dependencies between tasks. Through graph convolution operations, the D-GNN can effectively extract the topological structure information of the task graph, providing a foundation for subsequent task partitioning and hardware selection.

[0017] The joint model also employs a cross-modal attention mechanism to address the heterogeneity between task features and hardware features. In this process, the attention mechanism automatically identifies which task features and which hardware features have strong correlations, thereby aligning their feature spaces and further enhancing the model's expressive power.

[0018] The generated solution space contains two key elements: a task partitioning scheme and a grain selection sequence. The task partitioning scheme determines how each task is allocated across different grains, while the grain selection sequence determines which specific grains are used to execute the tasks.

[0019] 4. Bayesian Optimization Stage

[0020] The goal of this phase is to quickly search for the optimal design scheme based on the generated solution space using Bayesian optimization algorithms. Bayesian optimization first requires constructing a Gaussian process (GP) as a surrogate model to predict the performance of different design schemes. In the surrogate model, the inputs are the task partitioning scheme and the grain selection sequence, and the outputs are the corresponding performance metrics, such as power consumption, latency, and area.

[0021] Gaussian processes use kernel functions to model uncertainties in the design space, and the hyperparameters of the surrogate model are updated using methods such as maximum marginal likelihood estimation.

[0022] Bayesian optimization uses methods such as Expected Improvement (EI) as the acquisition function. EI can guide the search direction based on the uncertainty of the current model and select the evaluation point most likely to bring performance improvement. By calling the simulator multiple times, Bayesian optimization can gradually converge to a design scheme with optimal performance.

[0023] 5. Model Update Phase

[0024] After each optimization, the loss function is calculated based on the simulation results, and the weights of the graph neural network in the joint model are updated using the backpropagation algorithm. The loss function consists of two parts: one part is the cross-entropy loss of the task partitioning scheme and the grain selection sequence, which aims to ensure the rationality of task partitioning and hardware selection; the other part is the mean squared error (MSE) based on the simulation results, which is used to measure the gap between the predicted performance metrics and the actual performance.

[0025] The hyperparameters of the surrogate model are updated using methods such as marginal likelihood gradient descent (MLE) to improve the model's prediction accuracy. In each iteration, both the joint model and the surrogate model are updated based on the new simulation results, gradually optimizing the design until the preset convergence condition is met.

[0026] Compared with existing technologies, this invention is a method for design space construction and rapid parameter search for wafer-level chip system architecture. It has the following effects: revealing the temporal and spatial statistical characteristics of applications running on wafer-level chip systems; establishing domain-specific hardware and software co-computing wafer-level chip architecture design theories and methods; forming the fundamental theories and methods for wafer-level chip software development environments; and providing theoretical support and architectural guidance for the design and implementation of domain-specific wafer-level chips. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the initialization, feature extraction, and solution space generation process in this invention.

[0028] Figure 2 This is a schematic diagram of the Bayesian optimization process in this invention.

[0029] Figure 3 This is a flowchart illustrating the implementation of the design space construction and fast parameter search method of this invention. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings.

[0031] As attached Figure 1As shown, the input computation task and preform are first initialized, the computation task is represented as a directed acyclic graph, the quantization parameters of the preform are obtained, and the features of the task graph and preform parameters are extracted using graph convolutional networks and Transformers respectively. The features are input into an encoder network with an attention layer, and finally the solution space is output through a decoder network.

[0032] As attached Figure 2 As shown, the Gaussian model is first pre-trained using a simulator and a small number of random solutions. Then, the solution output by the joint model is provided to the Gaussian model, which outputs an evaluation value. Subsequently, based on the distribution of performance in the solution space, the next evaluation point is selected and the performance is evaluated using a simulator. If the performance meets the requirements, the optimal solution is output; otherwise, the parameters of the joint model and the Gaussian model are updated based on the simulator's evaluation results.

[0033] As attached Figure 3 As shown, the implementation process of the design space construction and fast parameter search method of the present invention includes an initialization stage, a feature extraction stage, a solution space generation stage, a Bayesian optimization stage, and a model update stage. The specific steps of each stage are as follows.

[0034] 1. Initialization phase:

[0035] Task Graph Construction: First, the computational tasks are represented as a graph, where each node represents a computational task. Dependencies between tasks are represented by edges between nodes. The structure of the task graph clearly shows the execution order and dependencies of the tasks.

[0036] Quantification of precast component parameters:

[0037] Static parameters: Static parameters are fixed by the hardware design, such as manufacturing process, number of cores in the chip, cache hierarchy, etc. These characteristics do not change during the calculation process.

[0038] Dynamic parameters: Dynamic parameters are the relationship between hardware performance and load during task execution, such as instruction cycle count, memory bandwidth utilization, and power consumption. These parameters are usually obtained through simulation tools and reflect the impact of the task on the hardware.

[0039] 2. Feature extraction stage:

[0040] Task graph feature extraction: The task graph is processed using a Graph Convolutional Network (GCN). Each task node contains features reflecting the computational requirements of that task, such as computation latency, memory requirements, and data transfer requirements. These features reflect the computational resource demands of each task.

[0041] Edge features: Edges in the task graph connect different tasks, and their features mainly describe the data flow dependencies and priorities between tasks. Edge features are particularly important in task scheduling because they affect the order and dependencies of task execution.

[0042] Prefab feature extraction: The Transformer network is used to process static and dynamic prefab parameters to extract hardware characteristics, such as chip hardware architecture characteristics and the impact of load on hardware performance. The key to this stage is to obtain precise information on how hardware resources affect task execution.

[0043] 3. Solution space generation stage:

[0044] Joint model input: The task features from the task graph and the hardware prefab parameter features are input into the joint model. The model fuses the task features and hardware features to generate a solution space.

[0045] D-GNN is used for feature fusion to extract topological information of the task graph and capture the dependencies between tasks. Graph Neural Networks (GNNs) have excellent graph data processing capabilities and can effectively uncover complex dependency structures between tasks.

[0046] Cross-modal attention mechanism: This mechanism addresses the heterogeneity between task features and hardware features. It automatically identifies which task features are strongly correlated with which hardware features, aligns these features, and thus enhances the model's expressive power.

[0047] Generating the solution space: The solution space contains two key elements:

[0048] Task partitioning scheme: Determines how tasks will be divided and assigned to different hardware units (dies) for execution.

[0049] Grain selection sequence: determines which specific grains to use to perform each task.

[0050] 4. Bayesian optimization stage:

[0051] Proxy model construction: The core of Bayesian optimization lies in constructing a surrogate model, usually a Gaussian process (GP) model, to predict the performance (such as power consumption, latency, etc.) of different design schemes. The surrogate model is obtained through simulation or experimental data.

[0052] Modeling of Gaussian processes: By selecting an appropriate kernel function, Gaussian processes model the uncertainty of the design space and can predict performance indicators between task partitioning schemes and grain selection sequences.

[0053] Acquisition Function (EI): Bayesian optimization automatically selects the scheme most likely to improve performance in the next evaluation by using Expected Improvement (EI).

[0054] Performance evaluation: Bayesian optimization guides the search direction based on the uncertainty of the current model, and gradually converges to the optimal design solution by continuously evaluating the results of the simulator.

[0055] 5. Model update phase:

[0056] Simulation Results and Loss Function: After each optimization, the actual performance of the task partitioning and grain selection schemes is calculated using a simulator. The simulation results are compared with the model's predictions, and the loss function is calculated.

[0057] The loss function consists of two parts:

[0058] Cross-entropy loss: used to optimize the rationality of task partitioning schemes and grain selection sequences, ensuring that task allocation and hardware selection meet actual needs.

[0059] Mean Squared Error (MSE): Used to measure the difference between the performance metrics predicted by the model (such as power consumption, latency, etc.) and the simulation results.

[0060] Backpropagation update: Based on the loss function, the weights of the graph neural network in the joint model are updated using the backpropagation algorithm to gradually optimize the model.

[0061] Surrogate Model Update: The Gaussian process model in Bayesian optimization also needs updating. The hyperparameters of the surrogate model are adjusted using marginal likelihood gradient descent (MLE) to improve the accuracy of performance predictions.

Claims

1. A method for constructing a wafer-level chip system design space and searching for fast parameters, wherein the method includes a Bayesian optimization algorithm and a joint model, characterized in that: (1) Initialization phase: After the computation task is input, it needs to be transformed into a task graph. The task graph is a directed graph consisting of a set of nodes and edges. Each node represents a computation task, and the edges represent the dependencies between tasks. At the same time, the available prefabricated parameters are quantified, including static parameters and dynamic parameters. (2) Feature extraction stage: The task graph is analyzed to extract node features and edge features. The node features include the task computing resource requirements, and the edge features include the data flow dependencies and priorities between tasks. At the same time, the hardware parameters of the pre-fabricated die are quantitatively modeled. The quantitative indicators include task execution latency, chip area and power consumption. (3) Solution space generation stage: Input the task graph features and grain features into the joint model, perform feature fusion through dynamic graph neural network and cross-modal attention mechanism, and output the solution space composed of task partitioning scheme and grain selection sequence; (4) Bayesian optimization stage: Based on the solution space, a Gaussian process proxy model is constructed, the expected improvement function is used to select the evaluation point, and the simulator is called to obtain the system performance index; (5) Model update stage: Calculate the loss function based on the simulation results, update the graph neural network weights of the joint model through backpropagation, and update the hyperparameters of the surrogate model at the same time. Iterate through steps (2)-(4) until the preset convergence condition is reached.

2. The method according to claim 1, characterized in that, The quantitative modeling of the pre-fabricated die in step (2) includes: static parameters including process technology, number of cores, cache hierarchy; dynamic parameters including instruction cycle count, memory bandwidth utilization and power consumption curve based on task load simulation.

3. The method according to claim 1, characterized in that, In step (2), the task graph feature extraction can use deep learning models or traditional machine learning algorithms to extract node features and edge features.

4. The method according to claim 1, characterized in that, In step (3), the joint model adopts an encoder-decoder architecture.

5. The method according to claim 4, characterized in that, Encoder side: High-dimensional features are extracted using graph convolutional networks, and cross-modal alignment of task features and grain parameters is achieved through multi-head attention layers.

6. The method according to claim 4, characterized in that, Decoder side: A reinforcement learning strategy is used to generate a task partitioning scheme, which is combined with the output of the gated recurrent unit to select the crystal.

7. The method according to claim 1, characterized in that, The implementation of Bayesian optimization in step (4) includes: the surrogate model adopts a Gaussian process model, in which the parameters of the hyperparameter covariance function and the variance of the noise are updated by the maximum marginal likelihood estimation method, and the acquisition function adopts the expected improvement function EI to guide Bayesian optimization.

8. The method according to claim 1, characterized in that, In step (5), the model update rule is as follows: the loss function of the joint model includes the cross-entropy loss of the task partitioning scheme and the grain selection sequence, as well as the mean square error of the simulation index. The hyperparameters of the surrogate model are updated by the marginal likelihood gradient descent method.

9. The method according to claim 1, characterized in that: This involves exploring the design space of wafer-level chip system architectures for selecting prefabricated components to match different task mappings in complex application scenarios.

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