Wiring method for improving signal integrity of high-speed bus

Abstract

The invention belongs to the field of signal wiring, particularly relates to a wiring method for improving the signal integrity of a high-speed bus, and aims to solve the problems that enough spacing isolation cannot be kept when a large number of high-speed signals are concentrated in a single signal layer for wiring due to the limited number of optimal wiring layers in a traditional lamination design, and the wiring quality is influenced. Therefore, the electromagnetic interference between the signals is increased, and the signal quality is reduced. The method comprises the steps that the number of internal signal layers, used for high-speed signal wiring, of a packaging substrate or a printed circuit board is determined; the number of high-speed bus signals is determined and sorted, and the high-speed bus signals are grouped according to the number of internal signal layers; and completing wiring of each group of high-speed bus signals in the corresponding internal signal layer, and setting corresponding reference ground wire layer copper-clad grounding processing. The internal signal layer and the ground wire layer are coated with copper in pairs for grounding, electromagnetic interference is reduced, and signal integrity is improved.

Description

Technical Field

[0001] The present invention belongs to the field of signal wiring, and particularly relates to a wiring method for improving the signal integrity of a high-speed bus. Background Art

[0002] Modern electronic design and chip manufacturing technologies are developing rapidly. With the increasing scale of system integration, the signal operating frequency is increasing day by day, the circuit interconnection density is continuously increasing, and signal integrity issues have received more and more attention. Signal integrity refers to the signal quality problems of signal voltage and current during transmission, including noise, interference, and the resulting timing effects, etc., indicating the functional characteristics that the signal can still maintain correctness after being transmitted through the signal line, that is, the signal can respond with the correct timing, amplitude, phase, etc. in the circuit.

[0003] For a high-speed bus, unreasonable wiring will cause or directly lead to signal distortion, timing errors, incorrect data, address and control signals, and system malfunctions, or even system crashes. In engineering applications, high-speed circuits use multi-layer packaging substrates or printed circuit boards for wiring. Among all wiring layers, the internal signal layer close to the ground layer is generally called the best wiring layer, which can ensure signal quality and reduce electromagnetic radiation.

[0004] In traditional stack-up designs, the number of best wiring layers is limited. And high-speed buses usually include a large number of signals and are concentrated on a single signal layer for wiring design. Its disadvantage is that the signal wiring area is restricted, and sufficient spacing isolation cannot be maintained between high-speed signals. The electromagnetic interference generated between signals will cause the signal quality to decline, reduce the accuracy of signal transmission, and even cause the system to malfunction.

[0005] Based on this, the present invention proposes a wiring method for improving the signal integrity of a high-speed bus. Summary of the Invention

[0006] In order to solve the above problems in the prior art, that is, in the design of high-speed circuits, due to the limited number of best wiring layers in traditional stack-up designs, when a large number of high-speed signals are concentrated on a single signal layer for wiring, sufficient spacing isolation cannot be maintained, resulting in an increase in electromagnetic interference between signals, a decline in signal quality, and ultimately the system may malfunction. The present invention provides a wiring method for improving the signal integrity of a high-speed bus, and the method includes the following steps:

[0007] Step S1, determining the number of internal signal layers of the packaging substrate or printed circuit board for high-speed signal wiring;

[0008] Step S2, determining the number of high-speed bus signals and sorting them, and grouping the high-speed bus signals according to the number of internal signal layers;

[0009] Step S3: Route each group of the high-speed bus signals on the corresponding internal signal layer and perform copper cladding grounding treatment on the corresponding reference ground layer.

[0010] Further, the packaging substrate or printed circuit board includes an external signal layer, internal signal layers, a power layer, and a ground layer.

[0011] Further, the external signal layer is used for routing low-speed signals, and its number of stacked layers is 2 layers, namely the top layer and the bottom layer;

[0012] The internal signal layers are used for routing design of high-speed signals, and the number of its stacked layers is 2n layers, where n is a positive integer;

[0013] The power layer is used to supply power to the high-speed bus, and the number of the power layer is 1 layer;

[0014] The ground layer provides a return path for the external signal layer, the internal signal layers, and the power layer, and the number of stacked layers of the ground layer is 2n + 1 layers.

[0015] Further, the number of the internal signal layers is an even number and is symmetrically arranged.

[0016] Further, define the number of the high-speed bus signals as m, sorted as Sig1, Sig2, Sig3... Sigm, and divide the m high-speed bus signals into 2n groups.

[0017] Further, the method for dividing the m high-speed bus signals into 2n groups is as follows:

[0018] Divide the Sigi-th high-speed bus signal into the k-th group:

[0019] k = (i - 1) mod 2n + 1;

[0020] where i is one of the m high-speed bus signals, i ≤ m; k is one of the 2n groups, k ≤ 2n; mod is the modulo operation.

[0021] Further, the method for routing each group of the high-speed bus signals on the corresponding internal signal layer is as follows:

[0022] Route the high-speed bus signals of the 1st group to the 2n-th group to the internal signal layers Inner1 to Inner2n respectively, so that the high-speed bus signals of the k-th group are routed on the internal signal layer Innerk;

[0023] Each internal signal layer Innerk and the corresponding ground layer Gndk are adjacently arranged in pairs to form a signal layer - ground layer pair.

[0024] Further, copper plating is performed on the blank areas where no signal conductors are arranged in the internal signal layers Inner1 to Inner2n, and on all areas of the ground layers Gnd1 to Gnd2n, and they are electrically connected to the system ground plane.

[0025] Further, a power layer Power and a corresponding ground layer Gnd are arranged between the internal signal layers Innerk and Innerk + 1 to complete the power copper plating design.

[0026] Advantages of the present invention:

[0027] (1) Optimize electromagnetic shielding performance: By strictly setting the internal signal layers and the corresponding ground layers in pairs, and copper plating and grounding the blank areas of the ground layer and the internal signal layer, a continuous electromagnetic shielding structure is formed, effectively reducing electromagnetic radiation and external interference during high-speed signal transmission, and improving signal integrity and impedance continuity.

[0028] (2) Improve wiring flexibility and signal isolation: Adopt a cyclic grouping rule based on the number of layers, evenly distribute the high-speed bus signals to multiple internal signal layers, significantly reduce the wiring density of a single layer, expand the adjacent signal spacing, avoid cross-talk between signals, and at the same time provide an independent wiring channel for key signals to enhance the timing control ability.

[0029] (3) Enhance power supply stability and reliability of the return path: A power layer and a corresponding ground layer are arranged between adjacent internal signal layers. Through power copper plating design and optimization of the low-impedance return path, the influence of power supply noise on high-speed signals is reduced, ensuring the stability and accuracy of signal transmission.

[0030] (4) Support the scalability of high-density high-speed buses: Through a formulaic stack design (4n + 4 layers, n = 1, 2, 3...), flexibly expand the number of internal signal layers to adapt to the wiring requirements of high-speed buses of different scales, and at the same time maintain the proportion of the best wiring layer (close to the ground layer), taking into account both system integration and signal quality. Description of the Drawings

[0031] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes, and advantages of the present application will become more obvious:

[0032] Figure 1 is a stack diagram of a package substrate or a printed circuit board of a wiring method for improving the signal integrity of a high-speed bus according to the present invention;

[0033] Figure 2 is a schematic diagram of a high-speed bus signal wiring method provided by the prior art;

[0034] Figure 3It is the wiring schematic diagram of the first group of high-speed bus signals on the internal signal layer Inner1 in a wiring method for improving the signal integrity of high-speed buses according to the present invention;

[0035] Figure 4 It is the wiring schematic diagram of the second group of high-speed bus signals on the internal signal layer Inner2 in a wiring method for improving the signal integrity of high-speed buses according to the present invention;

[0036] Figure 5 It is the wiring schematic diagram of the third group of high-speed bus signals on the internal signal layer Inner3 in a wiring method for improving the signal integrity of high-speed buses according to the present invention;

[0037] Figure 6 It is the wiring schematic diagram of the fourth group of high-speed bus signals on the internal signal layer Inner4 in a wiring method for improving the signal integrity of high-speed buses according to the present invention;

[0038] Figure 7 It is the comparison diagram of the return loss of high-speed bus signals between the wiring method of the present invention and the prior art in a wiring method for improving the signal integrity of high-speed buses according to the present invention. Detailed implementation manners

[0039] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. Additionally, it should be noted that for the sake of description, only parts related to the relevant invention are shown in the drawings.

[0040] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0041] The present invention provides a wiring method for improving the signal integrity of high-speed buses, and the method includes the following steps:

[0042] Step S1, determining the number of internal signal layers for high-speed signal wiring on the package substrate or printed circuit board;

[0043] Step S2, determining the number of high-speed bus signals and sorting them, and grouping the high-speed bus signals according to the number of internal signal layers;

[0044] Step S3, respectively wiring each group of the high-speed bus signals on the corresponding internal signal layer, and performing copper plating grounding treatment on the corresponding reference ground plane layer.

[0045] For a clearer description of a wiring method for improving the signal integrity of high-speed buses according to the present invention, the following is combined with Figures 1-7Details of each step in the embodiments of the present invention are elaborated below.

[0046] A wiring method for improving the signal integrity of a high-speed bus according to the first embodiment of the present invention includes steps S1 to S3, and each step is described in detail as follows:

[0047] Step S1: Determine the number of internal signal layers of the package substrate or printed circuit board for high-speed signal wiring.

[0048] The package substrate or printed circuit board includes four types: an external signal layer, an internal signal layer, a power layer, and a ground layer, and the total number of stack layers is 4n + 4 (n = 1, 2, 3...).

[0049] The external signal layer is used for low-speed signal wiring. The number of internal signal layers is even and symmetrically arranged. The number of stack layers is 2 layers, namely the top layer and the bottom layer, defined as Top and Bottom.

[0050] The internal signal layer is used for high-speed signal wiring design. The number of stack layers is 2n layers, where n is a positive integer, and the sorting is defined as Inner1, Inner2 to Inner2n.

[0051] The power layer is defined as Power and is used to supply power to the high-speed bus. The number of power layers is 1 layer.

[0052] The ground layer provides a stable and low-impedance return path for the external signal layer, the internal signal layer, and the power layer. The number of stack layers of the ground layer is 2n + 1 layers, respectively defined as Gnd, Gnd1, Gnd2 to Gnd2n, where the Gnd layer corresponds to the power layer Power layer, and Gnd1 to Gnd2n correspond to the internal signal layers Inner1 to Inner2n).

[0053] Step S2: Determine the number of high-speed bus signals and sort them, and group the high-speed bus signals according to the number of internal signal layers.

[0054] In the present invention, the number of the high-speed bus signals is defined as m, and the sorting is Sig1, Sig2, Sig3... Sigm. The m high-speed bus signals are divided into 2n groups.

[0055] Furthermore, the method of dividing the m high-speed bus signals into 2n groups is as follows:

[0056] The Sigi-th high-speed bus signal is divided into the k-th group:

[0057] k = (i - 1) mod 2n + 1;

[0058] Wherein, i is one of the m high-speed bus signals, i ≤ m; k is one of the 2n groups, k ≤ 2n; mod is the modulo operation.

[0059] In other words, the high-speed signals with serial numbers Sig1, Sig2n+1, Sig4n+1,... are divided into the first group; the high-speed signals with Sig2, Sig2n+2, Sig4n+2,... are divided into the second group; the high-speed signals with Sig3, Sig2n+3, Sig4n+3,... are divided into the third group, and so on. The high-speed signals with Sig2n, Sig4n, Sig6n,... are divided into the 2nth group.

[0060] Step S3: Route each group of the high-speed bus signals on the corresponding internal signal layer, and set the corresponding reference ground layer for copper cladding grounding treatment.

[0061] The grouped high-speed bus signals have been routed on the corresponding internal signal layer. That is, the first group of signals is routed on the internal signal layer Inner1, the second group of signals is routed on the internal signal layer Inner2, and so on. The 2nth group of signals is routed on the internal signal layer Inner2n. And the internal signal layer with the completed routing design is set in pairs with the corresponding ground layer, and copper cladding grounding treatment is performed on the blank areas of the internal signal layers Inner1 to Inner2n and the ground layers Gnd1 to Gnd2n.

[0062] A power layer Power and a ground layer Gnd corresponding to the power layer Power are set between the internal signal layers Innerk and Innerk+1 to complete the power copper cladding design.

[0063] As Figure 1 shown, the stacked design of the package substrate or printed circuit board applicable to the present invention is composed of an external signal top layer Top, an external signal bottom layer Bottom, internal signal layers Inner1 to Inner2n, a power layer Power, and ground layers Gnd, Gnd1 to Gnd2n. Assuming that the internal signal layer of the package substrate or printed circuit board is 4 layers (i.e., n = 2), the number of stacked layers is 12 layers. The stacking order from top to bottom is the external signal top layer Top, the ground layer Gnd1, the internal signal layer Inner1, the ground layer Gnd2, the internal signal layer Inner2, the ground layer Gnd, the power layer Power, the internal signal layer Inner3, the ground layer Gnd3, the internal signal layer Inner4, the ground layer Gnd4, and the external signal bottom layer Bottom.

[0064] As Figures 2-6 , wherein, Figure 2 is a schematic diagram of a high-speed bus signal routing method provided by the prior art. Figures 3-6Schematic diagram of the high-speed bus signal wiring method provided by the present invention.

[0065] It is assumed that the high-speed bus includes 17 signals, and the signals are sorted and defined as Sig1 to Sig17. Calculation is performed according to k = (i - 1) mod 2n + 1, specifically as follows:

[0066] Total number of signals: m = 17 (the signals are Sig1 to Sig17)

[0067] Number of groups 2n = 4 (i.e., n = 2)

[0068] Grouping formula: The signal serial numbers included in the kth group are: k = (i - 1) mod 2n + 1

[0069] Grouping calculation process

[0070] Step 1: Determine the value of 2n

[0071] According to the number of groups being 4, it can be known that:

[0072] Step 2: Calculate the group number k for each signal Sigi;

[0073] Calculate the group numbers to which all signals belong through the formula k = (i - 1) mod 4 + 1:

[0074] When the signal serial number is 1: (1 - 1) mod 4 + 1 = 0 + 1 = 1, that is, it is assigned to the 1st group;

[0075] When the signal serial number is 2: (2 - 1) mod 4 + 1 = 1 + 1 = 2, that is, it is assigned to the 2nd group;

[0076] When the signal serial number is 3: (3 - 1) mod 4 + 1 = 2 + 1 = 3, that is, it is assigned to the 3rd group;

[0077] When the signal serial number is 4: (4 - 1) mod 4 + 1 = 3 + 1 = 4, that is, it is assigned to the 4th group;

[0078] When the signal serial number is 5: (5 - 1) mod 4 + 1 = 0 + 1 = 1, that is, it is assigned to the 1st group;

[0079] When the signal serial number is 6: (6 - 1) mod 4 + 1 = 1 + 1 = 2, that is, it is assigned to the 2nd group;

[0080] When the signal serial number is 7: (7 - 1) mod 4 + 1 = 2 + 1 = 3, that is, it is assigned to the 3rd group;

[0081] And so on for the calculation;

[0082] When the signal serial number is 17: (17 - 1) mod 4 + 1 = 0 + 1 = 1, that is, it is assigned to the 1st group.

[0083] Therefore, signals Sig1, Sig5, Sig9, Sig13, and Sig17 are grouped into Group 1; Sig2, Sig6, Sig10, and Sig14 are grouped into Group 2; signals Sig3, Sig7, Sig11, and Sig15 are grouped into Group 3; and signals Sig4, Sig8, Sig12, and Sig16 are grouped into Group 4.

[0084] Referring to Figure 3 , Figure 4 , Figure 5 and Figure 6 , the routing of the high-speed bus signals in Group 1 is completed on the internal signal layer Inner1, the routing design of the high-speed bus signals in Group 2 is completed on the internal signal layer Inner2, the routing design of the high-speed bus signals in Group 3 is completed on the internal signal layer Inner3, the routing design of the high-speed bus signals in Group 4 is completed on the internal signal layer Inner4, and copper plating grounding treatment is performed in the blank areas of Gnd1-4 and the internal signal layers Inner1-4, and power copper plating design is completed on the power layer Power and the ground wire layer Gnd.

[0085] Referring to Figure 7 , it is a comparison chart of the return loss of high-speed bus signals using the routing method of the present invention and the prior art. It can be seen that according to the engineering requirement that the return loss is lower than -20 dB, the routing method provided by the present invention can improve the return loss of high-speed bus signals and enhance the signal integrity during signal transmission.

[0086] Although the steps are described in the above sequential order in the above embodiments, those skilled in the art can understand that in order to achieve the effects of this embodiment, different steps do not have to be executed in such an order, and they can be executed simultaneously (in parallel) or in a reversed order, and these simple changes are all within the protection scope of the present invention.

[0087] The terms "first", "second", etc. are used to distinguish similar objects, rather than to describe or represent a specific order or sequence.

[0088] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, so that a process, method, article, or device / equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent in these processes, methods, articles, or devices / equipment.

[0089] So far, the technical solution of the present invention has been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.

Claims

1. A wiring method for improving the signal integrity of a high-speed bus, characterized in that: The method comprises the following steps: Step S1, determining the number of internal signal layers of a package substrate or a printed circuit board for high-speed signal routing; Step S2, determining the number of high-speed bus signals and sorting them, and grouping the high-speed bus signals according to the number of internal signal layers; Step S3, routing each group of the high-speed bus signals in the corresponding internal signal layer, and setting the corresponding reference ground layer copper grounding treatment.

2. A wiring method for improving high-speed bus signal integrity according to claim 1, characterized in that: The packaging substrate or printed circuit board includes an external signal layer, an internal signal layer, a power layer and a ground layer.

3. A wiring method for improving high-speed bus signal integrity according to claim 2, characterized in that: The external signal layer is used for low-speed signal wiring, and has two layers, namely a top layer and a bottom layer; The internal signal layer is used for high-speed signal wiring design, and the number of stacked layers is 2n, where n is a positive integer; The power supply layer is used to provide power for the high-speed bus, and the number of the power supply layer is 1; The ground layer provides a return path for the external signal layer, the internal signal layer and the power layer, and the number of stacked layers of the ground layer is 2n+1.

4. A wiring method for improving high-speed bus signal integrity according to claim 2, characterized in that: The number of the internal signal layers is even and they are symmetrically arranged.

5. A wiring method for improving high-speed bus signal integrity according to claim 2, characterized in that: The number of the high-speed bus signals is defined as m, which are arranged as Sig1, Sig2, Sig3, ..., Sigm, and the m high-speed bus signals are divided into 2n groups.

6. A wiring method for improving high-speed bus signal integrity according to claim 3, characterized in that: The m high-speed bus signals are divided into 2n groups, and the division method is as follows: Divide the Sigi high-speed bus signal into the kth group: k = (i-1) mod 2n + 1; Among them, i is one of m high-speed bus signals, i≤m; k is one of 2n groups, k≤2n; mod is a modular operation.

7. A wiring method for improving high-speed bus signal integrity according to claim 5, characterized in that: The high-speed bus signals of each group are routed in the corresponding internal signal layers respectively, and the method is as follows: The first to the 2n groups of high-speed bus signals are respectively routed to the internal signal layers Inner1 to Inner2n, so that the kth group of high-speed bus signals is routed to the internal signal layer Innerk; Each internal signal layer Innerk is arranged adjacent to a corresponding ground layer Gndk in pairs to form a signal layer-ground layer pair.

8. A wiring method for improving high-speed bus signal integrity according to claim 6, characterized in that: Blank areas in the internal signal layers Inner1 to Inner2n where no signal conductors are laid, and all areas of the ground layers Gnd1 to Gnd2n, are copper-clad and electrically connected to the system ground plane.

9. A wiring method for improving high-speed bus signal integrity according to claim 7, characterized in that: A power layer Power and a ground layer Gnd corresponding to the power layer Power are set between the internal signal layers Innerk and Innerk+1 to complete the power copper cladding design.

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