Display device and test circuit board

Abstract

A display device and a test circuit board are provided. The display device includes: a substrate including a display area in which a plurality of display elements are disposed; and a display circuit board disposed outside the display area. The display circuit board includes: first and second pads disposed in the display circuit board and connected to the substrate; and an insulating layer disposed between the first pad and the second pad, and the first pad overlaps the second pad and at least a portion of the second pad has a thickness different from a thickness of the first pad.

Description

[0001] This application claims the priority of, and all benefits derived from, Korean Patent Application No. 10-2023-0182947, filed on December 15, 2023, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments relate to a display device and a test circuit board. More specifically, embodiments relate to a display device including a display circuit board and a test circuit board for testing the display circuit board in the display device. Background Art

[0003] A display device may provide visual information such as an image or a video to a user. The display device may include a substrate divided into a display area and a peripheral area. In the display area, scan lines and data lines are insulated from each other, and a plurality of pixels may be provided. In addition, in the display area, a thin film transistor and a pixel electrode electrically connected to the thin film transistor may be provided for each pixel. Further, a counter electrode may be provided commonly for the plurality of pixels in the display area. A scan driver, a data driver, a controller, a pad unit, and various wires for transmitting an electrical signal to the display area may be provided in the peripheral area.

[0004] The display device may include a printed circuit board (“PCB”) for transmitting an electrical signal. Various types of electronic components may be provided (e.g., mounted) on the PCB. In addition, the PCB may include pads that contact and electrically connect to other components. Summary of the Invention

[0005] A printed circuit board (“PCB”) may be connected to a test circuit board, and an electrical signal may be applied to the PCB to test the performance of the PCB and detect errors. The pads of the PCB and the pads of the test circuit board need to be aligned to contact each other correctly. The separation distance that allows normal execution of the test even though there is a partial error in the alignment of the pads of the PCB and the pads of the test circuit board is also referred to as the contact margin. When the contact margin is not sufficiently ensured, even a small error in the alignment may cause an error detection such as a detection failure or an inspection defect during the test process.

[0006] Additional features will be partly set forth in the description which follows and partly will be obvious from the description, or may be learned by practice of the embodiments presented herein.

[0007] In an embodiment of the present disclosure, a display device includes: a substrate including a display area where a plurality of display elements are provided; and a display circuit board provided outside the display area, wherein the display circuit board includes: a first pad and a second pad provided in the display circuit board and connected to the substrate; and an insulating layer provided between the first pad and the second pad, and the first pad and the second pad overlap and at least a part of the thickness of the second pad is different from the thickness of the first pad.

[0008] In an embodiment, the second pad may include a first part overlapping the first pad and a second part not overlapping the first pad, wherein the thickness of the first part may be less than the thickness of the second part.

[0009] In an embodiment, the insulating layer may include a first part provided between the first pad and the first part of the second pad and a second part provided between the first pad and the second part of the second pad.

[0010] In an embodiment, the thickness of the first part of the insulating layer may be equal to or greater than at least one of the thickness of the first pad and the thickness of the first part of the second pad.

[0011] In an embodiment, the top surface of the first pad, the top surface of the second pad, and the top surface of the insulating layer may be provided in the same plane.

[0012] In an embodiment, the insulating layer may contact at least one of the first pad and the second pad on two surfaces of at least one of the first pad and the second pad, and the two surfaces may extend in directions different from each other.

[0013] In an embodiment, the insulating layer may contact the side surface and the bottom surface of the first pad facing the second pad, and may contact the side surface and the top surface of the second pad facing the first pad.

[0014] In an embodiment, the two surfaces extending in the different directions may share the same edge.

[0015] In an embodiment, the first pad may be provided as a plurality of first pads spaced apart from each other in a first direction, the second pad may be provided as a plurality of second pads spaced apart from each other in the first direction, and in a plan view, the distance in the first direction between adjacent first pads among the plurality of first pads may be equal to or greater than the width in the first direction of one of the plurality of first pads.

[0016] In an embodiment, in a plan view, the first pad and the second pad may be spaced apart from each other by an insulating layer in a second direction, and in the plan view, the length of the insulating layer in the second direction may be equal to or greater than the length of at least one of the first pad and the second pad in the second direction.

[0017] In an embodiment of the present disclosure, a test circuit board for testing a display circuit board disposed outside the display device includes: a first test pad; a second test pad spaced apart from the first test pad; and an insulating layer disposed between the first test pad and the second test pad, wherein the first test pad and the second test pad overlap, and the thickness of at least a part of the second test pad is different from the thickness of the first test pad.

[0018] In an embodiment, the second test pad may include a first portion overlapping the first test pad and a second portion not overlapping the first test pad, wherein the thickness of the first portion may be less than the thickness of the second portion.

[0019] In an embodiment, the insulating layer may include a first portion disposed between the first test pad and the first portion of the second test pad and a second portion disposed between the first test pad and the second portion of the second test pad.

[0020] In an embodiment, the thickness of the first portion of the insulating layer may be equal to or greater than at least one of the thickness of the first test pad and the thickness of the first portion of the second test pad.

[0021] In an embodiment, the top surface of the first test pad, the top surface of the second test pad, and the top surface of the insulating layer may be disposed in the same plane.

[0022] In an embodiment, the insulating layer may contact at least one of the first test pad and the second test pad on two surfaces of at least one of the first test pad and the second test pad, and the two surfaces may extend in directions different from each other.

[0023] In an embodiment, the insulating layer may contact the side surface and the bottom surface of the first test pad facing the second test pad, and may contact the side surface and the top surface of the second test pad facing the first test pad.

[0024] In an embodiment, the two surfaces extending in directions different from each other may share the same edge.

[0025] In an embodiment, the first test pads may be provided as a plurality of first test pads spaced apart from each other in a first direction, the second test pads may be provided as a plurality of second test pads spaced apart from each other in the first direction, and in a plan view, a distance in the first direction between adjacent first test pads among the plurality of first test pads may be equal to or greater than a length in the first direction of one of the plurality of first test pads.

[0026] In an embodiment, in a plan view, the first test pads and the second test pads may be spaced apart from each other by an insulating layer therebetween in a second direction, and in the plan view, a length in the second direction of the insulating layer may be equal to or greater than a length in the second direction of at least one of the first test pads and the second test pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features and advantages of the illustrative embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1A is a plan view of an embodiment of a display device;

[0029] Figure 1B is including Figure 1A a side view of an embodiment of a display device including the components shown in;

[0030] Figure 2A is a plan view of an embodiment of a display device;

[0031] Figure 2B is including Figure 2A a side view of an embodiment of a display device including the components shown in;

[0032] Figure 3 is a cross-sectional view of an embodiment of a part of a display area of a display device;

[0033] Figure 4A is a plan view of an embodiment of a part of a display circuit board;

[0034] Figure 4B is a plan view of an embodiment of a part of a display circuit board;

[0035] Figure 5 is an enlarged plan view of an embodiment of a part of a display circuit board;

[0036] Figure 6A is a cross-sectional view of an embodiment of a pad unit;

[0037] Figure 6B is a cross-sectional view of an embodiment of a pad unit;

[0038] Figure 7 Perspective view of an embodiment that is part of a circuit board testing apparatus;

[0039] Figure 8A and Figure 8B Perspective view of an embodiment showing the stages of a method for testing a display circuit board;

[0040] Figure 9 Plan view of an embodiment of the alignment state of a pad unit and a test pad unit;

[0041] Figure 10 Plan view of an embodiment of the alignment state of a pad unit and a test pad unit; and

[0042] Figure 11 Plan view of an embodiment of the alignment state of a pad unit and a test pad unit. Detailed Description of the Invention

[0043] The present disclosure can have various modifications and various embodiments, and illustrative embodiments are shown in the drawings and described in detail in the detailed description. Referring to the embodiments described in detail with reference to the accompanying drawings, the effects and features of the present disclosure and the methods for realizing them will become apparent. However, the present disclosure is not limited to the embodiments described below and can be implemented in various forms.

[0044] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings, and in the following description with reference to the drawings, the same reference numerals refer to the same elements and their redundant descriptions will be omitted.

[0045] In the following embodiments, the terms "first" and "second" are not used in a limiting sense and are used to distinguish one component from another.

[0046] In the following embodiments, expressions used in the singular include plural expressions unless they have a clearly different meaning in the context.

[0047] In the following embodiments, it will be further understood that the terms "comprising" and / or "including" as used herein indicate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0048] It will be understood that when a layer, region, or element is referred to as being "formed on" another layer, region, or element, the layer, region, or element can be formed directly or indirectly on the other layer, region, or element. That is, for example, there can be intervening layers, regions, or elements.

[0049] In the drawings, for ease of description, the dimensions of components may be exaggerated or reduced. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the present disclosure is not necessarily limited thereto.

[0050] When exemplary embodiments can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

[0051] In the specification, "A and / or B" means only A, only B, or both A and B. In addition, "at least one of A and B" means only A, only B, or both A and B.

[0052] When a layer, region, or component, etc. is connected to another layer, region, or component, etc., the layer, region, or component, etc. may be directly connected to the other layer, region, or component, etc., or may be indirectly connected to the other layer, region, or component, etc., where an intermediate layer, region, or component is located between the layer, region, or component and the other layer, region, or component.

[0053] The ±x direction, ±y direction, and ±z direction are not limited to the directions corresponding to the three axes on an orthogonal coordinate system, but may be interpreted in a broad sense (including the directions corresponding to the three axes). For example, the ±x direction, ±y direction, and ±z direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0054] Figure 1A is a plan view of an embodiment of the display device 1. Figure 1B is included Figure 1A is a side view of an embodiment of the display device 1 including the components shown in

[0055] In Figure 1B the substrate 100 is a flexible substrate, and thus, the display panel 10 is bent in the bending region BA. For convenience, Figure 1A the display panel 10 in an unbent state is shown.

[0056] Refer to Figure 1A and Figure 1B, the display device 1 in the embodiment is a device for displaying moving images or still images, and can be used not only as a display screen of portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), mobile communication terminals, electronic notebooks, e-books, portable multimedia players ("PMPs"), navigation devices, and ultra-mobile PCs ("UMPCs"), but also as a display screen of various products such as televisions, laptop computers, monitors, billboards, and Internet of Things ("IoT") devices. In addition, the display device 1 can be used in wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays ("HMDs"). Further, the display device 1 can be used as a vehicle dashboard, a center information display ("CID") provided on the center dashboard or instrument panel of the vehicle, an in-vehicle mirror display replacing the side view mirror of the vehicle, or a display provided on the rear surface of the front seat as an entertainment facility for the rear seat of the vehicle.

[0057] For ease of description, the display device 1 is used as a smart phone in Figure 1A and Figure 1B . The display device 1 includes a cover window CW, a display panel 10, a display driver 11, a display circuit board 12, and a sensor driver 13. Obviously, the display device 1 may further include a bracket, a main circuit board, a battery, and a lower cover (not shown).

[0058] Hereinafter, the term "upper" indicates the direction in which the cover window CW is disposed with respect to the display panel 10 (i.e., the +z direction), and the term "lower" indicates the direction opposite to the cover window CW with respect to the display panel 10 (i.e., the -z direction). In the drawings, the x direction, y direction, and z direction indicated by the arrows may be the +x direction, +y direction, and +z direction, respectively, and the opposite directions may be the -x direction, -y direction, and -z direction, respectively.

[0059] When viewed in a direction perpendicular to the surface of the display device 1, the display device 1 may have an approximately quadrilateral shape (e.g., a rectangular shape as shown in Figure 1A ). In the embodiment, as shown in Figure 1A , the display device 1 may have a rectangular shape (e.g., generally a rectangular planar shape having short sides extending in the ±x direction and long sides extending in the ±y direction). The corners where the short sides in the ±x direction and the long sides in the ±y direction intersect may have a right angle shape, or may have an arc shape with a predetermined curvature. Obviously, the planar shape of the display device 1 is not limited to a rectangular shape, and may be other polygonal shapes, circular shapes, or elliptical shapes.

[0060] As shown in Figure 1BAs shown in the figure, the cover window CW can be disposed on the display panel 10 to cover the top surface of the display panel 10. The cover window CW can perform the function of protecting the top surface of the display panel 10.

[0061] The display panel 10 can be disposed below the cover window CW. The display panel 10 can overlap with the transmissive portion of the cover window CW. The display panel 10 can include a substrate 100 and display elements disposed on the substrate 100.

[0062] The display panel 10 displays (outputs) the information processed by the display device 1. In an embodiment, for example, the display panel 10 can display the running screen information of an application driven by the display device 1 or user interface (“UI”) or graphical user interface (“GUI”) information according to the running screen information. The display panel 10 can include a display layer for displaying an image and a touch layer for detecting a touch input of a user. Accordingly, the display panel 10 can be used as one of the input devices providing an input interface between the display device 1 and the user, and at the same time used as one of the output units providing an output interface between the display device 1 and the user.

[0063] The substrate 100 included in the display panel 10 can include an insulating material such as glass, quartz, or polymer resin. The substrate 100 can be a rigid substrate or a flexible substrate that can be bent, folded, or curled. In Figure 1B the figure, the substrate 100 is a flexible substrate, and thus, the display panel 10 is bent in the bending region BA.

[0064] The substrate 100 includes a display area DA and a peripheral area PA outside the display area DA, and display elements can be disposed in the display area DA of the substrate 100. The peripheral area PA of the substrate 100 can be an area where no image is displayed. The peripheral area PA can surround the display area DA. The peripheral area PA can be an area from the edge of the display area DA to the edge of the display panel 10. Not only pixels can be disposed in the display area DA, but also scan lines, data lines, and power lines connected to the pixels can be disposed in the display area DA. The scan driver for applying a scan signal to the scan line and the fan-out line for connecting the data line to the display driver 11 can be located in the peripheral area PA.

[0065] The display elements can include, for example, light-emitting elements. In an embodiment, for example, the display panel 10 can be an organic light-emitting display panel using an organic light-emitting diode (“LED”) including an organic emission layer, a micro-LED display panel using micro-LEDs, a quantum dot light-emitting display panel using a quantum dot LED including a quantum dot emission layer, or an inorganic light-emitting display panel using an inorganic LED including an inorganic semiconductor.

[0066] As Figure 1BAs shown, the display panel 10 may include a bending region BA on one side in the -y direction, and the display panel 10 may be bent in the bending region BA. In other words, for convenience, Figure 1A The display panel 10 in the unbent state is shown. When the display panel 10 is bent in this way, the display driver 11, the display circuit board 12, and the sensor driver 13 are disposed below the display panel 10 in the -z direction.

[0067] The display driver 11 may receive a control signal and a power voltage, and may generate and output signals and voltages for driving the display panel 10. The display driver 11 may include an integrated circuit (“IC”).

[0068] The display circuit board 12 may be electrically connected to the display panel 10. In addition, the display circuit board 12 may be electrically connected to a main circuit board (not shown). For example, the main circuit board may include a main processor including an IC, a camera device, a wireless communicator, an input unit, an output unit, an interface unit, a memory, and / or a power supply. To connect to the display panel 10 and / or the main circuit board, as Figure 1A and Figure 1B shown, the display circuit board 12 may overlap with the substrate 100. Here, the substrate 100 and the display circuit board 12 may each include a plurality of pads protruding toward each other. The pads of the substrate 100 and the pads of the display circuit board 12 are in contact with each other to electrically connect the display circuit board 12 to the substrate 100 and additionally to the display panel 10 and the main circuit board.

[0069] The display circuit board 12 may be a bendable flexible printed circuit board (“FPCB”) or a rigid printed circuit board (“PCB”) that is rigid and not easily bendable, and in some cases, the display circuit board 12 may be a composite PCB including both a rigid PCB and an FPCB.

[0070] The sensor driver 13 may be disposed on the display circuit board 12. The sensor driver 13 may include an IC. The sensor driver 13 may be attached to the display circuit board 12. The sensor driver 13 may be electrically connected to the touch electrodes of the display panel 10 through the display circuit board 12.

[0071] In addition, a power supply for supplying driving voltages for driving the pixels, the scan driver, and the display driver 11 of the display panel 10 may be additionally disposed on the display circuit board 12.

[0072] Although not shown in Figure 1B a panel lower cover may be disposed below the display panel 10. The panel lower cover may include at least one of a light absorption member for absorbing light incident from the outside, a buffer member for absorbing external shocks, and a heat dissipation member for effectively dissipating heat of the display panel 10.

[0073] Figure 2A is a plan view of an embodiment of the display device 1. Figure 2B includes Figure 2A is a side view of an embodiment of the display device 1 including the components shown in.

[0074] In Figure 2B the circuit film 14 is a flexible film, and thus, the circuit film 14 is bent in the bending region BA. For convenience, Figure 2A the circuit film 14 in the unbent state is shown.

[0075] Referring to Figure 2A and Figure 2B , the substrate 100 may not be bent. Instead, while overlapping the substrate 100, the circuit film 14 electrically connected to the substrate 100 may be bent. Although not shown in Figure 2B , pads protruding from the substrate 100 and the circuit film 14 to contact each other may be provided between the substrate 100 and the circuit film 14.

[0076] The circuit film 14 may be bent in the bending region BA such that a part of the circuit film 14 is disposed under the substrate 100. The circuit film 14 may include a flexible material. In an embodiment, the circuit film 14 may include polyimide (“PI”). The circuit film 14 may include a circuit formed on its surface. The display driver 11 may be provided on the circuit film 14. The display driver 11 may be electrically connected to the display panel 10 through the circuit formed on the circuit film 14.

[0077] The display circuit board 12 may be provided under the circuit film 14 and may overlap the circuit film 14. Here, the circuit film 14 and the display circuit board 12 may each include a plurality of pads protruding toward each other. The pads of the circuit film 14 and the pads of the display circuit board 12 contact each other to electrically connect the display circuit board 12 to the circuit film 14 and further electrically connect the display circuit board 12 to the substrate 100, the main circuit board, and the display panel 10.

[0078] Figure 3 is a cross-sectional view of an embodiment of a part of the display area DA of the display device 1. Figure 3 may be a cross-sectional view of the display device 1 taken along the line III-III' of Figure 1A .

[0079] Referring to Figure 3 , the organic light-emitting diode OLED may be provided on the substrate 100 as a display element. The organic light-emitting diode OLED may be electrically connected to the thin-film transistor TFT.

[0080] The barrier layer 101 and the buffer layer 103 may be disposed on the substrate 100. The barrier layer 101 and the buffer layer 103 may planarize the top surface of the substrate 100 while protecting the top surface of the substrate 100. The barrier layer 101 and the buffer layer 103 may include inorganic insulating materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), and / or silicon oxynitride (SiO x N y ), and may have a single-layer or multi-layer structure including the above materials.

[0081] The thin film transistor TFT may be disposed on the buffer layer 103. The thin film transistor TFT may include an active layer A, a gate electrode G, a source electrode S, and a drain electrode D. The thin film transistor TFT may be connected to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

[0082] The active layer A may be disposed on the buffer layer 103, and may include a drain region overlapping with the drain electrode D, a source region overlapping with the source electrode S, and a channel region provided between the drain region and the source region. The active layer A may include a semiconductor pattern, and the drain region and the source region of the active layer A may be regions doped with impurities.

[0083] The gate insulating layer 105 may be disposed on the active layer A. The gate insulating layer 105 may include an inorganic material containing an oxide or a nitride. In an embodiment, for example, the gate insulating layer 105 may include SiO x , SiN x , SiO x N y , aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO x , which may be ZnO and / or ZnO2), and may have a single-layer or multi-layer structure including the above materials.

[0084] The gate electrode G may be disposed on the gate insulating layer 105. The gate electrode G may at least partially overlap with the active layer A. In an embodiment, the gate electrode G may overlap with the channel region of the active layer A. For example, the gate electrode G may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer or multi-layer structure including the above materials.

[0085] The interlayer insulating layer 107 may be configured to cover the gate electrode G. The interlayer insulating layer 107 may include an inorganic material containing an oxide or a nitride. In an embodiment, for example, the interlayer insulating layer 107 may include SiO x , SiN x , SiO x N y , Al2O3, TiO2, Ta2O5, HfO2, and / or ZnO x , and may have a single-layer or multi-layer structure including the above materials.

[0086] Contact holes overlapping with the source region and the drain region of the active layer A may be defined in the gate insulating layer 105 and the interlayer insulating layer 107. The source electrode S and the drain electrode D may be disposed on the interlayer insulating layer 107. The source electrode S may be disposed to overlap with the source region of the active layer A, and the drain electrode D may be disposed to overlap with the drain region of the active layer A. The source electrode S and the drain electrode D may be connected to the active layer A through the contact holes formed in the gate insulating layer 105 and the interlayer insulating layer 107, respectively.

[0087] The organic insulating layer 109 may be disposed on the interlayer insulating layer 107. In an embodiment, for example, the first organic insulating layer 1109 and the second organic insulating layer 2109 may be sequentially disposed on the interlayer insulating layer 107. The first organic insulating layer 1109 and the second organic insulating layer 2109 may each define an opening overlapping with the drain electrode D. The connection metal CM may be disposed on the first organic insulating layer 1109. The connection metal CM may be disposed on the first organic insulating layer 1109 and connected to the drain electrode D through the opening of the first organic insulating layer 1109. The second organic insulating layer 2109 may be disposed on the first organic insulating layer 1109, and may include an opening overlapping with the connection metal CM.

[0088] The connection metal CM may include Al, Cu, and / or Ti, and may have a single-layer or multi-layer structure including the above materials.

[0089] The first organic insulating layer 1109 and the second organic insulating layer 2109 may include common polymers such as benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, or vinyl alcohol polymers, and may have a single-layer or multi-layer structure including the above materials.

[0090] In Figure 3 , two organic insulating layers and one connection metal are shown, but the present disclosure is not limited thereto. In an embodiment, the display panel may include three or more organic insulating layers and a plurality of connection metals.

[0091] The organic light-emitting diode OLED can be disposed on the organic insulating layer 109 and can include a pixel electrode 1113, an intermediate layer 2113, and a counter electrode 3113.

[0092] The pixel electrode 1113 can be disposed on the second organic insulating layer 2109. The pixel electrode 1113 can be connected to the connection metal CM through an opening in the second organic insulating layer 2109. Accordingly, the pixel electrode 1113 can be electrically connected to the thin-film transistor TFT through the connection metal CM and the drain electrode D and can receive a voltage.

[0093] The pixel electrode 1113 can include a conductive oxide such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). The pixel electrode 1113 can include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any combination thereof. Obviously, the configuration and material of the pixel electrode 1113 are not limited thereto and can be changed.

[0094] The bank layer 111 can be disposed on the organic insulating layer 109 (e.g., the second organic insulating layer 2109). The bank layer 111 can cover the edge (or edge region) of the pixel electrode 1113. In other words, an opening exposing the center of the pixel electrode 1113 can be defined in the bank layer 111. The size and shape of the emission region of the organic light-emitting diode OLED can be determined by the opening in the bank layer 111.

[0095] The intermediate layer 2113 can be disposed on the pixel electrode 1113. The intermediate layer 2113 can include an organic emission layer containing a low-molecular-weight or high-molecular-weight material. In an embodiment, the intermediate layer 2113 can include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”). In an embodiment, the intermediate layer 2113 can include a hole transport layer (“HTL”) and / or a hole injection layer (“HIL”). In an embodiment, the intermediate layer 2113 can include a plurality of ETLs and / or a plurality of EILs and / or a plurality of HTLs and / or a plurality of HILs.

[0096] The counter electrode 3113 may be disposed on the intermediate layer 2113. The counter electrode 3113 may be arranged to cover the entire intermediate layer 2113. The counter electrode 3113 may include a conductive material having a relatively low work function. In an embodiment, for example, the counter electrode 3113 may include a (semi) transparent layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or any alloy thereof. In an alternative embodiment, the counter electrode 3113 may further include a layer including ITO, IZO, ZnO, or In2O3 on the (semi) transparent layer containing the above materials.

[0097] In an embodiment, a cover layer (not shown) may be disposed on the counter electrode 3113 to cover the entire counter electrode 3113.

[0098] The thin film encapsulation layer TFE may be disposed on the counter electrode 3113. The thin film encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. In an embodiment, the thin film encapsulation layer TFE may include a first inorganic encapsulation layer 115 and a second inorganic encapsulation layer 119, and an organic encapsulation layer 117 located between the first inorganic encapsulation layer 115 and the second inorganic encapsulation layer 119. The first inorganic encapsulation layer 115 and the second inorganic encapsulation layer 119 may include one or more inorganic insulating materials such as SiO2, SiN x , SiO x N y , Al2O3, TiO2, Ta2O5, HfO2, and / or ZnO x . The organic encapsulation layer 117 may include a polymeric material. In an embodiment, the polymeric material may include a silicone resin, an acrylic resin, an epoxy resin, a polyimide resin, and a polyethylene resin.

[0099] Figure 4A is a plan view of an embodiment showing a part of the display circuit board 12.

[0100] Reference Figure 4A , the display circuit board 12 may include a plurality of pad units 122 arranged in a region. In an embodiment, the region where the pad units 122 are arranged may be Figure 1A the region where the display circuit board 12 and the substrate 100 overlap each other or Figure 2A the region where the display circuit board 12 and the circuit film 14 overlap each other.

[0101] The display circuit board 12 may include a display circuit board substrate 120. The display circuit board substrate 120 may be a flexible substrate or a rigid substrate. A plurality of pad units 122 may be arranged on the display circuit board substrate 120. In an embodiment, for example, the plurality of pad units 122 may be arranged on the top surface (the surface in the +z direction) of the display circuit board substrate 120. In an embodiment, the plurality of pad units 122 may be arranged in rows extending in one direction (e.g., the x direction). In an embodiment, the plurality of pad units 122 may include a plurality of pad rows 121 extending in the x direction as shown in Figure 4A . In an embodiment, for example, the plurality of pad units 122 may be arranged in a first pad row 121-1 extending in the x direction and a second pad row 121-2 extending in the x direction and arranged in the -y direction of the first pad row 121-1. Obviously, the present disclosure is not limited to two pad rows 121, and there may be three or more pad rows 121.

[0102] In an embodiment, the pad units 122 arranged in the first pad row 121-1 and the pad units 122 arranged in the second pad row 121-2 may not overlap each other. In an embodiment, for example, the pad units 122 arranged in the first pad row 121-1 and the pad units 122 arranged in the second pad row 121-2 may be arranged alternately. In other words, a virtual straight line parallel to the y direction may not simultaneously pass through the pad units 122 included in the first pad row 121-1 and the pad units 122 included in the second pad row 121-2.

[0103] In an embodiment, among the plurality of pad units 122, a predetermined number of pad units 122 may be grouped together, there may be multiple groups, and the distance between the pad units 122 may be less than the distance between the groups. In Figure 4A , one group of pad units 122 includes five pad units 122 in the first pad row 121-1 and four pad units 122 in the second pad row 121-2, but the present disclosure is not necessarily limited to such a number.

[0104] Each of the pad units 122 may include a first pad 123, a second pad 125, and an insulating layer 124 between the first pad 123 and the second pad 125. In an embodiment, the second pad 125 may be disposed in the -y direction of the first pad 123. In an embodiment, the second pad 125 may be disposed in the +y direction of the first pad 123. In an embodiment, the first pad 123, the insulating layer 124, and the second pad 125 may be sequentially arranged in the +y direction or the -y direction, and the pad unit 122 may extend in the y direction. In an embodiment, the first pad 123 and the second pad 125 may be pads that contact Figure 1B the substrate 100 orFigure 2B The portion of the pad of the circuit film 14. In an embodiment, the insulating layer 124 may separate the first pad 123 and the second pad 125 such that the first pad 123 and the second pad 125 are not electrically connected to each other.

[0105] Figure 4B It is a plan view of an embodiment showing a part of the display circuit board 12.

[0106] Reference Figure 4B , the pad row 121 may not include a group of pad units 122. In an embodiment, the first pad row 121-1 may include a plurality of pad units 122 arranged at regular intervals. In an embodiment, the second pad row 121-2 may include a plurality of pad units 122 arranged at regular intervals. In an embodiment, the pad units 122 arranged in the first pad row 121-1 and the pad units 122 arranged in the second pad row 121-2 may be alternately arranged. In other words, a virtual straight line parallel to the y direction may not pass through the pad units 122 included in the first pad row 121-1 and the pad units 122 included in the second pad row 121-2 at the same time.

[0107] Figure 5 It is an enlarged plan view of an embodiment showing a part of the display circuit board 12. Figure 5 Is Figure 4A An enlarged plan view of region V of

[0108] Reference Figure 5 , a plurality of pad units 122 may be arranged on the display circuit board substrate 120, in the first pad row 121-1 and the second pad row 121-2. The pad units 122 of the first pad row 121-1 and the pad units 122 of the second pad row 121-2 may be alternately arranged.

[0109] The pad unit 122 may include a first pad 123, an insulating layer 124, and a second pad 125. In an embodiment, the first pad 123, the insulating layer 124, and the second pad 125 may be arranged in the -y direction in the described order, or the second pad 125, the insulating layer 124, and the first pad 123 may be arranged in the -y direction in the described order. Hereinafter, for the sake of convenience of description, the case where the first pad 123, the insulating layer 124, and the second pad 125 are arranged in the -y direction in the described order will be described.

[0110] The width (or the length in the x-direction) of the first pad 123 may be defined as a first width X1. The length (or the length in the y-direction) of the first pad 123 may be defined as a first length Y1. The width (or the length in the x-direction) of the second pad 125 may be defined as a second width X2. The length (or the length in the y-direction) of the second pad 125 may be defined as a second length Y2. The length (or the length in the y-direction) of the insulating layer 124 may be defined as a third length Y3.

[0111] The features described below may equally apply to other pad units 122 arranged in the first pad row 121-1 and the second pad row 121-2.

[0112] In an embodiment, the first width X1 and the second width X2 may be the same. In an embodiment, the length of the insulating layer 124 in the x-direction may be the same as the first width X1 and / or the second width X2. In an embodiment, the first length Y1 and the second length Y2 may be the same. In an embodiment, the third length Y3 may be the same as the first length Y1 and / or the second length Y2, or may be greater than the first length Y1 and / or the second length Y2. In an embodiment, the first width X1 may be the same as the first length Y1. In an embodiment, the second width X2 may be the same as the second length Y2. In an embodiment, the length of the insulating layer 124 in the x-direction may be the same as the third length Y3. In an embodiment, the first pad 123, the insulating layer 124, and the second pad 125 may each have an approximate square shape in which the length in the x-direction and the length in the y-direction are the same, and the pad unit 122 may have an approximate quadrilateral shape (e.g., a rectangular shape in which the length in the y-direction is approximately three times the length in the x-direction).

[0113] The spacing between adjacent pad units 122 may be defined as a first spacing S1. In an embodiment, the spacing between adjacent pad units 122 may be the same. In other words, the first spacing S1 may be uniform. In an embodiment, the first spacing S1 may be the same as the first width X1, or may be greater than the first width X1. In an embodiment, the first spacing S1 may be the same as the second width X2, or may be greater than the second width X2. Accordingly, when viewed in the y-direction, the pad units 122 arranged in the first pad row 121-1 and the pad units 122 arranged in the second pad row 121-2 may not overlap each other.

[0114] Figure 6A is a cross-sectional view of an embodiment of the pad unit 122. Figure 6A may be a cross-sectional view of an embodiment of the pad unit 122 taken along Figure 4A the line VI-VI'.

[0115] Refer toFigure 6A , the first pad 123 and the second pad 125 can be arranged such that the top surface of the first pad 123 is set farther in the +y direction than the top surface of the second pad 125.

[0116] The first pad 123 can be disposed on the second pad 125. The insulating layer 124 can be disposed between the first pad 123 and the second pad 125. In an embodiment, the first pad 123 can have a shape extending in the y direction.

[0117] In an embodiment, the second pad 125 can have a shape that extends in the -z direction and then is bent to extend in the y direction. In an alternative embodiment, it can be described that the second pad 125 can have a shape that extends in the -y direction and then is bent to extend in the z direction. In an embodiment, a portion of the second pad 125 can overlap with the first pad 123. In an embodiment, for example, the first portion 125-1 of the second pad 125 that extends in the y direction can overlap with the first pad 123. In an embodiment, the length of the first portion 125-1 of the second pad 125 in the y direction can be greater than the length of the first pad 123 in the y direction. In other words, a portion of the first portion 125-1 of the second pad 125 can overlap with the first pad 123. In an embodiment, the second pad 125 can include a second portion 125-2 that does not overlap with the first pad 123. The second portion 125-2 of the second pad 125 can be a portion that extends in the z direction.

[0118] In an embodiment, the insulating layer 124 can have a shape that extends in the -z direction and then is bent to extend in the y direction. In an alternative embodiment, it can be described that the insulating layer 124 can have a shape that extends in the -y direction and then is bent to extend in the z direction. In an embodiment, a portion of the insulating layer 124 can overlap with the first pad 123. In an embodiment, the first portion 124-1 of the insulating layer 124 that extends in the y direction can overlap with the first pad 123. In an embodiment, for example, the length of the first portion 124-1 of the insulating layer 124 in the y direction can be the same as the length of the first pad 123 in the y direction. In other words, the first portion 124-1 of the insulating layer 124 can completely overlap with the first pad 123. In an embodiment, the insulating layer 124 can include a second portion 124-2 that does not overlap with the first pad 123. The second portion 124-2 of the insulating layer 124 can be a portion that extends in the z direction. In an embodiment, the first portion 124-1 of the insulating layer 124 can be disposed between the first pad 123 and the first portion 125-1 of the second pad 125. In an embodiment, the second portion 124-2 of the insulating layer 124 can be disposed between the first pad 123 and the second portion 125-2 of the second pad 125.

[0119] Accordingly, based on the first pad 123, the insulating layer 124 can be entirely disposed in the -y direction and the -z direction. Based on the insulating layer 124, the second pad 125 can be entirely disposed in the -y direction and the -z direction.

[0120] In an embodiment, the top surface of the pad unit 122 may include the top surface of the first pad 123, the top surface of the insulating layer 124, and the top surface of the second pad 125. In an embodiment, for example, the top surface of the pad unit 122 may include the top surface of the first pad 123, the top surface of the second portion 124-2 of the insulating layer 124, and the top surface of the second portion 125-2 of the second pad 125. In an embodiment, the top surface of the pad unit 122 may be disposed in a plane. In an embodiment, for example, the top surface of the first pad 123, the top surface of the second portion 124-2 of the insulating layer 124, and the top surface of the second portion 125-2 of the second pad 125 may be disposed in the same plane.

[0121] In an embodiment, the insulating layer 124 may contact both surfaces of the first pad 123. In an embodiment, the insulating layer 124 may contact the side surface (or the surface in the -y direction) and the bottom surface (or the surface in the -z direction) of the first pad 123. In an embodiment, the side surface of the second portion 124-2 of the insulating layer 124 facing the +y direction and the side surface of the first pad 123 facing the -y direction may be in contact with each other. In an embodiment, the top surface of the first portion 124-1 of the insulating layer 124 facing the +z direction and the bottom surface of the first pad 123 facing the -z direction may be in contact with each other. Accordingly, a part of each of the side surface and the top surface of the insulating layer 124 may be covered by the first pad 123. In an embodiment, it may be described that the surfaces of the insulating layer 124 covered by the first pad 123 share the same edge.

[0122] In an embodiment, the insulating layer 124 may contact two surfaces of the second pad 125. In an embodiment, the insulating layer 124 may contact a side surface (or a surface in the +y direction) and a top surface (or a surface in the +z direction) of the second pad 125. In an embodiment, a side surface of the second part 124-2 of the insulating layer 124 facing the -y direction and a side surface of the second part 125-2 of the second pad 125 facing the +y direction may contact each other. In an embodiment, a bottom surface of the insulating layer 124 facing the -z direction and a top surface of the first part 125-1 of the second pad 125 facing the +z direction may contact each other. Accordingly, a part of each of the side surface and the top surface of the second pad 125 may be covered by the insulating layer 124. In an embodiment, it may be described that surfaces of the second pad 125 covered by the insulating layer 124 share the same edge. According to the above structure, the first pad 123 and the second pad 125 may be insulated from each other.

[0123] In the above, lengths of the first pad 123, the second pad 125, and the insulating layer 124 in the y direction have been respectively defined as a first length Y1, a second length Y2, and a third length Y3. Here, the third length Y3 of the insulating layer 124 may be substantially the length of the second part 124-2 of the insulating layer 124 in the y direction. Additionally, the second length Y2 of the second pad 125 may be substantially the length of the second part 125-2 of the second pad 125 in the y direction.

[0124] In an embodiment, the length of the first part 124-1 of the insulating layer 124 in the y direction may be the same as the first length Y1. Accordingly, the entire length of the insulating layer 124 may be the same as the sum of the first length Y1 and the third length Y3. In an embodiment, the length of the first part 125-1 of the second pad 125 in the y direction may be the same as the sum of the first length Y1 and the third length Y3. Accordingly, the entire length of the second pad 125 may be the same as the sum of the first length Y1, the second length Y2, and the third length Y3.

[0125] The thickness (or the length in the z direction) of the first pad 123 may be defined as a first thickness Z1. The thickness (or the length in the z direction) of the first part 125-1 of the second pad 125 may be defined as a second thickness Z2. The thickness (or the length in the z direction) of the first part 124-1 of the insulating layer 124 may be defined as a third thickness Z3.

[0126] In an embodiment, the thickness of the second portion 124-2 of the insulating layer 124 may be the same as the sum of the first thickness Z1 and the third thickness Z3. Accordingly, the thicknesses of the first portion 124-1 and the second portion 124-2 of the insulating layer 124 may be different from each other. In an embodiment, for example, the thickness of the first portion 124-1 of the insulating layer 124 may be less than the thickness of the second portion 124-2. In an embodiment, the thickness of the second portion 125-2 of the second pad 125 may be the same as the sum of the first thickness Z1, the second thickness Z2, and the third thickness Z3. Accordingly, the thicknesses of the first portion 125-1 and the second portion 125-2 of the second pad 125 may be different from each other. In an embodiment, for example, the thickness of the first portion 125-1 of the second pad 125 may be less than the thickness of the second portion 125-2.

[0127] In an embodiment, the first thickness Z1 and the second thickness Z2 may be the same. In an embodiment, the third thickness Z3 may be the same as the first thickness Z1 and / or the second thickness Z2, or may be greater than the first thickness Z1 and / or the second thickness Z2. In an embodiment, the third thickness Z3 may be the same as the sum of the first thickness Z1 and the second thickness Z2.

[0128] Figure 6B is a cross-sectional view of an embodiment of the pad unit 122. Figure 6B may be a cross-sectional view of another embodiment of the pad unit 122 taken along the Figure 4A line VI-VI'.

[0129] Referring to Figure 6B , the first pad 123 and the second pad 125 may be arranged such that the top surface of the first pad 123 is set farther in the -y direction than the top surface of the second pad 125.

[0130] Based on the first pad 123, the insulating layer 124 may be entirely disposed in the +y direction and the -z direction. Based on the insulating layer 124, the second pad 125 may be entirely disposed in the +y direction and the -z direction.

[0131] Regarding the surface of the first pad 123 covered by the insulating layer 124 and the surface of the insulating layer 124 covered by the second pad 125, Figure 6B the embodiment shown in Figure 6A may be different from the embodiment shown in

[0132] In an embodiment, the insulating layer 124 may contact the side surface (or the surface in the +y direction) and the bottom surface (or the surface in the -z direction) of the first pad 123. In an embodiment, the side surface of the second portion 124-2 of the insulating layer 124 facing the -y direction and the side surface of the first pad 123 facing the +y direction may be in contact with each other. Accordingly, the side surface of the first pad 123 facing the +y direction and the bottom surface of the first pad 123 facing the -z direction may be covered by the insulating layer 124.

[0133] In an embodiment, the insulating layer 124 may contact the side surface (or the surface in the -y direction) and the top surface (or the surface in the +z direction) of the second pad 125. In an embodiment, the side surface of the second portion 124-2 of the insulating layer 124 facing the +y direction and the side surface of the second portion 125-2 of the second pad 125 facing the -y direction may be in contact with each other. Accordingly, the side surface of the insulating layer 124 facing the +y direction and the bottom surface of the insulating layer 124 facing the -z direction may be covered by the second pad 125.

[0134] Figure 7 Perspective view of an embodiment that is part of the circuit board testing device 2.

[0135] Reference Figure 7 , the circuit board testing device 2 may include a test circuit board 22. The display circuit board 12 to be tested may be disposed (e.g., mounted) on the circuit board testing device 2.

[0136] The test circuit board 22 may be configured in a manner similar to that of the display circuit board 12. In an embodiment, the test circuit board 22 may include a test circuit board substrate 220 and a plurality of test pad units 222 disposed on the test circuit board substrate 220. The test circuit board substrate 220 may correspond to the display circuit board substrate 120 of the display circuit board 12, and the test pad units 222 may correspond to the pad units 122 of the display circuit board 12.

[0137] The display circuit board 12 and the test circuit board 22 may be arranged such that their top surfaces face each other. The top surface of the display circuit board 12 may be the surface on which the pad units 122 are disposed on the display circuit board substrate 120 (i.e., the surface in the +z direction). The top surface of the test circuit board 22 may be the surface on which the test pad units 222 are disposed on the test circuit board substrate 220 (i.e., the surface in the -z direction). Hereinafter, the top surface of the display circuit board 12 may represent the surface on which the pad units 122 are disposed, and the top surface of the test circuit board 22 may represent the surface on which the test pad units 222 are disposed.

[0138] The test pad unit 222 may be configured in a manner similar to that of the pad unit 122. In an embodiment, the test pad unit 222 may include a first test pad 223, a test insulating layer 224, and a second test pad 225. In an embodiment, the first test pad 223, the test insulating layer 224, and the second test pad 225 may respectively have the characteristics of the first pad 123, the insulating layer 124, and the second pad 125 described above. In an embodiment, the test pad unit 222 may be obtained by arranging components identical to those of the pad unit 122 on the test circuit board substrate 220.

[0139] In an embodiment, the first test pad 223 may have a third width X3. The third width X3 may have the characteristics of the first width X1. In an embodiment, the second test pad 225 may have a fourth width X4. The fourth width X4 may have the characteristics of the second width X2. In an embodiment, the interval between adjacent test pad units 222 may be defined as a second interval S2. The second interval S2 may have the characteristics of the first interval S1. In an embodiment, the first test pad 223 may have a fourth length Y4. The fourth length Y4 may have the characteristics of the first length Y1. In an embodiment, the second test pad 225 may have a fifth length Y5. The fifth length Y5 may have the characteristics of the second length Y2. In an embodiment, the test insulating layer 224 may have a sixth length Y6. The sixth length Y6 may have the characteristics of the third length Y3. Although not shown in Figure 7 , the characteristics of the thickness of the components (e.g., the first test pad 223, the test insulating layer 224, and the second test pad 225) of the test pad unit 222 may be the same as or similar to the characteristics of the thickness of the components of the pad unit 122 described above.

[0140] In an embodiment, the test circuit board 22 may be translated relative to the display circuit board 12. Accordingly, the test pad unit 222 may be translated relative to the pad unit 122.

[0141] Figure 8A and Figure 8B are perspective views showing embodiments of the stages of a method for testing the display circuit board 12.

[0142] Reference Figure 8A , the display circuit board 12 and the test circuit board 22 may be aligned with each other. In an embodiment, the test circuit board 22 may be translated relative to the display circuit board 12. In an embodiment, for example, the test circuit board 22 may be moved relative to the display circuit board 12 in the x direction and / or the y direction and / or the z direction. In an embodiment, the display circuit board 12 may be fixed and the test circuit board 22 may be moved. In an embodiment, the test circuit board 22 may be fixed and the display circuit board 12 may be moved.

[0143] The alignment of the display circuit board 12 and the test circuit board 22 can be performed by aligning the pad unit 122 and the test pad unit 222. In an embodiment, when the pad unit 122 and the test pad unit 222 are completely aligned, the pad unit 122 and the test pad unit 222 can completely overlap each other when viewed in the +z direction. Here, the first test pad 223 can overlap with the first pad 123 and can not overlap with the insulating layer 124 and / or the second pad 125. In addition, the second test pad 225 can overlap with the second pad 125 and can not overlap with the insulating layer 124 and / or the first pad 123. In addition, the test pad unit 222 can not overlap with another pad unit 122 adjacent to the overlapping pad unit 122. In other words, the test pad unit 222 can only overlap with one corresponding pad unit 122. In an embodiment, in order to align the pad unit 122 and the test pad unit 222, the test circuit board 22 can be moved in the x direction and / or the y direction relative to the display circuit board 12.

[0144] Reference Figure 8B , while aligning the display circuit board 12 and the test circuit board 22, the display circuit board 12 and the test circuit board 22 can be moved closer to each other. In other words, the test circuit board 22 can be moved closer to the display circuit board 12.

[0145] In an embodiment, as Figure 8B shown, the test circuit board 22 can be lowered to be closer to the display circuit board 12. In an embodiment, different from Figure 8B shown, the display circuit board 12 can be raised to be closer to the test circuit board 22.

[0146] In an embodiment, the display circuit board 12 and the test circuit board 22 can be moved closer to each other so that the pad unit 122 and the test pad unit 222 are closer to each other. In an embodiment, the top surface (or the surface in the +z direction) of the pad unit 122 and the top surface (or the surface in the -z direction) of the test pad unit 222 can be in contact with each other. In an embodiment, the first test pad 223 can be in contact with the first pad 123 and can not be in contact with the insulating layer 124 and / or the second pad 125. In an embodiment, the second test pad 225 can be in contact with the second pad 125 and can not be in contact with the insulating layer 124 and / or the first pad 123. In an embodiment, the test pad unit 222 can only be in contact with one pad unit 122.

[0147] The pad unit 122 and the test pad unit 222 can be electrically connected to each other. Additionally, the display circuit board 12 and the test circuit board 22 can be electrically connected to each other. Then, a voltage can be applied to the test circuit board 22 to transmit an electrical signal to the display circuit board 12 through the test pad unit 222 and the pad unit 122. Based on whether a desired response signal is obtained by transmitting the electrical signal through the display circuit board 12, it can be tested whether the printed circuit of the display circuit board 12 has been manufactured as expected. When the corresponding response signals of various electrical signals transmitted to the display circuit board 12 through the test circuit board 22 are the same as the desired corresponding response signals, the display circuit board 12 can be determined to be normal and can be transferred to the next process. When the corresponding response signals of various electrical signals transmitted to the display circuit board 12 through the test circuit board 22 are different from the desired corresponding response signals, the printed circuit of the display circuit board 12 can be determined to be defective, and the display circuit board 12 can be discarded or can be transferred to a reassembly process.

[0148] During such a test process, the degree of alignment between the pad unit 122 and the test pad unit 222 can be an important factor in testing the display circuit board 12. In Figure 8A and Figure 8B , the pad unit 122 and the test pad unit 222 are completely aligned to completely overlap each other, but this may not be the case in the actual process. In an embodiment, for example, an alignment error may occur in which the pad unit 122 and the test pad unit 222 only partially overlap each other. When the test pad unit 222 contacts multiple pad units 122 simultaneously due to the alignment error, a short circuit may occur between adjacent pad units 122. In an alternative embodiment, when the first test pad 223 contacts the first pad 123 and the second pad 125 simultaneously, a short circuit may occur between the first pad 123 and the second pad 125. In an alternative embodiment, when the second test pad 225 contacts the first pad 123 and the second pad 125 simultaneously, a short circuit may occur between the first pad 123 and the second pad 125. In this case, although the display circuit board 12 is normal, it may be determined to be untestable or may be determined to be defective. As will be described below with reference to Figures 9 to 11 such a possibility can be reduced by the features of the embodiment.

[0149] Figure 9 is a plan view of an embodiment of the alignment state between the pad unit 122 and the test pad unit 222.

[0150] Reference Figure 9, the pad unit 122 and the test pad unit 222 may partially overlap each other. In other words, a part of the test pad unit 222 may overlap with the pad unit 122, and another part of the test pad unit 222 may overlap with the space between adjacent pad units 122.

[0151] The first test pad 223 may overlap with the first pad 123 and may not overlap with the insulating layer 124 and the second pad 125. The test insulating layer 224 may overlap with the first pad 123 and the insulating layer 124 and may not overlap with the second pad 125. The second test pad 225 may overlap with the insulating layer 124 and the second pad 125 and may not overlap with the first pad 123. When the test pad unit 222 contacts the pad unit 122 while in the state as shown in Figure 9 , the first test pad 223 may be electrically connected only to the first pad 123, and the second test pad 225 may be electrically connected only to the second pad 125. In this case, no short circuit occurs, and the test process can be normally executed.

[0152] Figure 10 is a plan view of an embodiment of the alignment state of the pad unit 122 and the test pad unit 222.

[0153] Reference Figure 10 , misalignment (e.g., misalignment in the x direction) may occur between the test pad unit 222 and the pad unit 122. In an embodiment, the test pad unit 222 may not overlap with the pad unit 122. In an embodiment, for example, the test pad unit 222 may be disposed in the space between adjacent pad units 122. Accordingly, in the plan view, the test pad unit 222 and the pad unit 122 may be alternately arranged in the x direction.

[0154] Here, a first interval S1 that is the interval between adjacent pad units 122 may be the same as a third width X3 and / or a fourth width X4 that is the width of the test pad unit 222, or may be greater than the third width X3 and / or the fourth width X4 that is the width of the test pad unit 222. In an embodiment, the first interval S1 may be greater than the third width X3 that is the width of the first test pad 223. In an embodiment, the first interval S1 may be greater than the fourth width X4 that is the width of the second test pad 225. Accordingly, even when the test pad unit 222 is aligned to be completely spaced apart from one pad unit 122, the test pad unit 222 may not overlap with another pad unit 122. In other words, one test pad unit 222 may not overlap with multiple pad units 122 at the same time. Accordingly, it is possible to prevent a short circuit from occurring between adjacent pad units 122 due to one test pad unit 222 contacting multiple pad units 122 at the same time.

[0155] When aligning the test pad unit 222 and the pad unit 122 as shown in Figure 10 even when the test pad unit 222 and the pad unit 122 are brought close to each other, they may not contact each other. Accordingly, the electrical signal applied to the test pad unit 222 is not transmitted to the pad unit 122, and thus, an alignment abnormality can be identified, and the test pad unit 222 and the pad unit 122 can be realigned. As a result, due to the contact margin (e.g., the first interval S1) ensured between adjacent pad units 122, even when misalignment occurs between the test pad unit 222 and the pad unit 122 in one direction (e.g., misalignment in the x direction), it is possible to prevent the display circuit board from being determined to be defective due to a short circuit between the pad units 122.

[0156] Figure 11 is a plan view of an embodiment of the alignment state of the pad unit 122 and the test pad unit 222.

[0157] Referring to Figure 11 misalignment may occur between the test pad unit 222 and the pad unit 122 (e.g., misalignment in the y direction). In the embodiment, the test pad unit 222 may partially overlap the pad unit 122.

[0158] In the embodiment, the test pad unit 222 may be set farther in the +y direction than the pad unit 122, the test insulating layer 224 may overlap the first pad 123, and the second test pad 225 may overlap the insulating layer 124. In the embodiment, the test pad unit 222 may be set farther in the -y direction than the pad unit 122, the first test pad 223 may overlap the insulating layer 124, and the test insulating layer 224 may overlap the second pad 125.

[0159] In the embodiment, the third length Y3 of the insulating layer 124 may be the same as the first length Y1 of the first pad 123 and the second length Y2 of the second pad 125, or may be greater than the first length Y1 of the first pad 123 and the second length Y2 of the second pad 125. In the embodiment, the sixth length Y6 of the test insulating layer 224 may be the same as the fourth length Y4 of the first test pad 223 and the fifth length Y5 of the second test pad 225, or may be greater than the fourth length Y4 of the first test pad 223 and the fifth length Y5 of the second test pad 225. In the embodiment, the third length Y3 and the sixth length Y6 may be the same as each other and may be greater than the first length Y1, the second length Y2, the fourth length Y4, and the fifth length Y5. In Figure 11 the first length Y1 to the sixth length Y6 are the same.

[0160] Accordingly, even when misalignment occurs in the y-direction between the test pad unit 222 and the pad unit 122, each of the first test pad 223 and the second test pad 225 may not overlap with the first pad 123 and the second pad 125 simultaneously. In an embodiment, as Figure 11 shown, the second test pad 225 may overlap with the insulating layer 124. For example, the third length Y3 of the insulating layer 124 may be the same as the fifth length Y5 of the second test pad 225, or may be greater than the fifth length Y5 of the second test pad 225. In Figure 11 the embodiment shown, when the test pad unit 222 is moved in the +y direction, the second test pad 225 may overlap with the first pad 123, but not with the second pad 125. In Figure 11 the embodiment shown, when the test pad unit 222 is moved in the -y direction, the second test pad 225 may overlap with the second pad 125, but not with the first pad 123. Accordingly, the second test pad 225 does not overlap with the first pad 123 and the second pad 125 simultaneously. Accordingly, the second test pad 225 cannot contact the first pad 123 and the second pad 125 simultaneously, and thus, a short circuit between the first pad 123 and the second pad 125 can be prevented.

[0161] When aligning the test pad unit 222 and the pad unit 122 as Figure 11 shown, even when the test pad unit 222 and the pad unit 122 are brought closer to each other, the first pad 123 and the second pad 125, and the first test pad 223 and the second test pad 225 may not contact each other. Accordingly, the electrical signal applied to the test pad unit 222 is not transmitted to the pad unit 122, and thus, an alignment abnormality can be identified and the test pad unit 222 and the pad unit 122 can be realigned. As a result, due to the contact margin ensured between the first pad 123 and the second pad 125 by the insulating layer 124, even when misalignment occurs (e.g., misalignment in the y-direction) between the test pad unit 222 and the pad unit 122 in one direction, it is possible to prevent the display circuit board from being determined to be defective due to a short circuit between the first pad 123 and the second pad 125. Apparently, in Figure 11 the embodiment shown, when the test pad unit 222 is moved in the +y direction such that the second test pad 225 overlaps and contacts the first pad 123 and the insulating layer 124, an alignment error can be identified. In Figure 11 the embodiment shown, when the test pad unit 222 is moved in the -y direction such that the second test pad 225 overlaps and contacts the insulating layer 124 and the second pad 125, it can be achieved Figure 9The embodiments shown in [the text] can normally execute the test process.

[0162] According to the above embodiments, a display device including a display circuit board having a contact margin equal to or greater than the size of the pad and a test circuit board corresponding to the display circuit board are provided.

[0163] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned can be clearly understood by those of ordinary skill in the art according to the scope of the claims.

[0164] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of the features or advantages in each embodiment should generally be considered applicable to other similar features or advantages in other embodiments. Although the embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes can be made to them in form and detail without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A substrate including a display area where a plurality of display elements are arranged; as well as A display circuit board is arranged outside the display area, and the display circuit board comprises: A first pad and a second pad are provided in the display circuit board and connected to the substrate; and an insulating layer, disposed between the first pad and the second pad, The first pad overlaps with the second pad, and a thickness of at least a portion of the second pad is different from a thickness of the first pad.

2. The display device according to claim 1, wherein: The second pad includes a first portion overlapping the first pad and a second portion not overlapping the first pad, and Wherein, the thickness of the first portion is smaller than the thickness of the second portion.

3. The display device according to claim 2, wherein: The insulating layer includes a first portion disposed between the first pad and the first portion of the second pad and a second portion disposed between the first pad and the second portion of the second pad.

4. The display device according to claim 3, wherein: The thickness of the first portion of the insulating layer is equal to or greater than at least one of the thickness of the first pad and the thickness of the first portion of the second pad.

5. The display device according to claim 1, wherein: A top surface of the first pad, a top surface of the second pad, and a top surface of the insulating layer are disposed in the same plane.

6. The display device according to claim 1, wherein: The insulating layer contacts at least one of the first pad and the second pad on both surfaces of the at least one of the first pad and the second pad, and The two surfaces extend in directions different from each other.

7. The display device according to claim 6, wherein: The insulating layer contacts a side surface and a bottom surface of the first pad facing the second pad, and contacts a side surface and a top surface of the second pad facing the first pad.

8. The display device according to claim 6, wherein: The two surfaces extending in the directions different from each other share a same edge.

9. The display device according to any one of claims 1 to 8, wherein: The first pad is provided in plurality to include a plurality of first pads spaced apart from each other in a first direction, and the second pad is provided in plurality to include a plurality of second pads spaced apart from each other in the first direction, In a plan view, a distance between adjacent first pads among the plurality of first pads in the first direction is equal to or greater than a width of one of the plurality of first pads in the first direction.

10. The display device according to claim 1, wherein: In a plan view, the first pad and the second pad are spaced apart from each other in a second direction with an insulating layer therebetween, and In the plan view, a length of the insulating layer in the second direction is equal to or greater than a length of at least one of the first pad and the second pad in the second direction.

11. A test circuit board disposed outside a display device for testing a display circuit board, the test circuit board comprising: A first test pad; a second test pad, spaced apart from the first test pad; as well as an insulating layer, disposed between the first test pad and the second test pad, The first test pad overlaps with the second test pad, and a thickness of at least a portion of the second test pad is different from a thickness of the first test pad.

12. The test circuit board according to claim 11, wherein: The second test pad includes a first portion overlapping the first test pad and a second portion not overlapping the first test pad, and Wherein, the thickness of the first portion is smaller than the thickness of the second portion.

13. The test circuit board according to claim 12, wherein: The insulating layer includes a first portion disposed between the first test pad and the first portion of the second test pad and a second portion disposed between the first test pad and the second portion of the second test pad.

14. The test circuit board according to claim 13, wherein: A thickness of the first portion of the insulating layer is equal to or greater than at least one of a thickness of the first test pad and a thickness of the first portion of the second test pad.

15. The test circuit board according to claim 11, wherein: A top surface of the first test pad, a top surface of the second test pad, and a top surface of the insulating layer are disposed in the same plane.

16. The test circuit board according to claim 11, wherein: The insulating layer contacts at least one of the first test pad and the second test pad on both surfaces of the at least one of the first test pad and the second test pad, and The two surfaces extend in directions different from each other.

17. The test circuit board according to claim 16, wherein: The insulating layer contacts a side surface and a bottom surface of the first test pad facing the second test pad, and contacts a side surface and a top surface of the second test pad facing the first test pad.

18. The test circuit board according to claim 16, wherein: The two surfaces extending in the directions different from each other share a same edge.

19. The test circuit board according to any one of claims 11 to 18, wherein: The first test pad is provided in plurality to include a plurality of first test pads spaced apart from each other in a first direction, and the second test pad is provided in plurality to include a plurality of second test pads spaced apart from each other in the first direction, Wherein, in a plan view, a distance between adjacent first test pads among the plurality of first test pads in the first direction is equal to or greater than a length of one of the plurality of first test pads in the first direction.

20. The test circuit board according to claim 11, wherein: In a plan view, the first test pad and the second test pad are spaced apart from each other in a second direction with an insulating layer therebetween, and In the plan view, a length of the insulating layer in the second direction is equal to or greater than a length of at least one of the first test pad and the second test pad in the second direction.

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