Pixel circuit and display panel

Abstract

The application discloses a pixel circuit and a display panel. The pixel circuit comprises a scan control module, a data storage module and a light-emitting module. The scan control module is used for writing a data signal. The data storage module is used for storing the data signal. The light-emitting module drives a light-emitting element based on a power supply flowing through the data storage module. The data storage module comprises a memory with a phase change material layer. The data signal adjusts a molecular state of the phase change material layer to adjust an impedance of the memory, so that the power supply has a voltage loss corresponding to the data signal after flowing through the data storage module. The pixel circuit stores the data signal by using the memory with the phase change material layer, can omit a capacitor and part of a switch tube, greatly reduces an occupied area of the pixel circuit, and effectively improves a pixel density of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a pixel circuit and a display panel. BACKGROUND

[0002] With the development of display technology, display panels have become an indispensable part of electronic devices, and are widely used in various electronic devices such as televisions, computers, mobile phones, tablet computers, e-readers, game consoles, cars, home appliances, medical devices, etc.

[0003] Pixel circuits are a key component of display panels, composed of a series of tiny electronic components (such as transistors) that control the color and brightness of each pixel in the display panel. With the development of technology and the increasing demand of consumers, the performance requirements of display panels are also becoming higher and higher. Among them, the pixel density (Pixel Per Inch, PPI) is an important indicator to measure the clarity of the display panel. PPI refers to the number of pixels within one inch, with units of ppi. The higher the PPI, the more delicate the displayed image, the richer the color, and the better the visual effect. However, in some electronic devices, due to size limitations, the display panel needs to have a very high PPI to meet the display requirements. The PPI of the current display panel is still not high enough to be applied to electronic devices with high PPI display requirements.

[0004] Therefore, it is desirable to provide an improved pixel circuit and display panel to solve the above problems. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a pixel circuit and a display panel to reduce the occupied area of the pixel circuit and improve the pixel density of the display panel.

[0006] According to an aspect of the present application, a pixel circuit is provided, comprising:

[0007] a scan control module for writing a data signal;

[0008] a data storage module for storing the data signal; and

[0009] a light emitting module for driving a light emitting element based on a power supply flowing through the data storage module,

[0010] wherein the data storage module includes a memory with a phase change material layer, the data signal adjusts the molecular state of the phase change material layer to adjust the impedance of the memory, so that the power supply has a voltage loss corresponding to the data signal after flowing through the data storage module.

[0011] Optionally, when the data signal is valid, the memory is in a low resistance state, the power supply drives the light emitting element to emit light, and when the data signal is invalid, the memory is in a high resistance state, the power supply drives the light emitting element to stop emitting light.

[0012] Optionally, the scan control module includes a first switch tube, a first current terminal of the first switch tube receives the data signal, a second current terminal is connected to a second terminal of the memory, and a control terminal receives a scan signal, the light emitting module includes a current source and the light emitting element, the current source is connected between the memory and the light emitting element, or the current source is connected between the power supply and the memory, a control terminal of the current source receives a reference signal, and a second terminal of the light emitting element receives a common voltage,

[0013] In the scan phase, the scan signal is valid, and the data signal is written into the memory, and in the light emitting phase, the scan signal is invalid, and the power supply drives the light emitting element through the memory.

[0014] Optionally, when a voltage difference between two ends of the phase change material layer is greater than a first threshold value and less than a second threshold value, molecules of the phase change material are in a first state, and when the voltage difference between the two ends of the phase change material layer is greater than or equal to the second threshold value, the molecules of the phase change material are in a second state,

[0015] The data signal is in an effective state when being a high level, and is in an invalid state when being a low level,

[0016] In the scan phase, a voltage difference between a voltage value of the power supply and a high level of the data signal is greater than the first threshold value and less than the second threshold value, and a voltage difference between the voltage value of the power supply and a low level of the data signal is greater than or equal to the second threshold value,

[0017] In the light emitting phase, a voltage difference between the voltage value of the power supply and a voltage value of the second terminal of the memory is less than the first threshold value.

[0018] Optionally, the scan control module includes a selector, a first terminal of the selector receives the data signal, and a second terminal is connected to a second terminal of the memory, a first terminal of the memory receives a scan signal, the light emitting module includes a current source and the light emitting element, a first current terminal of the current source is connected to the second terminal of the memory, a second current terminal is connected to a first terminal of the light emitting element, and a control terminal receives a reference signal, and a second terminal of the light emitting element receives a common voltage,

[0019] When an absolute value of a voltage difference between the first terminal and the second terminal of the selector is greater than / equal to a third threshold value, the selector is turned on,

[0020] In the scanning phase, the scanning signal is active, and the data signal writes the memory, in the light emitting phase, the scanning signal is inactive, and the power supply drives the light emitting element through the memory,

[0021] The scanning signal is in an active state when it is at a low level, and in an inactive state when it is at a high level, and the high level of the scanning signal is used as the power supply.

[0022] Optionally, the selector includes a diode, an anode of the diode receives the data signal, and a cathode of the diode is connected to the second end of the memory.

[0023] Optionally, when a voltage difference across the phase change material layer is greater than a first threshold value and less than a second threshold value, molecules of the phase change material are in a first state, and when the voltage difference across the phase change material layer is greater than or equal to the second threshold value, the molecules of the phase change material are in a second state,

[0024] The data signal is in an active state when it is at a low level, and in an inactive state when it is at a high level,

[0025] In the scanning phase, a voltage difference between a low level of the data signal and the third threshold value minus a low level of the scanning signal is greater than the first threshold value and less than the second threshold value, and a voltage difference between a high level of the data signal and the third threshold value minus a low level of the scanning signal is greater than or equal to the second threshold value,

[0026] In the light emitting phase, a difference between a high level of the data signal and a voltage value of the second end of the memory is less than the third threshold value, and a difference between a voltage value of the power supply and the voltage value of the second end of the memory is less than the first threshold value.

[0027] Optionally, the light emitting module further includes a third switch tube, a first current end of the third switch tube is connected to the first end of the light emitting element, a second current end is connected to a reference ground, and a control end receives a reset signal.

[0028] Optionally, the memory and / or the diode are formed above or below the first switch tube, the current source, and / or the third switch tube.

[0029] According to a second aspect of the present application, a display panel is provided, including the pixel circuit as described above.

[0030] The pixel circuit and the display panel provided by the application apply a memory with a phase change material layer to a pixel circuit by means of the combination of circuit design, semiconductor devices and process innovation, and the capacitor and part of the switch tube in the traditional pixel circuit are omitted, so that the area occupied by the pixel circuit is greatly reduced, the pixel density of the display panel is effectively improved, and a compact, reliable and low-cost display panel with high pixel density (Pixel Per Inch, PPI) can be realized.

[0031] In some optional embodiments, the number of switch tubes included in the pixel circuit is only three, and if the reset of the light emitting element is ignored, the number of switch tubes included in the pixel circuit is only two, the pixel circuit has a low requirement on the number of switch tubes, the area of the pixel circuit can be further reduced, and the pixel density of the display panel is improved.

[0032] In some optional embodiments, the number of switch tubes included in the pixel circuit is only two, and if the reset of the light emitting element is ignored, the number of switch tubes included in the pixel circuit is only one, the pixel circuit has a further reduced requirement on the number of switch tubes, the area of the pixel circuit can be further reduced, and the pixel density of the display panel is improved.

[0033] In some optional embodiments, the scan signal is used instead of the power supply, the multiplexing of signals is realized, the use of lines in the display panel can be reduced, the area of the pixel circuit can be further reduced, and the pixel density of the display panel is improved.

[0034] In some optional embodiments, the memory and the selector can be arranged above each switch tube as a back end of line (BEOL) process, and do not occupy the planar area of the pixel circuit, so that the pixel circuit can have high PPI and high reliability. It has been proved by practice that the size of the pixel circuit can support 20 nm and below. BRIEF DESCRIPTION OF DRAWINGS

[0035] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application, taken in conjunction with the accompanying drawings, in which:

[0036] Figure 1 A block diagram of a pixel circuit according to an embodiment of the present application is shown;

[0037] Figure 2 A circuit diagram of a pixel circuit according to a first embodiment of the present application is shown;

[0038] Figure 3 A circuit diagram of a pixel circuit according to a second embodiment of the present application is shown;

[0039] Figure 4A circuit diagram of a pixel circuit according to a third embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The present application will be described in more detail with reference to the drawings. Like elements in the various figures are denoted by like reference numerals. Each part in the drawings is not drawn to scale for the sake of clarity. Further, some parts that are well known can not be shown in the drawings.

[0041] Many specific details of the present application are described below in order to provide a thorough understanding of the present application. However, as will be understood by one skilled in the art, the present application can be practiced without incorporating these specific details.

[0042] It should be understood that the connection / coupling of A and B in the embodiments of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, which are not limited in the embodiments of the present application.

[0043] In a conventional pixel circuit, data is stored by a dynamic random access memory (DRAM), each bit of data is stored in a separate capacitor, and the capacitor and an access transistor together form a memory cell. The capacitor can store electric charge, and the transistor acts as a switch to control the reading and storing of the electric charge. In this technical solution, the capacitor is used to directly store the data signal DATA. However, the volume of the capacitor is usually large, which is not conducive to reducing the area occupied by the pixel circuit, and the capacitor storage data is greatly affected by the capacitance value and the leakage current of the switch tube, and the reliability is not high. In another conventional pixel circuit, data is stored by a static random access memory (SRAM), and a bistable latching circuitry is used to store each bit of data. The main disadvantage of the static random access memory is that it needs six transistors to store each bit of data, which makes the storage density of the static random access memory lower than that of the dynamic random access memory, and is more not conducive to reducing the area occupied by the pixel circuit.

[0044] In the embodiments of the present application, the state of the memory with a phase change material layer is changed by the data signal, and the light emitting element is driven based on the state of the memory. The memory has a very small feature size, and can achieve a good compromise in terms of speed, area, write times and power consumption. In addition, the capacitor element required by the conventional technology can be omitted, and display driving can be realized by a small number of switch tubes, which greatly reduces the area occupied by the pixel circuit and effectively improves the pixel density (Pixel Per Inch, PPI) of the display panel.

[0045] In the following embodiments, the pixel circuit is described in detail taking the light emitting element as an organic light emitting diode (OLED) as an example. It should be understood that in actual operation, the organic light emitting diode light emitting element in the pixel circuit can be replaced by other types of light emitting elements by those skilled in the art, for example, a light emitting diode (LED), a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro-LED), a mini light emitting diode (Mini-LED), an organic laser diode (OLD), etc.

[0046] The embodiments of the pixel circuit and the display panel provided by the present application will be described below with reference to the accompanying drawings.

[0047] Figure 1 A block diagram of a pixel circuit according to an embodiment of the present application is shown.

[0048] As shown in Figure 1 The pixel circuit 100 includes a scan control module 110, a data storage module 120 and a light emitting module 130. The pixel circuit 100 drives the light emitting element OLED in the light emitting module 130 to emit light at least according to the data signal DATA, the scan signal SCAN and the reference signal Vref.

[0049] The scan control module 110 is used to write the data signal DATA, and the scan control module 110 is controlled by the scan signal SCAN. For example, when the scan signal SCAN is valid, i.e. in the scanning stage, the scan control module 110 turns on the current path of the data signal DATA to the data storage module 120, so that the data signal DATA is written to the data storage module 120; when the scan signal SCAN is invalid, i.e. in the light emitting stage, the scan control module 110 turns off the current path of the data signal DATA to the data storage module 120.

[0050] The data storage module 120 is configured to store the data signal DATA. In an embodiment of the present application, the data storage module 120 comprises a memory with a layer of phase-change material, such as a Phase-Change Memory (PCM), which is a new type of Non-Volatile Random Access Memory that stores and reads data by controlling the phase-change process between the solid and liquid phases of the phase-change material. The first end of the memory PCM is connected to a power supply AVDD, and the second end is connected to the scan control module 110 and the light emitting module 130, respectively. In the scan phase, the data signal DATA is written into the data storage module 120 via the scan control module 110; in the light emitting phase, the power supply AVDD flows through the data storage module 120 to drive the light emitting module 130 to emit light. In some embodiments, the power supply AVDD has the same voltage value in the scan phase and the light emitting phase. In other embodiments, the power supply AVDD is an adjustable power supply that has different voltage values in the scan phase and the light emitting phase.

[0051] In an embodiment of the present application, the data storage module 120 stores and reads data by controlling the phase-change process between the solid and liquid phases of the phase-change material. Compared with the traditional hard disk, the phase-change memory technology has the advantages of faster speed, lower power consumption, and smaller size. When a current is passed through the phase-change material, it is heated, causing it to change from a crystalline state to an amorphous state. This change is reversible and can be controlled by the current. According to the working principle of the phase-change material, the amorphous and crystalline materials have completely different resistance, conductivity, and optical properties (such as transmittance and reflectance).

[0052] When a voltage is applied to the phase-change material, if the phase-change material is in an amorphous state, it will be in an off state before the voltage reaches the first threshold value, and no current will pass through. Only when the voltage exceeds the first threshold value will the current pass through. Once the current is turned on, the current will gradually increase as the voltage increases. The phase-change material in the conductive state is equivalent to a resistor, so it will heat up and cause the temperature to rise. When the voltage on the phase-change material remains at the first threshold value, the phase-change material will eventually reach a temperature of about 350 degrees Celsius. Although this temperature is not high enough to cause melting, if the temperature is maintained for about 100 ns, the molecules can be rearranged into a crystalline structure. Since the crystalline structure is also a stable state, once the phase-change material forms a crystalline state, even if the voltage on the phase-change material is removed and the temperature of the phase-change material decreases, the phase-change material will remain in the crystalline state. The phase-change material in the crystalline state has properties similar to ordinary resistors, and there is no voltage threshold for the amorphous state. When a voltage of about 0.5V is applied, there is about 0.5mA of current passing through.

[0053] When the phase change material is to be reset to the amorphous state, only a larger voltage (greater than the second threshold value) is needed to raise the temperature to about 600 degrees Celsius to heat the material to the molten state to melt the crystal structure. Then the voltage is removed immediately to allow the temperature to drop rapidly, and since the speed through the temperature interval of the crystal state is too fast, no crystal structure can be formed, and it is re-frozen to the amorphous state, and the reset is complete. At this time, if a voltage of about 0.5V is applied to the phase change material, no current will pass through. After the state of the phase change material is stable, when reading the state of the phase change material, a high voltage is not needed to read the state, and a voltage of about 0.1V can clearly distinguish the crystal state and the amorphous state of the phase change material.

[0054] Through the above process, it can be noted that the phase change memory PCM does not need to perform an erase operation before writing, like the traditional NAND memory. The molecular state of the phase change material can be directly changed by applying different voltages to the phase change material, without considering the previous state of the phase change material.

[0055] In the embodiment of the present application, the data signal DATA is used to adjust the molecular state of the phase change material layer of the memory in the data storage module 120 to adjust the impedance of the memory, so as to achieve the purpose of writing the data signal DATA into the data storage module 120. For example, when the voltage difference across the phase change material layer is greater than the first threshold value and less than the second threshold value, the molecules of the phase change material are in the first state (crystal state), and when the voltage difference across the phase change material layer is greater than or equal to the second threshold value, the molecules of the phase change material are in the second state (amorphous state). Therefore, the writing method of the present application is to store the data signal by defining the correspondence between the impedance of the memory and the data signal and adjusting the impedance of the memory using the data signal, which is completely different from the traditional technology of directly storing the data signal using a capacitor.

[0056] As an example, the data signal DATA is defined as invalid with a low level and valid with a high level. In the scanning phase, the power supply AVDD is high, the voltage difference between the voltage value of the power supply AVDD and the high level of the data signal DATA is greater than the first threshold value and less than the second threshold value, and the voltage difference between the voltage value of the power supply AVDD and the low level of the data signal DATA is greater than or equal to the second threshold value. Therefore, when the data signal DATA is valid, the memory PCM is in the first resistance state (for example, a low resistance state); when the data signal DATA is invalid, the memory PCM is in the second resistance state (for example, a high resistance state). In the light emitting phase, the voltage difference between the voltage value of the power supply AVDD and the voltage value of the second end of the memory is less than the first threshold value, that is, the voltage difference across the phase change material layer is less than the first threshold value, so that the molecular state of the phase change material layer is not changed, and the data signal that the memory can stably store can be used to stably drive the light emitting module 130 to emit light.

[0057] As another example, the data signal DATA is defined as valid with a low level and invalid with a high level. In the scanning phase, the power supply AVDD is low (for example, zero level). If a transistor is used for data writing, the low level of the data signal DATA is greater than the first threshold value and less than the second threshold value, and the high level of the data signal DATA is greater than or equal to the second threshold value; if a diode is used for data writing, the voltage difference between the low level of the data signal DATA and the low level of the power supply AVDD and the third threshold value (that is, the turn-on threshold value of the diode) is greater than the first threshold value and less than the second threshold value, and the voltage difference between the high level of the data signal DATA and the low level of the power supply AVDD and the third threshold value is greater than or equal to the second threshold value. Therefore, when the data signal DATA is valid, the memory PCM is in the first resistance state (for example, a low resistance state); when the data signal DATA is invalid, the memory PCM is in the second resistance state (for example, a high resistance state). In the light emitting phase, the difference between the high level of the data signal DATA and the voltage value of the second end of the memory is less than the third threshold value, and the difference between the high level of the power supply voltage and the voltage value of the second end of the memory is less than the first threshold value, so that the diode does not leak current and the molecular state of the phase change material layer is not changed, and the data signal that the memory can stably store can be used to stably drive the light emitting module 130 to emit light.

[0058] It should be understood that the embodiments of the present application are not limited thereto, and those skilled in the art can modify the definition of the valid state and invalid state of the data signal DATA and the correspondence between the resistance state of the memory PCM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is valid, the memory PCM is in the resistance state corresponding to data "1", and when the data signal DATA is invalid, the memory PCM is in the resistance state corresponding to data "0".

[0059] The light emitting module 130 includes a current source and a light emitting element, and the power source AVDD flows through the data storage module 120 and the light emitting source in sequence to drive the light emitting element. The current source is used to control the current size in the pixel circuit, so that the current source is turned off in the scanning stage and maintains the current in the pixel circuit in the light emitting stage, avoiding the change of the state of the memory. In the light emitting stage, the current source clamps the voltage of the memory at a higher potential to maintain the stable state of the memory. The current source is controlled by the reference signal Vref, which is an analog signal and can be used to adjust the current size of the current source. In some embodiments, the reference signal Vref is a signal with a constant voltage value, and all pixel circuits 100 in the display panel can share one reference signal Vref. In other embodiments, to avoid the misdirected conduction of the small current source in the scanning stage, the voltage value of the reference signal Vref can be adjusted in the scanning stage, so that the current source is directly turned off. For example, in the scanning stage, the reference signal Vref is invalid, and the current path from the data storage module 120 to the light emitting module 130 is turned off; in the light emitting stage, the reference signal Vref is valid, the current path from the data storage module 120 to the light emitting module 130 is turned on, and the voltage of the memory is clamped at a higher potential to maintain the stable state of the memory. In the light emitting stage, the power source AVDD has a voltage loss corresponding to the data signal DATA after flowing through the data storage module 120, so that the light emitting module 130 has a corresponding voltage loss when driving the light emitting module 130 to emit light, which can make the light emitting element OLED emit light corresponding to the data signal DATA. For example, when the data signal DATA is valid, the memory PCM is in a low resistance state, and the voltage loss of the power source AVDD after flowing through the memory PCM is small, and the light emitting element OLED is driven to emit light; when the data signal DATA is invalid, the memory PCM is in a high resistance state, and the current of the power source AVDD cannot pass through the memory PCM, so the light emitting element OLED stops emitting light.

[0060] In the embodiment of the present application, in the scanning phase, the scanning signal SCAN is active, the data signal DATA is written into the data storage module 120 through the scanning control module 110, and the data signal DATA is stored by adjusting the molecular state of the phase change material layer to adjust the impedance of the memory PCM; in the light emitting phase, the scanning signal SCAN is inactive, the power supply AVDD has a voltage loss corresponding to the data signal DATA after flowing through the data storage module 120, and therefore the light emitting module 130 has a corresponding voltage loss when it is driven to emit light, so that the light emitting element OLED can emit light corresponding to the data signal DATA. Therefore, the pixel circuit 100 does not directly store the data signal DATA by using the memory PCM, but changes the state of the memory by using the data signal DATA in the scanning phase, and correspondingly drives the light emitting element OLED based on the state of the memory PCM in the light emitting phase. The pixel circuit 100 stores the data signal DATA by using the memory PCM with a phase change material layer, and can omit part of the switching tube and the capacitor element required in the conventional technology, greatly reduces the occupied area of the pixel circuit 100, and effectively improves the pixel density of the display panel.

[0061] Figure 2 A circuit diagram of a pixel circuit according to the first embodiment of the present application is shown.

[0062] As Figure 2 shown, in the pixel circuit 200, the scanning control module 210 includes the first switching tube SW1, the data storage module 220 includes the memory PCM, and the light emitting module 230 includes the current source SW2, the third switching tube SW3 and the light emitting element OLED.

[0063] In particular, the first current terminal of the first switch SW1 receives the data signal DATA, the second current terminal is connected to the second terminal of the memory PCM, and the control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the second terminal of the memory PCM, the second current terminal is connected to the first terminal (anode) of the light emitting element OLED, and the control terminal receives the reference signal Vref. The first current terminal of the third switch SW3 is connected to the first terminal of the light emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The second terminal (cathode) of the light emitting element OLED receives the common voltage Vcom. The first terminal of the memory PCM is connected to the power supply AVDD, and the second terminal of the memory PCM is connected to the second current terminal of the first switch SW1 and the first current terminal of the current source SW2, respectively. When the scan signal SCAN is valid, the data signal DATA is written into the memory PCM, and when the scan signal SCAN is invalid, the power supply AVDD drives the light emitting element OLED through the memory PCM. In some embodiments, the reference signal Vref is in an active state in the scan phase and the light emitting phase, so as to clamp the voltage of the memory at a higher potential and maintain the stable state of the memory. In other embodiments, the reference signal Vref is in an inactive state in the scan phase, so as to turn off the current source SW2, and the reference signal Vref is in an active state in the light emitting phase, so as to clamp the voltage of the memory at a higher potential and maintain the stable state of the memory.

[0064] In this embodiment, when the voltage difference across the phase change material layer of the memory PCM is greater than a first threshold value and less than a second threshold value, the molecules of the phase change material are in a first state (crystalline state), and when the voltage difference across the phase change material layer is greater than or equal to the second threshold value, the molecules of the phase change material are in a second state (amorphous state).

[0065] As an example, the data signal DATA is defined as active in a high level and inactive in a low level. In the scanning phase, the power AVDD is in a high level, the voltage difference between the voltage value of the power AVDD and the high level of the data signal DATA is greater than a first threshold V1 and less than a second threshold V0, and the voltage difference between the voltage value of the power AVDD and the low level of the data signal DATA is greater than or equal to the second threshold V0. Therefore, when the data signal DATA is active, the memory PCM is in a first resistance state (e.g. a low resistance state) to write data "1"; when the data signal DATA is inactive, the memory PCM is in a second resistance state (e.g. a high resistance state) to write data "0". It should be understood that embodiments of the present application are not limited thereto, and those skilled in the art can modify the definition of the active state and the inactive state of the data signal DATA and the correspondence between the resistance state of the memory PCM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is active, the memory PCM is in a resistance state corresponding to data "1", and when the data signal DATA is inactive, the memory PCM is in a resistance state corresponding to data "0".

[0066] In the scanning phase, the scanning signal SCAN is active and the reset signal RESETB is active, so the first switch SW1 and the third switch SW3 are turned on. The current source SW2 is turned off in the scanning phase. The reference signal Vref can be in an inactive state or an active state. When the reference signal Vref is in the inactive state, the current source SW2 is turned off. When the reference signal Vref is in the active state, the current of the current source SW2 is much smaller than the write current of the memory, because the current source SW2 is considered to be in the off state. At this time, the first end of the memory PCM is connected to the power supply AVDD, and the voltage value of the power supply AVDD is Vavdd. The second end of the memory PCM receives the data signal DATA. The first end and the second end of the memory PCM have a voltage difference, so that the memory PCM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is active, that is, the voltage on the data line is high VdataH, then V1 < Vavdd - VdataH < V0. The molecules of the phase change material in the memory PCM are in a crystal state, and the memory PCM is in a low resistance state, representing the write data "1". If the data signal DATA is inactive, that is, the voltage on the data line is low VdataL, then Vavdd - VdataL > V0. The molecules of the phase change material in the memory PCM are in an amorphous state, and the memory PCM is in a high resistance state, representing the write data "0". The impedance of the memory PCM determines whether the light emitting element OLED can emit light in the light emitting phase. That is, the data signal DATA writes the memory PCM by adjusting the impedance of the memory PCM. The memory PCM is disconnected from the light emitting element OLED. The first end of the light emitting element OLED is connected to the reference ground to reset the residual charge on the light emitting element OLED.

[0067] In the light emitting phase, the scanning signal SCAN is inactive and the reset signal RESETB is inactive, so the first switch SW1 and the third switch SW3 are turned off, and the current source SW2 is turned on. At this time, the memory PCM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light emitting element OLED through the memory PCM. Therefore, the power supply AVDD has a voltage loss corresponding to the data signal DATA after flowing through the memory PCM. If the data signal DATA is active, the memory PCM is in a low resistance state, and the voltage loss of the power supply AVDD after flowing through the memory PCM is small or almost 0, so that the light emitting element OLED can be successfully driven to emit light. If the data signal DATA is inactive, the memory PCM is in a high resistance state, and the voltage loss of the power supply AVDD after flowing through the memory PCM is large, so that the light emitting element OLED cannot be driven to emit light.

[0068] As another example, the data signal DATA is defined as active in low level and inactive in high level, and the power supply AVDD is an adjustable power supply. In the scan phase, the power supply AVDD is low (for example, zero level), the low level of the data signal DATA is greater than the first threshold V1 and less than the second threshold V0, and the high level of the data signal DATA is greater than or equal to the second threshold V0. Therefore, when the data signal DATA is active, the memory PCM is in the first resistance state (for example, low resistance state), and the data "1" is written; when the data signal DATA is inactive, the memory PCM is in the second resistance state (for example, high resistance state), and the data "0" is written.

[0069] In the scan phase, the scan signal SCAN is active, and the reset signal RESETB is active, so the first switch SW1 and the third switch SW3 are turned on. The current source SW2 is turned off in the scan phase, and the reference signal Vref can be in an inactive state or an active state. When the reference signal Vref can be in the inactive state, the current source SW2 is turned off, and when the reference signal Vref can be in the active state, the current of the current source SW2 is much smaller than the write current of the memory, because it can be considered that the current source SW2 is in the off state. At this time, the first end of the memory PCM is connected to the power supply AVDD, and the voltage value of the power supply AVDD is Vavdd. The second end of the memory PCM receives the data signal DATA, and the first end and the second end of the memory PCM have a voltage difference, so that the memory PCM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is active, that is, the voltage on the data line is low VdataL, then V1 < VdataL < V0, the molecules of the phase change material in the memory PCM are in the crystal state, the memory PCM is in the low resistance state, and the data "1" is written; if the data signal DATA is inactive, that is, the voltage on the data line is high VdataH, then VdataH > V0, the molecules of the phase change material in the memory PCM are in the amorphous state, the memory PCM is in the high resistance state, and the data "0" is written. The impedance of the memory PCM determines whether the light emitting element OLED can emit light in the light emitting phase. That is, the data signal DATA writes the memory PCM by adjusting the impedance of the memory PCM. The memory PCM is disconnected from the light emitting element OLED. The first end of the light emitting element OLED is connected to the reference ground to reset the residual charge on the light emitting element OLED.

[0070] In the light emitting stage, the scanning signal SCAN is invalid, the reset signal RESETB is invalid, and thus the first switch SW1 and the third switch SW3 are turned off, and the current source SW2 is turned on. At this time, the memory PCM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light emitting element OLED through the memory PCM. Therefore, the power supply AVDD has a voltage loss corresponding to the data signal DATA after flowing through the memory PCM. If the data signal DATA is valid, the memory PCM is in a low resistance state, and the voltage loss of the power supply AVDD after flowing through the memory PCM is small or almost 0, and the light emitting element OLED can be successfully driven to emit light; if the data signal DATA is invalid, the memory PCM is in a high resistance state, and the voltage loss of the power supply AVDD after flowing through the memory PCM is large, and the light emitting element OLED cannot be driven to emit light.

[0071] In addition, if the light emitting element OLED in the pixel circuit 200 does not have high requirements for anode reset, the problem of the need for reset of the light emitting element OLED can be ignored, and the third switch SW3 is omitted, and thus the number of switches included in the pixel circuit 200 can be only two (the first switch SW1 and the current source SW2), and the pixel circuit 200 has low requirements for the number of switches.

[0072] In this embodiment, the first switch SW1, the current source SW2 and the third switch SW3 can be transistors of types such as bipolar transistors (BJT), field effect transistors (FET) and insulated gate bipolar transistors (IGBT).

[0073] As an example, the first switch SW1, the current source SW2 and the third switch SW3 are all Positive Channel Metal Oxide Semiconductor Field-Effect Transistors (PMOSFETs). When the gate-source voltage Vgs of a PMOSFET is less than / equal to the voltage threshold, i.e. the control terminal thereof receives a low-level control signal, the current path from the first current terminal to the second current terminal of the PMOSFET is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, i.e. the control terminal thereof receives a high-level control signal, the current path from the first current terminal to the second current terminal of the PMOSFET is turned off. Therefore, it is defined that the scan signal SCAN, the reference signal Vref and the reset signal RESETB are in the active state with low levels, and the scan signal SCAN, the reference signal Vref and the reset signal RESETB are in the inactive state with high levels. It should be understood that the embodiments of the present application are not limited thereto, and those skilled in the art can modify the types of the first switch SW1, the current source SW2 and the third switch SW3 and the specific levels of the scan signal SCAN, the reference signal Vref and the reset signal RESETB in the active state and the inactive state according to actual needs.

[0074] In this embodiment, in the light-emitting phase, due to the presence of the current source SW2, the memory is clamped at a higher potential, i.e. the voltage difference across the phase change material is clamped below the first threshold, so that the state of the memory will not be flipped.

[0075] In Figure 2 the memory PCM can be formed above or below the first switch SW1, the current source SW2 and / or the third switch SW3, which can further reduce the area occupied by the pixel circuit.

[0076] Figure 3 A circuit diagram of a pixel circuit according to a second embodiment of the present application is shown.

[0077] As Figure 3 shown, in the pixel circuit 300, the scan control module 310 includes a selector selector, the data storage module 320 includes a memory PCM, and the light-emitting module 330 includes a current source SW2, a third switch SW3 and a light-emitting element OLED.

[0078] Specifically, a first end of the selector selector receives the data signal DATA, and a second end of the selector selector is connected to a second end of the memory PCM. A first current end of the current source SW2 is connected to the second end of the memory PCM, a second current end of the current source SW2 is connected to a first end (anode) of the light emitting element OLED, and a control end of the current source SW2 receives the reference signal Vref. A first current end of the third switch SW3 is connected to the first end of the light emitting element OLED, a second current end of the third switch SW3 is connected to a reference ground, and a control end of the third switch SW3 receives the reset signal RESETB. A second end (cathode) of the light emitting element OLED receives the common voltage Vcom. A first end of the memory PCM receives the scan signal SCAN, and a second end of the memory PCM is connected to the second end of the selector selector and the first current end of the current source SW2, respectively. When the scan signal SCAN is active, the data signal DATA is written into the memory PCM, and when the scan signal SCAN is inactive, the scan signal SCAN drives the light emitting element OLED through the memory PCM. In some embodiments, the reference signal Vref is active in both the scan phase and the light emitting phase, so as to clamp the voltage of the memory at a higher potential and maintain a stable state of the memory. In other embodiments, the reference signal Vref is inactive in the scan phase, so as to turn off the current source SW2, and the reference signal Vref is active in the light emitting phase, so as to clamp the voltage of the memory at a higher potential and maintain a stable state of the memory.

[0079] In this embodiment, when the voltage difference across the phase change material layer is greater than a first threshold value V1 and less than a second threshold value V0, the molecules of the phase change material are in a first state, and when the voltage difference across the phase change material layer is greater than or equal to the second threshold value V0, the molecules of the phase change material are in a second state. The scan signal SCAN is active when at a low level and inactive when at a high level, and in the light emitting phase, the high level of the scan signal SCAN is reused as a power supply AVDD.

[0080] In this embodiment, the selector selector is preconfigured with a third threshold value, and when the absolute value of the voltage difference between the first end and the second end of the selector selector is greater than / equal to the third threshold value, the selector selector is turned on, and when the absolute value of the voltage difference between the first end and the second end of the selector selector is less than the third threshold value, the selector selector is turned off. As an example, the selector selector includes a diode, an anode of the diode receives the data signal DATAA, and a cathode of the diode is connected to the second end of the memory PCM.

[0081] Specifically, in the selector selector, when a forward bias greater than a third threshold Vd is applied, the impedance is small, and the selector selector is turned on. When the bias is reduced to less than the third threshold Vd, the impedance is large, and the selector selector is turned off. In some embodiments, the selector selector can be any combination of a PN diode, a Schottky diode, or a traditional type of diode such as a bipolar junction transistor (BJT), and can also be an Ovonic Threshold Switch (OTS), which is similar to a phase change memory (PCM), but the difference is that its molecules will not crystallize. The Ovonic Threshold Switch can be realized by adding other elements (such as arsenic) to the phase change material to prevent crystallization, and each time the voltage is removed, the temperature drops, and it returns to the amorphous state, never appearing in the crystal state, so it cannot be used as a memory but can be used as a switch.

[0082] In this embodiment, the data signal DATA is defined as active when having a low level and inactive when having a high level, and the scan signal SCAN is active when being low and inactive when being high. In the scan phase, the voltage difference between the low level of the data signal DATA and the low level of the scan signal and the third threshold Vd is greater than the first threshold V1 and less than the second threshold V0, and the voltage difference between the high level of the data signal DATA and the low level of the scan signal and the third threshold Vd is greater than or equal to the second threshold V0. Therefore, when the data signal DATA is active, the molecules of the phase change material layer in the memory PCM are in a crystal state, and the memory PCM is in a low resistance state, writing data "1"; when the data signal DATA is inactive, the molecules of the phase change material layer in the memory PCM are in an amorphous state, and the memory PCM is in a high resistance state, writing data "0". It should be understood that the embodiments of the present application are not limited thereto, and those skilled in the art can modify the definition of the active state and the inactive state of the data signal DATA and the correspondence between the resistance state of the memory PCM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is active, the memory PCM is in a resistance state corresponding to data "1", and when the data signal DATA is inactive, the memory PCM is in a resistance state corresponding to data "0".

[0083] In the scanning phase, the scanning signal SCAN is active, the reference signal Vref is inactive, and the reset signal RESETB is active, so the third switch SW3 is turned on. The current source SW2 is turned off in the scanning phase, and the reference signal Vref can be in an inactive state or an active state. When the reference signal Vref is in the inactive state, the current source SW2 is turned off, and when the reference signal Vref is in the active state, the current of the current source SW2 is much smaller than the write current of the memory, because the current source SW2 is considered to be in the off state. At this time, the first end of the memory PCM is connected to the scanning signal SCAN with a low level, and the voltage value of the scanning signal SCAN is AVDD, the second end of the memory PCM receives the data signal DATA, and the first end and the second end of the memory PCM have a voltage difference, so that the memory PCM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is active, that is, the voltage on the data line is low VdataL, then V1 < VdataL - VscanL - Vd < V0, the molecules of the phase change material in the memory PCM are in a crystal state, the memory PCM is in a low resistance state, and the write data "1" is represented; if the data signal DATA is inactive, that is, the voltage on the data line is high VdataH, VdataH - VscanL - Vd > V0, the molecules of the phase change material in the memory PCM are in an amorphous state, the memory PCM is in a high resistance state, and the write data "0" is represented. The impedance of the memory PCM determines whether the light emitting element OLED can emit light in the light emitting phase. That is, the data signal DATA writes the memory PCM by adjusting the impedance of the memory PCM. The memory PCM is disconnected from the light emitting element OLED. The first end of the light emitting element OLED is connected to the reference ground to reset the residual charge on the light emitting element OLED.

[0084] In the light emitting phase, the scanning signal SCAN is inactive, the reference signal Vref is active, and the reset signal RESETB is inactive, so the third switch SW3 is turned off and the current source SW2 is turned on. At this time, the memory PCM has an impedance corresponding to the data signal DATA, and the high-level scanning signal SCAN is connected to the light emitting element OLED through the memory PCM. Therefore, after the high-level scanning signal SCAN flows through the memory PCM, it has a voltage loss corresponding to the data signal DATA. If the data signal DATA is active, the memory PCM is in a low resistance state, and the voltage loss of the high-level scanning signal SCAN after flowing through the memory PCM is small or almost 0, so the light emitting element OLED can be successfully driven to emit light; if the data signal DATA is inactive, the memory PCM is in a high resistance state, and the voltage loss of the high-level scanning signal SCAN after flowing through the memory PCM is large, so the light emitting element OLED cannot be driven to emit light.

[0085] In addition, if the light emitting element OLED in the pixel circuit 300 does not have high requirements for anode reset, the reset problem of the light emitting element OLED can be ignored, and the third switch SW3 is omitted, so that the number of switch tubes included in the pixel circuit 300 can be only one (the current source SW2), and the pixel circuit 300 has low requirements for the number of switch tubes.

[0086] In this embodiment, the current source SW2 and the third switch SW3 can be transistors of types such as bipolar junction transistor (BJT), field effect transistor (FET), insulated gate bipolar transistor (IGBT), etc.

[0087] As an example, the current source SW2 and the third switch SW3 are both positive channel metal oxide semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than / equal to the voltage threshold, that is, the control end thereof receives a low-level control signal, the current path from the first current end to the second current end of the PMOSFET is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, the control end thereof receives a high-level control signal, the current path from the first current end to the second current end of the PMOSFET is turned off. Therefore, it is defined that the scanning signal SCAN and the reset signal RESETB having low levels are in an active state, and the scanning signal SCAN and the reset signal RESETB having high levels are in an inactive state. It should be understood that embodiments of the present application are not limited thereto, and those skilled in the art can modify the types of the first switch SW1, the current source SW2 and the third switch SW3 and the specific levels of the active state and the inactive state of the scanning signal SCAN and the reset signal RESETB according to actual needs.

[0088] In this embodiment, in the light emitting stage, the difference between the high level of the data signal and the voltage value of the second end of the memory is less than a third threshold, or the difference between the power supply voltage and the voltage value of the second end of the memory is less than a first threshold. Therefore, the selector selector will not be turned on, and there will be no additional current passing through the leakage of the selector selector. In the light emitting stage, the current source SW2 clamps the voltage of the memory PCM at a higher potential to maintain the stable state of the memory, so as to not cause the state of the memory PCM to flip. The “0” or “1” of the data signal can be long-term maintained in the memory PCM, which is crucial for the stability of the driving current during display.

[0089] In Figure 3In the third embodiment, the memory PCM and the selector selector can be formed above or below the first switch SW1, the current source SW2 and / or the third switch SW3, so that the area occupied by the pixel circuit can be further reduced.

[0090] Figure 4 A circuit diagram of a pixel circuit according to a third embodiment of the present application is shown.

[0091] As Figure 4 shown, in the pixel circuit 400, the scan control module includes the first switch SW1, the data storage module includes the memory PCM, and the light emitting module includes the current source SW2, the third switch SW3, the fourth switch SW4 and the light emitting element OLED.

[0092] Specifically, the first current terminal of the first switch SW1 receives the data signal DATA, the second current terminal is connected to the second terminal of the memory PCM, and the control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the power supply AVDD, the second current terminal is connected to the first terminal of the memory PCM, and the control terminal receives the reference signal Vref. The first current terminal of the third switch SW3 is connected to the first terminal of the light emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The first current terminal of the fourth switch SW4 is connected to the second terminal of the memory PCM, the second current terminal is connected to the first terminal (anode) of the light emitting element OLED, and the control terminal receives the control signal EMB. The second terminal (cathode) of the light emitting element OLED receives the common voltage Vcom. In this embodiment, the first terminal of the memory PCM is connected to the power supply AVDD via the current source SW2, and the second terminal of the memory PCM is connected to the second current terminal of the first switch SW1 and the first current terminal of the fourth switch, respectively. When the scan signal SCAN is valid, the data signal DATA is written into the memory PCM, and when the scan signal SCAN is invalid, the power supply AVDD drives the light emitting element OLED through the memory PCM. In this embodiment, the current source SW2 and the fourth switch SW4 are both P-type transistors. In the scan phase, the reference signal Vref is at a low level, the current source SW2 is turned on as an on-off switch, and the control signal EMB is at a high level, the fourth switch SW4 is turned off to avoid the light emitting element OLED being turned on. In the light emitting phase, the reference signal Vref is an analog signal with a predetermined value, the current size of the current source SW2 is adjusted to limit the voltage value across the memory to less than the write voltage of the memory, and the control signal EMB is at a low level to turn on the fourth switch SW4 to drive the light emitting element OLED to emit light.

[0093] In this embodiment, when the voltage difference across the memory PCM phase change material layer is greater than a first threshold and less than a second threshold, the molecules of the phase change material are in a first state (crystalline state), and when the voltage difference across the phase change material layer is greater than or equal to the second threshold, the molecules of the phase change material are in a second state (amorphous state).

[0094] As an example, the data signal DATA is defined to be in an active state with a high level and in an inactive state with a low level. In the scanning phase, the power supply AVDD is at a high level, the voltage difference between the voltage value of the power supply AVDD and the high level of the data signal DATA is greater than a first threshold V1 and less than a second threshold V0, and the voltage difference between the voltage value of the power supply AVDD and the low level of the data signal DATA is greater than or equal to the second threshold V0. Therefore, when the data signal DATA is active, the memory PCM is in a first resistance state (e.g. low resistance state) to write data "1", and when the data signal DATA is inactive, the memory PCM is in a second resistance state (e.g. high resistance state) to write data "0". It should be understood that embodiments of the present application are not limited thereto, and those skilled in the art can modify the definition of the active state and the inactive state of the data signal DATA and the correspondence between the resistance state of the memory PCM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is active, the memory PCM is in a resistance state corresponding to data "1", and when the data signal DATA is inactive, the memory PCM is in a resistance state corresponding to data "0".

[0095] In the scanning phase, the scanning signal SCAN is active, the reset signal RESETB is active, and the control signal EMB is inactive, so the first switch SW1 and the third switch SW3 are turned on, and the fourth switch SW4 is turned off. The current source SW2 is turned off in the scanning phase. The reference signal Vref can be in an inactive state or an active state. When the reference signal Vref can be in the inactive state, the current source SW2 is turned off. When the reference signal Vref can be in the active state, the current of the current source SW2 is far less than the write current of the memory, because the current source SW2 can be considered to be in the off state. At this time, the first end of the memory PCM is connected to the power supply AVDD, the voltage value of the power supply AVDD is Vavdd, the second end of the memory PCM receives the data signal DATA, and the first end and the second end of the memory PCM have a voltage difference, so that the memory PCM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is active, that is, the voltage on the data line is high VdataH, then V1 < Vavdd - VdataH < V0, the molecules of the phase change material in the memory PCM are in a crystal state, the memory PCM is in a low resistance state, and represents the write data "1". If the data signal DATA is inactive, that is, the voltage on the data line is low VdataL, then Vavdd - VdataL > V0, the molecules of the phase change material in the memory PCM are in an amorphous state, the memory PCM is in a high resistance state, and represents the write data "0". The impedance of the memory PCM determines whether the light emitting element OLED can emit light in the light emitting phase. That is, the data signal DATA writes the memory PCM by adjusting the impedance of the memory PCM. The memory PCM is disconnected from the light emitting element OLED. The first end of the light emitting element OLED is connected to the reference ground to reset the residual charge on the light emitting element OLED.

[0096] In the light emitting phase, the scanning signal SCAN is inactive, the reset signal RESETB is inactive, the reference signal Vref is an analog signal for adjusting the current, and the control signal EMB is active, so the first switch SW1 and the third switch SW3 are turned off, the current in the current source SW2 control circuit is controlled, and the fourth switch SW4 is turned on. At this time, the memory PCM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light emitting element OLED through the memory PCM. Therefore, after the power supply AVDD flows through the memory PCM, it has a voltage loss corresponding to the data signal DATA. If the data signal DATA is active, the memory PCM is in a low resistance state, the voltage loss of the power supply AVDD after flowing through the memory PCM is very small or almost 0, and the light emitting element OLED can be successfully driven to emit light; if the data signal DATA is inactive, the memory PCM is in a high resistance state, the voltage loss of the power supply AVDD after flowing through the memory PCM is large, and the light emitting element OLED cannot be driven to emit light.

[0097] As another example, the data signal DATA is defined as active with a low level and inactive with a high level, and the power supply AVDD is an adjustable power supply. In the scan phase, the power supply AVDD is low (for example, at zero level), the low level of the data signal DATA is greater than the first threshold V1 and less than the second threshold V0, and the high level of the data signal DATA is greater than or equal to the second threshold V0. Therefore, when the data signal DATA is active, the memory PCM is in the first resistance state (for example, a low resistance state), and the data "1" is written; when the data signal DATA is inactive, the memory PCM is in the second resistance state (for example, a high resistance state), and the data "0" is written.

[0098] In the scan phase, the scan signal SCAN is active, the reset signal RESETB is active, and the control signal EMB is inactive, so the first switch SW1 and the third switch SW3 are turned on, and the fourth switch SW4 is turned off. The current source SW2 is turned off in the scan phase, and the reference signal Vref can be in an inactive state or an active state. When the reference signal Vref can be in the inactive state, the current source SW2 is turned off, and when the reference signal Vref can be in the active state, the current of the current source SW2 is much smaller than the write current of the memory, because it can be considered that the current source SW2 is in the off state. At this time, the first end of the memory PCM is connected to the power supply AVDD, the voltage value of the power supply AVDD is Vavdd, the second end of the memory PCM receives the data signal DATA, and the first end and the second end of the memory PCM have a voltage difference, so that the memory PCM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is active, that is, the voltage on the data line is low VdataL, then V1 < VdataL < V0, the molecules of the phase change material in the memory PCM are in a crystal state, the memory PCM is in a low resistance state, and the data "1" is written; if the data signal DATA is inactive, that is, the voltage on the data line is high VdataH, then VdataH > V0, the molecules of the phase change material in the memory PCM are in an amorphous state, the memory PCM is in a high resistance state, and the data "0" is written. The impedance of the memory PCM determines whether the light emitting element OLED can emit light in the light emitting phase. That is, the data signal DATA writes the memory PCM by adjusting the impedance of the memory PCM. The memory PCM is disconnected from the light emitting element OLED. The first end of the light emitting element OLED is connected to the reference ground to reset the residual charge on the light emitting element OLED.

[0099] In the light emitting stage, the scanning signal SCAN is invalid, the reset signal RESETB is invalid, the reference signal Vref is an analog signal for adjusting current, the control signal EMB is valid, and thus the first switch SW1 and the third switch SW3 are turned off, the current source SW2 controls the current in the circuit, and the fourth switch SW4 is turned on. At this time, the memory PCM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light emitting element OLED through the memory PCM. Therefore, the power supply AVDD has a voltage loss corresponding to the data signal DATA after flowing through the memory PCM. If the data signal DATA is valid, the memory PCM is in a low resistance state, and the voltage loss of the power supply AVDD after flowing through the memory PCM is small or almost 0, so that the light emitting element OLED can be successfully driven to emit light; if the data signal DATA is invalid, the memory PCM is in a high resistance state, and the voltage loss of the power supply AVDD after flowing through the memory PCM is large, so that the light emitting element OLED cannot be driven to emit light.

[0100] In addition, if the light emitting element OLED in the pixel circuit 400 does not have high requirements for anode reset, the problem of the need for reset of the light emitting element OLED can be ignored, and the third switch SW3 is omitted, so that the number of switches included in the pixel circuit 400 can be only two (the first switch SW1 and the current source SW2), and the pixel circuit 400 has low requirements for the number of switches.

[0101] In this embodiment, the first switch SW1, the current source SW2, the third switch SW3 and the fourth switch SW4 can be transistors of types such as bipolar transistors (BJT), field effect transistors (FET) and insulated gate bipolar transistors (IGBT).

[0102] As an example, the first switch SW1, the current source SW2, the third switch SW3 and the fourth switch SW4 are all Positive Channel Metal Oxide Semiconductor Field-Effect Transistors (PMOSFETs). When the gate-source voltage Vgs of a PMOSFET is less than / equal to the voltage threshold, i.e. the control terminal thereof receives a low-level control signal, the current path from the first current terminal to the second current terminal of the PMOSFET is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, i.e. the control terminal thereof receives a high-level control signal, the current path from the first current terminal to the second current terminal of the PMOSFET is turned off. Therefore, it is defined that the scan signal SCAN, the reference signal Vref and the reset signal RESETB are in the active state with low levels, and the scan signal SCAN, the reference signal Vref and the reset signal RESETB are in the inactive state with high levels. It should be understood that embodiments of the present application are not limited thereto, and those skilled in the art can modify the types of the first switch SW1, the current source SW2 and the third switch SW3 and the specific levels of the scan signal SCAN, the reference signal Vref and the reset signal RESETB in the active state and the inactive state according to actual needs.

[0103] In this embodiment, in the light-emitting stage, due to the presence of the current source SW2, the memory is clamped at a higher potential, i.e. the voltage difference across the phase change material is clamped below the first threshold, so that the state of the memory will not be flipped.

[0104] In Figure 4 , the memory PCM can be formed above or below the first switch SW1, the current source SW2 and / or the third switch SW3, which can further reduce the occupied area of the pixel circuit.

[0105] In Figure 4 , the memory PCM and the selector selector can be formed above or below the first switch SW1, the current source SW2, the third switch SW3 and / or the fourth switch SW4, which can further reduce the occupied area of the pixel circuit.

[0106] In addition, the present application also provides a display panel comprising a plurality of pixel circuits as described above. Figure 2The pixel circuit shown in any one of the formulas 1 to 3, a plurality of pixel circuits are arranged in an array in the display panel, one column of pixel circuits shares one data line, one row of pixel circuits shares one scan line, and all the pixel circuits can share one common voltage. The type of the display panel can be any one of a Low-Temperature Polysilicon Organic Light-Emitting Diode (LTPS OLED) display panel, a Micro Organic Light Emitting Diode (Micro-OLED) display panel, a Mini Organic Light Emitting Diode (Mini-OLED) display panel, a Micro Light Emitting Diode (Micro-LED) display panel, a Passive Matrix Organic Light Emitting Diode (Passive Matrix OLED) display panel, an Active Matrix Organic Light Emitting Diode (Active Matrix OLED) display panel, a Flexible Organic Light Emitting Diode (Flexible OLED) display panel, a Transparent Organic Light Emitting Diode (Transparent OLED) display panel, and the like, and the present application does not limit the type of the display panel.

[0107] In summary, the present application provides a pixel circuit and a display panel. By combining the circuit design with the innovation of semiconductor devices and processes, the memory with the phase change material layer is applied to the pixel circuit, the capacitor in the traditional pixel circuit is omitted, the occupied area of the pixel circuit is greatly reduced, the pixel density of the display panel is effectively improved, and the compact, reliable and low-cost high-PPI display panel can be realized.

[0108] In some optional embodiments, the number of switching tubes included in the pixel circuit is only three, and if the reset problem of the light emitting element is ignored, the number of switching tubes included in the pixel circuit is only two, and the pixel circuit has low requirements on the number of switching tubes.

[0109] In some optional embodiments, a selector is used for data writing, and the number of switching tubes included in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switching tubes included in the pixel circuit is only one, and the pixel circuit further reduces the requirement for the number of switching tubes.

[0110] In some optional embodiments, a scanning signal is used instead of a power supply to achieve signal multiplexing, which can reduce the use of circuits in the display panel, further reduce the area of ​​the pixel circuit, and improve the pixel density of the display panel.

[0111] In some optional embodiments, the memory and selector can be fabricated above each switch transistor as a back-end of line (BEOL) process, eliminating the need for pixel circuit planar area. This allows for high PPI and high reliability. Practice has proven that this pixel circuit can be fabricated down to 20nm or smaller.

[0112] Some examples of pixel circuits and display panels according to the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited thereto and may be expanded and deformed in other ways.

[0113] For example, it should be understood that the reference ground potential in the aforementioned embodiments may be replaced by other non-zero reference potentials (having positive or negative voltage amplitudes) or controlled varying reference signals in alternative embodiments.

[0114] At the same time, those skilled in the art will appreciate that, in conjunction with the various exemplary structures and methods described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used for each structure or reasonable variations of the structure to achieve the described functions, but such implementations should not be considered beyond the scope of this application. Furthermore, it should be understood that the connection relationships between the various components of the amplifier in the aforementioned figures in the embodiments of this application are for illustrative purposes only and do not impose any limitations on the embodiments of this application.

[0115] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0116] In accordance with the practice of the present application, such embodiments have been described in terms of specific embodiments set forth in the description and illustrations, and it is apparent that many modifications and variations can be made by those skilled in the art. It is intended that the application be limited only by the appended claims, and their equivalents.

Claims

1. A pixel circuit, comprising: a scan control module configured to write a data signal; a data storage module configured to store the data signal; and a light emitting module comprising a current source and a light emitting element, the light emitting element being driven by the current source based on a power source flowing through the data storage module, wherein the data storage module comprises a memory having a phase change material layer, the data signal adjusting a molecular state of the phase change material layer to adjust an impedance of the memory such that the power source has a voltage loss corresponding to the data signal after flowing through the data storage module, the current source being connected between the memory and the light emitting element, or the current source being connected between the power source and the memory. When the data signal is active, the memory is in a low resistance state, and the power source drives the light emitting element to emit light, and when the data signal is inactive, the memory is in a high resistance state, and the power source drives the light emitting element to stop emitting light.

2. The pixel circuit of claim 1, wherein, The scan control module comprises a first switch tube, a first current terminal of the first switch tube receiving the data signal, a second current terminal of the first switch tube being connected to a second terminal of the memory, a control terminal of the first switch tube receiving a scan signal, a control terminal of the current source receiving a reference signal, a second terminal of the light emitting element receiving a common voltage, and a first terminal of the memory being connected to the power source, 3. The pixel circuit of claim 1, wherein, in a scan phase, the scan signal being active, the data signal being written into the memory, and in a light emitting phase, the scan signal being inactive, the power source driving the light emitting element through the memory. When a voltage difference between two terminals of the phase change material layer is greater than a first threshold value and less than a second threshold value, molecules of the phase change material are in a first state, and when the voltage difference between the two terminals of the phase change material layer is greater than or equal to the second threshold value, the molecules of the phase change material are in a second state, 4. The pixel circuit of claim 3, wherein, the data signal being in an active state when being at a high level and being in an inactive state when being at a low level, in the scan phase, a voltage difference between a voltage value of the power source and a high level of the data signal is greater than the first threshold value and less than the second threshold value, and a voltage difference between the voltage value of the power source and a low level of the data signal is greater than or equal to the second threshold value, in the light emitting phase, a voltage difference between the voltage value of the power source and a voltage value of the second terminal of the memory is less than the first threshold value. The scan control module comprises a selector, a first terminal of the selector receiving the data signal, a second terminal of the selector being connected to the second terminal of the memory, a first terminal of the current source being connected to the second terminal of the memory, a second current terminal of the current source being connected to a first terminal of the light emitting element, a control terminal of the current source receiving a reference signal, and a second terminal of the light emitting element receiving a common voltage, 5. The pixel circuit of claim 1, wherein, wherein the selector is turned on when an absolute value of a voltage difference between the first terminal and the second terminal of the selector is greater than / equal to a third threshold value, in the scan phase, the scan signal being active, the data signal being written into the memory, and in the light emitting phase, the scan signal being inactive, the power source driving the light emitting element through the memory, ​ The scanning signal is in an active state when it is at a low level and in an inactive state when it is at a high level, and the high level of the scanning signal is used as the power supply.

6. The pixel circuit of claim 5, wherein, The selector includes a diode, an anode of the diode receiving the data signal, and a cathode of the diode connected to the second terminal of the memory.

7. The pixel circuit of claim 5, wherein, When a voltage difference between two ends of the phase change material layer is greater than a first threshold value and less than a second threshold value, molecules of the phase change material are in a first state, and when the voltage difference between the two ends of the phase change material layer is greater than or equal to the second threshold value, the molecules of the phase change material are in a second state, The data signal is in an active state when it is at a low level and in an inactive state when it is at a high level, In the scanning phase, a voltage difference between a low level of the data signal and the third threshold value minus a low level of the scanning signal is greater than the first threshold value and less than the second threshold value, and a voltage difference between a high level of the data signal and the third threshold value minus the low level of the scanning signal is greater than or equal to the second threshold value, In the light emitting phase, a difference between a high level of the data signal and a voltage value of the second terminal of the memory is less than the third threshold value, and a difference between a voltage value of the power supply and the voltage value of the second terminal of the memory is less than the first threshold value.

8. The pixel circuit of claim 3, wherein, The light emitting module further includes a third switch tube, a first current terminal of the third switch tube connected to the first terminal of the light emitting element, a second current terminal of the third switch tube connected to a reference ground, and a control terminal of the third switch tube receiving a reset signal.

9. The pixel circuit of claim 8, wherein, The memory is formed above or below the first switch tube, the current source, and / or the third switch tube.

10. The pixel circuit of claim 6, wherein, The light emitting module further includes a third switch tube, a first current terminal of the third switch tube connected to the first terminal of the light emitting element, a second current terminal of the third switch tube connected to a reference ground, and a control terminal of the third switch tube receiving a reset signal.

11. The pixel circuit of claim 10, wherein, The memory and / or the diode are formed above or below the current source and / or the third switch tube.

12. A display panel, comprising the pixel circuit according to any one of claims 1 to 11.

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