Semiconductor element and manufacturing method thereof
By forming a patterned hard mask layer and a deposited oxide layer on the substrate of the semiconductor element, the defects in the trench filling process are solved, and higher electrical performance and filling quality are achieved.
Patent Information
- Application Number
- CN202410348155.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-14
- Filing Date
- 2024-03-26
- Publication Date
- 2025-06-17
AI Technical Summary
Defects may occur in semiconductor components during the trench filling process, resulting in changes in resistance and reduced breakdown voltage in subsequent processes, thereby reducing component performance.
By forming a patterned hard mask layer on the substrate surface, a hollow portion is formed to create a trench, and a first oxide layer is deposited by a first deposition process, followed by a second deposition process to fill the trench.
This method can effectively fill grooves with different depth and aspect ratios, reduce the difficulty of quality control of filling materials, reduce the chance of defect generation, avoid short circuit problems of dielectric layer in subsequent processes, and improve overall electrical performance.
Smart Images
Figure CN120164786A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] With the continuous evolution of semiconductor processes, the trench filling process will face challenges. For example, one of the related challenges brought by semiconductor devices is that if the trenches are not filled in an appropriate manner, defects may occur during the trench filling process. These defects are likely to cause resistance variations and a reduction in breakdown voltage in subsequent related processes (e.g., forming contact lines (CS) and word lines (WL) in the filling material), thereby degrading the performance of the entire semiconductor device. Summary of the Invention
[0003] In view of this, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems.
[0004] To achieve the above object, according to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a patterned hard mask layer on the surface of the substrate in the peripheral region and the array region of the substrate, wherein the patterned hard mask layer has a plurality of openings; forming a plurality of trenches on the surface of the substrate in the peripheral region and the array region through the openings of the patterned hard mask layer; depositing a first oxide layer on the inner surfaces of the plurality of trenches by a first deposition process; depositing a second oxide layer on the first oxide layer by a second deposition process, such that the trenches are filled, wherein the material of the first oxide layer is the same as the material of the second oxide layer.
[0005] In one or more embodiments of the present disclosure, performing the step of the first deposition process causes the first oxide layer to completely fill the trenches located in the array region.
[0006] In one or more embodiments of the present disclosure, performing the first deposition process causes the first oxide layer to completely fill the trenches located in the array region, but the first oxide layer does not completely fill the trenches located in the peripheral region due to different aspect ratios of the trenches located in the array region and the peripheral region.
[0007] In one or more embodiments of the present disclosure, the first oxide layer and the second oxide layer completely fill the trenches located in the peripheral region.
[0008] In one or more embodiments of the present disclosure, the step of depositing the second oxide layer is performed after the step of depositing the first oxide layer.
[0009] In one or more embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes annealing the first oxide layer after the step of depositing the first oxide layer.
[0010] In one or more embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes a step of densifying a second oxide layer, which is performed after the step of depositing the second oxide layer.
[0011] In one or more embodiments of the present disclosure, the process temperature of the step of densifying the second oxide layer is lower than the process temperature of the step of annealing the first oxide layer.
[0012] In one or more embodiments of the present disclosure, the step of densifying the second oxide layer is performed by an annealing process.
[0013] In one or more embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes a step of removing portions of the first oxide layer and the second oxide layer by a planarization process.
[0014] In one or more embodiments of the present disclosure, the step of removing portions of the first oxide layer and the second oxide layer causes the remaining portions of the first oxide layer and the second oxide layer to be coplanar with the patterned hard mask layer.
[0015] In one or more embodiments of the present disclosure, the step of removing portions of the first oxide layer and the second oxide layer is performed after the step of densifying the second oxide layer.
[0016] In one or more embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes a step of annealing the first oxide layer and the second oxide layer, which is performed after the step of depositing the second oxide layer.
[0017] To achieve the above object, according to an embodiment of the present disclosure, a semiconductor device includes a substrate, a first oxide layer, and a second oxide layer. The substrate has a plurality of trenches in a peripheral region and an array region of the substrate. The aspect ratio of the width to the depth of the trenches in the peripheral region is in the range of 1.25 to 1.5. The first oxide layer is disposed on inner surfaces of the trenches of the substrate. The second oxide layer is disposed on the first oxide layer such that the trenches are filled. The material of the first oxide layer is the same as the material of the second oxide layer. The aspect ratio of the trenches in the array region is different from the aspect ratio of the trenches in the peripheral region.
[0018] In one or more embodiments of the present disclosure, the first oxide layer completely fills the trenches in the array region.
[0019] In one or more embodiments of the present disclosure, the first oxide layer completely fills the trenches in the array region and does not fill the trenches in the peripheral region.
[0020] In one or more embodiments of the present disclosure, the first oxide layer and the second oxide layer completely fill the trenches located in the peripheral region.
[0021] In one or more embodiments of the present disclosure, the aspect ratio of the width to the depth of the trenches located in the array region is smaller than the aspect ratio of the width to the depth of the trenches located in the peripheral region.
[0022] In summary, in the semiconductor device and the method of manufacturing the same according to the present disclosure, since the deposition steps for filling trenches with different aspect ratios are divided into multiple steps, the difficulty of quality control of the filling material can be reduced. In the semiconductor device and the method of manufacturing the same according to the present disclosure, since the first deposition process is performed by flowable chemical vapor deposition, the trenches in the array region can be completely filled in a proper manner, thereby reducing the probability of generating defects and further avoiding the short-circuit problem of the dielectric layer after filling in subsequent processes. In the semiconductor device and the method of manufacturing the same according to the present disclosure, since the second deposition process is performed by spin-on dielectric coating deposition and the annealing temperature of the second oxide layer formed by spin-on dielectric coating deposition is relatively low, the second deposition process can prevent the collapse of the island structure of the array, thereby improving the overall electrical performance (e.g., In-die Overlay Performance).
[0023] The above is only used to illustrate the problems to be solved by the present disclosure, the technical means for solving the problems, and the effects produced thereby. The specific details of the present disclosure will be described in detail in the following embodiments and related drawings. Description of the Drawings
[0024] To make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows:
[0025] Figure 1 It is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0026] Figure 2 It is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0027] Figure 3 It is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0028] Figure 4 It is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0029] Figure 5FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0030] Figure 6 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0031] Figure 7 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0032] The following will disclose multiple embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be illustrated in a simple schematic manner in the drawings. The same reference numerals will be used to represent the same or similar elements in all drawings.
[0033] Please refer to Figure 1 . Figure 1 According to one embodiment of the present disclosure, Figure 7 A flow chart of method M of semiconductor device 100 is shown. Figure 1 The method M shown includes step S101, step S102, step S103 and step S104. For a better understanding of step S101, please refer to Figure 1 , Figure 2 as well as Figure 3 To better understand step S102, please refer to Figure 1 as well as Figure 4 To better understand step S103, please refer to Figure 1 as well as Figure 5 To better understand step S104, please refer to Figure 1 , Figure 6 as well as Figure 7 .
[0034] Step S101 , step S102 , step S103 , and step S104 are described in detail below.
[0035] Step S101: forming a patterned hard mask layer on the surface of the substrate in the peripheral region and the array region of the substrate, wherein the patterned hard mask layer has a plurality of hollow portions.
[0036] Please refer to Figure 2 . Figure 2is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In step S101, a patterned hard mask layer 120 is formed on the surface 110a of the substrate 110 in the array region 100A and the peripheral region 100B of the substrate 110, wherein the patterned hard mask layer 120 has a plurality of openings O1 and O2. As Figure 2 shown, the substrate 110 is provided. As Figure 2 shown, the substrate 110 includes an array region 100A and a peripheral region 100B.
[0037] In some embodiments, the substrate 110 may be a silicon-based substrate. In some embodiments, the substrate 110 may include single-crystalline silicon, polycrystalline silicon, amorphous silicon, or other similar materials. However, any suitable material may be used.
[0038] In some embodiments, the substrate 110 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or similar methods. The present disclosure is not intended to be limited to the method of forming the substrate 110.
[0039] Please refer to Figure 3 。 Figure 3 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As Figure 3 shown, the patterned hard mask layer 120 is disposed on the substrate 110. As Figure 3 shown, the patterned hard mask layer 120 has a plurality of openings O1 and O2. The opening O1 is located in the array region 100A, and the opening O2 is located in the peripheral region 100B. For simplicity of illustration, in Figure 3 the opening O2 is depicted as a single opening.
[0040] In some embodiments, the openings O1 and O2 may be formed by any suitable method, such as wet etching, dry etching, or other similar methods. The present disclosure is not intended to be limited to the method of forming the openings O1 and O2.
[0041] In some embodiments, the width of each opening O2 is greater than the width of each opening O1.
[0042] In some embodiments, the patterned hard mask layer 120 may include, like silicon nitride (Si x N y ), titanium nitride (Ti x N y) or other similar materials. However, any suitable materials can be used.
[0043] Step S102: Form a plurality of trenches on the surface of the substrate in the peripheral region and the array region by patterning the openings of the hard mask layer.
[0044] Please refer to Figure 4 . Figure 4 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In step S102, a plurality of trenches T1 and T2 are formed on the surface 110a of the substrate 110 in the array region 100A and the peripheral region 100B by patterning the openings O1 and O2 of the hard mask layer 120. As Figure 4 shown, the trenches T1 and T2 are formed by patterning the openings O1 and O2 of the hard mask layer 120, respectively. In some embodiments, the trenches T1 and T2 are recessed from the surface 110a of the substrate 110.
[0045] As Figure 4 shown, each trench T1 includes a depth D1 and a width W1. In some embodiments, the depth D1 can be greater than the width W1, but the present disclosure is not limited thereto.
[0046] As Figure 4 shown, each trench T2 includes a depth D2 and a width W2. In some embodiments, the aspect ratio of the width W2 to the depth D2 of the trench T2 is in the range of about 1.25 to about 1.5, but the present disclosure is not limited thereto. In some embodiments, the depth D2 can be less than the width W2, but the present disclosure is not limited thereto.
[0047] In some embodiments, the aspect ratio of the width W1 to the depth D1 of each trench T1 in the array region 100A is less than the aspect ratio of the width W2 to the depth D2 of each trench T2 in the peripheral region 100B.
[0048] In some embodiments, the trenches T1 and T2 can be formed by any suitable method, such as wet etching, dry etching, or similar methods. The present disclosure does not intend to limit the method for forming the trenches T1 and T2.
[0049] Step S103: Deposit a first oxide layer on the inner surface of the trench by a first deposition process.
[0050] Please refer to Figure 1 and Figure 5 . Figure 5It is a cross-sectional view of an intermediate stage of manufacturing a semiconductor element 100 according to an embodiment of the present disclosure. In step S103, a first oxide layer 130 is deposited on the inner surface T1a of each trench T1 of the substrate 110 and on the inner surface T2a of each trench T2. As Figure 5 shown, after step S102, a first oxide layer 130 is formed on the surface 120a of the patterned hard mask layer 120. Specifically, the first oxide layer 130 at least fills the trenches T1 located in the array region 100A. In some embodiments, the trenches T1 are completely filled with the first oxide layer 130. In some embodiments, the first oxide layer 130 completely fills the trenches T1 located in the array region 100A without filling the trenches T2 located in the peripheral region 100B.
[0051] In some embodiments, the first oxide layer 130 may comprise a material such as an oxide. For example, the material may comprise silicon oxide (SiO2) or other similar materials. The present disclosure is not intended to limit the material of the first oxide layer 130.
[0052] In some embodiments, the first oxide layer 130 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or similar methods. The present disclosure is not intended to limit the method of forming the first oxide layer 130.
[0053] In some embodiments, the first oxide layer 130 may be deposited by a flowable chemical vapor deposition (FCVD) process.
[0054] Step S104: Deposit a second oxide layer on the first oxide layer by a second deposition process, causing the trenches to be filled.
[0055] Please refer to Figure 1 and Figure 6 . Figure 6 It is a cross-sectional view of an intermediate stage of manufacturing a semiconductor element 100 according to an embodiment of the present disclosure. In step S104, a second oxide layer 140 is deposited on the first oxide layer 130 by a second deposition process. As Figure 6As shown, after step S103, a second oxide layer 140 is formed on the first oxide layer 130. Specifically, the second oxide layer 140 fills the trenches T2 located in the peripheral region 100B. In some embodiments, the trenches T2 are filled with the second oxide layer 140. In some embodiments, the second oxide layer 140 completely fills the trenches T2 located in the peripheral region 100B without filling the trenches T1 located in the array region 100A.
[0056] In some embodiments, the second oxide layer 140 may comprise a material such as an oxide. In some embodiments, the material may comprise silicon dioxide (SiO2) or other similar materials. The present disclosure is not intended to limit the material of the second oxide layer 140.
[0057] In some embodiments, the second oxide layer 140 may be formed by any suitable method, such as CVD (Chemical Vapor Deposition), PECVD (Plasma-Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), PEALD (Plasma-Enhanced Atomic Layer Deposition), ECP (Electrochemical Plating), electroless plating, or similar methods. The present disclosure is not intended to limit the method for forming the second oxide layer 140.
[0058] In some embodiments, the second oxide layer 140 may be deposited by Spin-on Dielectric Coating Deposition.
[0059] In some embodiments, the material of the second oxide layer 140 is the same as that of the first oxide layer 130.
[0060] In some other embodiments, the method M further comprises a step of annealing the first oxide layer 130. The step of annealing the first oxide layer 130 is performed after step S103. In some embodiments, the step of annealing the first oxide layer 130 is performed between step S103 and step S104. In some embodiments, the step of annealing the first oxide layer 130 may be an annealing process including a heating step and a cooling step after the heating step to solidify the first oxide layer 130 having possible defects (e.g., Grain Boundary). This ensures that no defects are formed in the first oxide layer 130 in the trenches T1 and the trenches T2.
[0061] In some other embodiments, method M further includes a step of densifying the second oxide layer 140. The step of densifying the second oxide layer 140 is performed after step S104 and before the step of annealing the first oxide layer 130. In some embodiments, the step of densifying the second oxide layer 140 may be an annealing process including a heating step and a cooling step after the heating step to solidify the second oxide layer 140 that may have defects (e.g., grain boundaries). This ensures that no defects are formed in the second oxide layer 140.
[0062] The step of annealing the first oxide layer 130 has a first process temperature, and the step of densifying the second oxide layer 140 has a second process temperature. The first process temperature and the second process temperature refer to the annealing temperature. In some embodiments, the second process temperature is lower than the first process temperature. Since the second process temperature is lower, the problem of the island structure of the array collapsing can be prevented. Therefore, the in-die overlay performance of the semiconductor element 100 can be well improved.
[0063] In some other embodiments, method M further includes a step of annealing both the first oxide layer 130 and the second oxide layer 140. The step of annealing both the first oxide layer 130 and the second oxide layer 140 is performed after step S104. In some embodiments, the step of annealing both the first oxide layer 130 and the second oxide layer 140 may be regarded as separately performing the above-mentioned densification of the second oxide layer 140 (i.e., not performing the above-mentioned annealing of the first oxide layer 130). This is because the densification step performed after the second deposition process not only densifies the second oxide layer 140 but also substantially anneals the first oxide layer 130.
[0064] Please refer to Figure 1 and Figure 7 . Figure 7 is a cross-sectional view of an intermediate stage of manufacturing the semiconductor element 100 according to an embodiment of the present disclosure. As Figure 7As shown, method M may further include the step of removing multiple portions of the first oxide layer 130 and the second oxide layer 140 by a planarization process. In some embodiments, the step of removing multiple portions of the first oxide layer 130 and the second oxide layer 140 is performed after the step of densifying the second oxide layer 140 (i.e., step S104). More specifically, in some embodiments, the step of depositing the first oxide layer 130 (i.e., step S103) and the step of depositing the second oxide layer 140 (i.e., step S104) are performed to transition-fill the trench T1 and the trench T2. In the removing step, the remaining portions of the first oxide layer 130 and the second oxide layer 140 are coplanar with the patterned hard mask layer 120. As Figure 7 shown, in some embodiments, the surface 130a of the first oxide layer 130 and the surface 140a of the second oxide layer 140 are flush with the surface 120a of the patterned hard mask layer 120.
[0065] In some embodiments, the planarization process may be performed by a chemical mechanical planarization (CMP) process.
[0066] By performing the method M disclosed herein, Figure 1 a semiconductor device 100 with better electrical performance can be formed.
[0067] Based on the above discussion, it can be seen that in the semiconductor device and its manufacturing method disclosed herein, since the deposition steps for filling trenches with different aspect ratios are divided into multiple steps, the difficulty of quality control of the filling material can be reduced. In the semiconductor device and its manufacturing method disclosed herein, since the first deposition process is performed by a flowable chemical vapor deposition, the trenches in the array region can be completely filled in a proper manner, thereby reducing the probability of generating defects and further avoiding the problem of short circuit in the dielectric layer after filling. In the semiconductor device and its manufacturing method disclosed herein, since the second deposition process is performed by a spin-on dielectric coating deposition and the annealing temperature of the second oxide layer formed by the spin-on dielectric coating deposition is relatively low, the second deposition process can prevent the problem of collapse of the island structure in the array, thereby improving the overall electrical performance (e.g., In-die Overlay Performance).
[0068] Although the present disclosure has been described in considerable detail with reference to certain of its embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0069] The above content outlines the features of several embodiments, enabling those skilled in the art to better understand the aspects of this case. Those skilled in the art should understand that, without departing from the spirit and scope of this case, the above content can be easily used as a basis for designing or modifying into other variations in order to implement the same purpose and / or achieve the same advantages of the embodiments introduced herein. The above content should be understood as an example of this disclosure, and the scope of protection should be subject to the claims.
[0070]
Symbol Description
[0071] 100: Semiconductor element
[0072] 100A: Array region
[0073] 100B: Peripheral region
[0074] 110: Substrate
[0075] 110a, 120a, 130a, 140a: Surfaces
[0076] 120: Patterned hard mask layer
[0077] 130: First oxide layer
[0078] 140: Second oxide layer
[0079] D1, D2: Depths
[0080] M: Method
[0081] O1, O2: Cutouts
[0082] S101, S102, S103, S104: Steps
[0083] T1, T2: Trenches
[0084] T1a, T2a: Inner surfaces
[0085] W1, W2: Widths.
Claims
1. A method for manufacturing a semiconductor element, characterized in that: Include: forming a patterned hard mask layer on the peripheral region of the substrate and on the surface of the substrate in the array region, wherein the patterned hard mask layer has a plurality of hollow portions; forming a plurality of grooves on the surface of the substrate in the peripheral area and the array area through the plurality of hollow portions of the patterned hard mask layer; depositing a first oxide layer on a plurality of inner surfaces of the plurality of trenches by a first deposition process, wherein the first deposition process is performed by flowable chemical vapor deposition; as well as A second oxide layer is deposited on the first oxide layer by a second deposition process so that the plurality of trenches are filled, wherein the material of the first oxide layer is the same as the material of the second oxide layer, wherein the second deposition process is performed by spin-on dielectric coating deposition.
2. The method according to claim 1, characterized in that The step of performing the first deposition process causes the first oxide layer to completely fill the plurality of trenches located in the array region.
3. The method according to claim 2, characterized in that Executing the first deposition process causes the first oxide layer to completely fill the plurality of trenches in the array region. However, because the plurality of trenches in the array region and the peripheral region have different aspect ratios, the first oxide layer does not completely fill the plurality of trenches in the peripheral region.
4. The method according to claim 1, characterized in that The first oxide layer and the second oxide layer completely fill the plurality of trenches in the peripheral region.
5. The method according to claim 1, characterized in that: The step of depositing the second oxide layer is performed after the step of depositing the first oxide layer.
6. The method according to claim 1, characterized in that The method further includes annealing the first oxide layer after depositing the first oxide layer.
7. The method according to claim 6, characterized in that Further comprising the step of densifying the second oxide layer after the step of depositing the second oxide layer.
8. The method according to claim 7, characterized in that A process temperature of the step of densifying the second oxide layer is lower than a process temperature of the step of annealing the first oxide layer.
9. The method according to claim 7, characterized in that: The step of densifying the second oxide layer is performed by an annealing process.
10. The method according to claim 7, characterized in that The method further includes removing multiple portions of the first oxide layer and the second oxide layer through a planarization process.
11. The method according to claim 10, characterized in that The step of removing the plurality of portions of the first oxide layer and the second oxide layer causes the plurality of remaining portions of the first oxide layer and the second oxide layer to be coplanar with the patterned hard mask layer.
12. The method according to claim 10, characterized in that The step of removing the first oxide layer and the plurality of portions of the second oxide layer is performed after the step of densifying the second oxide layer.
13. The method according to claim 1, characterized in that The method further includes annealing the first oxide layer and the second oxide layer after the step of depositing the second oxide layer.
14. A semiconductor device, characterized in that: Include: A substrate having a plurality of grooves located in a peripheral region and an array region of the substrate, wherein an aspect ratio of a width to a depth of the plurality of grooves in the peripheral region is in a range of 1.25 to 1.5; a first oxide layer disposed on a plurality of inner surfaces of the plurality of trenches of the substrate; as well as A second oxide layer is disposed on the first oxide layer so that the plurality of grooves are filled, wherein the material of the first oxide layer is the same as the material of the second oxide layer, and wherein the aspect ratio of the plurality of grooves located in the array area is different from the aspect ratio of the plurality of grooves located in the peripheral area.
15. The semiconductor device according to claim 14, characterized in that The first oxide layer completely fills the plurality of trenches in the array region.
16. The semiconductor device according to claim 15, characterized in that The first oxide layer completely fills the plurality of trenches located in the array region but does not fill the plurality of trenches located in the peripheral region.
17. The semiconductor device according to claim 16, characterized in that The first oxide layer and the second oxide layer completely fill the plurality of trenches in the peripheral region.
18. The semiconductor device according to claim 14, characterized in that The aspect ratio of the width to the depth of the plurality of trenches located in the array region is smaller than the aspect ratio of the width to the depth of the plurality of trenches located in the peripheral region.