Amplification circuit

Abstract

The invention provides an amplifier circuit capable of realizing miniaturization. The amplifier circuit includes: a first distributor; a control amplifier; a second dispenser; a first auxiliary amplifier; a second auxiliary amplifier; and a branch line coupler in which a first characteristic impedance at a center frequency of the first and third transmission lines is higher than a reference impedance, a second characteristic impedance at a center frequency of the second and fourth transmission lines is lower than the first characteristic impedance / square root of 2, and an amplitude of a power of the seventh signal is greater than an amplitude of a power of the sixth signal.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit. Background Art

[0002] An LMBA (Load Modulated Balanced Amplifier) includes: a control amplifier that amplifies one of the divided input signals; and a balanced amplifier that amplifies the other of the divided input signals. It is known that a 3dB branch-line coupler is used in a synthesizer that synthesizes the output signal of the control amplifier and the output signal of the balanced amplifier (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: US Patent Application Publication No. 2022 / 0255506

[0006] In an LMBA, from the viewpoint of the characteristics of the coupler, a distributed-constant type branch-line coupler using a 1 / 4 wavelength line is used as the 3dB branch-line coupler. However, due to the use of a 1 / 4 wavelength line, the distributed-constant type branch-line coupler is large, and the amplifier circuit becomes large-sized. Summary of the Invention

[0007] The present disclosure has been made in view of the above problems, and an object thereof is to provide an amplifier circuit that can be miniaturized.

[0008] One embodiment of the present disclosure is an amplifier circuit, comprising: a first divider that divides an input signal into a first signal and a second signal; a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal; a second divider that divides the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band; a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal; a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal; and a branch-line coupler, comprising: a first terminal for inputting the sixth signal; a second terminal for inputting the seventh signal; a third terminal for inputting the third signal; a fourth terminal for outputting an output signal; a first transmission line connecting the first terminal and the second terminal; a second transmission line connecting the first terminal and the third terminal; a third transmission line connecting the third terminal and the fourth terminal; and a fourth transmission line connecting the second terminal and the fourth terminal, wherein a first characteristic impedance of the first transmission line and the third transmission line at the center frequency is higher than a reference impedance, a second characteristic impedance of the second transmission line and the fourth transmission line at the center frequency is lower than the first characteristic impedance / √2, and an amplitude of the power of the seventh signal is greater than an amplitude of the power of the sixth signal.

[0009] Advantages of the Invention

[0010] According to the present disclosure, an amplifier circuit capable of miniaturization can be provided. Description of the Drawings

[0011] Figure 1 is a circuit diagram of the amplifier circuit of Example 1.

[0012] Figure 2 is a circuit diagram showing the divider of Example 1.

[0013] Figure 3 is a circuit diagram showing an example of the synthesizer of Example 1.

[0014] Figure 4 is a top view of the branch-line coupler of Example 1.

[0015] Figure 5 is a circuit diagram of the amplifier circuit of Comparative Example 1.

[0016] Figure 6 is a circuit diagram showing a part of the amplifier circuit of Comparative Example 2.

[0017] Figure 7 is a circuit diagram showing a part of the amplifier circuit of Comparative Example 2.

[0018] Figure 8It is a schematic diagram for explaining the operation of the synthesizers in Comparative Example 3 and Example 1.

[0019] Figure 9 It is a circuit diagram showing the balanced amplifier of Comparative Example 3.

[0020] Figure 10 It is a circuit diagram showing the balanced amplifier of Example 1 of Example 1.

[0021] Figure 11 It is a circuit diagram showing the balanced amplifier of Example 2 of Example 1.

[0022] Explanation of reference numerals:

[0023] 10: Control amplifier;

[0024] 10a: Main amplifier;

[0025] 11: Balanced amplifier;

[0026] 12: Peak amplifier;

[0027] 12a (first auxiliary amplifier), 12b (second auxiliary amplifier): Auxiliary amplifiers;

[0028] 14 (first distributor), 16 (second distributor): Distributors;

[0029] 18, 18a: Synthesizers;

[0030] 20, 22, 22a, 22b, 24, 24a: Matching circuits;

[0031] 26, 27, 28a, 28b: Bias circuits;

[0032] 30: Dielectric substrate;

[0033] 31: Conductor pattern;

[0034] 32: Transmission line;

[0035] 100, 110, 112: Amplifier circuits;

[0036] S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal), S7 (seventh signal): Signals;

[0037] Si: Input signal;

[0038] So: Output signal;

[0039] TL21 (First Transmission Line), TL22 (Second Transmission Line), TL23 (Third Transmission Line), TL24 (Fourth Transmission Line): Transmission lines. Detailed Implementation Manner

[0040] [Description of Embodiments of the Present Disclosure]

[0041] First, the content of the embodiments of the present disclosure will be listed for description.

[0042] (1) An embodiment of the present disclosure is an amplifier circuit, comprising: a first distributor that distributes an input signal into a first signal and a second signal; a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal; a second distributor that distributes the second signal into a fourth signal and a fifth signal with different phases at the center frequency of the operating band; a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal; a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal; and a branch-line coupler, comprising: a first end for inputting the sixth signal; a second end for inputting the seventh signal; a third end for inputting the third signal; a fourth end for outputting an output signal; a first transmission line connecting the first end and the second end; a second transmission line connecting the first end and the third end; a third transmission line connecting the third end and the fourth end; and a fourth transmission line connecting the second end and the fourth end, wherein a first characteristic impedance of the first transmission line and the third transmission line at the center frequency is higher than a reference impedance, a second characteristic impedance of the second transmission line and the fourth transmission line at the center frequency is lower than the first characteristic impedance / √2, and an amplitude of the power of the seventh signal is greater than an amplitude of the power of the sixth signal. Thereby, the branch-line coupler can be miniaturized, and variations in the load impedance of the control amplifier can be suppressed.

[0043] (2) In the above (1), it may also be that the difference between a first ratio and a second ratio is 1 dB or less, where the first ratio is the ratio of the amplitude of the power of the seventh signal to the amplitude of the power of the sixth signal, and the second ratio is the ratio of the amplitude of the power of an eighth signal, which is the sixth signal at the center frequency input to the first end and is distributed to the third end, to the amplitude of the power of a ninth signal, which is the sixth signal at the center frequency input to the first end and is distributed to the fourth end. Thereby, variations in the load impedance of the control amplifier can be suppressed.

[0044] (3) In the above (2), it may also be that the second ratio is 2 dB or more. Thereby, the branch-line coupler can be miniaturized.

[0045] (4) In any one of the above (1) to (3), it is also possible that the first characteristic impedance is 1.2 times or more of the reference impedance, and the second characteristic impedance is 0.9 / √2 times or less of the first characteristic impedance. Thereby, the branch-line coupler can be miniaturized.

[0046] (5) In any one of the above (1) to (4), it is also possible that the first width of the first transmission line and the third transmission line is smaller than the second width of the fifth transmission line connected to the first end, the second end, the third end, and the fourth end, and the third width of the second transmission line and the fourth transmission line is greater than the first width. Thereby, the branch-line coupler can be miniaturized.

[0047] (6) In any one of the above (1) to (5), it is also possible that the saturation power of the second auxiliary amplifier is greater than the saturation power of the first auxiliary amplifier. Thereby, the variation of the load impedance of the control amplifier can be suppressed.

[0048] (7) In any one of the above (1) to (5), it is also possible that the ratio of the saturation power of the second auxiliary amplifier to the saturation power of the first auxiliary amplifier is 2 dB or more. Thereby, the variation of the load impedance of the control amplifier can be suppressed.

[0049] (8) In any one of the above (1) to (5), it is also possible that the physical size of the second auxiliary amplifier is greater than the physical size of the first auxiliary amplifier. Thereby, the variation of the load impedance of the control amplifier can be suppressed.

[0050] (9) In any one of the above (1) to (8), it is also possible that the amplitude of the power of the fifth signal is greater than the amplitude of the power of the fourth signal. Thereby, the variation of the load impedance of the control amplifier can be suppressed.

[0051] (10) In the above (9), it is also possible that the ratio of the amplitude of the power of the fifth signal to the amplitude of the power of the fourth signal is 2 dB or more. Thereby, the variation of the load impedance of the control amplifier can be suppressed.

[0052] [Details of Embodiments of the Present Disclosure]

[0053] Hereinafter, with reference to the drawings, a specific example of the amplifier circuit according to the embodiment of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0054] [Example 1]

[0055] Figure 1 is a circuit diagram of the amplifier circuit of Example 1. AsFigure 1 As shown, in the amplifier circuit 100 of Embodiment 1, a control amplifier 10 and a balanced amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a base station for mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A distributor 14 (first distributor) distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal).

[0056] The signal S1 is input to the control amplifier 10 through a matching circuit (MN: Matching Network) 20. In Figure 1 this, each of the plurality of matching circuits is labeled as MN. The matching circuit 20 matches the impedance of the matching circuit 20 observed from the distributor 14 with the impedance of the control amplifier 10 observed from the matching circuit 20. A bias circuit (BC: Bias Circuit) 26 that supplies an input bias voltage VG1 to the control amplifier 10 is connected to a node in the line between the distributor 14 and the control amplifier 10. The bias circuit 26 supplies the input bias voltage VG1 to the control amplifier 10 and suppresses the leakage of the signal S1 to the power supply that supplies the input bias voltage VG1.

[0057] The control amplifier 10 amplifies the signal S1 and outputs the amplified signal as a signal S3 (third signal). The signal S3 amplified by the control amplifier 10 is input to terminal T23 of the synthesizer 18 through the matching circuit 24. The matching circuit 24 matches the impedance of the matching circuit 24 observed from the control amplifier 10 with the impedance of the synthesizer 18 observed from the matching circuit 24. A bias circuit 27 that supplies an output bias voltage VD to the control amplifier 10 is connected to a node in the line between the control amplifier 10 and the synthesizer 18. The bias circuit 27 supplies the output bias voltage VD to the control amplifier 10 and suppresses the leakage of the signal S3 to the power supply that supplies the output bias voltage VD.

[0058] The signal S2 distributed by the distributor 14 is input to the balanced amplifier 11. The balanced amplifier 11 includes a distributor 16, an auxiliary amplifier 12a, an auxiliary amplifier 12b, and a synthesizer 18. The distributor 16 (second distributor) distributes the signal S2 input to terminal T11 into a signal S4 (fourth signal) and a signal S5 (fifth signal), and outputs them from terminals T13 and T14, respectively. The phase of the signal S5 is delayed by, for example, about 90° with respect to the signal S4. The amplitudes of the signal S5 and the signal S4 are, for example, substantially the same. 90° may not be strictly 90°, for example, it may be greater than 85° and less than 95°, or 88° or more and 92° or less. The same applies to the synthesizer 18.

[0059] The signal S4 is input to the auxiliary amplifier 12a via the matching circuit 22a. The matching circuit 22a matches the impedance of the matching circuit 22a as observed from the distributor 16 with the impedance of the auxiliary amplifier 12a as observed from the matching circuit 22a. A bias circuit 28a for supplying the input bias voltage VG2a to the auxiliary amplifier 12a is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12a. The bias circuit 28a supplies the input bias voltage VG2a to the auxiliary amplifier 12a and suppresses the leakage of the signal S4 to the power supply for supplying the input bias voltage VG2a. The auxiliary amplifier 12a (first auxiliary amplifier) amplifies the signal S4 and outputs the amplified signal as a signal S6 (sixth signal). The signal S6 amplified by the auxiliary amplifier 12a is input to the terminal T21 of the synthesizer 18.

[0060] The signal S5 is input to the auxiliary amplifier 12b via the matching circuit 22b. The matching circuit 22b matches the impedance of the matching circuit 22b as observed from the distributor 16 with the impedance of the auxiliary amplifier 12b as observed from the matching circuit 22b. A bias circuit 28b for supplying the input bias voltage VG2b to the auxiliary amplifier 12b is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12b. The bias circuit 28b supplies the input bias voltage VG2b to the auxiliary amplifier 12b and suppresses the leakage of the signal S5 to the power supply for supplying the input bias voltage VG2b. The auxiliary amplifier 12b (second auxiliary amplifier) amplifies the signal S5 and outputs the amplified signal as a signal S7 (seventh signal). The signal S7 amplified by the auxiliary amplifier 12b is input to the terminal T22 of the synthesizer 18.

[0061] A matching circuit for impedance matching may also be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the signal of the control amplifier 10 adjusts the loads of the auxiliary amplifiers 12a and 12b. Therefore, a matching circuit may not be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. A high - order harmonic processing circuit for reflecting the high - order harmonic signals in the reflected signals S6 and S7 may also be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. When the operating frequency of the amplifier circuit is set to the fundamental wave, the high - order harmonic signals are, for example, the second - harmonic wave or the third - harmonic wave. A bias circuit for supplying the output bias voltage to the auxiliary amplifiers 12a and 12b may also be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the output bias voltages of the auxiliary amplifiers 12a and 12b are supplied from the bias circuit 27 via the synthesizer 18 to the auxiliary amplifiers 12a and 12b.

[0062] The synthesizer 18 is a distributed constant type branch line coupler. Terminals T21 to T24 are the terminals of the branch line coupler. Terminals T21 and T24 are located diagonally, and terminals T22 and T23 are located diagonally. The signal S6 is input to terminal T21 (the first terminal). The signal S7 is input to terminal T22 (the second terminal). The signal S3 is input to terminal T23 (the third terminal). The output signal So is output from terminal T24 (the fourth terminal). The synthesizer 18 synthesizes the signals S3, S6, and S7 and outputs the synthesized signal as the output signal So.

[0063] The control amplifier 10, the auxiliary amplifier 12a, and the auxiliary amplifier 12b are transistors such as FETs (Field Effect Transistors), for example. The source is grounded, the high-frequency signal is input to the gate, and the high-frequency signal is output from the drain. The FET is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). Multiple stages of FETs can also be provided in the control amplifier 10, the auxiliary amplifier 12a, and the auxiliary amplifier 12b, respectively. When the control amplifier 10, the auxiliary amplifier 12a, and the auxiliary amplifier 12b are FETs, the input bias voltages VG1, VG2a, and VG2b are gate bias voltages, and the output bias voltage VD is a drain bias voltage.

[0064] [Divider 16]

[0065] Figure 2 is a circuit diagram showing the divider 16 of Embodiment 1. As Figure 2As shown, the distributor 16 uses a distributed constant type branch line coupler. Transmission lines TL11, TL12, TL13, and TL14 are respectively connected between node N11 and N12, between node N11 and N13, between node N13 and N14, and between node N12 and N14. Transmission lines TL11 to TL14 are λ / 4 transmission lines. The electrical length of the λ / 4 transmission line is, for example, approximately λ / 4. Here, λ is the wavelength of the center frequency fo of the operating frequency band of the amplifier circuit 100. The electrical length of the λ / 4 transmission line may not be strictly λ / 4. For example, it may be 3λ / 16 or more and 5λ / 16 or less, or it may be 7λ / 32 or more and 9λ / 32 or less. The same applies to other λ / 4 transmission lines. Between terminal T11 and node N11, between terminal T12 and node N12, between terminal T13 and node N13, and between terminal T14 and node N14 are connected by transmission line 32. The signal S2 input to terminal T11 is split into signals S4 and S5 and output from terminals T13 and T14 respectively. The phase of the signal S5 at the center frequency fo is delayed by approximately 90° compared to the phase of the signal S4 at the center frequency fo. Terminal T12 is connected to the reference potential via resistor R1. The resistance value of resistor R1 is, for example, the reference impedance (e.g., 50 Ω).

[0066] As the distributor 16, it can be a Wilkinson type distributor, a distributor using λ / 4 transmission lines, a lumped multiplier type branch line coupler using inductors and capacitors, a distributed coupling type coupler formed by electromagnetic coupling of two transmission lines, or a closely wound coil coupler formed by electromagnetic coupling of two inductors.

[0067] [Synthesizer 18]

[0068] Figure 3 is a circuit diagram showing an example of the synthesizer 18 of Embodiment 1. As Figure 3 shown, the synthesizer 18 is a distributed constant type branch line coupler. Transmission lines TL21 (first transmission line), TL22 (second transmission line), TL23 (third transmission line), and TL24 (fourth transmission line) are respectively connected between node N21 and N22, between node N21 and N23, between node N23 and N24, and between node N22 and N24. Transmission lines TL21 to TL24 are λ / 4 transmission lines. Between terminal T21 and node N21, between terminal T22 and node N22, between terminal T23 and node N23, and between terminal T24 and node N24 are connected by transmission line 32. The signal S6 input to terminal T21, the signal S7 input to terminal T22, and the signal S3 input to terminal T23 are synthesized, and the synthesized signal is output as the output signal So from terminal T24.

[0069] Figure 4This is a top view of the branch-line coupler of Embodiment 1. As Figure 4 shown, the transmission lines TL21 to TL24 and the transmission line 32 are formed by a conductor pattern 31 provided on a dielectric substrate 30. A metal layer supplied with a reference potential is provided on the lower surface of the dielectric substrate 30. The transmission lines TL21 to TL24 and the transmission line 32 are microstrip lines. The characteristic impedance of the transmission line 32 is a reference impedance Zo, for example, 50 Ω. The widths of the transmission lines TL21 and TL23 are width W1, the widths of the transmission lines TL22 and TL24 are width W2, and the width of the transmission line 32 is width W3.

[0070] In the case where the dielectric substrate 30 is a mounting substrate, the dielectric substrate 30 is, for example, a glass epoxy substrate or a ceramic substrate. In the case of monolithically integrating the distributor 16 and the combiner 18 with the control amplifier 10, the auxiliary amplifier 12a, and the auxiliary amplifier 12b, the dielectric substrate 30 is, for example, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or a silicon substrate. The conductor pattern 31 is, for example, a metal layer such as a gold layer, a copper layer, or an aluminum layer.

[0071] The matching circuits 20, 22a, 22b, and 24 are passive circuits including inductors and capacitors, for example, inductors connected in series, a π-type circuit of the CLC structure, a T-type circuit of the LCL structure, an L-type circuit of the LC structure, or a circuit combining these circuits.

[0072] The control amplifier 10 corresponds to the main amplifier of the Doherty amplifier circuit, and the auxiliary amplifiers 12a and 12b correspond to the peak amplifiers of the Doherty amplifier circuit. The control amplifier 10 operates in class AB or class B, and the auxiliary amplifiers 12a and 12b operate in class C. When the input power of the input signal Si is small, the control amplifier 10 mainly amplifies the input signal Si. When the input power increases, in addition to the control amplifier 10, the auxiliary amplifiers 12a and 12b also amplify the peak of the input signal Si. Thus, the control amplifier 10, the auxiliary amplifier 12a, and the auxiliary amplifier 12b amplify the input signal Si.

[0073] [Comparative Example 1]

[0074] As Comparative Example 1, a Doherty amplifier circuit will be described. Figure 5 This is a circuit diagram of the amplifier circuit of Comparative Example 1. As Figure 5As shown, in the amplifier circuit 110 of Comparative Example 1, a main amplifier 10a and a peak amplifier 12 are provided in parallel between the input terminal Tin and the output terminal Tout. The distributor 14 distributes the input signal Si into signals S1 and S2. The main amplifier 10a amplifies the signal S1 that has passed through the matching circuit 20, and outputs the amplified signal as signal S3 to the synthesizer 18a via the matching circuit 24. The peak amplifier 12 amplifies the signal S2 that has passed through the matching circuit 22, and outputs the amplified signal as signal S9 to the synthesizer 18a via the matching circuit 24a.

[0075] The synthesizer 18a includes λ / 4 transmission lines TL51 and TL52 as impedance transformers. The λ / 4 transmission lines TL51 and TL52 are used to modulate the impedance of the synthesizer 18a observed from the matching circuit 24 and the load impedance of the peak amplifier 12.

[0076] In Comparative Example 1, when the frequency changes, the electrical length of the λ / 4 transmission line deviates from λ / 4. Therefore, it is difficult to widen the operating frequency band. In one example, the relative bandwidth of the synthesizer using the λ / 4 transmission lines TL51 and TL52 is about 8%. In the LMBA as shown in Embodiment 1, a branch-line coupler is used to modulate the load impedance of the auxiliary amplifiers 12a and 12b. Therefore, the widening of the operating frequency band can be achieved. The relative bandwidth of the branch-line coupler is, for example, up to 120% in a commercially available hybrid coupler. Thus, in the LMBA, the synthesizer 18 can be widened.

[0077] [Comparative Example 2]

[0078] As Comparative Example 2, an LMBA with a synthesis ratio of 1:1 for the synthesizer 18 will be described. Figure 6 and Figure 7 is a circuit diagram showing a part of the amplifier circuit 112 of Comparative Example 2. In Figure 6 and Figure 7 , the circuits after the control amplifier 10 and the balanced amplifier 11 are shown. In Comparative Example 2, in Figure 7 , the synthesis ratio of the powers of the signals S6 and S7 synthesized by the synthesizer 18 is 1:1.

[0079] Use Figure 6, when the power of the input signal Si is small and the auxiliary amplifiers 12a and 12b are not operating, the signal S3 input to the synthesizer 18 from terminal T23 is split into two signals S3a and S3b at terminals T21 and T22. The amplitude ratio of the powers of the signals S3a and S3b is 1:1. The phase of the signal S3b at terminal T22 is delayed by 90° compared to the phase of the signal S3a at terminal T21. The signals S3a and S3b are reflected at terminals T21 and T22 respectively. The reflected signals S3a and S3b are combined at terminal T24. The phase of the signal S3a reflected at terminal T21 is delayed by 90° compared to the phase of the signal S3b reflected at terminal T22. Thus, at terminal T24, the phases of the signals S3a and S3b are aligned and the signal S3 is combined. The combined signal S3 is output as the output signal So to the output terminal Tout.

[0080] At this time, the reflection coefficients of the synthesizer 18 as observed from the auxiliary amplifiers 12a and 12b (i.e., the absolute values of the impedances Z3a and Z3b) are greater than 1, and the impedances Z3a and Z3b as the loads of the auxiliary amplifiers 12a and 12b are substantially high. On the other hand, the impedance Z1 of terminal T23 as observed from the matching circuit 24 is the reference impedance (e.g., 50 Ω) of the input impedance of terminal T23.

[0081] Next, use Figure 7 , when the power of the input signal Si is large and the auxiliary amplifiers 12a and 12b are operating, the signal S7 is delayed in phase by 90° compared to the signal S6. The phase of the signal S3b at terminal T22 is delayed by 90° compared to the phase of the signal S3a at terminal T21. Thus, by appropriately adjusting the phase difference between the signals S1 and S2, the phases of the signals S6 and S3a at terminal T21 are optimized (e.g., the phases of the signals S6 and S3a are aligned), and preferably the phases of the signals S7 and S3b at terminal T22 (e.g., the phases of the signals S7 and S3b are aligned). At terminal T24, the signals S6 + S3a combined at terminal T21 and the signals S7 + S3b combined at terminal T22 are combined. The combined signal S3 + S6 + S7 is output as the output signal So to the output terminal Tout.

[0082] At this time, the signals incident on terminals T21 and T22 from auxiliary amplifiers 12a and 12b are substantially S6 + S3a and S7 + S3b respectively, and the signals reflected at terminals T21 and T22 are substantially S3a and S3b respectively. Therefore, the reflection coefficients (i.e., the absolute values of impedances Z3a and Z3b) of terminals T21 and T22 observed from auxiliary amplifiers 12a and 12b are less than 1, and the larger the amplitudes of the powers of signals S6 and S7, the smaller this reflection coefficient. The larger the amplitudes of the powers of signals S6 and S7, the lower the impedances Z3a and Z3b, which are the loads of auxiliary amplifiers 12a and 12b, substantially become. Thus, synthesizer 18 modulates the impedances Z3a and Z3b, which are the loads of synthesizer 18 observed from auxiliary amplifiers 12a and 12b, depending on the amplitudes of signals S6 and S7. On the other hand, regardless of the magnitudes of the amplitudes of signals S6 and S7, the impedance Z1 of terminal T23 observed from matching circuit 24 is the reference impedance (e.g., 50 Ω).

[0083] When the power of output signal So is the maximum value within the operating range of the amplifier circuit, the output power of output signal So is set as the saturation power Psat. At saturation power Psat, in Comparative Example 1, the output powers of main amplifier 10a and peak amplifier 12 are saturated, and in Comparative Example 2, the output powers of control amplifier 10, auxiliary amplifier 12a, and auxiliary amplifier 12b are saturated. It should be noted that here the output power saturation includes a state lower within a range of 1 dB or 2 dB or less from the complete saturation state. When the power of output signal So is the minimum value within the operating range of the amplifier circuit, it is set as the back-off power Pbo. At back-off power Pbo, in Comparative Example 1, saturation starts in main amplifier 10a, and in Comparative Example 2, the output power of control amplifier 10 is saturated.

[0084] Since a high-power signal is not applied to splitter 16, a splitter that can be miniaturized even with low high-frequency characteristics can also be used. However, a high-power signal is applied to synthesizer 18. Therefore, a coupler with high high-frequency characteristics is required for synthesizer 18. As a coupler with high high-frequency characteristics, use is made of Figure 3 and Figure 4 the shown distributed-constant type branch-line coupler. However, since the distributed-constant type branch-line coupler uses four λ / 4 transmission lines, the distributed-constant type branch-line coupler becomes large-sized. Refer to Figure 4, such as transmission lines TL22 and TL24, if the width W2 is large, the area occupied by transmission lines TL22 and TL24 is large. When the synthesis ratio of the power of the synthesized signals S6 and S7 by synthesizer 18 is set to 1:1, the characteristic impedance Zc1 at the center frequency fo of transmission lines TL21 and TL23 is the reference impedance Zo. The characteristic impedance Zc2 at the center frequency fo of transmission lines TL22 and TL24 is Zc1 / √2. Therefore, if the dielectric constant and thickness of the dielectric substrate 30 of Figure 4 are determined, the widths W1 and W2 of transmission lines TL21 to TL24 are determined. Thus, in Comparative Examples 1 and 2, synthesizer 18 is enlarged, and it is difficult to miniaturize amplifier circuit 112.

[0085] [Comparative Example 3]

[0086] As Comparative Example 3, an LMBA with a synthesis ratio of synthesizer 18 not being 1:1 will be described. Instead of the synthesis ratio of synthesizer 18, the distribution ratio of the power of signal S6 input to terminal T21 to terminals T24 and T23 is used as an index. Let the signal output to terminal T23 be signal S6a, and the signal output to terminal T24 be signal S6b. Let the amplitudes of the powers of signals S6, S6a, and S6b be A6, A6a, and A6b, respectively. The ratio of amplitude A6a to amplitude A6b is A6b:A6a, and when expressed in dB, it is A6a - A6b [dB]. Let Figure 3 and Figure 4 the characteristic impedances of transmission line TL21 and transmission line TL23 in be Zcl, and the characteristic impedances of transmission line TL22 and transmission line TL24 be Zc2.

[0087] Table 1 is a diagram showing the characteristic impedances Zc1 and Zc2 for achieving the ratio A6a - A6b [dB].

[0088] [Table 1]

[0089]

[0090] In Table 1, the reference impedance Zo is set to 50 Ω. The reference impedance Zp corresponds to the impedance when observing terminals T21, T22, T23, and T24 from the outside. As shown in Table 1, when amplitudes A6a and A6b are equal, that is, when signal S6 etc. is distributed into S6a and S6b, the characteristic impedance Zc1 is 50 Ω, the reference impedance Zo, and the characteristic impedance Zc2 is 35.35 Ω as .

[0091] When making A6a - A6b smaller than A6a - A6b = 0 dB, the characteristic impedance Zc1 is made lower than the reference impedance Z p , and the characteristic impedance Zc2 is made higher than In this case, the characteristic impedances Zc1 and Zc2 are respectively lower than Zc1 and Zc2 when A6a - A6b = 0 dB. Thus, the Figure 4 widths W1 and W2 in are respectively greater than the widths W1 and W2 when A6a - A6b = 0 dB. Thus, the synthesizer 18 is enlarged.

[0092] When making A6a - A6b greater than that when A6a - A6b = 0 dB, the characteristic impedance Zc1 is made higher than the reference impedance Zo, and the characteristic impedance Zc2 is made lower than In this case, the characteristic impedances Zc1 and Zc2 are respectively higher than Zc1 and Zc2 when A6a - A6b = 0 dB. Thus, the Figure 4 widths W1 and W2 in are thinner than the widths W1 and W2 when A6a - A6b = 0 dB. Thus, the synthesizer 18 can be miniaturized.

[0093] From the viewpoint of miniaturizing the synthesizer 18, the characteristic impedance Zc1 is made higher than the reference impedance Zo, and the characteristic impedance Zc2 is made lower than The characteristic impedance Zc1 can be set to 1.01 times or more, 1.2 times or more, 1.4 times or more, or 1.7 times or more of the reference impedance Zo. The characteristic impedance Zc2 can be set to 0.99 times or less, 0.85 times or less, 0.7 times or less, or 0.6 times or less of. From the viewpoint of not making A6a - A6b too large, the characteristic impedance Zc1 can be set to 3 times or less of the reference impedance Zo, and the characteristic impedance Zc2 can be set to 0.5 times or more of.

[0094] The width W1 can be set to 0.99 times or less, 0.7 times or less, or 0.5 times or less of the width W3. The width W1 can be set to 0.2 times or more of the width W3. The width W2 can be set to 1.01 times or more or 1.2 times or more of the width W1, and the width W2 can be set to 1.5 times or less of the width W1.

[0095] Figure 8 is a schematic diagram for explaining the operation of the synthesizers in Comparative Example 3 and Example 1. The characteristic impedance of the transmission line 32 is the reference impedance Zo, for example, 50 Ω. The width W3 of the transmission line 32 is determined in such a way that the characteristic impedance of the transmission line 32 is the reference impedance Zo. As shown in Table 1, the characteristic impedances Zc1 of the transmission lines TL21 and TL23 are greater than the reference impedance Zo. Therefore, the widths W1 of the transmission lines TL21 and TL23 are smaller than the width W3 of the transmission line 32. The characteristic impedances Zc2 of the transmission lines TL22 and TL24 are smaller than the reference impedance Zo. Therefore, the widths W2 of the transmission lines TL22 and TL24 are greater than the width W3 of the transmission line 32.

[0096] The amplitude of the signal S6 input to terminal T21 is A6, and the phase is 0°. The amplitude of the signal S7 input to terminal T22 is A7, and the phase is -90°. The signals S6 and S7 are represented as (A6, 0°) and (A7, -90°) respectively. The signal S6 is distributed, and the signals input to terminals T23 and T24 are the signal S6a and S6b respectively. The ratio of the amplitudes of the signals S6b and S6a is set to 1:N (N>1). At this time, the signals S6a and S6b are ((N / (1 + N))×A6, -90°) and ((1 / (1 + N))×A6, -180°) respectively. The signals S7a and S7b are ((1 / (1 + N))×A7, -270°) and ((N / (1 + N))×A7, -180°) respectively.

[0097] At terminal T24, the signals S6b and S7b are in the same phase, and the signal S6a with an amplitude of (1 / (1 + N))×A6 and the signal S7b with an amplitude of (N / (1 + N))×A7 are synthesized.

[0098] At terminal T23, the signals S6a and S7a are in opposite phases. When N = 1, the amplitudes of the signals S6a and S7a are (1 / 2)×A6 and (1 / 2)×A7 respectively. Since the amplitudes A6 and A7 are approximately the same, the signals S6a and S7a are compensated. Thus, no signal is output from terminal T23. Therefore, regardless of the amplitudes of the signals S6 and S7, the impedance Z1 of terminal T23 observed from the matching circuit 24 is fixed and is the reference impedance Zo.

[0099] Using Comparative Example 3, the case when N>1 is described. Figure 9 It is a circuit diagram showing the balanced amplifier in Comparative Example 3. As Figure 9 shown, in Comparative Example 3, as described in Figure 6 the ratio of the amplitudes of the signals S6b and S6a at the synthesizer 18 is A6b:A6a = 1:N (N>1). The ratio of the amplitude of the signal S5 and the amplitude of the signal S4 at the distributor 16 is 1:1. Therefore, the signal S4 output to terminal T13 is (A4, 0°). The signal S5 output from terminal T14 is (A4, -90°). The amplitudes of the signals S4 and S5 are approximately the same, which is A4. The physical sizes of the auxiliary amplifiers 12a and 12b are the same as each other, and the saturation powers are also the same as each other. The input bias voltages supplied to the auxiliary amplifiers 12a and 12b are the same as each other, and the output bias voltages are also the same as each other. Thus, the amplitudes of the signals S6 and S7 are approximately the same, which is A6. Thus, the signal S6 input to terminal T21 is (A6, 0°), and the signal S7 input to terminal T22 is (A6, -90°).

[0100] The signal S6a output from terminal T23 is ((N / (1 + N)) × A6, -90°), and the signal S7a is ((1 / (1 + N)) × A6, -270°). The signals S6a and S7a are in opposite phases. Therefore, the signal S6a + S7a is ((N - 1) / (1 + N) × A6, -90°). When N > 1, the signals S6a and S7a are not compensated. As a result, the impedance Z1, which is the load of the control amplifier 10, changes. For example, when the output power Pout is the back-off power Pbo, the impedance Z1 is the reference impedance Zo. When the output power Pout is the saturation power Psat, due to the influence of the signal S6a + S7a output from the terminal T23 of the synthesizer 18, the impedance Z1 changes from the reference impedance Zo.

[0101] [Example 1 of Embodiment 1]

[0102] Figure 10 is a circuit diagram showing the balanced amplifier in Example 1 of Embodiment 1. As Figure 10 shown, the signal distribution ratio of the distributor 16 is 1:1. The physical size of the auxiliary amplifier 12b is approximately N times the physical size of the auxiliary amplifier 12a. For example, when the auxiliary amplifiers 12a and 12b are FETs, the gate width of the auxiliary amplifier 12b is approximately N times the gate width of the auxiliary amplifier 12a. The saturation power of the auxiliary amplifier 12b is approximately N times the saturation power of the auxiliary amplifier 12a.

[0103] The amplitudes of the signals S4 and S5 distributed by the distributor 16 are substantially the same, which is A4. When both the auxiliary amplifiers 12a and 12b are used at the saturation power, the amplitude A7 of the signal S7 is N times the amplitude A6 of the signal S6. Thus, the signal S6 input to the terminal T21 is (A6, 0°), and the signal S7 input to the terminal T22 is (N × A6, -90°).

[0104] The signal S6a output from the terminal T23 is ((N / (1 + N)) × A6, -90°), and the signal S7a is ((1 / (1 + N)) × N × A6, -270°). The amplitudes of both the signals S6a and S7a are (N / (1 + N) × A6), and the signals S6a and S7a are in opposite phases. Therefore, the amplitude of S6a + S7a is substantially 0. Thus, when the output power Pout is the back-off power Pbo and when the output power Pout is the saturation power Psat, the impedance Z1 is the reference impedance Zo.

[0105] [Example 2 of Embodiment 1]

[0106] Figure 11 is a circuit diagram showing the balanced amplifier in Example 2 of Embodiment 1. As Figure 11As shown, the distribution ratio of the signal of the distributor 16 is N:1. The physical sizes of the auxiliary amplifiers 12a and 12b are substantially the same as each other. The saturation powers of the auxiliary amplifiers 12a and 12b are substantially the same as each other. In the case where the distributor 16 is a branch-line coupler, the characteristic impedances of the transmission lines TL11 to TL14 are set as in Table 1 to make the distribution ratio of the distributor 16 N:1. In the case where other couplers are used in the distributor 16, a known method can also be used to change the distribution ratio.

[0107] The amplitude of the signal S5 distributed by the distributor 16 is approximately N times the amplitude of the signal S4. Thus, the signal S4 is (A4, 0°), and the signal S5 is (N×A4, -90°). If the auxiliary amplifiers 12a and 12b do not reach the saturation power and the power gains are substantially the same, the amplitude A7 of the signal S7 is N times the amplitude of the signal S6. Thus, the signal S6 is (A6, 0°), and the signal S7 is (N×A6, -90°).

[0108] Thus, similar to Example 1, the signal S6a output from the terminal T23 is ((N / (1 + N))×A6, -90°), and the signal S7a is ((1 / (1 + N))×N×A6, -270°). The amplitude of S6a + S7a is substantially 0. Therefore, even if the magnitudes of the signals S6 and S7 change, the change in the impedance Z1 is suppressed.

[0109] According to Example 1, the characteristic impedance Zc1 (first characteristic impedance) of the transmission lines TL21 and TL23 at the center frequency fo in the branch-line coupler is higher than the reference impedance Zo. The characteristic impedance Zc2 (second characteristic impedance) of the transmission lines TL22 and TL24 at the center frequency fo is lower than Zc1 / √2. Thus, as shown in Table 1, the synthesizer 18 can be miniaturized. However, as in Comparative Example 3, the impedance Z1 of the synthesizer 18 observed from the control amplifier 10 changes according to the changes in the signals S6 and S7. Therefore, the amplitude of the power of the signal S7 is made larger than the amplitude of the power of the signal S6. Thus, as in Example 1 and Example 2 of Example 1, the signal S6a + S7a output from the terminal T23 can be reduced. Thus, the variation of the impedance Z1 caused by the changes in the signals S6 and S7 can be suppressed.

[0110] The first ratio of the amplitude A7 of the power of signal S7 to the amplitude A6 of the power of signal S6 is A7 / A6. The amplitude A6a of the power of the signal S6a (eighth signal) assigned to terminal T23 from the signal S6 with the center frequency fo input to terminal T21 and the amplitude A6b of the power of the signal S6b (ninth signal) assigned to terminal T24 from the signal S6 with the center frequency fo input to terminal T21 have a second ratio of A6a / A6b. When the first ratio A7 / A6 and the second ratio A6a / A6b are expressed in dB, as in Example 1 and Example 2 of Embodiment 1, when both the first ratio and the second ratio are N, the difference between the first ratio A7 / A6 and the second ratio A6a / A6b is 0 dB. At this time, the signal S6a + S7a output from terminal T23 is approximately 0. From the viewpoint of suppressing the change in impedance Z1 according to the magnitudes of signals S6 and S7, the difference between the first ratio A7 / A6 and the second ratio A6a / A6b can be set to 1 dB or less, can be set to 0.5 dB or less, and can be set to 0.3 dB or less. It should be noted that the difference between A7 / A6 and A6a / A6b corresponds to |A7 / A6 - A6a / A6b|.

[0111] From the viewpoint of miniaturizing the synthesizer 18, the second ratio A6a / A6b can be set to 2 dB or more, can be set to 3 dB or more, and can be set to 4 dB or more. In addition, the characteristic impedance Zc1 can be set to 1.2 times or more of the reference impedance Zo, can be set to 1.4 times or more, and can be set to 1.6 times or more. The characteristic impedance Zc2 can be set to 0.9×Zc1 / √2 times or less, can be set to 0.8×Zc1 / √2 times or less, and can be set to 0.7×Zc1 / √2 times or less.

[0112] If the second ratio A6a / A6b is too large, the signal output from terminal T24 deteriorates. From this viewpoint, the second ratio A6a / A6b can be set to 10 dB or less. The characteristic impedance Zc1 can be set to 3 times or less of the reference impedance Zo. The characteristic impedance Zc2 can be set to 0.3×Zx1 / √2 or more.

[0113] If the characteristic impedances Zc1 and Zc2 are set as described above, the width W1 (first width) of the transmission lines TL21 and TL23 is smaller than the width W3 (second width) of the transmission line 32 (fifth transmission line) connected to terminals T21, T22, T23, and T24. In addition, the width W2 (third width) of the transmission lines TL22 and TL24 is greater than the width W1.

[0114] From the viewpoint of increasing the second ratio A6a / A6b, the width W1 can be set to 0.7 times or less of the width W3, and can be set to 0.5 times or less. The width W2 can be set to 2.1 times or more of the width W1, and can be set to 2.5 times or more. From the viewpoint of not making the second ratio A6a / A6b too large, the width W1 can be set to 0.2 times or more of the width W3, and the width W2 can be set to 10 times or less of the width W1.

[0115] As in Example 1, Example 1, from the viewpoint of increasing the first ratio A7 / A6, the saturation power of the auxiliary amplifier 12b is greater than the saturation power of the auxiliary amplifier 12a. The saturation power of the auxiliary amplifier 12b relative to the saturation power of the auxiliary amplifier 12a can be set to 1 dB or more, can be set to 2 dB or more, can be set to 3 dB or more. From the viewpoint of not making the first ratio A7 / A6 too large, the saturation power of the auxiliary amplifier 12b relative to the saturation power of the auxiliary amplifier 12a can be set to 10 dB or less.

[0116] Since the saturation power of the auxiliary amplifier 12b is greater than the saturation power of the auxiliary amplifier 12a, the physical size of the auxiliary amplifier 12b is larger than the physical size of the auxiliary amplifier 12a. For example, when the auxiliary amplifiers 12a and 12b are FETs, the gate width of the auxiliary amplifier 12b can be greater than the gate width of the auxiliary amplifier 12a, and can be set to 1.3 times or more, 1.6 times or more, or 2 times or more of the gate width of the auxiliary amplifier 12a. In addition, the gate width of the auxiliary amplifier 12b can be set to 10 times or less of the gate width of the auxiliary amplifier 12a.

[0117] As in Example 1, Example 2, from the viewpoint of increasing the first ratio A7 / A6, the amplitude A5 of the power of the signal S5 is greater than the amplitude A4 of the power of the signal S4. The ratio of the amplitude A5 of the power of the signal S5 to the amplitude A4 of the power of the signal S4 can be set to 1 dB or more, can be set to 2 dB or more, can be set to 3 dB or more. From the viewpoint of not making the first ratio A7 / A6 too large, the ratio of the amplitude A5 to the amplitude A4 can be set to 10 dB or less.

[0118] As a method of making the first ratio A7 / A6 greater than 1, in addition to Example 1 and Example 2 of Example 1, for example, there is also a method of combining Example 1 and Example 2. That is, it is also possible to make the saturation power of the auxiliary amplifier 12b greater than the saturation power of the auxiliary amplifier 12a, and make the amplitude A5 of the power of the signal S5 greater than the amplitude A4 of the power of the signal S4. In addition, it is also possible to make the first ratio A7 / A6 greater than 1 by appropriately setting the bias voltages of the auxiliary amplifiers 12a and 12b.

[0119] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. An amplifier circuit comprising: A first distributor distributes an input signal into a first signal and a second signal; controlling the amplifier to amplify the first signal and output the amplified signal as a third signal; a second distributor, distributing the second signal into a fourth signal and a fifth signal with different phases at a center frequency of an operating frequency band; a first auxiliary amplifier, amplifying the fourth signal and outputting the amplified signal as a sixth signal; a second auxiliary amplifier, amplifying the fifth signal and outputting the amplified signal as a seventh signal; and A branch line coupler, comprising: a first end for inputting the sixth signal; a second end for inputting the seventh signal; a third end for inputting the third signal; a fourth end for outputting an output signal; a first transmission line connecting the first end and the second end; and a second transmission line connecting the first end and the third end; a third transmission line connecting the third end and the fourth end; and a fourth transmission line connecting the second end and the fourth end, wherein a first characteristic impedance of the first transmission line and the third transmission line at the center frequency is higher than a reference impedance, and a second characteristic impedance of the second transmission line and the fourth transmission line at the center frequency is lower than the first characteristic impedance / √2, The amplitude of the power of the seventh signal is greater than the amplitude of the power of the sixth signal.

2. The amplifier circuit according to claim 1, wherein: The difference between the first ratio and the second ratio is less than 1 dB, wherein the first ratio is the ratio of the amplitude of the power of the seventh signal to the amplitude of the power of the sixth signal, and the second ratio is the ratio of the amplitude of the power of the eighth signal assigned to the third end by the sixth signal of the center frequency input to the first end to the amplitude of the power of the ninth signal assigned to the fourth end by the sixth signal of the center frequency input to the first end.

3. The amplifier circuit according to claim 2, wherein: The second ratio is greater than or equal to 2 dB.

4. The amplifier circuit according to any one of claims 1 to 3, wherein: The first characteristic impedance is greater than or equal to 1.2 times the reference impedance, and the second characteristic impedance is less than or equal to 0.9 / √2 times the first characteristic impedance.

5. The amplifier circuit according to any one of claims 1 to 3, wherein: The first width of the first transmission line and the third transmission line is smaller than the second width of the fifth transmission line connected to the first end, the second end, the third end and the fourth end, and the third width of the second transmission line and the fourth transmission line is larger than the first width.

6. The amplifier circuit according to any one of claims 1 to 3, wherein: The saturation power of the second auxiliary amplifier is greater than the saturation power of the first auxiliary amplifier.

7. The amplifier circuit according to any one of claims 1 to 3, wherein: A ratio of a saturation power of the second auxiliary amplifier to a saturation power of the first auxiliary amplifier is greater than 2 dB.

8. The amplifier circuit according to any one of claims 1 to 3, wherein: The physical size of the second auxiliary amplifier is greater than the physical size of the first auxiliary amplifier.

9. The amplifier circuit according to any one of claims 1 to 3, wherein: The amplitude of the power of the fifth signal is greater than the amplitude of the power of the fourth signal.

10. The amplifier circuit according to claim 9, wherein: A ratio of an amplitude of power of the fifth signal to an amplitude of power of the fourth signal is greater than or equal to 2 dB.

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