A bounded-wave electromagnetic pulse simulation device

Abstract

This application belongs to the field of power electronics technology, and specifically discloses a bounded wave electromagnetic pulse simulation device. The device includes a pulse power source, an overcurrent and overvoltage protection module, and a pulse waveform shaping module. Among them, the pulse power source is used to generate a high-voltage pulse signal; the overcurrent and overvoltage protection module is used to monitor the current and voltage of the high-voltage pulse signal in real time; the pulse waveform shaping module is used to shape the high-voltage pulse signal and output a bounded wave. This application can achieve the precise generation and strict constraint of high-voltage pulses, and generate bounded waves suitable for complex electromagnetic environments.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology, and particularly relates to a bounded wave electromagnetic pulse simulation device. Background Art

[0002] Traditional high-voltage pulse simulation devices (such as Marx circuits based on mechanical switches or ordinary MOSFETs) often have the following problems: 1. Uncontrollable waveform: Due to slow switch speed and large inter-stage timing errors (>10 ns), the pulse superposition is asynchronous, easily causing waveform distortions such as ringing and overshoot; 2. Poor anti-interference ability: High-voltage switch noise is coupled to the control circuit through the common ground loop, resulting in distortion of the voltage feedback signal and inability to achieve closed-loop dynamic compensation; 3. Insufficient reliability: Mechanical switches are prone to wear, and ordinary MOSFETs have limited withstand voltage (<1 kV), and are easily broken down due to inter-stage voltage imbalance or electromagnetic interference (EMI) during long-term use; 4. Lagging protection mechanism: Traditional overcurrent / overvoltage protection relies on software judgment, with a response delay, and it is difficult to handle high-voltage transient abnormalities.

[0003] The above defects severely limit the application of high-voltage pulse systems in high-precision scenarios. Summary of the Invention

[0004] Aiming at the deficiencies in the prior art, the purpose of this application is to provide a bounded wave electromagnetic pulse simulation device, which aims to achieve the precise generation and strict constraint of high-voltage pulses.

[0005] To achieve the above purpose, this application provides the following technical solutions:

[0006] A bounded wave electromagnetic pulse simulation device, the device includes: a pulse power source, an overcurrent and overvoltage protection module, and a pulse waveform shaping module, wherein, the pulse power source is used to generate a high-voltage pulse signal; the overcurrent and overvoltage protection module is used to monitor the current and voltage of the high-voltage pulse signal in real time; the pulse waveform shaping module is used to shape the high-voltage pulse signal and output a bounded wave.

[0007] Optionally, the pulse power source includes: a four-stage Marx unit, and the structure of each stage of the Marx unit is the same. The first stage of the Marx unit includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a first optically controlled SiC MOSFET switch, a first operational amplifier, a first charging diode, a first inductor, a first resonant capacitor, a first digital isolator, a first AND gate, and a first driving MOSFET. Among them, the gate of the first optically controlled SiC MOSFET switch is connected to the first pulse width adjustment pin of FPGA1 through the first digital isolator. The source of the first optically controlled SiC MOSFET switch is connected to the first ground terminal, and the drain of the first optically controlled SiC MOSFET switch is connected to the source of the second optically controlled SiC MOSFET switch; the first end of the first capacitor is connected to the connection point of the drain of the first optically controlled SiC MOSFET switch and the source of the second optically controlled SiC MOSFET switch, and the second end of the first capacitor is connected to the second ground terminal; the anode of the first charging diode is connected to the 1.2KV power supply, and the cathode of the first charging diode is connected to the first end of the first capacitor; the first end of the first resistor is connected to the first end of the first capacitor, and the second end of the first resistor is connected to the third ground terminal through the second resistor; the positive input terminal of the first operational amplifier is connected to the connection point of the first resistor and the second resistor, the inverting input terminal of the first operational amplifier is short-circuited to its output terminal, and the output terminal of the first operational amplifier is connected to the first ADC input pin of FPGA2; the first end of the second capacitor is connected to the output terminal of the first operational amplifier, and the second end of the second capacitor is connected to the fourth ground terminal; the drain of the first driving MOSFET is connected to the 1.2KV power supply, the source of the first driving MOSFET is connected to the fourteenth ground terminal through the first resonant capacitor and the first inductor, and the gate of the first driving MOSFET is connected to the fifth pulse width adjustment pin and the first trigger signal pin of FPGA1 through the first AND gate.

[0008] Optionally, the overcurrent and overvoltage protection module includes: a voltage detection unit, a current detection unit, an overcurrent and overvoltage comparison unit, a latching and reset unit, and an output control unit. Among them, the voltage detection unit is used to detect the voltage amplitude of the high-voltage pulse signal in real time; the current detection unit is used to detect the instantaneous value of the current of the high-voltage pulse signal in real time; the overcurrent and overvoltage comparison unit is used to compare the high-voltage pulse signal with a preset reference value and output an overvoltage or overcurrent logic trigger signal; the latching and reset unit is used to perform hardware-level locking on the overcurrent or overvoltage signal; the output control unit is used to convert the protection signal sent by the latching and reset unit into a physical action to forcibly turn off the main circuit or switch to a bypass path.

[0009] Optionally, the voltage detection unit includes: a tenth resistor, an eleventh resistor, a voltage follower, a twelfth resistor, and a tenth capacitor. Among them, the first end of the tenth resistor is connected to the 1.2 KV power supply, and the second end of the tenth resistor is connected to the nineteenth ground terminal through the eleventh resistor; the non-inverting input terminal of the voltage follower is connected to the connection point of the tenth resistor and the eleventh resistor, and the inverting input terminal of the voltage follower is short-circuited to its output terminal; the twelfth resistor and the tenth capacitor are connected in parallel between the output terminal of the voltage follower and the twentieth ground terminal, and the output terminal of the voltage follower is connected to the second input terminal of the overcurrent and overvoltage comparison unit.

[0010] Optionally, the current detection unit includes: a current sampling resistor, a differential amplifier, a ninth resistor, and a ninth capacitor. Among them, the first end of the current sampling resistor serves as the input terminal of the overcurrent and overvoltage protection module; the inverting input terminal of the differential amplifier is connected to the first end of the current sampling resistor, the output terminal of the differential amplifier is connected to the second end of the current sampling resistor, and the output terminal of the differential amplifier and the second end of the current sampling resistor are commonly connected to the first input terminal of the overcurrent and overvoltage comparison unit; the non-inverting input terminal of the differential amplifier is connected to the connection point of the tenth resistor and the eleventh resistor; the ninth resistor and the ninth capacitor are connected in parallel between the output terminal of the differential amplifier and the eighteenth ground terminal.

[0011] Optionally, the overcurrent and overvoltage comparison unit includes: an overcurrent comparator, an overvoltage comparator, a thirteenth resistor, and a fourteenth resistor. Among them, the inverting input terminal of the overcurrent comparator serves as the first input terminal of the overcurrent and overvoltage comparison unit, the non-inverting input terminal of the overcurrent comparator is connected to a first reference voltage, and the output terminal of the overcurrent comparator is connected to the 5V power supply through the thirteenth resistor; the inverting input terminal of the overvoltage comparator serves as the second input terminal of the overcurrent and overvoltage comparison unit, the non-inverting input terminal of the overvoltage comparator is connected to a second reference voltage, and the output terminal of the overvoltage comparator is connected to the 12V power supply through the fourteenth resistor.

[0012] Optionally, the latching and reset unit includes: a D flip-flop, a first OR gate, and a fifth charging diode. Among them, the first input pin of the first OR gate is connected to the output terminal of the overcurrent comparator, the second input pin of the first OR gate is connected to the output terminal of the overvoltage comparator, and the output pin of the first OR gate is connected to the D pin of the D flip-flop; the anode of the fifth charging diode is connected to the Q pin of the D flip-flop, and the cathode of the fifth charging diode is connected to the input terminal of the output control unit.

[0013] Optionally, the output control unit includes: a triode, a light-emitting diode, and a fifteenth resistor. The base of the triode serves as the input end of the output control unit. The emitter of the triode is connected to the anode of the fifth charging diode. The collector of the triode BJT1 is connected to the cathode of the light-emitting diode. The anode of the light-emitting diode is connected to the emitter of the triode through the fifteenth resistor. The connection between the collector of the triode and the cathode of the light-emitting diode serves as the output end of the output control unit.

[0014] Optionally, the pulse waveform shaping module includes: an input matching network, an adjustable RC shaping unit, a dynamic amplitude limiting unit, and an output driving and isolation unit. The input matching network is used to perform impedance matching on the high-voltage pulse signal and isolate the interference of the previous-stage circuit. The adjustable RC shaping unit is used to optimize the waveform edge characteristics of the high-voltage pulse signal after impedance matching. The dynamic amplitude limiting unit is used to dynamically adjust the pulse amplitude of the optimized high-voltage pulse signal. The output driving and isolation unit is used to isolate and enhance the driving of the high-voltage pulse signal after the pulse amplitude is dynamically adjusted, and output a bounded wave.

[0015] Optionally, the input matching network includes: a transformer, an eleventh capacitor, and a sixteenth resistor. The primary side of the transformer is connected to the output end of the output control unit. The eleventh capacitor and the sixteenth resistor are connected in parallel. The first ends of the eleventh capacitor and the sixteenth resistor are connected to the secondary side of the transformer. The second ends of the eleventh capacitor and the sixteenth resistor are connected to the input end of the adjustable RC shaping unit.

[0016] The present application can bring the following beneficial effects:

[0017] By organically integrating the pulse power source, the overcurrent and overvoltage protection module, and the pulse waveform shaping module, and cooperating with the high-speed optically controlled SiC device, the FPGA precision control, and the LLC resonant topology, the present application can comprehensively constrain the high-voltage pulse signal in terms of amplitude, time parameters, and waveform integrity. Compared with the traditional solution, the present system has significant advantages such as stable waveform, controllable amplitude, no overshoot and ringing, fast response speed, and strong anti-electromagnetic interference ability. It can stably output a high-precision pulse signal that meets the definition of "bounded wave", and is particularly suitable for complex electromagnetic environments that require high reliability and high consistency. Description of the Drawings

[0018] Figure 1 is a schematic structural diagram of a bounded-wave electromagnetic pulse simulation device provided by an embodiment of the present application;

[0019] Figure 2 is a schematic circuit diagram of a pulse power source provided by another embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of the circuit structure of the overcurrent and overvoltage protection module provided by another embodiment of the present application;

[0021] Figure 4 It is a schematic diagram of the circuit structure of the pulse waveform shaping module provided by another embodiment of the present application;

[0022] Figure 5 It is a schematic diagram of the waveform generated by a traditional high-voltage pulse simulation device;

[0023] Figure 6 It is a schematic diagram of the waveform of the bounded wave generated based on the device described in the present application. Detailed implementation manners

[0024] Hereinafter, specific embodiments of the present application will be described in detail with reference to the accompanying drawings. Although specific embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0025] It should be noted that in the description of the specification and claims, certain terms are used to refer to specific components. Those skilled in the art should understand that technicians may use different terms to refer to the same component. The specification and claims of the present application do not use the difference in terms as a way to distinguish components, but use the difference in the functions of components as the criterion for distinction. For example, the terms "comprising" or "including" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to". The subsequent description of the specification is for the purpose of implementing the preferred embodiments of the present application, but the description is based on the general principles of the specification and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the scope defined by the appended claims.

[0026] For the convenience of understanding the embodiments of the present application, hereinafter, specific embodiments will be taken as examples to make further explanatory descriptions in combination with the accompanying drawings, and each accompanying drawing does not constitute a limitation on the embodiments of the present application.

[0027] Figure 1 It is a schematic diagram of the structure of a bounded wave electromagnetic pulse simulation device provided by an embodiment of the present application. As Figure 1 shown, the device includes: a pulse power source, an overcurrent and overvoltage protection module, and a pulse waveform shaping module. Among them, the pulse power source is used to generate a high-voltage pulse signal; the overcurrent and overvoltage protection module is used to monitor the current and voltage of the high-voltage pulse signal in real time; the pulse waveform shaping module is used to shape the high-voltage pulse signal and output a bounded wave.

[0028] In this embodiment, a bounded wave refers to a pulse signal that is strictly limited in terms of amplitude, time parameters, and waveform characteristics. Its core features include: Bounded amplitude: The voltage or current amplitude of the pulse is always controlled within a preset safe or functional range to avoid equipment damage or signal distortion caused by overvoltage or overcurrent. Bounded time parameters: Key time parameters such as pulse width, rise time, and fall time meet the design requirements and are highly repeatable. Waveform integrity: The pulse shape (such as rectangular wave, trapezoidal wave) remains stable during transmission or generation, without obvious ringing, overshoot, or oscillation.

[0029] By organically integrating a pulse power source, an overcurrent and overvoltage protection module, and a pulse waveform shaping module, this application can achieve strict constraints on the amplitude, time parameters, and waveform integrity of high-voltage pulses, and finally generate a highly stable pulse signal that meets the definition of a bounded wave.

[0030] In another exemplary embodiment, as Figure 2 shown, the pulse power source includes: a four-stage Marx unit. Among them, the first-stage Marx unit includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first optically controlled SiCMOSFET switch Q1, a first operational amplifier U1, a first charging diode d1, a first inductor L1, a first resonant capacitor C_LLC1, a first digital isolator T1, a first AND gate &1, and a first driving MOSFET Q_LLC1; the second-stage Marx unit includes a third capacitor C3, a fourth capacitor C4, a third resistor R3, a fourth resistor R4, a second optically controlled SiC MOSFET switch Q2, a second charging diode d2, a second operational amplifier U2, a second inductor L2, a second resonant capacitor C_LLC2, a second digital isolator T2, a second AND gate &2, and a second driving MOSFET Q_LLC2; the third-stage Marx unit includes a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, a sixth resistor R6, a third optically controlled SiC MOSFET switch Q3, a third charging diode d3, a third operational amplifier U3, a third inductor L3, a third resonant capacitor C_LLC3, a third digital isolator T3, a third AND gate &3, and a third driving MOSFET Q_LLC3; the fourth-stage Marx unit includes a seventh capacitor C4, an eighth capacitor C8, a seventh resistor R7, an eighth resistor R8, a fourth optically controlled SiCMOSFET switch Q4, a fourth charging diode d4, a fourth inductor L4, a fourth resonant capacitor C_LLC4, a fourth digital isolator T4, a fourth AND gate &4, and a fourth driving MOSFET Q_LLC4.

[0031] Among them, the gate of the first light-controlled SiC MOSFET switch Q1 is connected to the first pulse width adjustment pin PWM1 of FPGA1 through the first digital isolator T1 (such as the Si86xx series). The source of the first light-controlled SiC MOSFET switch Q1 is connected to the first ground terminal GND1. The drain of the first light-controlled SiC MOSFET switch Q1 is connected to the source of the second light-controlled SiC MOSFET switch Q2. The first end of the first capacitor C1 is connected to the connection point between the drain of the first light-controlled SiC MOSFET switch Q1 and the source of the second light-controlled SiC MOSFET switch Q2. The second end of the first capacitor C1 is connected to the second ground terminal GND2. The anode of the first charging diode d1 is connected to the 1.2KV power supply. The cathode of the first charging diode d1 is connected to the first end of the first capacitor C1. The first end of the first resistor R1 is connected to the first end of the first capacitor C1. The second end of the first resistor R1 is connected to the third ground terminal GND3 through the second resistor R2. The non-inverting input terminal of the first operational amplifier U1 is connected to the connection point between the first resistor R1 and the second resistor R2. The inverting input terminal of the first operational amplifier U1 is short-circuited to its output terminal. And the output terminal of the first operational amplifier U1 is connected to the first ADC input pin ADC1 of FPGA2. The first end of the second capacitor C2 is connected to the output terminal of the first operational amplifier U1. The second end of the second capacitor C2 is connected to the fourth ground terminal GND4. The drain of the first driving MOSFET Q_LLC1 is connected to the 1.2KV power supply. The source of the first driving MOSFET Q_LLC1 is connected to the fourteenth ground terminal GND14 through the first resonant capacitor C_LLC1 and the first inductor L1. The gate of the first driving MOSFET Q_LLC1 is connected to the fifth pulse width adjustment pin PWM5 and the first trigger signal pin TRIG1 of FPGA1 through the first AND gate &1.

[0032] The gate of the second light-controlled SiC MOSFET switch Q2 is connected to the second pulse width adjustment pin PWM2 of the FPGA1 through the second digital isolator T2. The drain of the second light-controlled SiC MOSFET switch Q2 is connected to the source of the third light-controlled SiC MOSFET switch Q3. The first end of the third capacitor C3 is connected to the connection point between the drain of the second light-controlled SiC MOSFET switch Q2 and the source of the third light-controlled SiC MOSFET switch Q3. The second end of the third capacitor C3 is connected to the fifth ground terminal GND5. The anode of the second charging diode d2 is connected to the 1.2 KV power supply, and the cathode of the second charging diode d2 is connected to the first end of the third capacitor C3. The first end of the third resistor R3 is connected to the first end of the third capacitor C3. The second end of the third resistor R3 is connected to the sixth ground terminal GND6 through the fourth resistor R4. The non-inverting input terminal of the second operational amplifier U2 is connected to the connection point between the third resistor R3 and the fourth resistor R4. The inverting input terminal of the second operational amplifier U2 is short-circuited to its output terminal, and the output terminal of the second operational amplifier U2 is connected to the second ADC input pin ADC2 of the FPGA2. The first end of the fourth capacitor C4 is connected to the output terminal of the second operational amplifier U2, and the second end of the fourth capacitor C4 is connected to the seventh ground terminal GND7. The drain of the second driving MOSFET Q_LLC2 is connected to the 1.2 KV power supply. The source of the second driving MOSFET Q_LLC2 is connected to the fifteenth ground terminal through the second resonant capacitor C_LLC2 and the second inductor L2. The gate of the second driving MOSFET Q_LLC2 is connected to the sixth pulse width adjustment pin PWM6 and the second trigger signal pin TRIG2 of the FPGA1 through the second AND gate &2.

[0033] The gate of the third optically controlled SiC MOSFET switch Q3 is connected to the third pulse width adjustment pin PWM3 of the FPGA1 through the third digital isolator T3. The drain of the third optically controlled SiC MOSFET switch Q3 is connected to the source of the fourth optically controlled SiC MOSFET switch Q4. The first end of the fifth capacitor C5 is connected to the connection point between the drain of the third optically controlled SiC MOSFET switch Q3 and the source of the fourth optically controlled SiC MOSFET switch Q4. The second end of the fifth capacitor C5 is connected to the eighth ground terminal GND8. The anode of the third charging diode d3 is connected to the 1.2 KV power supply, and the cathode of the third charging diode d3 is connected to the first end of the fifth capacitor C5. The first end of the fifth resistor R5 is connected to the first end of the fifth capacitor C5. The second end of the fifth resistor R5 is connected to the ninth ground terminal GND9 through the sixth resistor R6. The non-inverting input terminal of the third operational amplifier U3 is connected to the connection point between the fifth resistor R5 and the sixth resistor R6. The inverting input terminal of the third operational amplifier U3 is shorted to its output terminal, and the output terminal of the third operational amplifier U3 is connected to the third ADC input pin ADC3 of the FPGA2. The first end of the sixth capacitor C6 is connected to the output terminal of the third operational amplifier U3, and the second end of the sixth capacitor C6 is connected to the tenth ground terminal GND10. The drain of the third driving MOSFET Q_LLC3 is connected to the 1.2 KV power supply. The source of the third driving MOSFET Q_LLC3 is connected to the sixteenth ground terminal GND16 through the third resonant capacitor C_LLC3 and the third inductor L3. The gate of the third driving MOSFET Q_LLC3 is connected to the seventh pulse width adjustment pin PWM7 and the third trigger signal pin TRIG3 of the FPGA1 through the third AND gate &3.

[0034] The gate of the fourth optically controlled SiC MOSFET switch Q4 is connected to the fourth pulse width adjustment pin PWM4 of FPGA1 through the fourth digital isolator T4. The drain of the fourth optically controlled SiC MOSFET switch Q4 is used as the output terminal of the pulse power source and is connected to the input terminal of the overcurrent and overvoltage protection module. The first end of the seventh capacitor C7 is connected to the drain of the fourth optically controlled SiC MOSFET switch Q4, and the second end of the seventh capacitor C7 is connected to the eleventh ground terminal GND11; the anode of the fourth charging diode d4 is connected to the 1.2KV power supply, and the cathode of the fourth charging diode d4 is connected to the first end of the seventh capacitor C7; the first end of the seventh resistor R7 is connected to the first end of the seventh capacitor C7, and the second end of the seventh resistor R7 is connected to the twelfth ground terminal GND12 through the eighth resistor R8. The non-inverting input terminal of the fourth operational amplifier U4 is connected to the connection point of the seventh resistor R7 and the eighth resistor R8. The inverting input terminal of the fourth operational amplifier U4 is short-circuited to its output terminal, and the output terminal of the fourth operational amplifier U4 is connected to the fourth ADC input pin ADC4 of FPGA2; the first end of the eighth capacitor C8 is connected to the output terminal of the fourth operational amplifier U4, and the second end of the eighth capacitor C8 is connected to the thirteenth ground terminal GND13; the drain of the fourth driving MOSFET Q_LLC4 is connected to the 1.2KV power supply. The source of the fourth driving MOSFET Q_LLC4 is connected to the seventeenth ground terminal GND17 through the fourth resonant capacitor C_LLC4 and the fourth inductor L4. The gate of the fourth driving MOSFET Q_LLC4 is connected to the eighth pulse width adjustment pin PWM8 and the fourth trigger signal pin TRIG4 of FPGA1 through the fourth AND gate &4.

[0035] In this embodiment, during the charging stage, the 1.2kV power supply charges the capacitors (C1 to C8) of each stage Marx unit in parallel through each stage charging diode (d1 to d4). At the same time, each stage charging diode can prevent the reverse current during the discharging stage.

[0036] During the discharging stage, FPGA1 sends synchronous trigger signals through the PWM pins (PWM1 to PWM4) to turn on each optically controlled SiC MOSFET switch (Q1 to Q4) in each stage Marx unit one by one. When each stage optically controlled SiC MOSFET switch is turned on, the voltage of the corresponding capacitor is serially superimposed through the switch to the next stage, and finally a high-voltage pulse signal is formed at the output terminal (the drain of Q4) (for example, multiplying the 1.2kV input voltage to 4.8kV).

[0037] The described Marx cell includes a resonant circuit (L1 to L4, C_LLC1 to C_LLC4) and driving MOSFETs (Q_LLC1 to Q_LLC4). By using the PWM signals (PWM5 to PWM8) and trigger signals (TRIG1 to TRIG4) of FPGA1 to control the resonant frequency, it can precisely adjust the rise and fall times of the high-voltage pulse signal and waveform characteristics (such as the steepness of the rising edge and pulse width), thus meeting different application requirements.

[0038] In the pulse power source designed in this application, by using an optically controlled SiC MOSFET switch to replace the traditional mechanical switch or ordinary MOSFET and combining with a digital isolator, complete electrical isolation between the high-voltage side and the low-voltage control circuit can be achieved. Among them, the combination of the high breakdown voltage (>1.2 kV), high-frequency characteristics of the SiC material and the non-contact characteristics of optically controlled driving can significantly improve the switching speed (nanosecond level) and lifespan, and avoid spark discharge and electromagnetic interference (EMI).

[0039] In addition, the PWM pins of FPGA1 cooperate with the trigger signals to ensure that the conduction timings of each stage of switches are strictly aligned (error < 1 ns), thus avoiding energy loss caused by voltage asynchronization between stages.

[0040] Furthermore, each stage of the Marx cell is internally equipped with a resonant circuit (L1 to L4, C_LLC1 to C_LLC4) and driving MOSFETs (Q_LLC1 to Q_LLC4), thus forming an LLC resonant topology. FPGA1 controls the resonant frequency through PWM signals (PWM5 to PWM8) and realizes soft switching in combination with AND gate logic (&1 to &4), thereby optimizing the rising and falling edges of the high-voltage pulse signal.

[0041] Furthermore, in each stage of the Marx unit, a resistive voltage divider network (such as R1 and R2) attenuates the high-voltage signal of the capacitor (such as C1) proportionally and then inputs it into an operational amplifier (such as U1) for buffering and signal conditioning. The signal is then fed back to FPGA2 in real time through an ADC pin (such as ADC1). FPGA2 can dynamically adjust the PWM duty cycle and trigger timing of the corresponding optically controlled SiC MOSFET according to the feedback data to ensure that the charging voltages of the four-stage capacitors are strictly balanced (error < 1%), avoiding energy loss or device breakdown caused by inter-stage voltage differences. In addition, the pulse power source physically isolates the grounds of modules such as the high-voltage Marx unit (such as GND1 to GND13), the FPGA control circuit (GND14 to GND17), and the ADC sampling circuit (such as GND18 to GND20) by designing 17 independent ground terminals. Through the "star grounding" strategy in the PCB layout, the grounds of each module are only connected to the main power ground through a single point, completely blocking the common-mode noise propagation path. For example, the transient current in the high-voltage discharge circuit will not be coupled to the ADC sampling circuit through the ground wire, ensuring the purity of the voltage feedback signal.

[0042] In summary, the closed-loop feedback relies on high-precision voltage monitoring, while the multi-stage ground isolation significantly reduces the interference of high-voltage switching noise on the ADC sampling link (the measured noise suppression ratio > 60 dB), enabling the FPGA to capture microvolt-level voltage fluctuations. When the two are combined, the system can respond to overvoltage or inter-stage imbalance events (such as abnormal charging of a certain-stage capacitor) within nanoseconds, trigger the FPGA protection logic (such as turning off the driving MOSFET), and at the same time maintain the overall waveform stability (pulse jitter < 0.5%). Traditional Marx generators often suffer from insufficient reliability due to inter-stage voltage drift and ground-loop interference. However, through closed-loop dynamic compensation and ground isolation, this application can greatly improve the anti-interference ability of the system, especially suitable for high-voltage pulse application scenarios with complex electromagnetic environments.

[0043] In another exemplary embodiment, as Figure 3 shown, the overcurrent and overvoltage protection module includes a voltage detection unit 110, a current detection unit 120, an overcurrent and overvoltage comparison unit 130, a latching and reset unit 140, and an output control unit 150. Among them, the voltage detection unit 110 is used to detect the voltage amplitude of the high-voltage pulse signal in real time; the current detection unit 120 is used to detect the instantaneous current value of the high-voltage pulse signal in real time; the overcurrent and overvoltage comparison unit 130 is used to compare the high-voltage pulse signal with a preset reference value and output an overvoltage or overcurrent logic trigger signal; the latching and reset unit 140 is used to perform hardware-level latching on the overcurrent or overvoltage signal; the output control unit 150 is used to convert the protection signal issued by the latching and reset unit into a physical action to forcibly turn off the main circuit or switch to a bypass path.

[0044] In another exemplary embodiment, the voltage detection unit 110 includes a tenth resistor R10, an eleventh resistor R11, a voltage follower U6 (such as LM358), a twelfth resistor R12, and a tenth capacitor C10. Among them, the first end of the tenth resistor R10 is connected to a 1.2 kV power supply, and the second end of the tenth resistor R10 is connected to the nineteenth ground terminal GND19 through the eleventh resistor R11 (a voltage division point is formed at the connection of the tenth resistor R10 and the eleventh resistor R11, and a voltage signal after voltage division is output); the non-inverting input terminal of the voltage follower U6 is connected to the connection of the tenth resistor 10 and the eleventh resistor R11, the inverting input terminal of the voltage follower U6 is shorted to its output terminal, the twelfth resistor R12 and the tenth capacitor C10 are connected in parallel between the output terminal of the voltage follower U6 and the twentieth ground terminal GND20, and the output terminal of the voltage follower U6 is connected to the second input terminal of the overcurrent and overvoltage comparison unit.

[0045] In this embodiment, the voltage detection unit attenuates the 1.2 kV high voltage to a low voltage signal in proportion (such as the voltage division ratio is R11 / (R10 + R11)) through a voltage division resistor network (R10 and R11) to adapt to the input range of the low voltage comparator. The voltage signal at the voltage division point is buffered and output by the voltage follower U6. Its inverting input terminal is shorted to the output terminal to form a unity gain amplifier, achieving a high input impedance (to avoid the load effect of the voltage division network) and a low output impedance (to drive the subsequent circuit). The twelfth resistor R12 and the tenth capacitor C10 are connected in parallel at the output terminal to form an RC low-pass filter network to suppress high-frequency noise and ensure the stability of the sampling signal.

[0046] It should be noted that both the tenth resistor R10 and the eleventh resistor R11 are thick film resistors with high resistance values (such as in the order of megaohms) and high voltage tolerance (>2 kV), taking into account both power consumption (low self-heating) and voltage withstand safety. The inverting terminal and the output terminal of the voltage follower U6 are directly shorted, which simplifies the design and can eliminate gain errors, ensuring that the output voltage strictly follows the potential at the voltage division point. The twelfth resistor R12 and the tenth capacitor C10 form an RC filter, which can specifically filter out switching noise (such as the dV / dt interference of SiCMOSFET), thereby improving the reliability of overvoltage judgment.

[0047] In summary, the voltage detection unit realizes accurate and safe sampling of high voltage signals through three-level processing of voltage division, buffering, and filtering, providing a highly reliable input reference for overvoltage protection.

[0048] In another exemplary embodiment, the current detection unit 120 includes a current sampling resistor Rshunt, a differential amplifier U5 (such as INA180), a ninth resistor R9, and a ninth capacitor C9. Among them, the first end of the current sampling resistor Rshunt serves as the input end of the over-current and over-voltage protection module. The inverting input end of the differential amplifier U5 is connected to the first end of the current sampling resistor Rshunt. The output end of the differential amplifier U5 is connected to the second end of the current sampling resistor Rshunt, and the output end of the differential amplifier U5 and the second end of the current sampling resistor Rshunt are commonly connected to the first input end of the over-current and over-voltage comparison unit. The non-inverting input end of the differential amplifier U5 is connected to the connection point of the tenth resistor R10 and the eleventh resistor R11. The ninth resistor R9 and the ninth capacitor C9 are connected in parallel between the output end of the differential amplifier U5 and the eighteenth ground terminal GND18.

[0049] In this embodiment, the current detection unit converts the current flowing through the main circuit into a tiny voltage signal (ΔV = I×Rshunt) through the current sampling resistor Rshunt, and the differential amplifier U5 amplifies this tiny voltage signal with high precision. The non-inverting input end of the differential amplifier U5 is connected to the voltage division point (the connection point of R10 and R11) of the voltage detection unit, which can introduce common-mode voltage compensation, so as to cancel the influence of the high-voltage side potential fluctuation on the sampling signal. The inverting input end of the differential amplifier U5 is directly connected to the high-voltage end of the current sampling resistor Rshunt, which can ensure that only the pure differential-mode voltage across the current sampling resistor Rshunt is amplified. After the amplified signal is filtered by the RC low-pass filter network formed by the parallel connection of the ninth resistor R9 and the ninth capacitor C9 to remove high-frequency noise, it is output to the over-current and over-voltage comparison unit 130.

[0050] Specifically, in the high-voltage pulse circuit, the current sampling resistor Rshunt is used to detect the current flowing through the main circuit. Since the current sampling resistor Rshunt is located on the high-voltage side, there is not only a tiny differential-mode voltage (ΔV) generated by the current across its two ends, but also a common-mode voltage (Vcm) from the high-voltage side to the ground superimposed. If a common differential amplifier is directly used to measure the voltage across Rshunt, the amplifier may fail or be damaged because the common-mode voltage exceeds its input range. In this embodiment, a differential amplifier with a high common-mode rejection ratio is selected. The voltage division network (R10 and R11) in the voltage detection unit reduces the common-mode voltage on the high-voltage side proportionally to a low-voltage signal (e.g., 1.2 kV is divided to 1.2 V). The voltage at this voltage division point is input to the positive input terminal of the differential amplifier U5 as the reference value of the common-mode voltage. The inverting input terminal of the differential amplifier U5 is directly connected to the high-voltage end of Rshunt, and the voltage here includes the common-mode voltage (1.2 kV) and the differential-mode voltage (I×Rshunt). Since the divided common-mode reference value (1.2 V) has been introduced into the positive input terminal, the differential amplifier U5 can automatically cancel the common-mode component by comparing the voltages at the two input terminals.

[0051] In summary, in this embodiment, by introducing a common-mode reference voltage through the voltage division network (R10 and R11) and combining the high common-mode rejection characteristics of the differential amplifier U5, the accurate detection of the current on the high-voltage side is achieved.

[0052] In another exemplary embodiment, the overcurrent and overvoltage comparison unit 130 includes an overcurrent comparator U7 (e.g., using LM393), an overvoltage comparator U8 (e.g., using LM393), a thirteenth resistor R13, and a fourteenth resistor R14. The inverting input terminal of the overcurrent comparator U7 serves as the first input terminal of the overcurrent and overvoltage comparison unit. The non-inverting input terminal of the overcurrent comparator U7 is connected to the first reference voltage Vref1, and the output terminal of the overcurrent comparator U7 is connected to the 5V power supply through the thirteenth resistor R13. The inverting input terminal of the overvoltage comparator U8 serves as the second input terminal of the overcurrent and overvoltage comparison unit. The non-inverting input terminal of the overvoltage comparator U8 is connected to the second reference voltage Vref2, and the output terminal of the overvoltage comparator U8 is connected to the 12V power supply through the fourteenth resistor R14.

[0053] In this embodiment, the overcurrent comparator U7 and the overvoltage comparator U8 respectively monitor the current and voltage signals in real time and compare them with the preset reference voltages (Vref1, Vref2). When the current sampling signal (input to the inverting input terminal of U7) exceeds Vref1, U7 outputs a low level to trigger overcurrent protection; similarly, when the voltage sampling signal (input to the inverting terminal of U8) exceeds Vref2, U8 outputs a low level to trigger overvoltage protection. The thirteenth resistor R13 and the fourteenth resistor R14 serve as pull-up resistors, which can ensure that the two comparators output a high level when not triggered and quickly pull it down when triggered, so as to drive the subsequent circuit.

[0054] It should be particularly noted that the output stages of the comparator U7 and the comparator U8 are in an open-drain structure, which only contains a pull-down transistor inside and has no built-in pull-up ability.

[0055] The thirteenth resistor R13 (connected to the 5V power supply) and the fourteenth resistor R14 (connected to the 12V power supply) serve as external pull-up resistors, which can provide a high-level reference for the output terminals of the comparators U7 and U8. For example, in the non-triggered state, the output transistors of the comparators U7 and U8 are turned off, and the output terminals are kept at a high level through the pull-up resistors (such as the output of U7 is 5V and the output of U8 is 12V). In

[0056] In the triggered state, the output transistors of the comparators U7 and U8 are turned on, and the output terminals are pulled down to a near-ground level (close to 0V). The thirteenth resistor R13 and the fourteenth resistor R14 can, first, respectively form a definite logic level with the output terminals of the comparators U7 and U8 to avoid mis-triggering due to noise in the high-impedance state (such as the level drift caused by electromagnetic interference); second, in the high-voltage pulse scenario, the fast switching action may introduce transient noise, and by setting the pull-up resistors, such interference can be suppressed.

[0057] In another exemplary embodiment, the latch and reset unit 140 includes a D flip-flop (such as 74HC74), a first OR gate OR, and a fifth charging diode d5. The first input pin of the first OR gate OR is connected to the output terminal of the overcurrent comparator U7, the second input pin of the first OR gate OR is connected to the output terminal of the overvoltage comparator U8, and the output pin of the first OR gate OR is connected to the D pin of the D flip-flop; the anode of the fifth charging diode d5 is connected to the Q pin of the D flip-flop, and the cathode of the fifth charging diode d5 is connected to the input terminal of the output control unit.

[0058] In this embodiment, when the overcurrent comparator U7 or the overvoltage comparator U8 detects an abnormality, a high-level signal is output and merged through the OR gate OR and then input to the D terminal of the D flip-flop. The D flip-flop latches the high level at the D terminal to the Q terminal at the valid edge (such as the rising edge) of the clock signal (usually provided by an FPGA or a fixed-frequency source), and the Q terminal continuously outputs a high level even if the original trigger signal disappears. At the same time, the Q terminal continuously outputs a high level and drives the output control unit (such as an optocoupler or a triode) through the diode d5 (to prevent reverse current), forcibly turning off the main circuit or switching to the bypass. After the abnormality is eliminated, an external reset signal (manual or program instruction) is required to clear the D flip-flop to resume operation. The latching and reset unit realizes hardware-level protection with a nanosecond-level response speed, filters transient interference through the latching mechanism to ensure that the protection state persists, and at the same time relies on manual or program reset to avoid misrecovery, with high anti-interference, safety isolation and flexible adaptation characteristics, providing stable and reliable fault protection for the high-voltage pulse system.

[0059] In another exemplary embodiment, the output control unit 150 includes a triode BJT1, a light-emitting diode d6, and a fifteenth resistor R15. The base of the triode BJT1 serves as the input terminal of the output control unit. The emitter of the triode BJT1 is connected to the anode of the fifth charging diode d5. The collector of the triode BJT1 is connected to the cathode of the light-emitting diode d6. The anode of the light-emitting diode d6 is connected to the emitter of the triode BJT1 through the fifteenth resistor R15, and the connection between the collector of the triode BJT1 and the cathode of the light-emitting diode d6 serves as the output terminal of the output control unit.

[0060] In this embodiment, the output control unit 150 receives the protection signal (high level) from the latching and reset unit through the base of the triode BJT1. When the signal is triggered, BJT1 conducts, and its collector-emitter path forms a low-impedance path, driving the light-emitting diode d6 to emit light (indicating that the protection is activated). At the same time, the level at the output terminal (the connection between the collector and the cathode of d6) is pulled low, forcibly turning off the main circuit or switching to the bypass; the fifteenth resistor R15 is connected in series between the anode of d6 and the emitter of BJT1 to limit the current of the light-emitting diode to prevent overcurrent damage and reduce the system power consumption. This unit adopts a compact direct connection structure (triode - light-emitting diode - current-limiting resistor), realizes a microsecond-level fast response through the switching characteristics of the triode, and at the same time uses the light-emitting diode to provide an intuitive status indication; the electrical isolation design of BJT1 blocks the interference of the high-voltage circuit to the control signal, and the diode d5 (if integrated in the previous stage) further prevents the impact of reverse current, ensuring the reliability and safety of hardware-level protection, and is suitable for efficient fault isolation and status monitoring of the high-voltage pulse system.

[0061] In another exemplary embodiment, such as Figure 4As shown, the pulse waveform shaping module includes an input matching network 210, an adjustable RC shaping unit 220, a dynamic amplitude limiting unit 230, and an output driving and isolation unit 240. Among them, the input matching network 210 is used to perform impedance matching on the high-voltage pulse signal and isolate the interference of the previous-stage circuit; the adjustable RC shaping unit 220 is used to optimize the waveform edge characteristics of the high-voltage pulse signal after impedance matching; the dynamic amplitude limiting unit 230 is used to dynamically adjust the pulse amplitude of the optimized high-voltage pulse signal; the output driving and isolation unit 240 is used to isolate and enhance the driving of the high-voltage pulse signal after the pulse amplitude is dynamically adjusted, and output a bounded wave.

[0062] In another exemplary embodiment, the input matching network 210 includes a transformer TR, an eleventh capacitor C11, and a sixteenth resistor R16. Among them, the primary side of the transformer TR is connected to the output end of the output control unit, the eleventh capacitor C11 and the sixteenth resistor R16 are connected in parallel, the first ends of the eleventh capacitor C11 and the sixteenth resistor R16 are connected to the secondary side of the transformer TR, and the second ends of the eleventh capacitor C11 and the sixteenth resistor R16 are connected to the input end of the adjustable RC shaping unit 220.

[0063] In this embodiment, the input matching network 210 realizes the impedance matching and electrical isolation of the previous-stage high-voltage pulse signal through the electromagnetic coupling of the transformer TR, and adjusts the equivalent impedance of the secondary side by using the transformer turns ratio (primary-to-secondary turns ratio) to match it with the input impedance of the subsequent adjustable RC shaping unit 220, reducing signal reflection. At the same time, the parallel-connected eleventh capacitor C11 and sixteenth resistor R16 form a low-pass filter network. The eleventh capacitor C11 presents a low impedance to high-frequency noise, can filter out the high-frequency harmonics at the pulse edge, and suppress ringing and overshoot. The sixteenth resistor R16 can provide damping to absorb the residual energy and absorb the residual reflected energy, and finally transmit a stable and low-interference pulse signal to the subsequent shaping unit, providing a reliable input for waveform optimization.

[0064] In another exemplary embodiment, the adjustable RC shaping unit 220 includes a multi-stage RC network. The multi-stage RC network includes a first-stage RC network, a second-stage RC network, and a third-stage RC network. The first-stage RC network includes a seventeenth resistor R17 and a twelfth capacitor C12. The first end of the seventeenth resistor R17 serves as the input end of the adjustable RC shaping unit. The second end of the seventeenth resistor R17 is connected to the input end of the second-stage RC network through the twelfth capacitor C12. The second-stage RC network includes an eighteenth resistor R18 and a thirteenth capacitor C13. The eighteenth resistor R18 and the thirteenth capacitor C13 are connected in parallel. The first ends of the eighteenth resistor R18 and the thirteenth capacitor C13 together serve as the input end of the second-stage RC network. The second ends of the eighteenth resistor R18 and the thirteenth capacitor C13 together serve as the output end of the second-stage RC network and are connected to the input end of the third-stage RC network. The third-stage RC network includes a nineteenth resistor R19 and a fourteenth capacitor C14. The first end of the nineteenth resistor R19 serves as the input end of the third-stage RC network. The second end of the nineteenth resistor R19 is connected to a twenty-first ground terminal GND21 through the fourteenth capacitor C14. The connection between the nineteenth resistor R19 and the fourteenth capacitor C14 is connected to the input end of the dynamic limiting unit.

[0065] In this embodiment, the adjustable RC shaping unit 220 gradually optimizes the pulse waveform through a three-stage RC network: the first stage (R17 and C12 in series) performs preliminary high-frequency attenuation on the input pulse to suppress the transient noise of the fast edge; the second stage (R18 and C13 in parallel) constitutes a low-pass filter to further smooth the waveform and reduce overshoot; the third stage (R19 and C14 in series grounded) stabilizes the DC component of the pulse and eliminates residual oscillation through resistor-capacitor voltage division and ground filtering. The above multi-stage structure can flexibly control the rise or fall time and edge steepness of the pulse signal by adjusting the RC parameters of each stage, and finally outputs a shaped pulse signal with a smooth edge, adjustable time parameters, and no high-frequency distortion.

[0066] The adjustable RC shaping unit adopts a hierarchical design of a third-order RC network (series-parallel-series grounded). The first order (R17-C12 in series) initially attenuates high-frequency noise, the second order (R18-C13 in parallel) smooths the waveform and suppresses overshoot, and the third order (R19-C14 in series grounded) stabilizes the DC component, enabling the pulse edge characteristics to be refined step by step. The innovation of the adjustable RC shaping unit lies in the alternating use of the series and parallel structures of the third-order RC network, which can balance high-frequency suppression (series RC) and low-frequency energy retention (parallel RC), and can break through the bandwidth limitation of the traditional single-order RC network. Among them, the third-order RC network forms a low-pass path through a series resistor and a grounded capacitor (R19 and C14), which can specifically eliminate residual oscillations and avoid DC component offset, thereby improving the waveform stability of the pulse signal.

[0067] In another exemplary embodiment, the dynamic limiting unit 230 includes a fifth optically controlled SiC MOSFET switch Q5, a TVS diode D_TVS, a comparator U9, a twentieth resistor R20, a first protection diode d7, and a second protection diode d8. Among them, the drain of the fifth optically controlled SiC MOSFET switch Q5 serves as the input end of the dynamic limiting unit. The source of the fifth optically controlled SiC MOSFET switch Q5 is connected to the twenty-second ground terminal GND22. The gate of the fifth optically controlled SiC MOSFET switch Q5 is connected to the ninth pulse width adjustment pin PWM9 of the FPGA1 through the twentieth resistor R20 to receive a dynamically controlled PWM signal. The anode of the TVS diode D_TVS is grounded, and the cathode of the TVS diode D_TVS is connected to the drain of the fifth optically controlled SiC MOSFET switch Q5. The non-inverting input terminal of the comparator U9 is connected to the drain of the fifth optically controlled SiC MOSFET switch Q5. The inverting input terminal of the comparator U9 is connected to the DAC output pin (programmable reference voltage) of the FPGA2. The output terminal of the comparator U9 is connected to the fifth ADC input pin ADC5 of the FPGA2 and is also connected to the input end of the drive and isolation unit. The anode of the first protection diode d7 is connected to the non-inverting input terminal of the comparator U9, and the cathode is connected to the VCC power supply. The anode of the second protection diode d8 is connected to the inverting input terminal of the comparator U9, and the cathode is connected to the twenty-third ground terminal GND23.

[0068] In this embodiment, FPGA1 outputs a high-frequency PWM signal (with adjustable duty cycle) through the PWM9 pin, drives the gate of the fifth light-controlled SiC MOSFET switch Q5 through the twentieth resistor R20, and controls its conduction state. When the input pulse amplitude approaches the preset threshold, FPGA1 dynamically reduces the PWM duty cycle, causing the on-resistance of the fifth light-controlled SiC MOSFET switch Q5 to increase, shunting part of the current to the ground (the twenty-second ground terminal GND22), actively reducing the pulse amplitude, and thus achieving dynamic soft limiting. The TVS diode D_TVS is connected in parallel between the drain of the fifth light-controlled SiC MOSFET switch Q5 and the ground, and its breakdown voltage is set to the upper limit of the pulse amplitude. When the input voltage exceeds the TVS breakdown voltage (such as 4.8 kV), the TVS diode D_TVS conducts instantaneously, clamping the voltage to a safe value to prevent the amplitude from exceeding the limit, and thus achieving hard limiting. The non-inverting input terminal of the comparator U9 monitors the drain voltage of the fifth light-controlled SiC MOSFET switch Q5 in real time, and the inverting input terminal receives the programmable reference voltage (such as 4.5 kV) output by the DAC of FPGA2. When the drain voltage exceeds the reference value, the comparator U9 outputs a low level, and the signal is fed back to FPGA2 through ADC5, triggering the protection logic (such as further reducing the PWM duty cycle or turning off the drive signal), and thus achieving closed-loop feedback. The first protection diode d7 (clamped to VCC) and the second protection diode d8 (clamped to GND23) can ensure that the input voltage of the comparator U9 is always within the safe range (0 - VCC), preventing overvoltage damage.

[0069] The dynamic limiting unit 230 adopts a "soft-hard collaboration + closed-loop feedback" composite architecture. By combining the PWM dynamic impedance adjustment of the light-controlled SiC MOSFET (Q5) and the hard clamping of the TVS diode (D_TVS), it realizes the dual-redundancy limiting control of the pulse amplitude. At the same time, it integrates the comparator U9 and the DAC / ADC closed-loop feedback of the FPGA to monitor and dynamically adjust the limiting threshold in real time. The innovation of the dynamic limiting unit 230 lies in taking into account the flexibility of dynamic adjustment and the reliability of hard limiting through the nanosecond-level response of the light-controlled SiC device and the transient protection characteristics of the TVS, and using the protection diodes (d7 and d8) to perform bidirectional clamping on the input voltage of the comparator U9 to prevent overvoltage damage. After testing, the above design can make the pulse amplitude control accuracy of the high-voltage pulse signal reach ±1%, the transient overvoltage response time < 10 ns, the anti-electromagnetic interference ability is improved by > 50 dB, and the TVS life is extended by more than 5 times, which can significantly improve the safety and stability of the system in high-voltage transient scenarios.

[0070] In another exemplary embodiment, the output driving and isolation unit 240 includes a high-speed digital optical coupler ISO, a level conversion chip TXB (TXB0108 series such as TXB0108 can be used, or NVT200x series such as NVT2008 can be used), a sixth optically controlled SiC MOSFET switch Q6, a twenty-first resistor R21, a twenty-second resistor R22, and a fifth operational amplifier U10. Among them, the positive input terminal (A) of the high-speed digital optical coupler ISO serves as the input terminal of the driving and isolation unit. The negative input terminal (K) of the high-speed digital optical coupler ISO is connected to the twenty-fourth ground terminal GND24 through the twenty-first resistor R21. The positive output terminal (C) of the high-speed digital optical coupler ISO is connected to the input pin (IN) of the level conversion chip TXB. The negative output terminal (E) of the high-speed digital optical coupler ISO is connected to the twenty-fifth ground terminal GND25. The output pin (OUT) of the level conversion chip TXB is connected to the gate of the sixth optically controlled SiC MOSFET switch Q6. The source of the sixth optically controlled SiC MOSFET switch Q6 is connected to the twenty-sixth ground terminal GND26. The drain of the sixth optically controlled SiC MOSFET switch Q6 is connected to the twenty-seventh ground terminal GND27 through the twenty-second resistor R22. The connection point between the drain of the sixth optically controlled SiC MOSFET switch Q6 and the twenty-second resistor R22 serves as the output terminal of the pulse waveform shaping module. The non-inverting input terminal and the inverting input terminal of the fifth operational amplifier U10 are connected in parallel with the twenty-second resistor R22. The output terminal of the fifth operational amplifier U10 is connected to the sixth ADC pin ADC6 of FPGA2.

[0071] In this embodiment, the high-voltage pulse signal after dynamic amplitude limiting is electrically isolated through a high-speed digital optocoupler ISO to block the common-mode noise of the front-stage high-voltage circuit. The output end of the optocoupler boosts the logic level (such as 3.3V) to the high-voltage level (such as 15V) required to drive the sixth optically controlled SiC MOSFET switch Q6 through a level conversion chip TXB. When Q6 is controlled to conduct, its drain is grounded (GND27) through a current-limiting resistor R22, and a high-voltage pulse signal synchronized with the input is generated at the output end (the connection between the drain of Q6 and R22). At the same time, the fifth operational amplifier U10 monitors the voltage across the twenty-second resistor R22 in real time and feeds it back to the ADC6 pin of FPGA2, thereby forming a closed-loop calibration to accurately control the pulse amplitude (error < 1%). The output driving and isolation unit 240 combines the optocoupler isolation, level conversion, and high-frequency characteristics of SiC devices, and the synergistic effects of the front-stage dynamic amplitude limiting and RC shaping, and finally outputs a bounded wave with a stable amplitude (doubly constrained by TVS hard limiting and FPGA soft adjustment), a steep edge (the rise / fall time can be adjusted to the 10ns level), and no ringing or overshoot, which can ensure that the waveform meets the high-precision application requirements in terms of amplitude, time parameters, and integrity.

[0072] Figure 5 and Figure 6 show the waveforms generated by two different high-voltage pulse simulation devices. Figure 5 The waveform shown is the one generated by a traditional high-voltage pulse simulation device. This waveform has obvious overshoot and ringing phenomena, resulting in unstable signal amplitude, inaccurate rise and fall times of the pulse, and significant waveform distortion. Such a waveform usually affects the test results, especially in electromagnetic compatibility (EMC) tests and high-voltage pulse tests with high precision requirements, which may cause equipment damage or measurement errors.

[0073] while Figure 6 shows the bounded wave pulse waveform generated based on the device of the present application. This waveform has no overshoot and ringing, the amplitude is strictly controlled within the preset range, the waveform is stable, and the time parameters (such as pulse width, rise time, and fall time) are accurately controlled, and the edge is very steep, almost approaching vertical. Figure 6 The waveform in Figure 6 reflects high-precision signal control, ensuring that there is no situation of too high or too low voltage during the test, and there is no high-frequency noise or clutter, showing excellent signal quality. Therefore, compared with the traditional device,

[0074] In summary, compared with Figure 5 , Figure 6The waveform shown fully embodies the technical definition of "bounded wave" from three aspects: amplitude stability, time controllability, and waveform integrity, verifying that this application has the ability to output with high precision and high reliability in high-voltage pulse applications and can meet the engineering requirements in complex electromagnetic environments.

[0075] The above are only the preferred embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A bounded-wave electromagnetic pulse simulation device, characterized in that The device includes: a pulse power source, an over-current and over-voltage protection module, and a pulse waveform shaping module, where the pulse power source is used to generate a high-voltage pulse signal; the over-current and over-voltage protection module is used to monitor the current and voltage of the high-voltage pulse signal in real time; the pulse waveform shaping module is used to shape the high-voltage pulse signal and output a bounded wave; the pulse power source includes: a four-stage Marx unit, and the structure of each stage of Marx unit is the same. The first stage of Marx unit includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a first optically controlled SiC MOSFET switch, a first operational amplifier, a first charging diode, a first inductor, a first resonant capacitor, a first digital isolator, a first AND gate, and a first driving MOSFET; where the gate of the first optically controlled SiC MOSFET switch is connected to the first pulse width adjustment pin of FPGA1 through the first digital isolator, the source of the first optically controlled SiC MOSFET switch is connected to the first ground terminal, and the drain of the first optically controlled SiC MOSFET switch is connected to the source of the second optically controlled SiC MOSFET switch; the over-current and over-voltage protection module includes: a voltage detection unit, a current detection unit, an over-current and over-voltage comparison unit, a latching and reset unit, and an output control unit, where the voltage detection unit is used to detect the voltage amplitude of the high-voltage pulse signal in real time; the current detection unit is used to detect the instantaneous current value of the high-voltage pulse signal in real time; the over-current and over-voltage comparison unit is used to compare the high-voltage pulse signal with a preset reference value and output an over-voltage or over-current logic trigger signal; the latching and reset unit is used to perform hardware-level locking on the over-current or over-voltage signal; the output control unit is used to convert the protection signal sent by the latching and reset unit into a physical action to forcibly turn off the main circuit or switch to a bypass path; the pulse waveform shaping module includes: an input matching network, an adjustable RC shaping unit, a dynamic amplitude limiting unit, and an output driving and isolation unit, where the input matching network is used to perform impedance matching on the high-voltage pulse signal and isolate the interference of the previous-stage circuit; the adjustable RC shaping unit is used to optimize the waveform edge characteristics of the high-voltage pulse signal after impedance matching; the dynamic amplitude limiting unit is used to dynamically adjust the pulse amplitude of the optimized high-voltage pulse signal; the output driving and isolation unit is used to isolate and enhance the drive of the high-voltage pulse signal with dynamically adjusted pulse amplitude and output a bounded wave.

2. The bounded-wave electromagnetic pulse simulation device according to claim 1, wherein the first end of the first capacitor is connected to the connection point of the drain of the first optically controlled SiC MOSFET switch and the source of the second optically controlled SiC MOSFET switch, and the second end of the first capacitor is connected to the second ground terminal; the anode of the first charging diode is connected to a 1.2 KV power supply, and the cathode of the first charging diode is connected to the first end of the first capacitor; The first end of the first resistor is connected to the first end of the first capacitor, and the second end of the first resistor is connected to the third ground terminal through the second resistor; The non-inverting input terminal of the first operational amplifier is connected to the connection point of the first resistor and the second resistor. The inverting input terminal of the first operational amplifier is shorted to its output terminal, and the output terminal of the first operational amplifier is connected to the first ADC input pin of FPGA2; The first end of the second capacitor is connected to the output terminal of the first operational amplifier, and the second end of the second capacitor is connected to the fourth ground terminal; The drain of the first driving MOSFET is connected to the 1.2KV power supply. The source of the first driving MOSFET is connected to the fourteenth ground terminal through the first resonant capacitor and the first inductor. The gate of the first driving MOSFET is connected to the fifth pulse width adjustment pin and the first trigger signal pin of FPGA1 through the first AND gate; 3. The bounded-wave electromagnetic pulse simulation device according to claim 1, characterized in that The voltage detection unit includes: A tenth resistor, an eleventh resistor, a voltage follower, a twelfth resistor, and a tenth capacitor, where The first end of the tenth resistor is connected to the 1.2KV power supply, and the second end of the tenth resistor is connected to the nineteenth ground terminal through the eleventh resistor; The non-inverting input terminal of the voltage follower is connected to the connection point of the tenth resistor and the eleventh resistor. The inverting input terminal of the voltage follower is shorted to its output terminal; The twelfth resistor and the tenth capacitor are connected in parallel between the output terminal of the voltage follower and the twentieth ground terminal, and the output terminal of the voltage follower is connected to the second input terminal of the overcurrent and overvoltage comparison unit; 4. The bounded-wave electromagnetic pulse simulation device according to claim 3, wherein The current detection unit includes: A current sampling resistor, a differential amplifier, a ninth resistor, and a ninth capacitor, where The first end of the current sampling resistor serves as the input terminal of the overcurrent and overvoltage protection module; The inverting input terminal of the differential amplifier is connected to the first end of the current sampling resistor. The output terminal of the differential amplifier is connected to the second end of the current sampling resistor, and the output terminal of the differential amplifier and the second end of the current sampling resistor are jointly connected to the first input terminal of the overcurrent and overvoltage comparison unit; The non-inverting input terminal of the differential amplifier is connected to the connection point of the tenth resistor and the eleventh resistor; The ninth resistor and the ninth capacitor are connected in parallel between the output terminal of the differential amplifier and the eighteenth ground terminal; 5. The bounded-wave electromagnetic pulse simulation device according to claim 4, wherein, The overcurrent and overvoltage comparison unit includes: An overcurrent comparator, an overvoltage comparator, a thirteenth resistor, and a fourteenth resistor, where The inverting input terminal of the overcurrent comparator serves as the first input terminal of the overcurrent and overvoltage comparison unit. The non-inverting input terminal of the overcurrent comparator is connected to a first reference voltage, and the output terminal of the overcurrent comparator is connected to the 5V power supply through the thirteenth resistor; The inverting input terminal of the overvoltage comparator serves as the second input terminal of the overcurrent and overvoltage comparison unit. The non-inverting input terminal of the overvoltage comparator is connected to a second reference voltage, and the output terminal of the overvoltage comparator is connected to the 12V power supply through the fourteenth resistor; 6. The bounded wave electromagnetic pulse simulation device according to claim 5, characterized in that, The latching and reset unit includes: A D flip-flop, a first OR gate, and a fifth charging diode, where The first input pin of the first OR gate is connected to the output terminal of the overcurrent comparator, the second input pin of the first OR gate is connected to the output terminal of the overvoltage comparator, and the output pin of the first OR gate is connected to the D pin of the D flip-flop; The anode of the fifth charging diode is connected to the Q pin of the D flip-flop, and the cathode of the fifth charging diode is connected to the input terminal of the output control unit.

7. The bounded wave electromagnetic pulse simulation device according to claim 6, characterized in that, The output control unit includes: a triode, a light-emitting diode, and a fifteenth resistor, where the base of the triode serves as the input terminal of the output control unit, the emitter of the triode is connected to the anode of the fifth charging diode, and the collector of the triode BJT1 is connected to the cathode of the light-emitting diode; the anode of the light-emitting diode is connected to the emitter of the triode through the fifteenth resistor, and the connection between the collector of the triode and the cathode of the light-emitting diode serves as the output terminal of the output control unit.

8. The bounded wave electromagnetic pulse simulation device according to claim 1, characterized in that The input matching network includes: a transformer, an eleventh capacitor, and a sixteenth resistor, where the primary side of the transformer is connected to the output terminal of the output control unit; the eleventh capacitor and the sixteenth resistor are in parallel, and the first ends of the eleventh capacitor and the sixteenth resistor are connected to the secondary side of the transformer; the second ends of the eleventh capacitor and the sixteenth resistor are connected to the input terminal of the adjustable RC shaping unit.

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