A digital lock-in amplifier and weak signal acquisition system and method based on frequency adaptive technology

Abstract

This invention relates to a digital lock-in amplifier and a weak signal acquisition system and method based on frequency adaptive technology. The system includes: a front-end signal processing module for acquiring a weak signal under test; a frequency adaptive tracking module for performing a fast Fourier transform on the frequency of the weak signal under test to obtain the position of the maximum spectral line, thereby synthesizing a frequency control word, further generating a local reference signal, and simultaneously adjusting the coefficients of the low-pass filter and the loop filter, as well as the stage adjustment mode of the carrier synchronization loop; a multi-rate narrowband low-pass filter module for multiplying the digital signal with the local reference signal and then filtering and downsampling the high-frequency signal to obtain multiple mutually orthogonal difference frequency components; a vector operation module for performing vector operations on the multiple mutually orthogonal difference frequency components to obtain the phase and amplitude of the weak signal under test; and a human-computer interaction module for displaying and storing the phase and amplitude of the weak signal under test.

Description

Technical Field

[0001] This invention relates to the field of weak signal detection technology, and in particular to a digital lock-in amplifier and a weak signal acquisition system and method based on frequency adaptive technology. Background Technology

[0002] Weak signal acquisition systems are widely used in many locations and environments requiring high sensitivity and accurate measurement. Typical applications include medical diagnostics, environmental monitoring, physical experiments, aerospace communications, and earthquake monitoring. For example, in the medical field, the acquisition of weak biosignals (such as electrocardiograms and electroencephalograms) is a common application, and weak signal acquisition systems can be used to capture these minute bioelectrical signals. In environmental monitoring, such as gas leak detection, air quality monitoring, and seismic wave detection, high-sensitivity weak signal acquisition systems are also required. Common weak signal acquisition methods include traditional amplifier methods, filter enhancement methods, digital signal processing methods, and lock-in amplification technology. These methods enhance weak signals and reduce noise through different technical means, thereby improving signal detection accuracy.

[0003] While existing weak signal acquisition methods have played a crucial role in practical applications, they also have some significant drawbacks. First, traditional amplifier methods, although capable of amplifying signals, tend to amplify noise, leading to an imbalance in the signal-to-noise ratio and affecting signal reliability. Second, while filter enhancement methods can reduce noise, filter design optimization is highly complex and may result in the loss of some useful signal components, especially when the signal frequency varies significantly. Digital signal processing methods (such as FFT) can effectively extract signals within specific frequency bands, but when dealing with high-frequency or nonlinear noise, the processing algorithms may require lengthy computation times, resulting in poor real-time performance. Furthermore, traditional lock-in amplification techniques typically rely on external reference signals; if the reference signal is unstable or has significant errors, it will also affect the signal acquisition accuracy.

[0004] Digital lock-in amplifiers (DLAs), as a signal acquisition technology, possess high sensitivity and anti-interference capabilities. However, current DLAs still have some shortcomings. First, the performance of DLAs may be limited in high-noise environments, especially when the signal frequency varies significantly. In such cases, the locking accuracy of the DLA may decrease, leading to inaccurate measurement results. Second, DLAs require a precise reference signal. Poor quality reference signals may introduce additional errors or even prevent proper signal locking. Third, the design and debugging of DLAs are complex, particularly in terms of frequency adaptability. If the system fails to adaptively adjust the operating frequency, it may affect the system's sensitivity and stability. Finally, DLAs place high demands on the low-pass filter in demodulation. Accurate results require a very narrow bandwidth filter, but achieving such a narrow bandwidth at high sampling rates necessitates very high filter orders, requiring substantial hardware resources. Therefore, improving the frequency adaptability of DLAs, reducing dependence on reference signals, and enhancing the performance of low-pass filters remain current technical challenges. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention aims to provide a digital lock-in amplifier and weak signal acquisition system and method based on frequency adaptive technology. The present invention employs a dual tracking mechanism of frequency domain analysis and carrier synchronization loop feedback control. Furthermore, the carrier synchronization loop utilizes an adaptive adjustment unit, which can adjust the correlation coefficients according to the signal's frequency range and noise levels, greatly enhancing the system's weak signal detection capability. This results in superior performance and reliability in high-noise environments, enabling rapid and accurate detection of weak signals. The present invention also employs cascaded downsampling technology from multi-rate digital signal processing, achieving an extremely narrow 0.1Hz low-pass filter within limited FPGA resources.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] A digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology, comprising:

[0008] The front-end signal processing module is used to acquire weak signals to be tested, process the weak signals to be tested, and convert them into digital signals.

[0009] The frequency adaptive tracking module is used to perform a fast Fourier transform on the frequency of the digital signal, extract the main frequency components in the signal, obtain the position of the maximum spectral line, and convert it into a direct digital frequency in the carrier synchronization loop. The direct digital frequency is synthesized into a frequency control word. Based on the frequency control word, a local reference signal with the same frequency and phase as the carrier of the weak signal under test is generated. At the same time, the coefficients of the low-pass filter and the loop filter and the stage adjustment mode of the carrier synchronization loop are adjusted.

[0010] A multi-rate narrowband low-pass filter module is used to multiply the digital signal with the local reference signal and then filter and downsample the high-frequency signal to retain key information and obtain multiple mutually orthogonal difference frequency components.

[0011] The vector operation module is used to perform vector operations on multiple mutually orthogonal difference frequency components to obtain the phase and amplitude of the weak signal under test;

[0012] The human-computer interaction module is used to display and store the phase and amplitude of the weak signal under test.

[0013] Optionally, the front-end signal processing module includes:

[0014] The preamplifier circuit is used to suppress noise interference while performing preliminary amplification of the weak signal under test.

[0015] The post-amplifier circuit is used to amplify the weak signal under test after primary amplification and to provide the main gain of the system.

[0016] Anti-aliasing filters are used to filter out signals that exceed the target sampling frequency;

[0017] An analog-to-digital converter circuit is used to convert the filtered signal into the digital signal.

[0018] The preamplifier circuit, the post-amplifier circuit, the anti-aliasing filter, and the analog-to-digital converter circuit are connected in sequence.

[0019] Optionally, the frequency adaptive tracking module includes:

[0020] The adaptive notch filter submodule is used to suppress interference signals at specific frequencies using the LMS algorithm, without losing other useful signals. At the same time, when there is a significant frequency difference between the target signal and the interference signal in the spectrum, the interference frequency is removed while other frequency components are preserved by adjusting the filter parameters.

[0021] The Fast Fourier Transform (FFT) submodule is used to perform a Fast Fourier Transform on the digital signal frequency processed by the Adaptive Notch Filter (AFF) submodule, extract the main frequency components in the signal, obtain the position of the maximum spectral line, convert it into the direct digital frequency in the carrier synchronization loop, and synthesize the direct digital frequency into a frequency control word.

[0022] The carrier synchronization loop submodule is used to generate a local reference signal that is in phase and frequency with the carrier of the weak signal under test according to the frequency control word, and to adjust the coefficients of the low-pass filter and the loop filter as well as the stage adjustment mode of the carrier synchronization loop.

[0023] Optionally, the Fast Fourier Transform submodule includes:

[0024] The FFT unit is used to perform a fast Fourier transform on the frequency of the digital signal processed by the adaptive notch filter submodule, converting the signal from the time domain to the frequency domain.

[0025] The data modulus extraction unit is used to extract the modulus value of the spectrum in the frequency domain, obtain the strongest frequency component, and infer the carrier frequency;

[0026] The maximum spectral line value calculation unit is used to obtain the frequency point with the largest amplitude in the spectrum while inferring the carrier frequency, and the frequency point is the main carrier frequency corresponding to the signal.

[0027] The conversion unit converts the primary carrier frequency into a frequency control word:

[0028] M0 = (number-1) * 2 DDS_N-N = (number-1) << 22

[0029] Where M0 is the DDS frequency control word, number is the position of the maximum spectral line, DDS_N is the phase accumulation word length of the DDS, and N is the number of FFT sampling points.

[0030] Optionally, the carrier synchronization loop submodule includes:

[0031] The overall performance parameter design unit is used to determine the natural angular frequency and damping coefficient; wherein, the natural angular frequency and damping coefficient are both related to the loop filter coefficient and the low-pass filter cutoff frequency;

[0032] The expression for the natural angular frequency is determined as follows:

[0033]

[0034] Where ζ is the damping coefficient, (S / N) i The input signal carrier power and the bandwidth B before the carrier synchronization loop are given. i The ratio of noise power (S / N)L It is the ratio of the input signal carrier power to the noise power of the one-sided noise bandwidth;

[0035] The lower limit expression for the natural angular frequency is determined as follows:

[0036] ΔW L =2ζW n

[0037] Among them, W n It is the natural angular frequency;

[0038] The adaptive adjustment unit is used to determine the frequency range of the signal through the frequency control word, and set the initial loop filter coefficients and the cutoff frequency of the low-pass filter according to the frequency range, thereby entering the first-level fast locking state. It further employs a dual-threshold oscillation judgment method to detect whether steady-state phase difference oscillates. When oscillation occurs, it judges based on the maximum value of the steady-state phase difference. If the maximum value is less than threshold one, the loop filter coefficients are switched to the third-level adjustment mode. If the maximum value is between threshold one and threshold two, the loop filter coefficients are switched to the second-level adjustment mode. If the maximum value is greater than threshold two, the loop filter coefficients are maintained in the first-level adjustment mode. When switching to the third-level adjustment mode, the dual-threshold oscillation judgment method is applied again in the second-level slow tracking state to detect whether steady-state phase difference oscillation occurs. If the oscillation continues, it further enters the third-level precise tracking state, thereby maintaining optimal frequency locking.

[0039] Optionally, the steady-state phase difference detection method using the dual threshold oscillation judgment method includes:

[0040] When the carrier synchronization loop captures the signal, it goes through the fast acquisition process and the tracking process in sequence, that is, the steady-state phase difference presents an oscillating signal with up and down fluctuations.

[0041] During the fast acquisition process, the maximum and minimum values ​​of the steady-state phase difference are determined based on the coefficient of the steady-state phase difference. After the maximum and minimum values ​​of the fast acquisition process have been sustained for a first target time, the tracking process begins. During the tracking process, the maximum and minimum values ​​of the tracking process are determined based on the coefficient of the steady-state phase difference. After the maximum and minimum values ​​of the tracking process have been sustained for a second target time, an oscillation enable signal is output to determine whether the steady-state phase difference oscillates.

[0042] Optionally, the carrier synchronization loop submodule further includes:

[0043] The multiplier unit is used to multiply the received output signal of the adaptive notch filter submodule with the reference carrier signal generated by the local DDS oscillator to generate low-frequency and high-frequency signals. As the frequency is continuously adjusted, a signal containing DC component and frequency doubling is obtained. Based on the signal containing DC component and frequency doubling, the carrier frequency component is extracted from the input signal under test, and the carrier frequency component is converted into a baseband signal.

[0044] A low-pass filter unit is used to filter out high-frequency components in the baseband signal, retain DC components, and obtain phase error information based on DC components;

[0045] The loop filter unit is used to smooth the error voltage signal of the low-pass filter, remove high-frequency noise, and retain low-frequency components;

[0046] The DDS oscillator unit is used to generate a high-precision, adjustable frequency signal based on the low-frequency components, namely a local reference signal that is in phase and frequency with the carrier of the weak signal under test.

[0047] Optionally, the multi-rate narrowband low-pass filter module includes:

[0048] The integral combing filter unit is used to extract the high sampling rate signal of the analog-to-digital conversion circuit by a first target multiple, and reduce the original sampling rate of the integral combing filter to the first target sampling rate.

[0049] A half-band filter unit is used to extract the signal after extraction by the integral comb filter unit according to a second target multiple, thereby reducing the original sampling rate of the half-band filter to the second target sampling rate.

[0050] The low-pass filter unit is used to extract signal changes below the low-frequency threshold and remove high-frequency noise. At the same time, the sampling rate of the low-pass filter has been reduced to the third target sampling rate to achieve a narrowband low-pass filtering function of 0.1Hz.

[0051] Optionally, the vector operation module includes:

[0052] The amplitude calculation unit is used to perform a vector operation of taking the square root of the sum of squares of multiple mutually orthogonal difference frequency components to obtain a DC result that is proportional to the amplitude of the external modulation signal under test, thereby demodulating the amplitude of the weak signal under test.

[0053] The phase operation unit is used to divide the multiple mutually orthogonal difference frequency components, calculate their arctangent, and then make appropriate adjustments according to the positive and negative relationship between the internal divisor and dividend to obtain the phase of the weak signal under test.

[0054] To achieve the above objectives, the present invention also provides a digital lock-in amplifier based on frequency adaptive technology and a method for weak signal acquisition, comprising:

[0055] A weak test signal is acquired, processed, and converted into a digital signal. A fast Fourier transform is performed on the frequency of the digital signal to extract the main frequency components, obtain the position of the maximum spectral line, and convert it into a direct digital frequency in the carrier synchronization loop. The direct digital frequency is synthesized into a frequency control word. Based on the frequency control word, a local reference signal with the same frequency and phase as the carrier of the weak test signal is generated. At the same time, the coefficients of the low-pass filter and the loop filter, as well as the stage adjustment mode of the carrier synchronization loop, are adjusted.

[0056] The digital signal is multiplied by the local reference signal, and then filtered and downsampled for high frequency to retain key information and obtain multiple mutually orthogonal difference frequency components. Vector operations are performed on the multiple mutually orthogonal difference frequency components to obtain the phase and amplitude of the weak test signal. The phase and amplitude of the weak test signal are then displayed and stored.

[0057] The beneficial effects of this invention are as follows:

[0058] The frequency adaptive tracking module in this invention improves the system's frequency adaptation capability and locking stability. By optimizing the adaptive tracking algorithm and combining a dual tracking mechanism of frequency domain analysis and carrier synchronization loop feedback control, this invention enables the system to stably lock onto the target frequency even under conditions of significant noise and frequency variations. This overcomes the problem in existing technologies where lock-in amplifiers are prone to loss of lock or decreased locking accuracy when frequency variations are large. Especially in high-dynamic environments, such as when signal frequencies change frequently, it can provide more reliable and accurate signal acquisition, significantly improving the system's robustness and reliability.

[0059] The adaptive adjustment unit in the carrier synchronization loop of this invention solves the problem that a single carrier synchronization loop cannot simultaneously meet the requirements of fast locking, high dynamics, and high precision. Traditional digital lock-in amplifiers usually rely on a single carrier synchronization loop for frequency tracking, but a single carrier synchronization loop often has limitations when fast locking and high precision are required at the same time. To address this problem, this invention introduces an adaptive adjustment unit that uses a two-stage dynamic threshold judgment and a three-stage coefficient adjustment mechanism to achieve frequency synchronization in high-noise environments and over a wider frequency range. This not only improves the system's adaptability but also enables the system to achieve a good balance between high precision requirements and dynamic response, solving the bottleneck problem in traditional technologies, reducing system bandwidth, and minimizing hardware resources.

[0060] This invention employs cascaded downsampling technology in multi-rate digital signal processing. By gradually reducing the high sampling rate of the front-end ADC, the amount of data that the system needs to process is effectively reduced. This technological innovation enables the system to achieve a narrowband filtering function of 0.1Hz within limited FPGA hardware resources, significantly improving the utilization efficiency of hardware resources and the subsequent demodulation accuracy. Compared with the requirements of high sampling rate and high processing power in existing technologies, this invention greatly reduces the consumption of hardware resources and system power consumption while achieving the same function, and has higher engineering practicality and economy.

[0061] The design architecture of this invention combines a front-end signal processing module, a frequency adaptive tracking module, a multi-rate narrowband low-pass filter module, and a vector operation module, enabling the system to flexibly process different types of weak signals. This further enhances the system's versatility and adaptability. Especially when facing complex signal environments, the system can adaptively adjust its working mode and stably output high-quality acquisition results. Compared with traditional systems, this flexibility and scalability allow this invention to better meet complex and dynamically changing application requirements.

[0062] In summary, by introducing frequency adaptive tracking, dynamic adjustment, and multi-rate downsampling techniques, this invention overcomes the limitations of existing technologies and improves the system's accuracy, robustness, and resource utilization efficiency. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a block diagram of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to an embodiment of the present invention.

[0065] Figure 2 This is a flowchart of an adaptive damper in the frequency adaptive tracking module of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0066] Figure 3 This is an FPGA simulation diagram of an adaptive damper in the frequency adaptive tracking module of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0067] Figure 4This is a frequency estimation error diagram of the FFT carrier frequency estimation in the frequency adaptive tracking module of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology in an embodiment of the present invention, under different signal-to-noise ratios in the low frequency range;

[0068] Figure 5 This is a frequency estimation error diagram of the FFT carrier frequency estimation in the frequency adaptive tracking module of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology in an embodiment of the present invention, under different signal-to-noise ratios in the high frequency range;

[0069] Figure 6 This is a table showing the relationship between the loop coefficient, locking time, and steady-state phase difference in a traditional carrier synchronization loop of a digital lock-in amplifier based on frequency adaptive technology and a weak signal acquisition system according to an embodiment of the present invention.

[0070] Figure 7 This is a curve showing the relationship between the single-sided noise bandwidth and damping coefficient of an ideal second-order carrier synchronization loop in a carrier synchronization loop of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0071] Figure 8 This is a table showing the relationship between the stage adjustment mode and loop coefficient changes of the adaptive adjustment unit in the carrier synchronization loop of a digital lock-in amplifier based on frequency adaptive technology and a weak signal acquisition system according to an embodiment of the present invention, in different frequency ranges.

[0072] Figure 9 This is a basic flowchart of the adaptive adjustment unit in the carrier synchronization loop of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0073] Figure 10 This is a basic flowchart of a dual threshold oscillation judgment method for an adaptive adjustment unit in a carrier synchronization loop of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0074] Figure 11 The amplitude-frequency response curves of IIR filters with different function designs are shown for a low-pass filter unit in a carrier synchronization loop of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0075] Figure 12 This is a curve showing the IIR filter coefficients and the finite word length effect of the output data in the low-pass filter unit of a carrier synchronization loop in a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0076] Figure 13This table shows whether the loop filter in the carrier synchronization loop of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention, is a causal stable system under different coefficients.

[0077] Figure 14 This invention relates to an embodiment of the error rate of a digital lock-in amplifier based on frequency adaptive technology and a single carrier synchronization loop of a weak signal acquisition system under different frequency ranges and different signal-to-noise ratios.

[0078] Figure 15 This invention relates to an embodiment of a frequency adaptive tracking module for a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, under different frequency ranges and different signal-to-noise ratios.

[0079] Figure 16 This invention relates to a frequency adaptive tracking module of a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, which provides the locking time of the module in different frequency ranges and different signal-to-noise ratios under different frequency ranges and signal-to-noise ratios.

[0080] Figure 17 This invention presents the spectral characteristics of a CIC filter unit in a multi-rate narrowband low-pass filter module of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology at different stages.

[0081] Figure 18 This is a basic structural block diagram of the CIC filter unit in a multi-rate narrowband low-pass filter module of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to an embodiment of the present invention.

[0082] Figure 19 This is a waveform diagram of FPGA and MATLAB co-simulation of a multi-rate narrowband low-pass filter module of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology under different mixing signals, according to an embodiment of the present invention.

[0083] Figure 20 This is a waveform diagram from the FPGA and MATLAB co-simulation of a multi-rate narrowband low-pass filter module for a digital lock-in amplifier and a weak signal acquisition system based on frequency adaptive technology, according to an embodiment of the present invention.

[0084] Figure 21 This is a test result table at the MATLAB software level for a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to an embodiment of the present invention, under a specified test signal.

[0085] Figure 22The following figures illustrate the specific test results of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology under a specified test signal at the MATLAB software level, according to an embodiment of the present invention: (a) shows the amplitude and phase test results of the test signal at a signal-to-noise ratio of 100dB; (b) shows the amplitude and phase test results of the test signal at a signal-to-noise ratio of 40dB; (c) shows the amplitude and phase test results of the test signal at a signal-to-noise ratio of 0dB; (d) shows the amplitude and phase test results of the test signal at a signal-to-noise ratio of -6dB; (e) shows the amplitude and phase test results of the test signal at a signal-to-noise ratio of -20dB; and (f) shows the amplitude and phase test results of the test signal at a signal-to-noise ratio of -25dB.

[0086] Figure 23 This is a test result table of the overall system of a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to an embodiment of the present invention, under a specified test signal at the FPGA hardware level. Detailed Implementation

[0087] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0088] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0089] This embodiment discloses a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology, including the following steps: a front-end signal processing module for preprocessing, conditioning, and filtering the weak test signal to ensure that the input signal can be transmitted to the core part of the lock-in amplifier with optimal quality; a frequency adaptive tracking module for automatically adjusting and locking the target signal frequency in high-noise and dynamically changing signal frequency environments to ensure that the reference signal inside the lock-in amplifier is always synchronized with the target signal, thereby maximizing the detection sensitivity and accuracy of the signal; a multi-rate narrowband low-pass filter module for gradually reducing the high sampling rate of the front-end ADC to achieve a 0.1Hz narrowband low-pass filter function in limited FPGA hardware resources, thereby effectively reducing the amount of computation and storage in the signal processing process; a vector operation module for mathematically processing the two cross-correlation functions obtained by the front-end module and using correlation algorithms to effectively and accurately extract the phase and amplitude from the weak test signal; and a human-computer interaction module for displaying and storing the detection results, completing the digital lock-in amplifier and weak signal acquisition based on frequency adaptive technology.

[0090] The front-end signal processing module consists of a preamplifier circuit, a post-amplifier circuit, an anti-aliasing filter, and an analog-to-digital converter circuit. The preamplifier circuit suppresses noise interference while performing preliminary signal amplification. The post-amplifier circuit, composed of multiple amplifier stages, is the main gain provider of the system. The anti-aliasing filter and the analog-to-digital converter module are responsible for filtering out signals greater than half the system sampling frequency to ensure that the system does not have aliasing effects. The other converts the analog signal into a digital signal and sends the resulting digital signal to the FPGA for further processing.

[0091] The frequency adaptive tracking module consists of an adaptive notch filter, a Fast Fourier Transform (FFT) carrier frequency estimation module, and a carrier synchronization loop. The adaptive notch filter removes or suppresses interference signals at specific frequencies, specifically removing 50Hz power frequency signals during signal acquisition, processing, and analysis. Its function is to adaptively adjust the filter coefficients using the LMS algorithm based on the phase and amplitude of the interference frequency signal, tracking parameter changes to maintain effective filtering of interference signals. The FFT carrier frequency estimation module is used for approximate estimation and analysis of the weak frequency of the signal under test, thereby obtaining the position of the maximum spectral line and converting it into a Direct Digital Frequency Synthesis (DDS) frequency control word in the carrier synchronization loop. This lays the foundation for improving the accuracy and accelerating the locking time of the subsequent carrier synchronization loop. Due to the picket-fence effect of FFT, this method can only capture some discrete frequencies. Frequencies between FFT transform spectral lines cannot be tracked, thus requiring a carrier synchronization loop for more precise locking. The carrier synchronization loop generates a local reference signal that is in phase and frequency with the carrier of the weak signal under test, which is then used by the demodulator for demodulation. After the FFT points to the vicinity of the carrier frequency, the carrier synchronization loop searches for and achieves true carrier frequency synchronization, effectively eliminating the influence of frequency difference. Compared with the traditional carrier synchronization loop, this carrier synchronization loop introduces an adaptive adjustment unit, which can realize real-time switching of loop coefficients under different frequencies and noise levels, effectively improving the loop locking time and accuracy, and solving the problem that traditional carrier synchronization loops cannot simultaneously meet the requirements of fast locking, high dynamics, and high precision.

[0092] The multi-rate narrowband low-pass filter module consists of an integrating comb (CIC) filter, a half-band (HB) filter, and a 0.1Hz narrowband low-pass filter. The integrating comb (CIC) filter is used to decimate the high sampling rate signal of the front-end ADC by 2500 times. Due to its simple structure and lack of multiplier units, it is a zero-cancellation-based FIR filter, making it suitable for operation under high sampling rate conditions. The half-band (HB) filter is used to further decimate the signal after decimation by the CIC filter by 2 times, achieving a 64-fold decimation through a 6-stage cascade. However, because its transition band is often too large for the last stage of a multi-stage filter, it cannot meet the overall requirements of the filtering characteristics and is therefore unsuitable as the last stage of a multi-stage decimation filter. The 0.1Hz narrowband low-pass filter is used to extract very low-frequency (around 0.1Hz) signal changes, thereby effectively extracting the frequency components and amplitude changes of weak test signals. By filtering out high-frequency noise and other irrelevant signals, it can accurately capture subtle changes in the target signal, especially in low signal-to-noise ratio environments, enhancing the detectability of weak signals and improving the sensitivity and accuracy of the system.

[0093] The vector operation module consists of an amplitude operation unit and a phase operation unit. The amplitude operation unit performs a vector operation by squaring and taking the square root of the sum of the squares of the two mutually orthogonal difference frequency components after passing through the multi-rate narrowband low-pass filter module. This eliminates the influence of the phase difference and obtains a DC result proportional to the amplitude of the external modulated signal under test, thereby demodulating the amplitude of the weak signal under test. The phase operation unit divides the two mutually orthogonal difference frequency components after passing through the multi-rate narrowband low-pass filter module, calculates their arctangent, and then makes appropriate adjustments based on the positive and negative relationship between the internal divisor and dividend to obtain the corresponding phase result.

[0094] The human-computer interaction module consists of the FPGA's PS terminal, Ethernet, and QT host computer. The FPGA's PS terminal is used to store relevant results and configure the Ethernet port. The Ethernet terminal is used to transmit relevant results from the lower-level machine to the host computer via the TCP protocol. The QT host computer is used to display relevant output results and can pass parameters.

[0095] This embodiment also provides a digital lock-in amplifier and a weak signal acquisition method based on frequency adaptive technology, including the following steps: preprocessing, conditioning, and filtering the weak signal to be measured, and filtering out signals greater than half of the system sampling frequency to ensure that the system does not have aliasing effects, and then using an ADC to convert the analog signal into a digital signal; under the action of the frequency adaptive tracking module, the system first performs adaptive filtering of the acquired weak digital signal on the power frequency signal, and then combines the dual tracking mechanism of frequency domain analysis and carrier synchronization loop feedback control, as well as the algorithm control of the adaptive adjustment unit, so that the system can stably lock the target frequency in environments with high noise and large frequency changes, and effectively reduce phase error. Finally, the system can generate a local reference signal that is in phase and at the same frequency as the carrier of the weak signal to be measured.

[0096] The local sine and cosine reference signals generated by the frequency adaptive tracking module are multiplied by the weak signal under test, and then filtered and downsampled by a multi-rate narrowband low-pass filter to reduce the amount of data and computation while retaining key information, resulting in two mutually orthogonal difference frequency components. Vector operations are performed on these two components to obtain the phase and amplitude information of the weak signal under test. The detection results are then displayed and stored, completing the acquisition of the weak signal.

[0097] The method for tracking weak signals using a frequency adaptive tracking module to obtain a local reference signal with the same frequency and phase as the carrier of the weak signal under test is as follows: First, the acquired weak signal under test is adaptively filtered out using the LMS algorithm to remove the 50Hz power frequency signal; then, after performing a 65536-point FFT carrier frequency estimation, the data is modulo-divided to obtain the position of the maximum spectral line, and then converted into a DDS frequency control word using correlation operations; the obtained DDS frequency control word is provided to the DDS in the carrier synchronization loop to generate a preliminary reference signal, and the initial IIR filter, loop coefficients, and several adjustment modes are determined by the adaptive adjustment unit, and the subsequent steady-state phase difference is considered. The correlation coefficient is adjusted in real time according to the changes; then the reference signal is multiplied with the weak test signal to obtain the error phase, and then the error voltage is obtained through the IIR filter. The error voltage is then filtered through the loop to obtain the control voltage. Finally, the control voltage is applied to the DDS to generate a frequency shift, thereby tracking the frequency of the weak test signal. If this frequency is a fixed frequency, under the action of the control voltage, the frequency of the reference signal will gradually approach the frequency of the weak test signal. Once the two are equal, if certain conditions are met, the carrier synchronization loop can stabilize, thereby achieving locking. A certain steady-state phase difference is maintained between the two, thus generating a local reference signal with the same frequency and phase as the carrier of the weak test signal.

[0098] The adaptive adjustment unit performs real-time coefficient adjustment as follows: By analyzing the DDS frequency control word output by the FFT carrier frequency estimation module, the system sets the initial IIR filter and loop filter coefficients and selects an appropriate adjustment mode. First, the system enters a fast lock-on state, rapidly bringing the frequency of the reference signal close to the frequency of the target signal, thus achieving fast lock-on. When the signal frequency range meets the second-level adjustment mode, the system uses a dual-threshold oscillation judgment method to detect whether the steady-state phase difference oscillates to a certain extent, thereby determining whether to enter the second-level slow tracking state. In this stage, the frequencies of the reference signal and the target signal further approach each other, achieving higher accuracy. If the signal frequency range meets the third-level adjustment mode, after entering the second-level slow tracking state, the system continues to use the dual-threshold oscillation judgment method to determine the oscillation of the steady-state phase difference, deciding whether to enter the third-level precise tracking state. In this stage, the frequencies of the reference signal and the target signal reach higher accuracy, achieving final precise lock-on.

[0099] The first-level adjustment mode is a fast-lock state, in which the natural angular frequency and loop coefficient are relatively large, enabling the carrier synchronization loop to quickly bring the phase of the reference signal close to the phase of the signal under test, thus achieving fast locking. The second-level adjustment mode is a slow-track state, in which the natural angular frequency and loop coefficient are reduced, allowing the phase of the reference signal to get even closer to the phase of the signal under test without losing lock. The third-level adjustment mode is a precise tracking state, in which the natural angular frequency and loop coefficient are further reduced from the previous levels, making the phase of the reference signal almost identical to the phase of the signal under test, thus achieving precise tracking.

[0100] More specifically, in the first-level adjustment mode, the error voltage signal generated by the carrier synchronization loop is relatively large, which causes a significant change in the DDS frequency control word, allowing the frequency of the reference signal to quickly approach the signal under test; the subsequent two adjustment modes are for more precise locking.

[0101] The steps of the dual-threshold oscillation judgment method are as follows: When the carrier synchronization loop captures the signal, it first undergoes a fast acquisition process, that is, the steady-state phase difference changes greatly. Then, after capturing the signal frequency, it begins the tracking process, that is, the steady-state phase difference presents an oscillating signal with up and down fluctuations. Thus, for each locked state, it first enters the first threshold tracking (fast acquisition process), and determines the maximum and minimum values ​​according to the coefficient of the steady-state phase difference. When these two thresholds meet for a certain duration, it enters the second threshold tracking (tracking process). When the same requirements are met, it outputs an oscillation enable signal.

[0102] The method for filtering and downsampling high-frequency signals by multiplying the local sine and cosine reference signals generated by the frequency adaptive tracking module with the weak test signal and then passing them through a multi-rate narrowband low-pass filter is as follows: First, a three-stage CIC filter cascade is used to achieve a 2500-fold decimation filter, reducing the sampling rate from 50MHz to 20kHz. At this point, the attenuation of the first sidelobe level reaches 40.38dB, and the stopband attenuation can meet the basic practical requirements without excessive passband attenuation causing signal distortion. The three-stage CIC filter structure implements the Hogenauer decimation filter based on the transposition theorem and Noble's identity, which greatly improves the system's operation speed and reduces resource consumption. Since the HB filter can reduce the number of multiplications per second when performing a 2x decimation by nearly half compared to a general linear phase FIR filter, a six-stage HB filter cascade is used to achieve a 64-fold decimation filter, reducing 20kHz to 312.5Hz. Finally, a 0.1Hz FIR filter is implemented at a sampling rate of 312.5Hz.

[0103] like Figure 1As shown, this embodiment discloses a digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology. To achieve the system's requirements of high dynamic range, high precision, high speed, strong anti-interference capability, and frequency adaptability, the system employs a front-end signal processing module, a frequency adaptive tracking module, a multi-rate narrowband low-pass filter module, a vector operation module, and a human-computer interaction module. This enables the system to provide stable and accurate weak signal extraction in strong noise environments. Specifically, it includes a front-end signal processing module for preprocessing, conditioning, and filtering the weak signal under test, ensuring that the input signal can be transmitted to the core of the lock-in amplifier with optimal quality. The frequency adaptive tracking module is used to automatically adjust and lock the target signal frequency in a dynamically changing signal frequency environment, ensuring that the reference signal inside the lock-in amplifier is always synchronized with the target signal. This maximizes the system's frequency tracking accuracy, anti-interference capability, adaptability, and demodulation performance. It can also meet the requirements of high dynamism and high precision, adapting to signal frequency changes in real time. Especially in high noise, frequency drift, or drastic frequency changes, it can always ensure accurate tracking of the target signal by dynamically adjusting relevant parameters. Precise carrier frequency estimation and synchronization can significantly improve signal demodulation performance, especially in high noise or low signal-to-noise ratio environments, improving demodulation robustness and bit error rate performance.

[0104] A further implementation involves a frequency adaptive tracking module comprised of an adaptive notch filter module, an FFT carrier frequency estimation module, and a carrier synchronization loop module. The adaptive notch filter module employs the LMS algorithm to effectively suppress interference signals at specific frequencies without losing other useful signals. Particularly when the target signal and interference signal have significant frequency differences in the spectrum, it can effectively remove interference frequencies while retaining other frequency components by adjusting its filter parameters. Figure 2 The diagram shows the principle block diagram of an adaptive notch filter for filtering out single-frequency power frequency signals. x(t) is the input signal superimposed with interference, and s(t) is the useful signal to be retained. By using two orthogonal single-frequency signals and adjusting their weights w1 and w2, a signal identical to the interference signal can be synthesized, thus outputting the useful signal. In this example, it is mainly used to eliminate 50Hz power frequency interference, improve the signal-to-noise ratio of the target signal, and increase the accuracy of subsequent processing steps. Figure 3As shown in the figure, the useful signal in the input data is a 100Hz sine wave, and the interference signal is a 50Hz single-frequency signal. The figure shows that the output signal converges quickly, and the useful signal is consistent with the output signal, indicating that this module can automatically filter out interference signals. The FFT carrier frequency estimation module is used to perform a fast Fourier transform on the weak signal under test, extract the main frequency components of the signal, thereby obtaining the position of the maximum spectral line, and converting it into a direct digital frequency synthesis (DDS) frequency control word in the carrier synchronization loop. This lays the foundation for improving the accuracy and accelerating the locking time of the subsequent carrier synchronization loop.

[0105] A further implementation method includes an FFT carrier frequency estimation module comprising: an FFT unit for performing a Fast Fourier Transform (FFT), an algorithm for converting a signal from the time domain to the frequency domain; in this embodiment, a signal can be decomposed into multiple frequency components using a 65536-point FFT, each frequency component represented by a complex number, where the input is a 12-bit weak signal to be measured, and the outputs are 12-bit real parts representing the amplitude and imaginary parts representing the phase; and a data modulus extraction unit for extracting the modulus value of the spectral data, identifying the strongest frequency component, and inferring the carrier frequency; in this embodiment, the output of the FFT unit is first transcoded, i.e., converted from two's complement to original code. When the two's complement is negative, then... When converting to original code, the sign bit remains unchanged, the value bits are inverted bit by bit and incremented by one. When the two's complement is positive, the two's complement is the original code. Then, the square root operation is performed on the squared sum of the converted data. The enable signal of the square root unit needs to be delayed. The maximum spectral value calculation unit is used to find the frequency point with the largest amplitude in the spectrum, which usually corresponds to the main carrier frequency of the signal. In this embodiment, the effective modulo signal is given to the enable signal of the maximum spectral value calculation unit, and then the counter starts counting. The result after modulo continuously updates the maximum value. Whenever the maximum value changes, the position (number) of the maximum spectral line also changes. The sampling frequency (F) of the system... s The FFT sampling frequency (F) is 50MHz, and the number of FFT sampling points (N) is 65536, meaning the output frequency (F) at this time is... out )for:

[0106]

[0107] The conversion unit is used to convert the main carrier frequency obtained by the maximum spectral value calculation unit into a DDS frequency control word, which is then provided to the carrier synchronization loop. In this embodiment, the relationship between the DDS frequency control word (M0) and the signal frequency is as follows:

[0108]

[0109] Where DDS_N is the phase accumulation word length of DDS, which is 38 bits. From formulas (1) and (2), the frequency control word can be obtained as follows:

[0110]

[0111] The FFT sampling points (N) are 65536, which can be represented as 2^16. In an FPGA, multiplication and division operations can be transformed into shift operations, reducing resources and speeding up the operation. That is, the frequency control word becomes:

[0112] M0 = (number-1) * 2 DDS_N-N = (number-1) << 22 (4)

[0113] like Figure 4 , Figure 5 The figure shows the frequency offset variation of the FFT carrier frequency estimation module under different signal-to-noise ratios (SNRs) in the low-frequency and mid-to-high-frequency ranges. As can be seen from the figure, the frequency offset remains constant across the entire frequency range with varying SNR, indicating that the module can maintain a relatively stable frequency estimation difference over a wide range of SNRs from 100dB to -25dB. Furthermore, it further demonstrates that the module's error rate is almost zero within the test range, meaning that the FFT carrier frequency estimation module can provide very accurate frequency estimates under these settings.

[0114] Specifically, due to the picket fence effect in the FFT algorithm, FFT can only capture a portion of discrete frequencies, resulting in a deviation from the actual frequency. After calculation, the resolution of FFT is 762.94Hz, meaning the maximum deviation between the frequency estimated by FFT and the actual frequency is 762.94Hz / 2 = 381.47Hz. Furthermore, below 381.47Hz, the estimated frequency is 0. To address this issue, the system internally sets the DDS frequency control word to 200Hz when the estimated frequency is 0, reducing the error caused by this effect. Figure 4 As shown, the maximum frequency shift in the low-frequency range is 4.633%, while... Figure 5 In the high-frequency range, the maximum frequency offset is 0.098%. This indicates that as the signal frequency decreases, the frequency estimation deviation of the FFT carrier frequency estimation module increases. In other words, the frequency offset of low-frequency signals is larger, which means that the subsequent carrier synchronization loop needs a longer time to lock. Conversely, in the high-frequency range, the frequency estimation error is smaller and has a relatively smaller impact on system performance.

[0115] In summary, although the FFT carrier frequency estimation module exhibits very good stability under different signal-to-noise ratios, the accuracy of frequency estimation is still affected by the signal frequency. The frequency estimation offset is relatively high in the low-frequency signal range, which also places greater demands on the subsequent carrier synchronization loop.

[0116] The carrier synchronization loop module is used to overcome the picket fence effect of the FFT carrier frequency estimation module. That is, FFT can only capture some discrete frequencies and cannot track frequencies between FFT transform spectral lines, which has certain defects. The carrier synchronization loop can generate a local reference signal that is in phase and frequency with the carrier of the weak signal under test, which can be used by the subsequent demodulator for demodulation. After FFT points to the vicinity of the carrier frequency, the carrier synchronization loop searches and achieves true carrier frequency synchronization, overcoming the picket fence effect limitation of simple FFT tracking and effectively eliminating the influence of frequency difference.

[0117] like Figure 6 The results shown are the test results of a single carrier synchronization loop at a sampling rate of 128kHz. The results indicate that the smaller the natural angular frequency coefficient, i.e. the smaller the loop filter coefficient, the smaller the steady-state phase difference after locking, and the more accurate the frequency tracking, but the longer the locking time. Conversely, the larger the steady-state phase difference, the shorter the locking time. When the coefficient changes, the loop first uses a large coefficient for fast locking, and then switches to a small coefficient for accurate tracking. In this way, both the steady-state phase difference and the locking time can be minimized, thus simultaneously meeting the requirements of fast locking and high accuracy.

[0118] To address the issue that a single carrier synchronization loop cannot simultaneously meet the requirements of fast locking, high dynamics, and high precision, and often suffers from insufficient response speed and low synchronization accuracy when facing rapidly changing signal conditions, especially in high-noise environments where the frequency synchronization process of the carrier synchronization loop may be affected by internal fixed coefficients, ultimately impacting its locking accuracy or even preventing locking altogether, this invention proposes a more flexible and efficient adaptive adjustment unit. This unit combines a two-stage dynamic threshold judgment and a three-stage coefficient adjustment mechanism, enabling precise adjustment in variable operating environments. Through this design, the system can automatically optimize and adjust across different frequency ranges, modifying the correlation coefficients of the low-pass filter and loop filter in real time, thereby ensuring accurate frequency synchronization in high-noise environments and over a wider frequency range.

[0119] A further implementation includes a carrier synchronization loop module comprising: an overall performance parameter design unit for determining the natural angular frequency (W). n The damping coefficient (ζ) is crucial because it is closely related to the loop filter coefficients (C1, C2) and the low-pass filter cutoff frequency; therefore, these two parameters need to be confirmed first. In this embodiment, the natural angular frequency is related to the one-sided noise bandwidth (B) of the carrier synchronization loop. LIt is related to the input signal-to-noise ratio:

[0120] The one-sided noise bandwidth reflects the carrier synchronization loop's ability to filter input noise. For an ideal second-order phase-locked loop, as shown in expression (5), the smaller the one-sided noise bandwidth, the smaller the output phase variance (σ) under Gaussian white noise input signal conditions.

[0121]

[0122] The curves of these three coefficients can be obtained from expression (6), as follows: Figure 7 As shown, this curve has a minimum value, namely when ζ = 0.5, the noise suppression capability is also optimal. However, considering that the smaller ζ is, the slower the system response speed and the longer the transient response, in engineering, ζ = 0.707 is usually selected, at which point BL = 0.53Wn, which is close to the minimum value.

[0123] The signal-to-noise ratio (SNR) of the carrier synchronization loop input is used to measure signal quality; it is the ratio of the input signal carrier power to the bandwidth (B) of the carrier synchronization loop preamplifier. i The ratio of the noise power of ) to the noise power of , that is:

[0124]

[0125] The signal-to-noise ratio (SNR) of the carrier synchronization loop directly determines the magnitude of phase jitter after locking, which can be expressed as the ratio of the input signal carrier power to the noise power of the single-sided noise bandwidth, i.e.:

[0126]

[0127] From expressions (7) and (8), the relationship between the carrier synchronization loop signal-to-noise ratio and the carrier synchronization loop input signal-to-noise ratio can be derived:

[0128]

[0129] From expressions (6) and (9), the relationship expression for natural angular frequency can be derived as follows:

[0130]

[0131] Because this carrier synchronization loop is a nonlinear system, it exhibits a threshold effect (threshold signal-to-noise ratio). In a carrier synchronization loop, an output phase error of 0.25 is typically used as the unlock threshold, meaning unlock occurs when the carrier synchronization loop signal-to-noise ratio is 6dB. When the input signal-to-noise ratio is set to 1dB, the preamplifier bandwidth is 25MHz, and the damping coefficient is 0.707, the upper limit of the natural angular frequency is 1251.128kHz; while the lower limit of the natural angular frequency is determined by the loop's fast capture band (W). L The determination is made by the expression:

[0132] ΔWL =2ζW n (11)

[0133] This allows us to obtain the range of the natural angular frequency and the value of the damping coefficient. Since the smaller the natural angular frequency, the lower the signal-to-noise ratio required for carrier synchronization loop locking, the smaller the steady-state phase difference after stabilization, and the longer the acquisition time; conversely, the higher the carrier synchronization loop fast acquisition bandwidth, the faster the acquisition. Therefore, in order to balance the steady-state phase difference and the fast acquisition bandwidth, a suitable value for the natural angular frequency needs to be selected, which will be adjusted during testing.

[0134] An adaptive adjustment unit is used to adjust the coefficients of the low-pass filter and the loop filter, as well as the stage adjustment mode of the carrier synchronization loop. In this embodiment, in order to adapt to a wide frequency range of 100Hz to 25MHz and to achieve the requirements of fast locking, high precision, and wide bandwidth when locking the input signal, its frequency is divided into 6 intervals.

[0135] like Figure 8 As shown, the system's stage adjustment mode, loop filter coefficients, and low-pass filter cutoff frequency vary for different frequency ranges to adapt to different operating frequencies and noise requirements. The stage adjustment state is divided into three modes: two-level fixed adjustment, two-level dynamic adjustment, and three-level dynamic adjustment. Each mode selects different loop coefficients according to the system's needs and current state. Within each level, there are fast locking state, slow tracking state, and precise tracking state to achieve efficient and accurate synchronous control in different frequency ranges.

[0136] In dynamic adjustment mode, the system analyzes the steady-state phase difference using a dual dynamic threshold judgment method to determine whether it has started to oscillate to a certain extent. The dual dynamic threshold judgment method mainly relies on real-time monitoring of phase deviation changes and determines whether it is in an oscillating state based on the amplitude and trend of the phase error.

[0137] After determining that the steady-state phase difference is oscillating using the dual dynamic threshold judgment method, the system analyzes whether it meets the conditions for entering the next level based on the relevant steady-state phase difference threshold. Especially under high noise and large frequency changes, the system can adjust its regulation mechanism based on the real-time feedback signal to ensure that the system is always in the optimal working state.

[0138] In the low-frequency band below 5kHz, the system also underwent noise analysis to avoid the impact of noise interference on system performance. The first-stage state coefficients (natural angular frequencies) were the same, but after a certain oscillation occurred due to a steady-state phase difference, if the highest value of the system oscillation reached the high noise threshold, it indicated that the system's locking effect was not ideal. In this case, the state coefficient of the second stage was dynamically increased. Increasing the state coefficient could increase the system's fast acquisition bandwidth, thereby improving the locking success rate and ensuring that the system could effectively resist high noise interference, thus maintaining a stable frequency synchronization state. Conversely, a lower state coefficient indicated an ideal locking effect, which could reduce the relevant loop coefficients, allowing the loop to enter a more accurate locking state.

[0139] The key to this process lies in balancing the fast acquisition bandwidth with system stability. It is necessary to ensure that the system can respond quickly to frequency changes while preventing false locking or frequency deviation caused by overly aggressive adjustments. Through this multi-level adjustment mechanism and a refined noise control strategy, the system can provide a more stable and efficient frequency synchronization solution under different operating conditions.

[0140] In this embodiment, the methods used above are divided into adaptive three-level adjustment and dual threshold oscillation judgment method: adaptive three-level adjustment method, such as... Figure 9 As shown, the system first obtains the frequency control word through the FFT carrier frequency estimation module, determines the frequency range of the signal, and sets the initial loop filter coefficients and the cutoff frequency of the low-pass filter based on this frequency, enabling the system to enter the first-level fast locking state. Next, a dual-threshold oscillation judgment method is used to detect whether steady-state phase difference oscillation occurs. When oscillation occurs, the system judges based on the maximum value of the steady-state phase difference: if the maximum value is less than threshold one, it switches to the third-level adjustment mode; if the maximum value is between threshold one and threshold two, it enters the second-level adjustment mode; if the maximum value is greater than threshold two, it remains in the first-level adjustment mode. If the signal meets the requirements for entering the third-level adjustment mode, the system will again apply the dual-threshold oscillation judgment method to detect whether steady-state phase difference oscillation occurs in the second-level slow tracking state. If the oscillation continues, the system will further enter the third-level precise tracking state to ensure accurate frequency synchronization. Through this hierarchical judgment and adjustment strategy, the system can dynamically adjust the control mode according to different frequency changes to achieve optimal frequency locking and stability.

[0141] Double threshold oscillation judgment method, such as Figure 10As shown, the acquisition process of a carrier synchronization loop typically includes two stages: a fast acquisition stage and a tracking stage. First, the system undergoes a fast acquisition stage, during which the steady-state phase difference varies significantly. When the reference signal frequency approaches the target signal, the tracking stage begins, and the steady-state phase difference exhibits an oscillating signal with fluctuating up and down. In simple terms, the steady-state phase difference first undergoes large fluctuations to approach the signal frequency, then enters a smaller fluctuation phase to maintain accurate signal tracking. During the fast acquisition stage, the system determines the maximum and minimum values ​​based on the steady-state phase difference and sets a first threshold. When these two thresholds meet a certain duration condition, the system enters the second threshold tracking stage. During tracking, if the second threshold condition is also met, an oscillation enable signal is output. Specifically, for low-frequency signals below 5kHz, when judged as high-noise signals, the system adjusts the duration of the second threshold to reduce the risk of an excessively long threshold preventing entry into the subsequent large-coefficient acquisition stage, thereby optimizing tracking performance.

[0142] The multiplier unit is used to multiply the received input signal under test with the reference carrier signal generated by the local DDS oscillator to generate low-frequency and high-frequency signals. As the frequency is continuously adjusted, the signal output by the multiplier will contain a DC component (related to phase synchronization) and a frequency doubling component (which needs to be filtered out). Through this multiplication process, the carrier frequency component can be extracted from the received signal and converted into a baseband signal.

[0143] The low-pass filter unit is used to filter out high-frequency components in the multiplier output signal and retain the DC component. The DC component is proportional to the phase shift of the carrier, so it can provide phase error information. Since this stage only needs to extract a single frequency carrier signal, the filter does not need to have a linear phase within its bandwidth. Under the same amplitude-frequency characteristic requirements, using an IIR filter can reduce more hardware resources.

[0144] In this embodiment, a Butterworth filter is used as the low-pass filter for this module for the following reasons: To meet performance requirements, the low-pass filter needs to ensure that the useful signal passes through completely while filtering out noise and interference as much as possible, especially to effectively suppress the harmonic components introduced by adjacent A / D mirror frequencies and digital down-conversion, and to ensure that the passband width is greater than the acquisition bandwidth of the carrier synchronization loop; according to Figure 11 As shown, for IIR filters of the same order, the filter designed using the ellip function performs best in terms of amplitude-frequency response, filter band, and stopband attenuation; while the IIR filter designed using the butter function has the flattest amplitude-frequency response in the passband. Given the flatness of the butter function in the passband, this unit chooses to use the butter filter for design.

[0145] like Figure 12As shown, the filter coefficients and output data word length amplitude-frequency response curves of the butter filter at a sampling rate of 50MHz, a cutoff frequency of 70kHz, and a filter order of 2 are displayed. It can be seen that when the quantization coefficients of the filter are 24 bits and the output data is 34 bits, its amplitude-frequency response curve basically coincides with the ideal output curve. Since the input data is 24 bits after being processed by the multiplier, when the low-pass filter output data is set to 34 bits, it indicates that the loop gain is increased by 1024 times. This not only ensures that the IIR filter maintains its optimal performance and improves the filter's accuracy and reduces quantization errors, but also significantly improves the resolution of the subsequent DDS oscillator, thereby enabling the DDS oscillator to generate more refined frequency modulation signals.

[0146] The loop filter unit is used to smooth the error voltage signal from the low-pass filter, remove high-frequency noise, and ensure that only low-frequency components are transmitted to the DDS oscillator unit. In this embodiment, the key to the loop filter design lies in obtaining the coefficients C1 and C2, which are mainly determined by the natural angular frequency, damping coefficient, and total gain (K). After transforming the system function of the analog carrier synchronization loop into the system function of the digital carrier synchronization loop using the bilinear transformation method and performing equality processing with the system function of the digital ideal second-order carrier synchronization loop, it is found that when W n When T<<1, its loop coefficients C1 and C2 can be expressed by the following expressions:

[0147]

[0148] In this embodiment, the overall performance parameter design unit has already obtained the natural angular frequency and damping coefficient. Currently, only the total gain needs to be calculated to obtain the loop coefficient; the expression for the total gain K is:

[0149]

[0150] Among them, T dds The DDS phase accumulator word update period is selected based on the following principle: the period should be greater than the total delay during the carrier synchronization loop operation, while being as short as possible to improve the correlation between the phase accumulator word and the input data. According to the simulation waveform results, T... dds Taking 8 data sampling periods is more reasonable; B lp This refers to the effective data bit width of the loop filter output. In this example, the loop filter output bit width is the same as the input data bit width, which is the output data bit width of the low-pass filter. Therefore, B lp =34; N is the word length of the DDS phase accumulation word. In engineering, K is usually chosen to be close to 1, at which time the carrier synchronization loop effect is the best. Based on this condition, the value of N can be deduced to be approximately 37.6, that is, N can be 38 bits. At this time, K≈0.7854, which is close to 1.

[0151] Based on these coefficients, the loop coefficients C1 and C2 can be calculated. To ensure the stable operation of the carrier synchronization loop, it is necessary to ensure that the digital carrier synchronization loop is a causal and stable system. According to the theory of discrete-time systems, the necessary and sufficient condition for the stability of a digital system is that all poles of the closed-loop function lie inside the unit circle. Figure 13 As shown, the left figure is the pole plot when the natural angular frequency is 100kHz, and the right figure is the pole table for all coefficients. By analyzing the pole positions corresponding to the coefficients of the loop filter, it is found that they are all located inside the unit circle, proving that the loop system is stable.

[0152] The DDS oscillator unit is used to generate high-precision, adjustable frequency signals. In this embodiment, by adjusting the input DDS frequency control word, the frequency of the output signal can be continuously changed, thereby achieving rapid frequency adjustment and phase locking.

[0153] In summary, the carrier synchronization loop, through its adaptive adjustment unit, can dynamically adjust the loop parameters to achieve high-precision carrier synchronization. This enables the system to effectively cope with signal changes and noise interference, maintaining stable and reliable synchronization performance. Figure 14 As shown, the error rate of the carrier synchronization loop under different frequency ranges and signal-to-noise ratios (SNRs) is plotted using the standard deviation of SEM, with the critical frequencies at both ends of each frequency range selected for testing. In the high SNR range of 100dB to 0dB, the error is controlled below 0.16595%, and in the low SNR range of 0dB to -25dB, the error is controlled below 0.44715%. Specifically, at frequencies from 1200Hz to 25MHz, the system can achieve frequency phase locking under SNR conditions of 100dB to -25dB, with locking errors less than 0.04585% in the 100dB to 0dB range and less than 0.44% in the 0dB to -25dB range. 715%; In the low-frequency band of 400Hz to 1200Hz, the system can achieve frequency phase locking under a signal-to-noise ratio of 100dB to -20dB, with a locking error of less than 0.0778% when the signal-to-noise ratio is 100dB to 0dB and less than 0.3283% when it is 0dB to -25dB; In the low-frequency band of 100Hz to 400Hz, the system can achieve frequency phase locking under a signal-to-noise ratio of 100dB to -6dB, with a locking error of less than 0.16595% when the signal-to-noise ratio is 100dB to 0dB and less than 0.2403% when it is 0dB to -6dB; Below 100Hz, due to the excessively high sampling rate, a loss of lock will occur.

[0154] After pre-processing by the FFT carrier frequency estimation module, the locking speed and accuracy of the entire frequency adaptive tracking module are significantly improved, and the error is correspondingly reduced. Figure 15As shown, the error rate of the entire frequency adaptive tracking module is displayed in different frequency ranges and with different signal-to-noise ratios. The plotting principle is the same as... Figure 14 Consistent; within the high signal-to-noise ratio range of 100dB to 0dB, the error is controlled below 0.0962%, and within the low signal-to-noise ratio range of 0dB to -25dB, the error is controlled below 0.3708%; compared with a single carrier synchronization loop, the error rates are reduced by 0.06975% and 0.07635% respectively, and the system accuracy is significantly improved.

[0155] like Figure 16 The figure shows the locking time required by the entire frequency adaptive tracking module in different frequency ranges and with different signal-to-noise ratios. The plotting principle is the same as... Figure 14 Consistent; in the high signal-to-noise ratio range of 100dB to 0dB, the lock time is controlled below 20.3ms, and in the low signal-to-noise ratio range of 0dB to -25dB, the lock time is controlled below 35.3ms; the simulation time of the FFT carrier frequency estimation unit is fixed at 5.3ms, so the time of the carrier synchronization loop unit is the total time minus the time of the FFT carrier frequency estimation unit; it can be found that when the frequency is above 400Hz and in the range of 100dB to 0dB, the overall lock time is less than 10ms, which greatly improves the lock time and accuracy compared with the traditional phase-locked loop.

[0156] A multi-rate narrowband low-pass filter module is used to gradually reduce the high sampling rate of the front-end ADC, achieving a narrowband filtering function of 0.1Hz within limited FPGA hardware resources. A further implementation involves the multi-rate narrowband low-pass filter module consisting of an integral comb filter unit, a half-band filter unit, and a low-pass filter unit. The integral comb filter unit decimates the high sampling rate signal from the front-end ADC by a factor of 2500. Due to its simple structure and lack of a multiplier unit, it is a zero-cancellation-based FIR filter, making it suitable for operation under high sampling rate conditions. In this embodiment, a three-stage CIC filter cascade method is used to achieve a 2500-fold decimation filter, reducing the 25MHz sampling rate to 20kHz. Figure 17 As shown, the attenuation of the first sidelobe level reaches 40.38 dB at this point. The stopband attenuation meets basic practical requirements and will not cause signal distortion due to excessive passband attenuation. Figure 18As shown, this is the basic structure of a three-stage CIC filter. It implements the Hogenauer decimation filter based on the transposition theorem and Noble's identity, greatly improving the system's processing speed and reducing resource consumption. The half-band filter unit is used to decimate the signal after the CIC filter by a factor of 2. In this example, a 6-stage cascade method is used to achieve a 64-fold decimation, reducing 20kHz to 312.5Hz. Because its transition band is often too large for the last stage of a multi-stage filter, it cannot meet the overall requirements of the filtering characteristics and is therefore unsuitable as the last stage of a multi-stage decimation filter. The low-pass filter unit is used to extract very low-frequency (around 0.1Hz) signal variations, remove high-frequency noise, and improve signal stability. In this example, the sampling rate of this unit has been reduced to 312.5Hz. At this point, using a low-pass filter with a transition band of [0.1, 2]Hz and a passband ripple of 0.001, the order only needs to be 1194, greatly reducing the FPGA's hardware resources.

[0157] In summary, MATLAB was used to analyze FPGA simulation test data, such as... Figure 19 As shown, this is a multi-rate narrowband low-pass filter module performing multi-rate filtering on 0.1, 500, 5000, and 50000Hz mixed signals at a 50MHz sampling rate. Due to the large amount of data, only half a cycle of the waveform is displayed. It can be seen that this module not only reduces the sampling rate but also filters the signal, and the final FIR output signal is a 0.1Hz undistorted standard signal. Figure 20 As shown, the simulation data of the multi-rate narrowband low-pass filter module performing analog lock-in amplifier operation on a 1MHz signal with a difference frequency of 0.05Hz at a sampling rate of 50MHz is shown. It can be found that the final FIR output signal exhibits an almost linear cross-correlation signal, from which the amplitude and phase of the signal can be calculated using the vector operation module.

[0158] The vector operation module is used to mathematically process the relationship between the weak test signal and the reference signal, effectively and accurately extracting the phase and amplitude from the weak test signal. A further implementation of this module involves a multiplier unit, an adder unit, a square root operation unit, and a Cordic operation unit: The multiplier unit performs the squaring operation on two cross-correlated signals; in this example, the FPGA's multiplier IP core is used for signed multiplication of the data. The adder unit performs the addition operation on the multiplier outputs. The square root operation unit calculates the amplitude of the input test signal; by extending the decimal places of the output bits, the accuracy of the amplitude result is effectively improved. The Cordic operation unit calculates the phase of the input test signal; in this example, the FPGA's Cordic IP core is used for data operation. The human-machine interaction module displays and stores the detection results, completing the acquisition of weak signals using a digital lock-in amplifier based on frequency adaptive technology.

[0159] In summary, the overall system was tested using MATLAB and FPGA code, with the weak signal under test being a 1MHz frequency signal with an amplitude of 2048 kHz. The first step involved relevant tests at the MATLAB software level, such as... Figure 21 As shown, within the high signal-to-noise ratio (SNR) range of 100dB to 0dB, the amplitude error is controlled below 0.02%, and the phase error is controlled below 0.04%, indicating that the system's accuracy performance is excellent under high SNR conditions. Within the low SNR range of 0dB to -25dB, the amplitude error is controlled below 0.05%, and the phase error is controlled below 0.3%. Although this is slightly higher than the high SNR range, it still remains within a reasonable error range. Figure 22 As shown in (a)-(f), the specific test results of amplitude and phase are further presented, thus more intuitively demonstrating the system's performance under different signal-to-noise ratios;

[0160] Then, relevant tests are performed at the FPGA hardware level, such as... Figure 23 As shown, within the high signal-to-noise ratio (SNR) range of 100dB to 0dB, the amplitude error is controlled below 0.03%, and the phase error is controlled below 0.7%. Within the low SNR range of 0dB to -25dB, the amplitude error is controlled below 0.07%, and the phase error is controlled below 1.8%. Compared to the MATLAB software-level test, the FPGA hardware-level error is slightly larger, but it still performs well under high SNR conditions. However, the amplitude and phase errors are more pronounced under low SNR conditions, especially in the phase aspect, where the error increases significantly.

[0161] The main reason for this difference is the finite word length effect of FPGA. Due to the bit width limitation during FPGA calculation, quantization error is introduced when processing high-precision signals, which affects the test results. In particular, the phase calculation is greatly affected by the finite word length, resulting in a significantly higher error than the software level. In MATLAB, because its software platform can handle high-precision floating-point operations, the error control is better.

[0162] Overall, although the FPGA is limited by hardware conditions, which leads to larger errors, it can still guarantee relatively accurate amplitude and phase measurement results at high signal-to-noise ratios. At low signal-to-noise ratios, the phase results are more affected, but still remain at a good level of accuracy. By optimizing the FPGA hardware design and further reducing the impact of the finite word length effect, it is expected to improve the system's accuracy performance at low signal-to-noise ratios.

[0163] In summary, this invention, through a dual tracking mechanism combining frequency domain analysis and carrier synchronization loop feedback control, enables the system to stably lock onto the target signal frequency even in noisy environments, effectively reducing phase errors. It also overcomes the limitations of traditional systems: conventional carrier synchronization loops often struggle to balance fast locking, high dynamic range, and high precision. This system, by introducing an adaptive adjustment unit, a two-stage dynamic threshold judgment mechanism, and a three-stage coefficient adjustment method, can adjust relevant parameters in the carrier synchronization loop in real time, enabling the system to accurately lock onto the target signal in a wide range of noise environments (from 100dB to -25dB), significantly improving the system's reliability and sensitivity in complex environments. To improve system bandwidth utilization and save hardware resources, this invention employs cascaded downsampling technology in multi-rate digital signal processing. By gradually reducing the sampling rate of the front-end ADC, this technology effectively reduces the system's bandwidth requirements, enabling the system to achieve narrowband filtering at 0.1Hz with lower resource consumption. This not only improves signal processing accuracy but also reduces the occupation of hardware resources such as FPGAs, making the system more efficient. In summary, this weak signal acquisition system combines advanced adaptive tracking, dynamic adjustment, and multi-rate downsampling technologies, possessing advantages such as strong noise immunity, high-precision locking, and resource saving. It can achieve efficient and accurate signal acquisition and processing in various signal environments.

[0164] This embodiment discloses a digital lock-in amplifier and a weak signal acquisition method based on frequency adaptive technology, applied to the above-mentioned system, including the following steps: Step 1: First, start the power supply module and initialize each module to its default settings to ensure normal system operation; Step 2: The weak signal to be measured first enters the front-end signal processing module, where the signal undergoes preliminary amplification and filtering through two stages of amplification circuits to improve the signal strength and quality, preparing for subsequent processing; Step 3: The amplified signal then enters the anti-aliasing filter and analog-to-digital conversion module. The anti-aliasing filter filters out high-frequency signals greater than half the system sampling frequency to ensure that the signal frequency range is suitable for sampling; the filtered analog signal is converted into a digital signal and sent to the FPGA for further processing; Step 4: The digital signal passes through an adaptive notch filter to remove 50Hz power frequency interference signals, improving the signal-to-noise ratio; once the data is valid, the system will raise the enable signal of the FFT carrier frequency estimation module to start spectral analysis of the signal; Step 5: The FFT carrier frequency estimation module performs spectrum analysis on the useful signal after removing the power frequency interference signal, obtains the maximum spectral value, converts it into a DDS frequency control word, and simultaneously raises the carrier synchronization loop enable signal. Step 6: The carrier synchronization loop uses the obtained DDS frequency control word to adaptively adjust the loop coefficients, allowing the reference signal to gradually synchronize with the weak signal under test until it stably locks onto the target frequency. Then, it raises the enable signals of the multiplier module and the multi-rate narrowband low-pass filter module. Step 7: The multi-rate narrowband low-pass filter module downsamples and low-pass filters the two multiplied signals (sine and cosine reference signals multiplied with the signal under test, respectively), obtains two cross-correlation functions, and raises the vector operation module. Step 8: The vector operation module processes the two cross-correlation functions to obtain the amplitude and phase of the weak signal under test, and raises the human-machine interaction module. Step 9: The human-machine interaction module transmits the amplitude and phase information obtained by the system to the QT host computer via Ethernet for display, and finally presents the processing results to the user.

[0165] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology, characterized in that, include: The front-end signal processing module is used to acquire weak signals to be tested, process the weak signals to be tested, and convert them into digital signals. The frequency adaptive tracking module is used to perform a fast Fourier transform on the frequency of the digital signal, extract the main frequency components in the signal, obtain the position of the maximum spectral line, and convert it into a direct digital frequency in the carrier synchronization loop. The direct digital frequency is synthesized into a frequency control word. Based on the frequency control word, a local reference signal with the same frequency and phase as the carrier of the weak signal under test is generated. At the same time, the coefficients of the low-pass filter and the loop filter and the stage adjustment mode of the carrier synchronization loop are adjusted. A multi-rate narrowband low-pass filter module is used to multiply the digital signal with the local reference signal and then filter and downsample the high-frequency signal to retain key information and obtain multiple mutually orthogonal difference frequency components. The vector operation module is used to perform vector operations on multiple mutually orthogonal difference frequency components to obtain the phase and amplitude of the weak signal under test; The human-computer interaction module is used to display and store the phase and amplitude of the weak signal under test.

2. The digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 1, characterized in that, The front-end signal processing module includes: The preamplifier circuit is used to suppress noise interference while performing preliminary amplification of the weak signal under test. The post-amplifier circuit is used to amplify the weak test signal after primary amplification and to provide the main gain of the system. Anti-aliasing filters are used to filter out signals that exceed the target sampling frequency; An analog-to-digital converter circuit is used to convert the filtered signal into the digital signal. The preamplifier circuit, the post-amplifier circuit, the anti-aliasing filter, and the analog-to-digital converter circuit are connected in sequence.

3. The digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 1, characterized in that, The frequency adaptive tracking module includes: The adaptive notch filter submodule is used to suppress interference signals at specific frequencies using the LMS algorithm, without losing other useful signals. At the same time, when there is a significant frequency difference between the target signal and the interference signal in the spectrum, the interference frequency is removed while other frequency components are preserved by adjusting the filter parameters. The Fast Fourier Transform (FFT) submodule is used to perform a Fast Fourier Transform on the digital signal frequency processed by the Adaptive Notch Filter (AFF) submodule, extract the main frequency components in the signal, obtain the position of the maximum spectral line, convert it into the direct digital frequency in the carrier synchronization loop, and synthesize the direct digital frequency into a frequency control word. The carrier synchronization loop submodule is used to generate a local reference signal that is in phase and frequency with the carrier of the weak signal under test according to the frequency control word, and to adjust the coefficients of the low-pass filter and the loop filter as well as the stage adjustment mode of the carrier synchronization loop.

4. The digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 3, characterized in that, The Fast Fourier Transform submodule includes: The FFT unit is used to perform a fast Fourier transform on the frequency of the digital signal processed by the adaptive notch filter submodule, converting the signal from the time domain to the frequency domain. The data modulus extraction unit is used to extract the modulus value of the spectrum in the frequency domain, obtain the strongest frequency component, and infer the carrier frequency; The maximum spectral line value calculation unit is used to obtain the frequency point with the largest amplitude in the spectrum while inferring the carrier frequency, and the frequency point is the main carrier frequency corresponding to the signal. The conversion unit converts the primary carrier frequency into a frequency control word: M0=(number-1)*2 DDS_N-N =(number-1)<<22 Where M0 is the DDS frequency control word, number is the position of the maximum spectral line, DDS_N is the phase accumulation word length of the DDS, and N is the number of FFT sampling points.

5. A digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 3, characterized in that, The carrier synchronization loop submodule includes: The overall performance parameter design unit is used to determine the natural angular frequency and damping coefficient; wherein, the natural angular frequency and damping coefficient are both related to the loop filter coefficient and the low-pass filter cutoff frequency; The expression for the natural angular frequency is determined as follows: Where ζ is the damping coefficient, (S / N) i The input signal carrier power and the bandwidth B before the carrier synchronization loop are given. i The ratio of noise power (S / N) L It is the ratio of the input signal carrier power to the noise power of the one-sided noise bandwidth; The lower limit expression for the natural angular frequency is determined as follows: ΔW L =2ζW n Among them, W n It is the natural angular frequency; The adaptive adjustment unit is used to determine the frequency range of the signal through the frequency control word, and set the initial loop filter coefficients and the cutoff frequency of the low-pass filter according to the frequency range, thereby entering the first-level fast locking state. It further employs a dual-threshold oscillation judgment method to detect whether steady-state phase difference oscillates. When oscillation occurs, it judges based on the maximum value of the steady-state phase difference. If the maximum value is less than threshold one, the loop filter coefficients are switched to the third-level adjustment mode. If the maximum value is between threshold one and threshold two, the loop filter coefficients are switched to the second-level adjustment mode. If the maximum value is greater than threshold two, the loop filter coefficients are maintained in the first-level adjustment mode. When switching to the third-level adjustment mode, the dual-threshold oscillation judgment method is applied again in the second-level slow tracking state to detect whether steady-state phase difference oscillation occurs. If the oscillation continues, it further enters the third-level precise tracking state, thereby maintaining optimal frequency locking.

6. The digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 5, characterized in that, The method of detecting steady-state phase difference using a dual-threshold oscillation judgment includes: When the carrier synchronization loop captures the signal, it goes through the fast acquisition process and the tracking process in sequence, that is, the steady-state phase difference presents an oscillating signal with up and down fluctuations. During the fast acquisition process, the maximum and minimum values ​​of the steady-state phase difference are determined based on the coefficient of the steady-state phase difference. After the maximum and minimum values ​​of the fast acquisition process have been sustained for a first target time, the tracking process begins. During the tracking process, the maximum and minimum values ​​of the tracking process are determined based on the coefficient of the steady-state phase difference. After the maximum and minimum values ​​of the tracking process have been sustained for a second target time, an oscillation enable signal is output to determine whether the steady-state phase difference oscillates.

7. A digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 5, characterized in that, The carrier synchronization loop submodule also includes: The multiplier unit is used to multiply the received output signal of the adaptive notch filter submodule with the reference carrier signal generated by the local DDS oscillator to generate low-frequency and high-frequency signals. As the frequency is continuously adjusted, a signal containing DC component and frequency doubling is obtained. Based on the signal containing DC component and frequency doubling, the carrier frequency component is extracted from the input signal under test, and the carrier frequency component is converted into a baseband signal. A low-pass filter unit is used to filter out high-frequency components in the baseband signal, retain DC components, and obtain phase error information based on DC components; The loop filter unit is used to smooth the error voltage signal of the low-pass filter, remove high-frequency noise, and retain low-frequency components; The DDS oscillator unit is used to generate a high-precision, adjustable frequency signal based on the low-frequency components, namely a local reference signal that is in phase and frequency with the carrier of the weak signal under test.

8. A digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 1, characterized in that, The multi-rate narrowband low-pass filter module includes: The integral combing filter unit is used to extract the high sampling rate signal of the analog-to-digital conversion circuit by a first target multiple, and reduce the original sampling rate of the integral combing filter to the first target sampling rate. A half-band filter unit is used to extract the signal after extraction by the integral comb filter unit according to a second target multiple, thereby reducing the original sampling rate of the half-band filter to the second target sampling rate. The low-pass filter unit is used to extract signal changes below the low-frequency threshold and remove high-frequency noise. At the same time, the sampling rate of the low-pass filter has been reduced to the third target sampling rate to achieve a narrowband low-pass filtering function of 0.1Hz.

9. A digital lock-in amplifier and weak signal acquisition system based on frequency adaptive technology according to claim 1, characterized in that, The vector operation module includes: The amplitude calculation unit is used to perform a vector operation of taking the square root of the sum of squares of multiple mutually orthogonal difference frequency components to obtain a DC result that is proportional to the amplitude of the external modulation signal under test, thereby demodulating the amplitude of the weak signal under test. The phase operation unit is used to divide the multiple mutually orthogonal difference frequency components, calculate their arctangent, and then make appropriate adjustments according to the positive and negative relationship between the internal divisor and dividend to obtain the phase of the weak signal under test.

10. A digital lock-in amplifier and a weak signal acquisition method based on frequency adaptive technology, characterized in that, include: A weak test signal is acquired, processed, and converted into a digital signal. A fast Fourier transform is performed on the frequency of the digital signal to extract the main frequency components, obtain the position of the maximum spectral line, and convert it into a direct digital frequency in the carrier synchronization loop. The direct digital frequency is synthesized into a frequency control word. Based on the frequency control word, a local reference signal with the same frequency and phase as the carrier of the weak test signal is generated. At the same time, the coefficients of the low-pass filter and the loop filter, as well as the stage adjustment mode of the carrier synchronization loop, are adjusted. The digital signal is multiplied by the local reference signal, and then filtered and downsampled for high frequency to retain key information and obtain multiple mutually orthogonal difference frequency components. Vector operations are performed on the multiple mutually orthogonal difference frequency components to obtain the phase and amplitude of the weak test signal. The phase and amplitude of the weak test signal are then displayed and stored.

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