Excessive delay compensation circuit and method of band-pass ADC based on N-path filter
By introducing a delay chain and a delay path selection unit in a bandpass Delta-Sigma ADC based on N path filter, the control code is used to regulate signal delay, and the excessive loop delay problem is solved and the performance of the ADC is improved.
Patent Information
- Application Number
- CN202510227652.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-06-17
AI Technical Summary
The bandpass Delta-Sigma ADC based on N-path filters has excessive loop delay problems, resulting in reduced system stability and noise shaping capabilities.
An excessive delay compensation circuit and method for bandpass ADC based on an N-path filter is proposed. The controllable delay of the input signal is realized through the delay chain and the delay path selection unit, and the number of delay units through which the signal is passed is determined by using the control code to regulate the delay.
High-precision control of the delay time length of the quantized signal to the feedback DAC is realized, and loop delay is accurately adjusted, which significantly improves the overall performance of the ADC.
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Figure CN120165689A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog-to-digital converters (ADCs), and particularly to an excessive delay compensation circuit and method for a band-pass ADC based on an N-path filter. Background Art
[0002] The passive N-path filter has advantages such as low power consumption, adjustable center frequency, high Q value, and good CMOS process compatibility. By utilizing its high-Q resonance and band-pass characteristics, replacing the traditional active resonator with a passive N-path filter can reduce the power consumption of the loop filter, realize the direct digitization of intermediate-frequency or radio-frequency signals, and provide a flexible and efficient solution for analog front-end design.
[0003] The typical structure of the passive N-path filter and the N-phase clock waveform for controlling it are respectively as Figure 1 shown in (a) and (b) therein. Each path consists of a switch and a capacitor C i (i = 1, 2,..., N), the switch sizes of each path are equal, the capacitor sizes are also equal, and all paths share a resistor R at the input end. The switch of each path is controlled by an N-phase clock P1 to P s = 1 / T s with a frequency of f N The time constant RC of each path i is much larger than the clock period T s , that is, RC i >> T s . Particularly, taking the structure of a sixth-order band-pass Delta-Sigma analog-to-digital converter (ADC) based on a passive 4-path filter as an example, as Figure 2a shown, the control timing waveform is as Figure 2b shown. In this structure, the passive 4-path filter controlled by the four-phase clock P1 to P4 serves as the resonator for each stage. The four-phase clock P1 to P4 has a repetition frequency of f s , and an operational trans-conductance amplifier (OTA) is inserted between adjacent two stages. On the one hand, it is to avoid the inter-stage load effect of the passive circuit, and on the other hand, it provides sufficient loop gain for the Delta-Sigma ADC. After the differential input signals V IP , V IN are processed by cascading three stages of resonators, the output of the last stage is sampled and quantized by a single-bit quantizer at a frequency of 4f s before the falling edge of each phase clock period, generating differential output signals V OP , V ONNote that for a general bandpass Delta-Sigma ADC based on an N-path filter, the sampling frequency is N*f s , taking 4 paths as an example here, so the sampling frequency is 4f s . The sampling frequency is related to the number of paths N and has nothing to do with the order of the Delta-sigma structure. The 4 D flip-flops (Data Flip-Flop, DFF) cascaded after the quantizer delay the quantization result by (7 / 8)T s . (3 / 4)T s The delay is to ensure that the quantization output of each capacitor unit in the previous clock cycle is fed back to the corresponding capacitor (for a general passive N-path filter as a resonator, (N - 1 / N)T s delay is required. The fixed delay is related to the number of paths N and has nothing to do with the order of the Delta-sigma structure, so it is applicable to 2nd-order, 4th-order or higher-order bandpass ADCs). In addition, the resistor R fi (i = 1, 2, 3) serves as a Return to Zero Digital-to-Analog Converter (RZ DAC) to provide feedback for the loop, which requires (1 / 8)T s delay (for a general structure, RZ feedback requires (1 / 2N)T s delay), so a total inherent (7 / 8)T s delay is required (for a general structure, it is ((2N - 1) / 2N)T s delay). For a continuous-time Delta-Sigma ADC, there is always a delay in the circuit implementation process. The time from the feedback of the quantization result to the next in-phase clock cycle usually exceeds (7 / 8)T s (for a general structure, it is ((2N - 1) / 2N)T s ), so there is a problem of excess loop delay (ELD) in the entire system. ELD will reduce the stability of the system and affect the noise shaping ability of the system. Therefore, it is urgent to propose an ELD compensation technology to mitigate the impact of excess delay of the bandpass Delta-Sigma ADC based on an N-path filter. Summary of the Invention
[0004] The main purpose of the present invention is to propose an excess delay compensation circuit and method for a bandpass ADC based on an N-path filter to solve the problem that the loop delay exceeds the expected value caused by the propagation delay introduced by circuit elements during actual operation, aiming at the excess loop delay problem faced by the bandpass Delta-Sigma ADC based on an N-path filter.
[0005] To achieve the above object, an excessive delay compensation circuit for a band-pass ADC based on an N-path filter according to an aspect of the present invention includes: a delay chain including a plurality of serially connected delay units; a delay path selection unit configured to determine the number of delay units that the input of the excessive delay compensation circuit needs to pass through during transmission according to a control code, so as to achieve: regulating the delay from the input to the output of the excessive delay compensation circuit by the passed delay units.
[0006] Further, the control code includes: 2 M extended full codes generated by an M-bit input short code through an M-to-2 M decoder; the delay path selection unit includes 2 M transmission gates, the number of transmission gates is 1 more than the number of delay units, wherein the first transmission gate is connected between the input and the output of the excessive delay compensation circuit, and the remaining 2 M -1 transmission gates are respectively connected between the outputs of 2 M -1 delay units and the output of the excessive delay compensation circuit; configuring the states of the 2 M transmission gates according to the 2 M extended full codes to determine the number of delay units that the input of the excessive delay compensation circuit needs to pass through during transmission.
[0007] Further, the delay chain further includes: an output inverter pair connected between the output of the delay path selection unit and the output of the excessive delay compensation circuit, for ensuring a preset minimum delay and improving the driving ability.
[0008] Further, the delay unit is implemented by an inverter pair and a load capacitor, and the delay provided by each delay unit is determined by the aspect ratio of the inverter pair, the operating voltage, and the value of the connected load capacitor of the delay unit.
[0009] Further, the delay unit is implemented by a 555 timer or an RC delay network.
[0010] Another aspect of the present invention proposes an excess delay compensation method for a bandpass ADC based on an N-path filter, which is used to apply a controllable timing delay to the signal path from the output of a single-bit quantizer to a feedback DAC in the bandpass ADC. The method includes: applying a first control timing and a second control timing to the last D flip-flop of N D flip-flops cascaded at the output end of the single-bit quantizer and any one of the remaining N-1 D flip-flops, respectively, wherein the rising edge of the first control timing is ahead of the rising edge of the second control timing, and the advance time is used to compensate for the propagation delay of the last D flip-flop and the delay of the buffer of the feedback DAC; wherein the first control timing and the second control timing are obtained by respectively performing a first delay and a second delay on the main clock signal of the bandpass ADC by the excess delay compensation circuit described in any one of claims 1 to 6.
[0011] Furthermore, the advance time does not exceed T s / N,T s is the clock period of the bandpass ADC.
[0012] Further, the first delay is performed on the master clock signal by the excess delay compensation circuit to obtain the first control timing, including: using the M-bit first input short code through M to 2 M The decoder generates 2 M The method comprises: using a first extended full code to control the number of delay units that the master clock signal needs to pass through in the excess delay compensation circuit to adjust the duration of the first delay; performing the second delay on the master clock signal through the excess delay compensation circuit to obtain the second control timing, including: using a second input short code of M bits through M to 2 M The decoder generates 2 M A second extended full code controls the number of delay units that the main clock signal needs to pass through in the excess delay compensation circuit to adjust the duration of the second delay.
[0013] Furthermore, the excess delay compensation method further comprises: performing an online fast Fourier transform test using automatic testing equipment to determine an optimal control code that minimizes in-band noise.
[0014] The present invention further proposes a bandpass ADC based on an N-path filter, comprising the aforementioned excess delay compensation circuit; among the N D flip-flops of the bandpass ADC, the control timing of the last D flip-flop and any one of the remaining N-1 D flip-flops is obtained by the excess delay compensation circuit according to the aforementioned excess delay compensation method.
[0015] The beneficial effects of the technical solution of the present invention are embodied in:
[0016] 1) By adopting the digitally programmable excessive delay compensation circuit of the present invention, high-precision control over the delay time length from the quantization signal to the feedback DAC can be achieved, which helps to precisely adjust the loop delay in the band-pass Delta-Sigma ADC based on the N-path filter, thereby significantly improving the overall performance of the ADC.
[0017] 2) The excessive delay compensation method proposed by the present invention generates two independently adjustable clock signals based on the proposed digitally programmable excessive delay compensation circuit, and applies controllable timing delays to the signal path from the single-bit quantizer output to the feedback DAC through these clock signals, thereby effectively adjusting the signal propagation timing within the loop to achieve precise compensation for the overall loop delay.
[0018] 3) The digitally programmable excessive delay compensation circuit and its compensation method proposed by the present invention are applicable to band-pass Delta-sigma ADCs based on N-path filters from the second order to higher orders, and have wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is the typical structure of a passive N-path filter and the N-phase clock waveform for controlling it.
[0020] Figure 2a is a schematic structural diagram of a sixth-order band-pass Delta-Sigma ADC based on a passive 4-path filter, Figure 2b is the control timing waveform of this structure.
[0021] Figure 3 is the excessive delay compensation circuit of the band-pass ADC based on the N-path filter according to the embodiment of the present invention.
[0022] Figure 4 is the timing control diagram provided to the DFF when the excessive delay compensation method of the embodiment of the present invention is applied in a band-pass ADC based on a 4-path filter. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0023] The present invention will be further described below in conjunction with the accompanying drawings, specific embodiments, and examples. The purpose of providing the examples is only for illustration and not for any limitation.
[0024] An excessive delay compensation circuit (hereinafter referred to as "delay compensation circuit") for a band-pass ADC based on an N-path filter is proposed in an embodiment of the present invention. The delay from the input to the output of this delay compensation circuit is precisely regulated by 2 extended full codes generated by an M-bit input short code input externally through an M to 2 M decoder. Please refer to M This compensation circuit includes 2 Figure 3 connected in series after the input IN. M-1 delay unit and 2 M transmission gates, and the 2 M transmission gates TG(0), TG(1), …, TG(2 M -1) can form a delay path selection unit, which is used to determine the number of delay units that the input of the delay compensation circuit needs to pass through during transmission according to 2 M extended full codes, so as to achieve: regulating the delay from the input to the output of the delay compensation circuit by the delay units passed through by the input. Specifically, among the 2 M transmission gates, the first transmission gate TG(0) is connected between the input IN and the output OUT of the delay compensation circuit, and the remaining 2 M -1 transmission gates are respectively connected between the outputs of 2 M -1 delay units and the output OUT of the delay compensation circuit. In some preferred embodiments, in order to ensure a certain minimum delay and improve the driving ability, an inverter pair 100 is added before the output OUT. In this way, the first transmission gate TG(0) is connected between the input IN of the delay compensation circuit and the inverter pair 100, and the remaining 2 M -1 transmission gates are respectively connected between the outputs of 2 M -1 delay units and the inverter pair 100. In the embodiments of the present invention, the states of the 2 M transmission gates can be configured according to 2 M extended full codes to determine the number of delay units that the input of the excessive delay compensation circuit needs to pass through during transmission, and further regulate the delay from the input to the output.
[0025] As Figure 3 shown, in some specific embodiments, the delay unit is implemented by an inverter pair and a load capacitor C, and the delay provided by each delay unit is determined by the aspect ratio of the inverter pair of the delay unit, the operating voltage VDD (VDD is the operating voltage, and VSS is generally the power ground), and the value of the connected load capacitor. In other embodiments, the delay unit can be implemented by an RC delay network or other common delay unit circuits (such as a 555 timer, etc.). The above is only an example, and the present invention does not limit the specific implementation circuit of the delay unit. In some embodiments, a pluggable delay unit is designed to allow users to replace or upgrade the delay unit according to needs, improving the maintainability and upgradability of the circuit.
[0026] As Figure 3As shown, in some specific embodiments, the transmission gate is implemented using NMOS and PMOS. A high-level signal can turn on the NMOS, and a low-level signal can turn on the PMOS. Taking M = 3 as an example, if the 3-bit input short code is 000, after passing through the 3-to-8 decoder, the generated extended full code A[0] will be set to the high level "1", and the corresponding complementary code ~A[0] will be at the low level (while the other extended full codes will still be at the low level, and the corresponding complementary codes will be at the high level, and the corresponding transmission gates will be closed). Then, the transmission gate TG(0) will conduct, and the input IN will be directly transmitted through the transmission gate TG(0) to the inverter pair 100 and then reach the output OUT. In this case, the input IN does not pass through the delay unit, and the delay compensation circuit is equivalent to a buffer at this time. If the 3-bit input short code is 111, the transmission gate TG(7) will conduct, and the other transmission gates will be closed. In this case, the input signal IN must pass through 7 delay units, then be propagated through the transmission gate TG(7) to the inverter pair 100, and finally reach the output OUT. At this time, the delay from the input IN to the output OUT is the cumulative delay of the 7 delay units passed through.
[0027] It should be noted that the delays provided by each delay unit can be the same, that is, the delay intervals are in arithmetic progression; they can also be different, that is, the delay intervals are not in arithmetic progression. If an arithmetic progression interval design is adopted, higher-resolution delay control can be provided by increasing the number of bits of the input short code. Because when the maximum delay (determined by the actual circuit requirements) is certain, for example, divided into 8 parts (3-bit input short code) and divided into 16 parts (4-bit input short code) for adjustment, the accuracy of the latter is higher. If a non-arithmetic progression design is adopted, the functions of coarse adjustment and fine adjustment can be realized. Taking a 3-bit input short code as an example, there are a total of 7 delay units. Assuming that the first 3 delay units are designed to be the same, and the delay intervals are all Ts / 16, and the latter 4 delay units are designed to be the same, and the delay intervals are all Ts / 32, then the latter 4 delay units can achieve fine adjustment relative to the first 3 delay units. The above is only an example, which is only used to illustrate that the delay compensation circuit of the embodiment of the present invention has the above functions and does not constitute a limitation on the circuit structure.
[0028] In summary, the embodiment of the present invention proposes a digitally programmable excessive delay compensation circuit for the excessive loop delay problem faced by the band-pass Delta-Sigma ADC based on the N-path filter. The key of this circuit lies in: ① The delay time of each delay unit is known (set by the device parameters and working parameters of the delay unit), and by combining different numbers of delay units, very precise delay control can be achieved; ② The control logic of the digital code, using digital logic codes to control the number of signal passing through the delay units, realizes a high degree of programmability. The implementation process can be illustrated by the following example:
[0029] a. The input signal arrives at the input terminal of the delay compensation circuit;
[0030] b. The digital control code is set to determine the required delay time. For example, if the input short code A[2:0] is set to 111, it means the signal needs to pass through 7 delay units;
[0031] c. The signal first passes through the first delay unit and experiences one delay;
[0032] d. The signal after experiencing the first delay is transmitted to the second delay unit;
[0033] e. This process continues until the signal has passed through all the delay units selected by the digital control code;
[0034] f. Finally, the signal is output from the last selected delay unit, passes through the last inverter pair and is output from the output terminal OUT. At this time, the signal has experienced the preset delay time.
[0035] Applying the digital programmable delay compensation circuit of the foregoing embodiment to a band-pass Delta-Sigma ADC based on an N-path filter (for example Figure 2a the sixth-order band-pass Delta-Sigma ADC of the passive 4-path filter shown), a method for compensating excessive delay of a band-pass ADC based on an N-path filter is proposed, which is used to apply a controllable timing delay to the signal path from the output of the single-bit quantizer 10 to the feedback DAC ( Figure 2a in the example structure, the feedback DAC is the resistor R fi (i = 1, 2, 3)).
[0036] The method for compensating excessive delay of a band-pass ADC based on an N-path filter proposed in the embodiment of the present invention includes: applying a first control timing and a second control timing to the last D flip-flop (DFF) and any one of the remaining N - 1 D flip-flops among the N D flip-flops (DFFs) cascaded at the output terminal of the single-bit quantizer respectively. The rising edge of the first control timing is ahead of the rising edge of the second control timing, and the advanced duration is used to compensate for the propagation delay of the last D flip-flop and the delay of the buffer of the feedback DAC; wherein, the first control timing and the second control timing are obtained by respectively performing a first delay and a second delay on the main clock signal of the band-pass ADC by the delay compensation circuit of the foregoing embodiment.
[0037] Still taking Figure 2a the structure of the sixth-order band-pass Delta-Sigma ADC based on the passive 4-path filter shown as an example, an exemplary implementation process of the above method is as follows: for the problem of loop excessive delay, in order to compensate for the delay in the loop, the control timings of the last two DFFs are set as Figure 4As shown, the control timing of the last DFF is the clock signal CKB2, and the control timing of the penultimate DFF is the clock signal CKB'. Both the clock signals CKB2 and CKB' are obtained by delaying the master clock signal CK. Therefore, the rising edge arrival times of CKB2 and CKB' can be controlled by adjusting the delay length, that is, the enabling times of the corresponding feedback DACs can be controlled. In the embodiment of the present invention, the rising edge of the clock signal CKB2 is slightly ahead of CKB', and this advanced time is used to compensate for the propagation delay of the last DFF and the delay of the buffer driving the DAC. Generally, this advanced time does not exceed T s / N, T s is the clock period of the band-pass ADC.
[0038] Both the clock signals CKB2 and CKB' are obtained by delaying the master clock CK by a certain amount. Different delays are applied to CK to obtain the above two clock signals CKB2 and CKB', which are implemented by using the delay compensation circuit in the foregoing embodiment. In an exemplary implementation, the delay lengths of the clock signals CKB2 and CKB' relative to the master clock CK are controlled by 3-bit input short codes A[2:0] and B[2:0] respectively, corresponding to 8 extended full codes used to configure the states of 8 transmission gates. That is, the number of delay units that the master clock signal CK needs to pass through in the excessive delay compensation circuit is controlled by the first extended full code generated by the 3-bit first input short code A[2:0] through a 3-to-8 decoder, so as to adjust the duration of the first delay and obtain the clock signal CKB2. Additionally, the number of delay units that the master clock signal CK needs to pass through in the excessive delay compensation circuit is controlled by the second extended full code generated by the 3-bit second input short code B[2:0] through a 3-to-8 decoder, so as to adjust the duration of the second delay and obtain the clock signal CKB'. In fact, there are 8 extended full codes for the 3-bit input short code that can control the propagation time of the quantization signal from the second DFF to the third DFF (i.e., the penultimate DFF), thus realizing the control of the entire loop delay time and avoiding the situation of excessive loop delay. It should be understood that more bits of input short codes can also be used to achieve more precise control. A[2:0] and B[2:0] can use delay chains designed with the same parameters, or delay chains designed with different parameters according to the actual circuit situation.
[0039] It should be understood that the foregoing M = 3-bit input short code is only exemplary. Those skilled in the art should know that input short codes with, for example, M = 2, M = 4 or other numbers of bits can also be used.
[0040] In some preferred embodiments, an automatic test equipment with an online FFT function can be used to perform an online fast Fourier transform test to determine the optimal control code for minimizing in-band noise, ensuring the robustness performance of the system and effective ELD compensation. For example, the two delay lengths corresponding to the two code values when the in-band noise is minimized obtained through testing correspond to the delays of the clock signals CKB2 and CKB' relative to CK. The general process of using the automatic test equipment to perform an online fast Fourier transform test to determine the optimal control code in the embodiments of the present invention includes: performing FFT on the test data, removing the signal components, only calculating the in-band noise, and then traversing all the code values of the ELD trimming to determine the minimum in-band noise energy, and the code value corresponding to the minimum in-band noise energy is the optimal control code. In this way, the above tests can be performed separately to obtain the optimal control code for the first input short code and the optimal control code for the second input short code respectively.
[0041] The control logic of the delay compensation circuit of the present invention essentially is: the digital control code determines the number of delay units that the clock signal passes through from input to output, and thus determines the delay length of CKB' / CKB2 relative to CK. By adopting the digitally programmable delay compensation circuit of the embodiments of the present invention, high-precision control of the delay time length from the quantization signal to the feedback DAC can be achieved. This helps to accurately adjust the loop delay in the band-pass Delta-Sigma ADC based on the N-path filter, thereby significantly improving the overall performance of the ADC. The technical solution of the present invention is not only applicable to the band-pass Delta-Sigma ADC based on the N-path filter, but also can be extended and applied to other technical fields that require precise delay control, such as wireless communication, digital signal processing, and autonomous driving systems, etc. In addition, it can be used for:
[0042] (1) Radar and sonar systems: controlling the delay of pulse signals for accurate distance measurement and target positioning.
[0043] (2) High-speed data acquisition systems: adjusting the sampling clock to match the speeds and timings of different data sources.
[0044] (3) Test and measurement equipment: used for calibrating the time base and signal path in oscilloscopes and other measurement equipment.
[0045] The digital programmable delay compensation circuit and corresponding compensation method of the present invention provide a more flexible, precise and easily implementable solution. It can effectively solve the excessive loop delay problem for the specific requirements of the bandpass Delta-Sigma ADC based on the N-path filter, thereby improving the overall ADC performance. By fine-tuning the configuration of the digital programmable delay circuit, the phase of the clock signal can be dynamically adjusted, which in turn affects the propagation time of the quantization signal in the loop. This timing adjustment mechanism allows circuit designers to optimize the loop delay according to specific application requirements and circuit characteristics, so as to maintain the performance indicators of the ADC system, such as linearity, bandwidth and stability, while reducing signal distortion and system performance degradation caused by excessive loop delay.
[0046] As mentioned above, for the bandpass Delta-Sigma ADC based on the N-path filter, the present invention is a continuous-time ADC design at the forefront of academic research. Its unique structure and working principle make it difficult to directly apply traditional delay compensation methods or the effects are limited. In this context, the digital programmable delay compensation circuit and its compensation method proposed by the present invention represent the first innovative solution to the excessive delay problem of the bandpass ADC based on the N-path filter.
[0047] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those skilled in the technical field to which the present invention belongs, without departing from the concept of the present invention, several equivalent substitutions or obvious variations can be made, and as long as the performance or use is the same, they should all be regarded as belonging to the protection scope of the present invention.
Claims
1. An excess delay compensation circuit for a bandpass ADC based on an N-path filter, characterized in that: include: A delay chain, which includes a number of delay cells connected in series; The delay path selection unit is used to determine the number of delay units that the input of the excess delay compensation circuit needs to pass through during transmission according to the control code, so as to achieve: regulating the delay from the input to the output of the excess delay compensation circuit through the delay units passed through.
2. The excess delay compensation circuit according to claim 1, wherein: The control code includes: an M-bit input short code via M to 2 M The decoder generates 2 M An extended full code; The delay path selection unit comprises 2 M The number of transmission gates is one more than the number of delay units, wherein the first transmission gate is connected between the input and output of the excess delay compensation circuit, and the remaining two transmission gates are connected between the input and output of the excess delay compensation circuit. M -1 transmission gate connected to 2 M - between the output of one delay unit and the output of the excess delay compensation circuit; According to 2 M An extended full code to configure the 2 M The state of a transmission gate is used to determine the number of delay units that the input of the excess delay compensation circuit needs to pass through during the transmission process.
3. The excess delay compensation circuit according to claim 1, wherein: The delay chain further includes: an output inverter pair connected between the output of the delay path selection unit and the output of the excess delay compensation circuit, for ensuring a preset shortest delay and improving driving capability.
4. The excess delay compensation circuit according to claim 1, wherein: The delay unit is implemented by an inverter pair and a load capacitor, and the delay provided by each delay unit is determined by the width-to-length ratio of the inverter pair of the delay unit, the operating voltage, and the connected load capacitor value.
5. The excess delay compensation circuit according to claim 1, wherein: The delay unit is implemented by using a 555 timer or an RC delay network.
6. A method for compensating excess delay of a bandpass ADC based on an N-path filter, characterized in that: For applying a controllable timing delay to a signal path from a single-bit quantizer output to a feedback DAC in the bandpass ADC, the method comprising: A first control timing and a second control timing are applied to the last D flip-flop of the N D flip-flops cascaded at the output end of the single-bit quantizer and any one of the remaining N-1 D flip-flops, respectively, wherein the rising edge of the first control timing is ahead of the rising edge of the second control timing, and the advance time is used to compensate for the propagation delay of the last D flip-flop and the delay of the buffer of the feedback DAC; wherein the first control timing and the second control timing are obtained by respectively performing a first delay and a second delay on the main clock signal of the bandpass ADC by the excess delay compensation circuit described in any one of claims 1 to 5.
7. The excess delay compensation method according to claim 6, wherein: The advance time does not exceed T s / N,T s is the clock period of the bandpass ADC.
8. The excess delay compensation method according to claim 6, wherein: The first control timing is obtained by performing the first delay on the master clock signal through the excess delay compensation circuit, including: using the M-bit first input short code through M to 2 M The decoder generates 2 M A first extended full code controls the number of delay units that the main clock signal needs to pass through in the excess delay compensation circuit, so as to adjust the duration of the first delay; The second delay is performed on the master clock signal by the excess delay compensation circuit to obtain the second control timing, including: using the second input short code of M bits through M to 2 M The decoder generates 2 M A second extended full code controls the number of delay units that the main clock signal needs to pass through in the excess delay compensation circuit to adjust the duration of the second delay.
9. The method for compensating excess delay as claimed in claim 8, wherein: Also includes: Online Fast Fourier Transform testing is performed using automatic test equipment to determine the optimal control code that minimizes in-band noise.
10. A bandpass ADC based on an N-path filter, characterized in that: It includes the excess delay compensation circuit as described in any one of claims 1-5; among the N D flip-flops of the passband ADC, the control timing of the last D flip-flop and any one of the remaining N-1 D flip-flops is obtained by the excess delay compensation circuit according to the excess delay compensation method as described in any one of claims 6-9.