LDPC code construction method, device, terminal equipment and storage medium for flash memory

Abstract

The present application relates to the field of flash memory control technology, and in particular to a flash memory LDPC code construction method, device, terminal device and storage medium. The method includes: determining the construction parameters of the LDPC code, the construction parameters are used to construct the mother matrix of the LDPC code; constructing the prototype matrix of each sub-matrix, and simplifying the structure of each sub-matrix to obtain each simplified sub-matrix; merging each simplified sub-matrix to obtain the sub-code rate matrix of the mother matrix, merging each sub-code rate matrix to obtain the mother code prototype matrix; assigning cyclic shift values ​​to the mother code prototype matrix by an arithmetic progression; detecting whether each sub-matrix in the mother code prototype matrix contains 4 rings under the current shift value, if it does, then re-execute the step of assigning cyclic shift values ​​to the mother code prototype matrix by an arithmetic progression method, if it does not contain 4 rings, then the construction is terminated. By simplifying the sub-matrix, the construction of the LDPC code is simplified, and the computational difficulty in error correction applications is also simplified.

Description

Technical Field

[0001] The present application relates to the field of flash memory control technology, and in particular to a method, apparatus, terminal device, and storage medium for constructing LDPC codes for flash memory. Background Art

[0002] QC-LDPC codes are low-density parity-check codes with specific structural characteristics. They are generally described by a base matrix and a lifting size (LS) Z. Each element in the base matrix corresponds to a cyclic right shift of the Z×Z identity matrix. That is, the element "0" represents a Z×Z identity matrix. The element "-1" is defined to represent a Z×Z zero matrix. Other cyclic shift values ​​are between 1 and (Z-1).

[0003] However, the diversity of NAND flash page sizes (PS) poses a challenge to the construction of LDPC matrices. For example, in MLC flash, the size of a single page may be relatively small, while in QLC flash, the size of a single page may be much larger, and the SpareSize of QLC pages varies from one particle manufacturer to another. This requires that the error correction code be designed to be compatible with flash memories of different page sizes. However, existing LDPC matrix construction methods are typically optimized for specific page sizes. This requires constructing different LDPC matrices for different types of NAND flash during the design process, increasing design complexity and potentially affecting the efficiency of hardware implementation. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a method, apparatus, terminal device and storage medium for constructing LDPC codes for flash memory, which can effectively solve problems such as affecting hardware implementation efficiency and design complexity.

[0005] In a first aspect, an embodiment of the present application provides a method for constructing an LDPC code for a flash memory, comprising:

[0006] Determining construction parameters of an LDPC code, wherein the construction parameters are used to construct a mother matrix of the LDPC code;

[0007] Constructing the prototype matrix of each submatrix and simplifying the structure of each submatrix to obtain each simplified submatrix;

[0008] Merging the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merging the sub-rate matrices to obtain a mother code prototype matrix;

[0009] Assigning a cyclic shift value to the mother code prototype matrix by an arithmetic progression;

[0010] Under the current shift value, whether each sub-matrix in the mother code prototype matrix contains 4 rings is detected. If it contains 4 rings, the step of assigning a cyclic shift value to the mother code prototype matrix by the arithmetic progression method is re-executed. If it does not contain 4 rings, the construction is terminated.

[0011] In some embodiments, determining construction parameters of an LDPC code, where the construction parameters are used to construct a mother matrix of the LDPC code, includes:

[0012] Calculating a boost factor according to hardware parameters of the target flash memory, and calculating the number of columns of the user data matrix according to the boost factor;

[0013] The maximum code rate and the minimum code rate of the target flash memory are determined, and the number of rows of the mother matrix and the number of rows of each sub-matrix are calculated according to the number of columns of the user data matrix, the maximum code rate and the minimum code rate.

[0014] In some embodiments, the sub-matrix includes a user data matrix, a rate compatibility matrix, an all-1 matrix, a dense matrix, and a specific structure sub-matrix;

[0015] The step of constructing a prototype matrix of each submatrix and simplifying the structure of each submatrix includes:

[0016] Setting the first row of the user data matrix to 0 and the diagonal data of the rate compatibility matrix to 0;

[0017] The dense matrix is ​​set to a full matrix, and based on a preset column weight, the column weight of each sub-matrix is ​​set to a value within a preset range; the column weight is the number of 1s in a column of matrix data.

[0018] In some embodiments, the step of setting the column weight of each submatrix to a value within a preset range based on the preset column weight further includes:

[0019] The maximum column weight of the mother matrix is ​​not greater than the preset column weight + 1;

[0020] The maximum column weight of the user data matrix is ​​not greater than the preset column weight - 1;

[0021] The maximum column weight of the rate compatibility matrix is ​​not greater than the preset column weight - 1;

[0022] In some embodiments, merging the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix includes:

[0023] Constructing a prototype matrix for each sub-matrix using a progressive edge algorithm, and merging each simplified sub-matrix according to a preset position;

[0024] Determine the number of rows and columns to be deleted, continuously delete the rows to be deleted starting from the second row, and continuously delete the columns to be deleted starting from the second column of the rate compatibility matrix to obtain a sub-rate matrix of the mother matrix.

[0025] In some embodiments, the combining of the sub-rate matrices to obtain a mother code prototype matrix includes:

[0026] Perform a logical OR operation on the position of each sub-rate matrix 1 and the cumulative temporary matrix to obtain a mother code prototype matrix.

[0027] In some embodiments, assigning a cyclic shift value to the mother code prototype matrix by an arithmetic progression comprises:

[0028] Select any prime number between 0 and the lifting factor as the arithmetic difference value of each row of the mother code prototype matrix; the arithmetic difference value of each row is different;

[0029] Setting initial values ​​for each row in the first column of the mother code prototype matrix;

[0030] The cyclic shift value of each row is generated according to the initial value of each row and the arithmetic difference value of each row.

[0031] In some embodiments, the hardware parameters include firmware padding length, cyclic redundancy check length, minimum page capacity, maximum page capacity, throughput rate, and operating frequency;

[0032] The step of calculating the boost factor according to the hardware parameters of the target flash memory, and calculating the number of columns of the user data field according to the boost factor, includes:

[0033] Calculating a maximum codeword length based on the maximum page capacity and the number of codewords;

[0034] Calculate the size of the user data field of each codeword according to the length of the firmware padding and the cyclic redundancy check;

[0035] Calculating a boost factor based on the maximum codeword length, throughput, operating frequency, a size of a user data field of each codeword, and hardware parameters of the target flash memory controller;

[0036] The number of columns of the user data field is calculated according to the lifting factor and the size of the user data field of each codeword.

[0037] In some embodiments, determining the compatible highest bit rate and lowest bit rate, and calculating the number of rows of the mother matrix and the number of rows of each sub-matrix according to the highest bit rate and the lowest bit rate, includes:

[0038] Calculate the number of rows of the mother matrix and the number of rows of each sub-matrix according to a preset inequality;

[0039] The expression of the inequality is:

[0040] ;

[0041] ;

[0042] Wherein, R is the minimum code rate, R1 is the maximum code rate, K is the number of columns of the user data field, M is the number of rows of the mother matrix, and M1 is the number of rows of the sub-matrix corresponding to the maximum code rate.

[0043] In a second aspect, the present application further provides a flash memory LDPC code construction device, comprising:

[0044] A first construction module is used to determine construction parameters of an LDPC code, where the construction parameters are used to construct a mother matrix of the LDPC code;

[0045] The second construction module is used to construct a prototype matrix of each sub-matrix and simplify the structure of each sub-matrix to obtain each simplified sub-matrix;

[0046] a merging module, configured to merge the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merge the sub-rate matrices to obtain a mother code prototype matrix;

[0047] An assignment module is used to assign a cyclic shift value to the mother code prototype matrix through an arithmetic progression;

[0048] A detection module is configured to detect whether each sub-matrix in the mother code prototype matrix contains four rings under a current shift value. If so, re-execute the step of assigning a cyclic shift value to the mother code prototype matrix using an arithmetic progression method; if not, the construction is terminated.

[0049] In a third aspect, the present application also provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the LDPC code construction method for flash memory.

[0050] In a fourth aspect, the present application also provides a computer-readable storage medium storing a computer program, which, when executed on a processor, implements the LDPC code construction method for flash memory.

[0051] The embodiments of the present application have the following beneficial effects:

[0052] The flash memory LDPC code construction method of the present application simplifies the structure of each sub-matrix, so that the LDPC code can reduce the shift calculation amount in subsequent error correction applications, and also simplifies the design structure. The prototype matrix is ​​assigned a cyclic shift value through the arithmetic progression method, and the random shift is reduced to a fixed shift, which simplifies the hardware implementation complexity and the storage overhead of the cyclic shift value. Then, by detecting the shift value, it is ensured that the finally generated LDPC code does not contain 4 rings, thereby ensuring the error correction performance of the LDPC code. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic diagram of a process for constructing an LDPC code for a flash memory according to an embodiment of the present application is shown;

[0055] Figure 2 A schematic diagram of an LDPC code structure according to an embodiment of the present application is shown;

[0056] Figure 3 A schematic diagram of an LDPC code sub-matrix according to an embodiment of the present application is shown;

[0057] Figure 4 A schematic diagram of a constructed LDPC code according to an embodiment of the present application is shown;

[0058] Figure 5 A schematic diagram showing the sum product performance of different half-port codes of each sub-matrix under an additive Gaussian noise channel according to an embodiment of the present application is shown;

[0059] Figure 6 A schematic structural diagram of an LDPC code construction device for a flash memory according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0061] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0062] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0064] QC-LDPC code is a low-density parity-check code with specific structural characteristics. The diversity of different NAND flash memory page sizes (PS) poses a challenge to the construction of LDPC matrices. This application provides a flash memory LDPC code construction method. After the sub-matrices are constructed, simplification operations are performed to obtain each sub-matrix, and then the sub-matrices are spliced ​​to obtain a mother matrix. Then, corresponding check operations are performed to remove loops in the mother matrix, and finally the required QC-LDPC code matrix is ​​obtained.

[0065] The following describes the method for constructing the LDPC code for the flash memory in conjunction with some specific embodiments.

[0066] Figure 1 A flow chart of a method for constructing an LDPC code for a flash memory according to an embodiment of the present application is shown. Exemplarily, the method for constructing an LDPC code for a flash memory includes the following steps:

[0067] Step S100: determining construction parameters of an LDPC code, wherein the construction parameters are used to construct a mother matrix of the LDPC code.

[0068] LDPC code is a QC-LDPC code matrix, which is used for error correction and data protection in flash memory. LDPC code consists of multiple sub-matrices, and its specific form is as follows Figure 2 As shown, it includes seven parts, A, B, C, D, E, F and G. Part A corresponds to the user data matrix, part B corresponds to the rate compatibility matrix, part C is an all-'-1' matrix, corresponding to the all-0 matrix after expansion, D, F, G correspond to dense matrices, and the diagonal elements of part E are "0", corresponding to the unit matrix after expansion.

[0069] The construction of the LDPC code is related to the flash memory in which it works. The LDPC code needs to be designed according to the hardware parameters of the flash memory, otherwise the generated LDPC code will not work properly in the flash memory.

[0070] For the convenience of explanation, in this embodiment, the hardware parameters of the target flash memory that the QC-LDPC code needs to be compatible are preset, where the hardware parameters include the minimum page capacity, maximum page capacity, throughput, and operating frequency. For the convenience of explanation and calculation, example data of each operating parameter are given here: the minimum page capacity is recorded as MLC: 16384+1536 Bytes, corresponding to the highest code rate of the matrix; the maximum page capacity size is QLC: 16384+2608 Bytes, corresponding to the lowest code rate of the matrix. The number of codewords stored in each logical page is 4. The design throughput φ>=4 G Bps, and the design operating frequency f is 500 MHz.

[0071] First, the maximum codeword length L is calculated according to the maximum page capacity. The specific calculation expression is: L = (16384 + 2608) / T = 4748 Bytes.

[0072] In the formula, T as the denominator is 4, and the above result can be obtained by substituting it into the denominator.

[0073] The size of the user data field of each codeword is calculated based on the length of the firmware padding and the cyclic redundancy check.

[0074] The firmware padding length is a known value, preferably 12 in this embodiment, recorded as OOB (Out-of-Bandfield), and the cyclic redundancy check is a known value, preferably 4 in this embodiment, recorded as CRC (Cyclic Redundancy Check).

[0075] The size of the user data field of each codeword is Lu = (16384 / T) + OOB + CRC = 4748 Bytes.

[0076] A boosting factor is calculated according to the maximum codeword length and the size of the user data field of each codeword.

[0077] The lifting factor needs to satisfy the following inequality:

[0078] .

[0079] Where i is the number of convergence iterations, which is preferably 3 in this embodiment. Then, the following equation can be obtained:

[0080] .

[0081] In order to facilitate data transmission and conversion, the size of Z is generally taken as an integer power of 2, and the lifting factor Z here is preferably 256.

[0082] The number of columns of the user data field is calculated according to the lifting factor and the size of the user data field of each codeword.

[0083] The calculation expression for the user field K is: K = ceil(Lu / Z), where ceil represents rounding up. Here, K = ceil(4112 / 32) = 129, which means that the number of columns corresponding to the user field is 129. During encoding, 16 bytes of padding are required at the end of the user data to meet the Z-size alignment requirement of the QC-LDPC code.

[0084] Next, we need to calculate the number of rows in the mother matrix M and the number of rows in the sub-matrix M1 corresponding to the highest bit rate, which has the following expression:

[0085] ;

[0086] ;

[0087] For example, the highest compatible code rate is R1 = 0.9214, R2 = 0.8694; by substituting the above expression, we can calculate M = 19, M1 = 11, thus obtaining the construction parameters of the LDPC code.

[0088] According to the above construction parameters, we can construct Figure 2 The mother matrix of the LDPC code shown is the size of the maximum matrix. At this time, each element in the mother matrix has no initial value and can be a default value such as 0 or null.

[0089] Among them, N in the figure is the number of columns of the mother matrix, which is based on the number of columns of the sub-matrix, so it is not calculated separately here. After the mother matrix is ​​constructed by the sub-matrix in the subsequent steps, the number of columns N is the number of columns of the constructed mother matrix.

[0090] Step S200: constructing prototype matrices of each sub-matrix and simplifying the structure of each sub-matrix.

[0091] The two matrices of all -1 and all 0 do not need special processing, so the main processing is the user data matrix, the code rate compatible matrix and the dense matrix.

[0092] The first row of the user data matrix is ​​set to 0, and the diagonal data of the rate compatibility matrix is ​​set to 0. This simplifies the encoding complexity because the rows with all 0s do not require a cyclic shift operation, which directly reduces the cyclic shift operation on the first row and allows direct XOR calculation.

[0093] In order to ensure that the check bit is partially reversible, the dense matrix G is set to a full matrix, and based on a preset column weight, the column weight of each submatrix is ​​set to a value within a preset range.

[0094] This determines the maximum column weight of the mother matrix to be g + 1. To ensure balanced hardware power consumption, keep the column weights relatively concentrated, and facilitate subsequent solution steps, the column weights of matrices A and B are defined as g - 1, and the column weight of the D + F part is defined as g.

[0095] Column weight refers to the number of 1s in a column of matrix data. Because decoding is performed column by column, the size of the column determines the processor's power consumption when processing that column. By allocating column weights in the above manner, each column's weight falls within a range around the preset column weight g. This prevents significant power consumption fluctuations during processing, allowing the processor to operate in a stable state. This is very stable and user-friendly for both the processor and the power supply. This completes the construction of each sub-matrix.

[0096] Step S300: Merge the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merge the sub-rate matrices to obtain a mother code prototype matrix.

[0097] In order to ensure the maximum local girth and reduce the number of loops in the prototype matrix as much as possible, this embodiment may use a Progressing Edge Growth (PEG) algorithm to construct a prototype matrix for each sub-matrix.

[0098] Each sub-matrix is ​​divided into Figure 2 After the structures shown are spliced, a prototype matrix is ​​obtained, which meets the construction parameters in step S100.

[0099] Among them, if the current flash memory logical page size adaptation length is N-2 columns, it means that the current number of N columns is greater than the flash memory logical page size. To adapt to the flash memory logical page size, 2 rows and 2 columns need to be deleted.

[0100] At the same time, to ensure the maximum local girth and minimize the number of loops in the prototype matrix, a loop must be a structure in the matrix. A QC-LDPC code matrix cannot have four loops, and a loop is composed of 1s. Therefore, rows and columns containing 1s need to be deleted. Therefore, this embodiment deletes rows and columns based on the logical page size of the flash memory.

[0101] A loop is a closed circuit consisting of variable nodes, check nodes, and edges connected end to end. A 4-loop is a loop with a side length of 4. For QC-LDPC codes, 4-loops in the matrix can be eliminated after proper value assignment.

[0102] For rows, since the first row is set to all 0s, there will definitely be no 1s. Therefore, when you need to delete a row, you don't need to delete the first row, so you can start from the second row. The first row can be obtained by XORing the information block to obtain the first check block, which is also the first row of all sub-matrices.

[0103] When deleting columns, start from the second column of the rate compatibility matrix. Because each element in the rate compatibility matrix can be calculated from its first element, as long as the first element is retained, subsequent element deletions will not be affected. Therefore, you can start from the second column of the rate compatibility matrix.

[0104] Therefore, reflected in the entire mother matrix, for example, the flash memory particle with a compatible page capacity of 16384+2432 Bytes has a corresponding sub-matrix of 18×147. The second row and the 131st column are removed from the mother matrix. The final prototype matrix example is as follows: Figure 4 shown.

[0105] It should be noted that the sub-rate matrix obtained by merging in the above manner is a sub-rate matrix, that is, a sub-rate matrix corresponding to each sub-rate supported by the device. In the above manner, a corresponding sub-rate matrix can be obtained for each sub-rate. In this embodiment, each sub-rate matrix is ​​further merged to obtain a mother code prototype matrix.

[0106] In this embodiment, the sub-rate matrices are combined into a mother code prototype matrix. The position of 1 in the sub-rate matrix and the position of 1 in the corresponding mother matrix are logically ORed, and the mother code prototype matrix is ​​obtained by traversing all sub-matrices that need to be supported. When the sub-matrix size is (M-1)×(N-1), the combination is as follows: Figure 3 As shown, the cumulative or temporary matrix 1 is the matrix before the bitwise OR operation with the sub-matrix (M-1)×(N-1), and the cumulative or temporary matrix 2 is the matrix after the bitwise OR operation with the sub-matrix (M-1)×(N-1). After all sub-matrices are bitwise ORed, the cumulative or temporary matrix is ​​the mother code prototype matrix.

[0107] The cumulative or temporary matrix is ​​a matrix initially filled with all zeros. For example, if there are five sub-rate matrices, these five sub-rate matrices are sequentially ORed with the cumulative or temporary matrix. After five OR operations, the final cumulative or temporary matrix is ​​the mother code prototype matrix, which is the LDPC matrix used for verification.

[0108] Step S400: assigning a cyclic shift value to the mother code prototype matrix through an arithmetic progression.

[0109] The arithmetic progression method assigns an arithmetic difference value to each row of the mother code prototype matrix, sets an initial value for the first column, and then calculates the value of each element in each row based on the arithmetic difference value and the initial value.

[0110] According to the 4-cycle-free theory of QC-LDPC codes, the arithmetic difference values ​​of each row must be different. Prime numbers in the range of 0 to Z can be used as the arithmetic difference values.

[0111] For example, in this embodiment, Z is 256. Therefore, for the first few rows, the last valid element is "0", and the initial value of the first column needs to be obtained according to the row weight of the row. In this embodiment, the arithmetic difference values ​​of rows 1 to 19 are 0, 5, 7, 2, 3, 1, 23, 6, 10, 110, 214, 27, 167, 163, 149, 17, 223, 151, and 4, respectively. In this embodiment, the initial values ​​of rows 1 to 19 are 0, 175, 150, 138, 246, 97, 206, 154, 106, 256, 126, 47, 61, 174, 197, 94, 62, 70, and 229, respectively.

[0112] In this way, the shift value at each position in the matrix can be calculated.

[0113] Step S500: Detect whether each sub-matrix in the mother code prototype matrix contains four rings under the current shift value. If so, re-perform the step of assigning a cyclic shift value to the mother code prototype matrix using the arithmetic progression method. If not, the construction is terminated.

[0114] After the calculation is completed, it is necessary to check whether each submatrix contains a quaternary ring, which is a ring composed of four ones. If it does not contain a quaternary ring, the construction is terminated. If it does contain a quaternary ring, the above step S400 needs to be executed again until there is no quaternary ring in each submatrix.

[0115] like Figure 5Figure 2 shows the performance analysis of the sum-product decoding of different half-port codes in an additive Gaussian noise channel for each submatrix after passing through the aforementioned Divide-by-4 loop. The decoding algorithm is an ideal sum-product decoding algorithm. The size in the figure represents the submatrix size, the horizontal axis represents the raw bit error rate, and the vertical axis represents the uncorrected bit error rate. It can be seen that as the raw bit error rate increases, the uncorrected bit error rate of each submatrix converges, indicating that the uncorrected bit error rate of each submatrix is ​​effectively controlled after passing through the Divide-by-4 loop.

[0116] The flash memory LDPC code construction method of this embodiment simplifies the structure of each submatrix, thereby reducing the amount of shift calculations required in subsequent error correction applications. It also simplifies the design structure. By assigning cyclic shift values ​​to the prototype matrix using an arithmetic progression method, random shifts are reduced to fixed shifts, simplifying hardware implementation complexity. The storage overhead of the cyclic shift values ​​is also reduced, requiring only the initial value and the difference to be stored. Shift value detection ensures that the resulting LDPC code will not contain loops, increasing the stability of the LDPC code construction and simplifying the construction process of the resulting LDPC code. This ensures stable power consumption during actual computational use, reduces computational operations, and thus reduces the burden on hardware and improves efficiency.

[0117] Figure 6 An LDPC code construction device for a flash memory according to an embodiment of the present application is shown, comprising:

[0118] A first construction module 10 is used to determine construction parameters of an LDPC code, where the construction parameters are used to construct a mother matrix of the LDPC code;

[0119] The second construction module 20 is used to construct a prototype matrix of each sub-matrix and simplify the structure of each sub-matrix to obtain each simplified sub-matrix;

[0120] a merging module 30, configured to merge the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merge the sub-rate matrices to obtain a mother code prototype matrix;

[0121] An assignment module 40 is configured to assign a cyclic shift value to the mother code prototype matrix by an arithmetic progression;

[0122] The detection module 50 is configured to detect whether each sub-matrix in the mother code prototype matrix contains four rings under the current shift value. If so, the step of assigning a cyclic shift value to the mother code prototype matrix using the arithmetic progression method is re-executed. If not, the construction is terminated.

[0123] The present application also provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the LDPC code construction method for flash memory.

[0124] The terminal device of this embodiment can be an electronic device such as a computer, a mobile phone, or a tablet computer equipped with a flash memory. The LDPC code in the flash memory is constructed based on the LDPC code construction method of the above embodiment.

[0125] The present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, the method for constructing an LDPC code for a flash memory is implemented.

[0126] It can be understood that the apparatus of this embodiment corresponds to the method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0127] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0128] The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving an execution instruction.

[0129] The computer-readable storage medium of this application is used to store the computer program used in the terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0131] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0132] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0133] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A method for constructing an LDPC code for a flash memory, characterized in that: include: Determining construction parameters of an LDPC code, wherein the construction parameters are used to construct a mother matrix of the LDPC code; Constructing the prototype matrix of each submatrix and simplifying the structure of each submatrix to obtain each simplified submatrix; Merging the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merging the sub-rate matrices to obtain a mother code prototype matrix; Assigning a cyclic shift value to the mother code prototype matrix by an arithmetic progression; Detecting whether each sub-matrix in the mother code prototype matrix contains four rings under the current shift value; if so, re-performing the step of assigning a cyclic shift value to the mother code prototype matrix using the arithmetic progression method; and completing the construction if not. The sub-matrices include a user data matrix, a rate compatibility matrix, an all-1 matrix, a dense matrix and a specific structure sub-matrix; The step of constructing a prototype matrix of each submatrix and simplifying the structure of each submatrix includes: Setting the first row of the user data matrix to 0 and the diagonal data of the rate compatibility matrix to 0; The dense matrix is ​​set to a full matrix, and based on a preset column weight, the column weight of each sub-matrix is ​​set to a value within a preset range; the column weight is the number of 1s in a column of matrix data.

2. The method for constructing an LDPC code for a flash memory according to claim 1, wherein: The determining of the construction parameters of the LDPC code, where the construction parameters are used to construct a mother matrix of the LDPC code, includes: Calculating a boost factor according to hardware parameters of the target flash memory, and calculating the number of columns of the user data matrix according to the boost factor; The maximum code rate and the minimum code rate of the target flash memory are determined, and the number of rows of the mother matrix and the number of rows of each sub-matrix are calculated according to the number of columns of the user data matrix, the maximum code rate and the minimum code rate.

3. The method for constructing an LDPC code for a flash memory according to claim 1, wherein: The step of setting the column weight of each submatrix to a value within a preset range based on the preset column weight further includes: The maximum column weight of the mother matrix is ​​not greater than the preset column weight + 1; The maximum column weight of the user data matrix is ​​not greater than the preset column weight - 1; The maximum column weight of the rate compatibility matrix is ​​not greater than the preset column weight-1.

4. The method for constructing an LDPC code for a flash memory according to claim 1, wherein: Combining the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix includes: Constructing a prototype matrix for each sub-matrix using a progressive edge algorithm, and merging each simplified sub-matrix according to a preset position; Determine the number of rows and columns to be deleted, continuously delete the rows to be deleted starting from the second row, and continuously delete the columns to be deleted starting from the second column of the rate compatibility matrix to obtain a sub-rate matrix of the mother matrix.

5. The method for constructing an LDPC code for a flash memory according to claim 1, wherein: The combining of the sub-rate matrices to obtain a mother code prototype matrix includes: Perform a logical OR operation on the position of each sub-rate matrix 1 and the cumulative temporary matrix to obtain a mother code prototype matrix.

6. The method for constructing an LDPC code for a flash memory according to claim 2, wherein: The assigning a cyclic shift value to the mother code prototype matrix by an arithmetic progression method includes: Select any prime number between 0 and the lifting factor as the arithmetic difference value of each row of the mother code prototype matrix; the arithmetic difference value of each row is different; Setting initial values ​​for each row in the first column of the mother code prototype matrix; The cyclic shift value of each row is generated according to the initial value of each row and the arithmetic difference value of each row.

7. The method for constructing an LDPC code for a flash memory according to claim 2, wherein: The hardware parameters include firmware padding length, cyclic redundancy check length, minimum page capacity, maximum page capacity, throughput rate and operating frequency; The step of calculating the boost factor according to the hardware parameters of the target flash memory, and calculating the number of columns of the user data field according to the boost factor, includes: Calculating a maximum codeword length based on the maximum page capacity and the number of codewords; Calculate the size of the user data field of each codeword according to the length of the firmware padding and the cyclic redundancy check; Calculating a boost factor based on the maximum codeword length, throughput, operating frequency, a size of a user data field of each codeword, and hardware parameters of the target flash memory controller; The number of columns of the user data field is calculated according to the lifting factor and the size of the user data field of each codeword.

8. The method for constructing an LDPC code for a flash memory according to claim 7, wherein: The determining of the maximum code rate and the minimum code rate of the target flash memory, and calculating the number of rows of the mother matrix and the number of rows of each sub-matrix according to the number of columns of the user data matrix, the maximum code rate, and the minimum code rate, includes: Calculate the number of rows of the mother matrix and the number of rows of each sub-matrix according to a preset inequality; The expression of the inequality is: ； ； Wherein, R is the minimum code rate, R1 is the maximum code rate, K is the number of columns of the user data field, M is the number of rows of the mother matrix, and M1 is the number of rows of the sub-matrix corresponding to the maximum code rate.

9. A flash memory LDPC code construction device, characterized in that: include: A first construction module is used to determine construction parameters of an LDPC code, where the construction parameters are used to construct a mother matrix of the LDPC code; The second construction module is used to construct a prototype matrix of each sub-matrix and simplify the structure of each sub-matrix to obtain each simplified sub-matrix; a merging module, configured to merge the simplified sub-matrices to obtain a sub-rate matrix of the mother matrix, and merge the sub-rate matrices to obtain a mother code prototype matrix; An assignment module is used to assign a cyclic shift value to the mother code prototype matrix through an arithmetic progression; a detection module, configured to detect whether each sub-matrix in the mother code prototype matrix contains four rings under a current shift value; if so, re-execute the step of assigning a cyclic shift value to the mother code prototype matrix using an arithmetic progression method; and terminate the construction if not. The sub-matrices include a user data matrix, a rate compatibility matrix, an all-1 matrix, a dense matrix and a specific structure sub-matrix; The step of constructing a prototype matrix of each submatrix and simplifying the structure of each submatrix includes: Setting the first row of the user data matrix to 0 and the diagonal data of the rate compatibility matrix to 0; The dense matrix is ​​set to a full matrix, and based on a preset column weight, the column weight of each sub-matrix is ​​set to a value within a preset range; the column weight is the number of 1s in a column of matrix data.

10. A terminal device, characterized in that: The terminal device includes a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the LDPC code construction method for a flash memory according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The device stores a computer program, which, when executed on a processor, implements the LDPC code construction method for a flash memory according to any one of claims 1 to 8.

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