Time calibration method, electronic equipment and storage medium
By synchronizing the target timestamps between FPGA devices and receiving pulse signals for calibration, the problem that local clock drift in FPGA devices affects the accuracy of time synchronization is solved, and the resource consumption of established time calibration protocols is reduced, achieving efficient and accurate time synchronization is achieved.
Patent Information
- Application Number
- CN202510398006.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-06-17
AI Technical Summary
The drift of local clocks in FPGA devices affects the accuracy of time synchronization, and the prior art when establishing a time calibration protocol between multiple FPGA devices, resource consumption is too high, making it difficult to cope with the needs of large-scale networks.
By obtaining the target timestamp sent by the first FPGA device, the local time of the second FPGA device is synchronized, and the synchronization time is maintained based on the local clock, and the pulse signal sent by the first FPGA device in accordance with the preset period is received to calibrate the local synchronization time.
Improves the accuracy of time calibration between FPGA devices, reduces the consumption of system resources by establishing time calibration protocols, and reduces the cost of time synchronization.
Smart Images
Figure CN120165803A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of time calibration, and particularly relates to a time calibration method, an electronic device, and a storage medium. Background Art
[0002] In the design of FPGA systems, time calibration plays a crucial role. It is not only the cornerstone for ensuring data synchronization and consistency, providing an accurate time reference to ensure the orderly transmission of data, thus effectively avoiding a series of problems caused by time deviation and significantly reducing the cumulative effect of errors. Further, the time calibration mechanism significantly improves the overall performance and reliability of the system, laying a solid foundation for the efficient operation of the system by reducing latency, enhancing the fault tolerance of the system, and maintaining a high degree of stability. Therefore, ensuring accurate time calibration between multiple FPGA devices is not only a necessary condition for maintaining the normal and stable operation of the FPGA system, but also an important means to promote system performance improvement and function optimization.
[0003] In the current related technologies, the time synchronization between each FPGA device is mainly ensured by the local clock of the FPGA device. However, the drift of the local clock in the FPGA device will affect the accuracy of time synchronization. Moreover, the local clock drift can be caused by various factors, such as temperature, voltage, etc., and this instability will lead to an increase in synchronization errors. Summary of the Invention
[0004] Embodiments of this application provide a time calibration method, an electronic device, and a storage medium, which can improve the accuracy of time calibration of FPGA devices.
[0005] In a first aspect, embodiments of this application provide a time calibration method, which includes:
[0006] Obtain a target timestamp sent by a first FPGA device;
[0007] Synchronize the local time of a second FPGA device based on the target timestamp to obtain the local synchronization time of the second FPGA device;
[0008] Determine the clock accumulation frequency of the local synchronization time based on the local clock of the second FPGA device, and maintain the local synchronization time based on the clock accumulation frequency;
[0009] Receive a pulse signal sent by the first FPGA device at a preset period, and calibrate the local synchronization time based on the pulse signal.
[0010] In a second aspect, embodiments of this application provide a time calibration device, which includes:
[0011] An acquisition module to acquire a target timestamp sent by a first FPGA device;
[0012] A synchronization module to synchronize the local time of a second FPGA device based on the target timestamp to obtain the local synchronized time of the second FPGA device;
[0013] A maintenance module to determine the clock accumulation frequency of the local synchronized time based on the local clock of the second FPGA device and maintain the local synchronized time based on the clock accumulation frequency;
[0014] A calibration module to receive a pulse signal sent by the first FPGA device according to a preset period and calibrate the local synchronized time based on the pulse signal.
[0015] In a third aspect, an embodiment of the present application provides an electronic device, which includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the time calibration method as described in the first aspect is implemented.
[0016] In a fourth aspect, an embodiment of the present application provides a computer storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the time calibration method as described in the first aspect is implemented.
[0017] In a fifth aspect, an embodiment of the present application provides a computer program product, and when the instructions in the computer program product are executed by a processor of an electronic device, the electronic device is caused to execute the time calibration method as described in the first aspect.
[0018] In the time calibration method, apparatus, device, and storage medium according to the embodiments of the present application, after the second FPGA device receives the target timestamp sent by the first FPGA device, it first synchronizes the local time of the second FPGA device through the target timestamp, and then while maintaining the local synchronized time of the second FPGA device through the local clock, the first FPGA device will send a pulse signal to the second FPGA device according to a preset period. Since the transmission of the pulse signal not only has a low delay, and even the delay is basically negligible, and there is no need to establish a time calibration protocol between each FPGA device, therefore, the second FPGA device calibrates the local synchronized time according to the received pulse signal, which can not only avoid calibration errors caused by transmission delay, but also reduce the consumption of system resources for establishing a time calibration protocol, improving the accuracy of time synchronization while reducing the cost of time synchronization. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0020] Figure 1 It is a schematic flowchart of a time calibration method provided by an embodiment of the present application;
[0021] Figure 2 It is a schematic structural diagram of an FPGA system provided by an embodiment of the present application;
[0022] Figure 3 It is a schematic flowchart of another time calibration method provided by an embodiment of the present application;
[0023] Figure 4 It is a schematic structural diagram of a time calibration device provided by an embodiment of the present application;
[0024] Figure 5 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed Embodiments
[0025] The following will describe in detail the features and exemplary embodiments of various aspects of the present application. To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.
[0026] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise", or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device including a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article, or device including the said elements.
[0027] In the new generation of electronic systems, due to its reconfigurability and flexibility, FPGA is often designed as the interface of various buses in communication networks, carrying the services and data streams with the highest bandwidth in complex electronic systems, including control instructions, video signal transmission, etc. The time determinacy of this information becomes one of the very important indicators of an electronic system. Ensuring precise time calibration among multiple FPGA devices is not only a necessary condition for maintaining the normal and stable operation of the FPGA system, but also an important means to promote system performance improvement and function optimization.
[0028] In the current related technologies, the time synchronization among FPGA devices is mainly ensured by the local clocks of FPGA devices. However, the drift of the local clocks in FPGA devices will affect the accuracy of time synchronization. Moreover, the local clock drift can be caused by various factors, such as temperature, voltage, etc. This kind of instability will lead to an increase in synchronization errors. In addition, in some related technologies, the time synchronization among multiple FPGA devices is achieved through time calibration protocols, such as the PTP protocol. However, when using the PTP protocol for point-to-point connections, when there are too many communication nodes, a large number of connections need to be established, which will result in excessive consumption of system resources and heavy network load. At the same time, when adding or deleting nodes, the entire network needs to be reconfigured. This lack of scalability makes it difficult for the PTP technology to meet the requirements of large-scale networks. Therefore, the method of deploying the PTP protocol stack on each FPGA device can no longer meet the time synchronization requirements of large-scale electronic systems composed of multiple FPGA devices.
[0029] To solve the problems of the existing technologies, the embodiments of the present application provide a time calibration method, device, electronic device, computer storage medium and computer program product to reduce the consumption of system resources for establishing the time calibration protocol, improve the accuracy of time synchronization, and at the same time reduce the cost of time synchronization. First, the time calibration method provided by the embodiments of the present application will be introduced below.
[0030] Figure 1 The flowchart of a time calibration method provided by an embodiment of the present application is shown. As Figure 1 shown, the method includes the following steps:
[0031] S101, obtain the target timestamp sent by the first FPGA device.
[0032] Specifically, in the FPGA system of the present application, there are multiple FPGA devices. Refer to Figure 2, where the multiple FPGA devices included in the FPGA system can be classified into types: timing device 011, master device 021, and slave device 031. Time synchronization is performed between the timing device and multiple master devices, with the time of the timing device as the main time. Time synchronization is performed between each master device and multiple slave devices, with the time of the master device as the main time. It should be noted that in some embodiments, the time calibration method of the embodiments of the present application can be applied to the time synchronization between the master device and the slave device. At this time, the first FPGA device is the master device, and the second FPGA device can be any one of the slave devices. In some embodiments, the time calibration method of the embodiments of the present application can also be applied to the time synchronization between the timing device and the master device. At this time, the first FPGA device is the timing device, and the second FPGA device can be any one of the master devices.
[0033] In one example, when the time calibration method of the embodiments of the present application can be applied to the time synchronization between the master device and the slave device, time synchronization can be performed between the timing device and the master device through a time calibration protocol, and then the time synchronization between the master device and the slave device can be completed through the time calibration method of the embodiments of the present application.
[0034] Since the time calibration method of the embodiments of the present application does not require establishing a resource-consuming time calibration protocol between multiple FPGA devices for time synchronization, the target timestamp can be transmitted through the communication interface between the first FPGA device and the second FPGA device. In one example, to initially synchronize the time of the first FPGA device and the second FPGA device, the first FPGA device will send the target timestamp to the second FPGA device after generating the target timestamp, and the second FPGA device receives the target timestamp sent by the first FPGA device. In some embodiments, the target timestamp of the first FPGA device can be generated based on a certain local time of the first FPGA device, or can be generated based on a certain clock information sent by the timing device through the time calibration protocol, and this is not limited. It should be noted that for the convenience of understanding, the above Figure 1 corresponding embodiments are described from the perspective of the second FPGA device, that is, the execution subject of the above Figure 1 corresponding embodiments is the second FPGA device.
[0035] In some embodiments, the above-mentioned target timestamp may consist of two parts, that is, the above-mentioned target timestamp includes a value in a first time unit and a value in a second time unit, and the level of the first time unit is higher than that of the second time unit. Specifically, both the first time unit and the second time unit can be set as needed. For example, the first time unit can be milliseconds, seconds or a higher-level unit. The second time unit can be microseconds, nanoseconds or a finer unit. In one example, a certain target timestamp may be composed of the values of two time units, seconds and nanoseconds. Among them, when the value corresponding to nanoseconds accumulates to 1*10 9 When it reaches, the value corresponding to seconds is incremented by 1.
[0036] S102, synchronize the local time of the second FPGA device based on the target timestamp to obtain the local synchronized time of the second FPGA device.
[0037] In specific implementation, after receiving the target timestamp sent by the first FPGA device, the second FPGA device can synchronize the local time of the second FPGA device according to the target timestamp. Specifically, it can directly make the local time of the second FPGA device consistent with the target timestamp to obtain the local synchronized time of the second FPGA device. It should be noted that since the target timestamp is not transmitted through a time calibration protocol, the time synchronization at this time may be affected by network transmission delay.
[0038] In order to further reduce the error introduced by the timestamp transmission delay, in some embodiments, obtaining the target timestamp sent by the first FPGA device includes:
[0039] Successively obtain the value in the first time unit and the value in the second time unit included in the above-mentioned target timestamp sent by the above-mentioned first FPGA device;
[0040] Among them, when receiving the value in the second time unit included in the above-mentioned target timestamp, synchronize the local time of the above-mentioned second FPGA device.
[0041] In specific implementation, considering that there will be a delay in timestamp transmission, in the embodiments of the present application, when the first FPGA device sends the target timestamp, it will separately send the value in the first time unit and the value in the second time unit successively, that is, first send the value in the first time unit, and then immediately send the value in the second time unit. In this way, when sending the value in the first time unit, the value in the second time unit can still be accumulated, and then when sending the value in the second time unit, it can be ensured that the value in the second time unit is the latest value, further reducing the error introduced by the target timestamp transmission delay. It should be noted that when the second FPGA device receives the value in the second time unit included in the above target timestamp, it synchronizes the local time of the second FPGA device, that is, when the second FPGA device receives the value in the second time unit, it marks the entire target timestamp as effective and completes the synchronization of the local time of the second FPGA device with this.
[0042] It should be noted that the time interval between the second FPGA device receiving the value in the first time unit and the value in the second time unit needs to be less than the time represented by the single value of the first time unit. For example, when the first FPGA device distributes the target timestamp to the second FPGA device, the process is specifically divided into the continuous transmission of a custom second-level timestamp and a nanosecond-level timestamp. This process first starts the transmission of the second-level timestamp, and then immediately follows the transmission of the nanosecond-level timestamp. The time interval between starting the transmission of the second-level timestamp and the transmission of the nanosecond-level timestamp cannot be greater than 1 second. On this basis, the arrival of the nanosecond-level timestamp marks the effectiveness of the entire target timestamp.
[0043] S103, determine the clock accumulation frequency of the local synchronization time based on the local clock of the second FPGA device, and maintain the local synchronization time based on the clock accumulation frequency.
[0044] In specific implementation, in the embodiments of the present application, the time of the FPGA device is a continuously accumulating variable, and in different local FPGA devices, this variable is maintained by the local clock. However, since the local clock may be affected by the environment and cause clock drift, when maintaining the local synchronization time or local time through the local clock, there may be a time deviation. However, in order to ensure that the time difference between multiple FPGA devices remains within a certain error range, after the second FPGA device synchronizes the local time to obtain the local synchronization time, it is necessary to determine the clock accumulation frequency of the local synchronization time based on the local clock of the second FPGA device, and maintain the local synchronization time based on the clock accumulation frequency. The clock accumulation frequency can be the single accumulation value of time within each clock cycle, or the number of times of time accumulation within a certain time period, and no limitation is made in this regard.
[0045] In some embodiments, the local time or local synchronization time of the second FPGA device may be stored in a register of the second FPGA device. The register may be a multi-bit register, specifically allocated as follows: a part of the bit width is used to store the value (timestamp) of the first time unit, while another part of the bit width is used to store the value (timestamp) of the second time unit.
[0046] S104, receive the pulse signal sent by the first FPGA device at a preset period, and calibrate the local synchronization time based on the pulse signal.
[0047] In specific implementation, to ensure the unity and high precision of the time synchronization between the local synchronization time of the second FPGA device and the time of the first FPGA device, when maintaining the local synchronization time through the local clock, the first FPGA device will send a pulse signal to the second FPGA device at a preset period. Since the delay of this pulse signal can be ignored, therefore, the second FPGA device calibrates the local synchronization time according to the received pulse signal sent by the first FPGA device, which can further improve the accuracy of time synchronization. Moreover, the first FPGA device sends the pulse signal to the second FPGA device at a preset period, that is, the second FPGA device can receive the pulse signal sent by the first FPGA device periodically. Therefore, it can continuously ensure that the time of the first FPGA device and the second FPGA device remains highly synchronized.
[0048] In order to accurately calibrate the local synchronization time through the pulse signal, in some embodiments, calibrating the local synchronization time based on the reception time corresponding to the above pulse signal includes:
[0049] In response to the first reception of the above pulse signal, clear the value of the local synchronization time at the time of receiving the above pulse signal that is located in the above second time unit;
[0050] In response to the non-first reception of the above pulse signal, adjust the above clock accumulation frequency based on the local synchronization time at the time of receiving the above pulse signal.
[0051] In specific implementation, considering that after the local time of the second FPGA device is synchronized with the target timestamp, the difference between the obtained local synchronized time and the time of the first FPGA device is not particularly large. Therefore, when the second FPGA device first receives the above pulse signal, the value in the second time unit of the local synchronized time when the pulse signal is received is cleared, so as to eliminate the delay generated when the software writes data to the register. Then, when the second FPGA device receives the above pulse signal non-first time, the above clock accumulation frequency will be dynamically adjusted according to the magnitude of the local synchronized time when the above pulse signal is received. The pulse signal sent non-first time is mainly used to calculate the initial time error between the first FPGA device and the second FPGA device. In the subsequent time calibration process, based on the initial error, it is dynamically adjusted to calculate the dynamic error, and the clock accumulation frequency is adjusted according to this dynamic error.
[0052] It should be noted that in order to further improve the accuracy of time synchronization, the first FPGA device can send a pulse signal to the second FPGA device when the value in the first time unit accumulates (for example, at the beginning of each second), so as to ensure that the second FPGA device can accurately perform time synchronization and calibration.
[0053] In order to accurately calibrate the local synchronized time through the pulse signal, in some embodiments, adjusting the above clock accumulation frequency based on the above local synchronized time when the above pulse signal is received includes:
[0054] Determine the unit interval time based on the above preset period;
[0055] Calculate the remainder of the above local synchronized time when the above pulse signal is received divided by the above unit interval time;
[0056] In response to the above remainder being greater than zero and less than half of the above unit interval time, reduce the above clock accumulation frequency based on the above remainder;
[0057] In response to the above remainder being greater than half of the above unit interval time, increase the above clock accumulation frequency based on the above remainder.
[0058] In specific implementation, considering that the difference between the local synchronization time of the second FPGA device and the time of the first FPGA device is not particularly large, and the inventor found that this difference is generally less than half of the unit interval time. For example, if the unit interval time is 1 second, then the difference between the local synchronization time of the second FPGA device and the time of the first FPGA device is less than 0.5. On this basis, calculate the remainder of the local synchronization time when receiving the above pulse signal divided by the unit interval time (1 second). This remainder is the part that cannot be evenly divided by the unit interval time. If this part is between 0.5 and 1 second, it means that the local synchronization time at this time is relatively slow, and the clock accumulation frequency can be increased to reduce the difference between the local synchronization time and the time of the first FPGA device. If this part is between 0 and 0.5 second, it means that the local synchronization time at this time is relatively fast, that is, it has already advanced to the front, and the clock accumulation frequency can be reduced. In some embodiments, the specific amount of increase or decrease in the clock accumulation frequency can be determined by the remainder. For example, if a certain remainder is 0.9 second, it means that at this time, the local synchronization time is 0.1 second slower than the time of the first FPGA device, then the 0.1 second gap can be offset by increasing the clock accumulation frequency.
[0059] In order to accurately calibrate the local synchronization time through the pulse signal, in some embodiments, based on the local synchronization time when receiving the above pulse signal, adjusting the above clock accumulation frequency includes:
[0060] Determining the unit interval time based on the above preset period;
[0061] In response to determining that the unit interval time is equal to the time corresponding to the unit value of the first time unit, determining the target value in the second time unit of the local synchronization time when receiving the above pulse signal;
[0062] In response to the time corresponding to the above target value being greater than zero and less than half of the above unit interval time, reducing the above clock accumulation frequency based on the above target value;
[0063] In response to the time corresponding to the above target value being greater than half of the above unit interval time, increasing the above clock accumulation frequency based on the above target value.
[0064] In specific implementation, when it is determined that the unit interval time corresponding to the preset period is equal to the time corresponding to the unit value of the first time unit, the speed of the current local synchronization time can be directly judged by the target value in the second time unit of the local synchronization time when receiving the pulse signal. For example, if a certain first time unit is seconds and the second time unit is milliseconds, if a certain target value is 1*10 8If the time corresponding to the target value is 0.1 second, and at this time the target value is less than 0.5 second, it can be determined that the local synchronization time is faster than the time of the first FPGA device. The above clock accumulation frequency can be reduced according to this 0.1 second.
[0065] It should be noted that in the embodiments of the present application, when calibrating the local synchronization time, the local synchronization time is not directly and rigidly aligned with the time of the first FPGA device, but the time difference between the two is gradually reduced by adjusting the clock accumulation frequency, so as to avoid the problem of time backtracking.
[0066] In some embodiments, after calibrating the local synchronization time based on the above pulse signal, the time calibration method of the present application further includes:
[0067] Determine the deviation between the calibrated local synchronization time and the time of the first FPGA device through an oscilloscope;
[0068] In response to determining that the deviation is greater than the first threshold, reduce the unit interval time corresponding to the above preset period;
[0069] In response to determining that the deviation is less than the second threshold, increase the unit interval time corresponding to the above preset period.
[0070] Specifically, in this embodiment, after calibrating the local synchronization time based on the above pulse signal, an oscilloscope can be used to determine the quality of the calibration effect, that is, to determine the deviation between the calibrated local synchronization time and the time of the first FPGA device through an oscilloscope. When it is determined that the deviation is greater than the first threshold, it means that the calibration effect needs to be improved at this time. The unit interval time corresponding to the above preset period can be reduced, that is, the emission rate of the pulse signal can be increased to improve the time calibration effect. Correspondingly, when it is determined that the deviation is less than the second threshold, it means that the calibration effect can meet the usage requirements at this time. Therefore, the unit interval time corresponding to the above preset period can be appropriately increased, that is, the emission rate of the pulse signal can be appropriately reduced to save energy consumption.
[0071] In some embodiments, before calibrating the local synchronization time based on the above pulse signal, the time calibration method of the present application further includes:
[0072] Determine the unit interval time based on the above preset period;
[0073] Determine whether the deviation between the local synchronization time and the time of the first FPGA device is less than half of the above unit interval time;
[0074] In response to determining that the deviation between the above-mentioned local synchronization time and the time of the above-mentioned first FPGA device is not less than one-half of the above-mentioned unit interval time, re-obtain the target timestamp sent by the above-mentioned first FPGA device;
[0075] Based on the re-obtained target timestamp, re-synchronize the local time of the second FPGA device to obtain the re-synchronized local synchronization time.
[0076] In specific implementation, considering that when calibrating time through pulse signals in the embodiments of the present application, the time deviation needs to be less than half of the unit interval time. For example, when sending a pulse signal once every 1 second, the time deviation needs to be less than 0.5 seconds. Normally, the deviation between FPGA devices will meet this condition, but in some cases, the deviation may be greater than this range. Therefore, to avoid this situation, before calibrating through pulse signals, it can be determined whether the time deviation meets the condition for using pulse calibration. If not, the target timestamp can be re-obtained for time synchronization.
[0077] In some embodiments, the time calibration method of the present application further includes:
[0078] Determine whether the deviation between the re-synchronized local synchronization time and the time of the above-mentioned first FPGA device is less than one-half of the above-mentioned unit interval time;
[0079] In response to determining that the deviation between the re-synchronized local synchronization time and the time of the above-mentioned first FPGA device is not less than one-half of the above-mentioned unit interval time, increase the unit interval time of the above-mentioned preset period.
[0080] In specific implementation, considering that when the time deviation is large and this deviation cannot be offset by re-obtaining the target timestamp. To be able to use pulse signals for time calibration, the unit interval time of the preset period can be increased.
[0081] Reference Figure 3 , is a schematic flowchart of another time calibration method provided by an embodiment of the present application. As Figure 1 shown, the method includes the following steps:
[0082] S201, Obtain standard clock information from the timing device and convert the standard clock information into a target timestamp.
[0083] S202, Send the target timestamp to the second FPGA device corresponding to the first FPGA device, so that the second FPGA device synchronizes its local time based on the target timestamp.
[0084] S203, send a pulse signal to the second FPGA device every preset time period, so that the second FPGA device calibrates the synchronized local time according to the pulse signal.
[0085] In specific implementation, in the embodiment of the present application, the first FPGA device first obtains standard clock information from the timing device and converts the standard clock information into a target timestamp. In an example, the target timestamp includes a value in a first time unit and a value in a second time unit, and the level of the first time unit is higher than that of the second time unit. After generating the target timestamp, the first FPGA device sends the target timestamp to the second FPGA device corresponding to the first FPGA device, so that the second FPGA device synchronizes the local time based on the target timestamp. At the same time, the first FPGA device sends a pulse signal to the second FPGA device every preset time period, so that the second FPGA device calibrates the synchronized local time according to the pulse signal.
[0086] It should be noted that, for the convenience of understanding, the above Figure 3 corresponding embodiments are described from the perspective of the first FPGA device, that is, the execution subject of the above Figure 3 corresponding embodiments is the second FPGA device.
[0087] In the time calibration method of the embodiment of the present application, after receiving the target timestamp sent by the first FPGA device, the second FPGA device first synchronizes the local time of the second FPGA device through the target timestamp, and then while maintaining the local synchronization time of the second FPGA device through the local clock, the first FPGA device will send a pulse signal to the second FPGA device according to a preset period. Since the transmission of the pulse signal not only has a low delay, and even the delay is basically negligible, and there is no need to establish a time calibration protocol between each FPGA device, therefore, the second FPGA device calibrates the local synchronization time according to the received pulse signal, which can not only avoid calibration errors caused by transmission delay, but also reduce the consumption of system resources for establishing a time calibration protocol, while improving the accuracy of time synchronization and reducing the cost of time synchronization.
[0088] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides a time calibration device.
[0089] Referring to Figure 4 , the time calibration device includes:
[0090] An acquisition module 401, which acquires the target timestamp sent by the first FPGA device;
[0091] The synchronization module 402 synchronizes the local time of the second FPGA device based on the target timestamp to obtain the local synchronized time of the second FPGA device;
[0092] The maintenance module 403 determines the clock accumulation frequency of the local synchronized time based on the local clock of the second FPGA device, and maintains the local synchronized time based on the clock accumulation frequency;
[0093] The calibration module 404 receives the pulse signal sent by the first FPGA device at a preset period, and calibrates the local synchronized time based on the pulse signal.
[0094] For convenience of description, when describing the above device, various modules are described separately according to their functions. Of course, when implementing the present application, the functions of each module can be implemented in one or more software and / or hardware.
[0095] The time calibration device of the above embodiment is used to implement the corresponding time calibration method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated herein.
[0096] Figure 5 The hardware structure diagram of the electronic device provided by the embodiment of the present application is shown.
[0097] In some embodiments, the electronic device may include a processor 501 and a memory 502 storing computer program instructions.
[0098] Specifically, the above processor 501 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.
[0099] The memory 502 may include a mass storage for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a tape, or a universal serial bus (USB) drive or a combination of two or more of these. In a suitable case, the memory 502 may include a removable or non-removable (or fixed) medium. In a suitable case, the memory 502 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, the memory 502 is a non-volatile solid state memory.
[0100] In a specific embodiment, the memory 502 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 502 may store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 502 and are called and executed by the processor 501. The processor 501 reads and executes the computer program instructions stored in the memory 502 to implement any one of the time calibration methods in the above embodiments.
[0101] In one example, the electronic device may further include a communication interface 503 and a bus 510. Among them, as Figure 5 shown, the processor 501, the memory 502, and the communication interface 503 are connected through the bus 510 and complete communication with each other.
[0102] The communication interface 503 is mainly used to implement communication between each module, device, unit, and / or device in the embodiments of the present application.
[0103] The bus 510 includes hardware, software, or both, and couples the components of the online data flow metering device to each other. By way of example and not limitation, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses or a combination of two or more of these. In a suitable case, the bus 510 may include one or more buses. Although the embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.
[0104] The electronic device in the above embodiments is used to implement the corresponding time calibration method in any one of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here.
[0105] In addition, in combination with the time calibration method in the above embodiments, the embodiments of the present application may provide a computer storage medium to implement. Computer program instructions are stored on the computer storage medium; when the computer program instructions are executed by a processor, any one of the time calibration methods in the above embodiments is implemented.
[0106] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette tapes, magnetic disk storage, or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.
[0107] The computer instructions stored in the storage medium of the above embodiment are used to cause the computer to execute the time calibration method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be elaborated here.
[0108] The embodiment of the present application also provides a computer program product, including a computer program, and when the computer program is executed, it implements any one of the time calibration methods in the above embodiments.
[0109] In some embodiments, the computer program instructions can be executed by one or more processors of the computer so that the computer and / or the processor execute the time calibration method described in the above embodiments. Corresponding to the execution subject of each step in the respective embodiments of the time calibration method, the processor that executes the corresponding step can belong to the corresponding execution subject.
[0110] The computer program product of the above embodiment is used to cause the computer and / or the processor to execute the time calibration method described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here.
[0111] It should be clear that the present application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, the detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order between steps after understanding the spirit of the present application.
[0112] The functional blocks shown in the above-described structural block diagrams can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, and so on. When implemented in software, the elements of the present application are programs or code segments for performing the required tasks. The program or code segment can be stored in a machine-readable medium or transmitted via a data signal carried in a carrier wave over a transmission medium or a communication link. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical discs, hard disks, fiber optic media, radio frequency (RF) links, and so on. The code segment can be downloaded via a computer network such as the Internet, an intranet, and so on.
[0113] It should also be noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be executed in the order mentioned in the embodiments, or different from the order in the embodiments, or several steps can be executed simultaneously.
[0114] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It should also be understood that each block in the block diagrams and / or flowcharts, and the combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware for performing the specified functions or actions, or by a combination of dedicated hardware and computer instructions.
[0115] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application.
Claims
1. A time calibration method, characterized in that: include: Obtain a target timestamp sent by the first FPGA device; Synchronize the local time of the second FPGA device based on the target timestamp to obtain the local synchronization time of the second FPGA device; Determine a clock accumulation frequency of the local synchronization time based on a local clock of the second FPGA device, and maintain the local synchronization time based on the clock accumulation frequency; A pulse signal sent by the first FPGA device according to a preset period is received, and the local synchronization time is calibrated based on the pulse signal.
2. The method according to claim 1, characterized in that The target timestamp includes a value located in a first time unit and a value located in a second time unit, and the level of the first time unit is higher than the level of the second time unit; Calibrating the local synchronization time based on the reception time corresponding to the pulse signal includes: In response to receiving the pulse signal for the first time, clearing the value of the local synchronization time at the time when the pulse signal is received and located in the second time unit to zero; In response to not receiving the pulse signal for the first time, adjusting the clock accumulation frequency based on the local synchronization time when the pulse signal is received.
3. The method according to claim 2, characterized in that Adjusting the clock accumulation frequency based on the local synchronization time when the pulse signal is received includes: Determining a unit interval time based on the preset period; Calculate the remainder of the local synchronization time when the pulse signal is received divided by the unit interval time; In response to the remainder being greater than zero and less than one-half of the unit interval time, reducing the clock accumulation frequency based on the remainder; In response to the remainder being greater than one-half of the unit interval time, increasing the clock accumulation frequency based on the remainder.
4. The method according to claim 2, characterized in that: Adjusting the clock accumulation frequency based on the local synchronization time when the pulse signal is received includes: Determining a unit interval time based on the preset period; In response to determining that the unit interval time is equal to the time corresponding to the unit value of the first time unit, determining a target value in the second time unit in the local synchronization time when the pulse signal is received; In response to the time corresponding to the target value being greater than zero and less than one-half of the unit interval time, reducing the clock accumulation frequency based on the target value; In response to the time corresponding to the target value being greater than half of the unit interval time, the clock accumulation frequency is increased based on the target value.
5. The method according to any one of claims 1 to 4, characterized in that: After calibrating the local synchronization time based on the pulse signal, the method further includes: Determine, by an oscilloscope, a deviation between the calibrated local synchronization time and the time of the first FPGA device; In response to determining that the deviation is greater than a first threshold, reducing the unit interval time corresponding to the preset period; In response to determining that the deviation is less than a second threshold, the unit interval time corresponding to the preset period is increased.
6. The method according to claim 1, characterized in that Before calibrating the local synchronization time based on the pulse signal, the method further includes: Determining a unit interval time based on the preset period; Determine whether the deviation between the local synchronization time and the time of the first FPGA device is less than half of the unit interval time; In response to determining that the deviation between the local synchronization time and the time of the first FPGA device is not less than one-half of the unit interval time, reacquiring a target timestamp sent by the first FPGA device; The local time of the second FPGA device is resynchronized based on the reacquired target timestamp to obtain the resynchronized local synchronization time.
7. The method according to claim 6, characterized in that The method further comprises: Determine whether the deviation between the local synchronization time after resynchronization and the time of the first FPGA device is less than half of the unit interval time; In response to determining that the deviation between the local synchronization time after resynchronization and the time of the first FPGA device is not less than half of the unit interval time, the unit interval time of the preset period is increased.
8. The method according to claim 2, characterized in that: Get the target timestamp sent by the first FPGA device, including: successively acquiring a value in a first time unit and a value in a second time unit included in the target timestamp sent by the first FPGA device; When the value in the second time unit included in the target timestamp is received, the local time of the second FPGA device is synchronized.
9. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the method according to any one of claims 1 to 8 is implemented.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the time calibration method according to any one of claims 1 to 8 is implemented.